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clk: initialize wifi lp_clk in esp_perip_clk_init

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wuzhenghui
2022-12-29 12:29:10 +08:00
committed by lvshisheng
parent bba409eec1
commit a5fdc53bb7
1 changed files with 17 additions and 0 deletions
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17
components/esp_system/port/soc/esp32c6/clk.c
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@@ -180,6 +180,23 @@ void rtc_clk_select_rtc_slow_clk(void)
__attribute__((weak)) void esp_perip_clk_init(void) __attribute__((weak)) void esp_perip_clk_init(void)
{ {
modem_clock_domain_pmu_state_icg_map_init(); modem_clock_domain_pmu_state_icg_map_init();
/* During system initialization, the low-power clock source of the modem
* (WiFi, BLE or Coexist) follows the configuration of the slow clock source
* of the system. If the WiFi, BLE or Coexist module needs a higher
* precision sleep clock (for example, the BLE needs to use the main XTAL
* oscillator (40 MHz) to provide the clock during the sleep process in some
* scenarios), the module needs to switch to the required clock source by
* itself. */ //TODO - WIFI-5233
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t) ( \
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: IDF-5658 #if 0 // TODO: IDF-5658
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;