From 1b38494df4887306653d0ccf444c1192c983f2fd Mon Sep 17 00:00:00 2001 From: Liu Zhi Fu Date: Fri, 6 Jan 2017 12:23:11 +0800 Subject: [PATCH 1/3] bootloader: modify bootloader dram start address to 0x3fff0000 Modify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from 0x20000 to 0x10000. Please be notified that this is just a workaround for fixing app data overwrite bootloader data issue! --- components/bootloader/src/main/esp32.bootloader.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bootloader/src/main/esp32.bootloader.ld b/components/bootloader/src/main/esp32.bootloader.ld index 6a77eb6ade..0c57bdf48d 100644 --- a/components/bootloader/src/main/esp32.bootloader.ld +++ b/components/bootloader/src/main/esp32.bootloader.ld @@ -17,7 +17,7 @@ MEMORY dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */ iram_seg (RWX) : org = 0x40080000, len = 0x400 /* 1k of IRAM used by bootloader functions which need to flush/enable APP CPU cache */ iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */ - dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ + dram_seg (RW) : org = 0x3FFF0000, len = 0x10000 /* Shared RAM, minus rom bss/data/stack.*/ } /* Default entry point: */ From 61c6ce86d200428985f0539c0255899d58d46330 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 6 Jan 2017 13:03:07 +0800 Subject: [PATCH 2/3] esp32: put .data before .bss MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change reduces chances that a large .bss segment will push .data all the way into 0x3ffe1320 — 0x3ffe5320 range where the bootloader stack is, creating a problem when bootloader will be loading application into memory. With this change, .data would need to be at least 200k big to cause problems. --- components/esp32/ld/esp32.common.ld | 42 ++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/components/esp32/ld/esp32.common.ld b/components/esp32/ld/esp32.common.ld index 09b7634445..c199a41d3d 100644 --- a/components/esp32/ld/esp32.common.ld +++ b/components/esp32/ld/esp32.common.ld @@ -85,6 +85,27 @@ SECTIONS _iram_text_end = ABSOLUTE(.); } > iram0_0_seg + .dram0.data : + { + _data_start = ABSOLUTE(.); + KEEP(*(.data)) + KEEP(*(.data.*)) + KEEP(*(.gnu.linkonce.d.*)) + KEEP(*(.data1)) + KEEP(*(.sdata)) + KEEP(*(.sdata.*)) + KEEP(*(.gnu.linkonce.s.*)) + KEEP(*(.sdata2)) + KEEP(*(.sdata2.*)) + KEEP(*(.gnu.linkonce.s2.*)) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + *libesp32.a:panic.o(.rodata .rodata.*) + _data_end = ABSOLUTE(.); + . = ALIGN(4); + _heap_start = ABSOLUTE(.); + } >dram0_0_seg + /* Shared RAM */ .dram0.bss (NOLOAD) : { @@ -108,27 +129,6 @@ SECTIONS _bss_end = ABSOLUTE(.); } >dram0_0_seg - .dram0.data : - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - *(.dram1 .dram1.*) - *libesp32.a:panic.o(.rodata .rodata.*) - _data_end = ABSOLUTE(.); - . = ALIGN(4); - _heap_start = ABSOLUTE(.); - } >dram0_0_seg - .flash.rodata : { _rodata_start = ABSOLUTE(.); From 0b264f4f7b38a10d30ab864cbd5fe1a9b9b909fa Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 6 Jan 2017 13:47:53 +0800 Subject: [PATCH 3/3] bootloader: update ld script comment --- components/bootloader/src/main/esp32.bootloader.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bootloader/src/main/esp32.bootloader.ld b/components/bootloader/src/main/esp32.bootloader.ld index 0c57bdf48d..500478814c 100644 --- a/components/bootloader/src/main/esp32.bootloader.ld +++ b/components/bootloader/src/main/esp32.bootloader.ld @@ -17,7 +17,7 @@ MEMORY dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */ iram_seg (RWX) : org = 0x40080000, len = 0x400 /* 1k of IRAM used by bootloader functions which need to flush/enable APP CPU cache */ iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */ - dram_seg (RW) : org = 0x3FFF0000, len = 0x10000 /* Shared RAM, minus rom bss/data/stack.*/ + dram_seg (RW) : org = 0x3FFF0000, len = 0x10000 /* 64k at the end of DRAM, after ROM bootloader stack */ } /* Default entry point: */