From a90c9101ff6fe46e30d203900dc32239939e4f8a Mon Sep 17 00:00:00 2001 From: Fu Zhibo Date: Tue, 2 Jul 2024 16:56:16 +0800 Subject: [PATCH] feat: support regi2c for esp32c61 --- .../src/esp32c5/bootloader_esp32c5.c | 1 - .../src/esp32c61/bootloader_esp32c61.c | 12 +- .../port/esp32c61/CMakeLists.txt | 2 +- .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c61/esp_rom_caps.h | 3 +- .../esp_rom/patches/esp_rom_regi2c_esp32c61.c | 178 ++++++++++++++++++ .../hal/esp32c61/include/hal/regi2c_ctrl_ll.h | 2 - .../soc/esp32c5/include/soc/i2c_ana_mst_reg.h | 80 ++++---- .../soc/esp32c6/include/soc/i2c_ana_mst_reg.h | 82 ++++---- .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 + .../esp32c61/include/soc/i2c_ana_mst_reg.h | 82 ++++---- .../soc/esp32c61/include/soc/reg_base.h | 2 +- .../soc/esp32c61/include/soc/soc_caps.h | 2 +- 13 files changed, 317 insertions(+), 137 deletions(-) create mode 100644 components/esp_rom/patches/esp_rom_regi2c_esp32c61.c diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 7009b9afae..5c5ac3d6ed 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -38,7 +38,6 @@ #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" -#include "hal/clk_tree_ll.h" #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index 5b618fab87..45d26a18db 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -43,6 +43,8 @@ #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" +#include "modem/modem_lpcon_reg.h" +#include "modem/modem_syscon_reg.h" static const char *TAG = "boot.esp32c61"; @@ -94,12 +96,10 @@ static inline void bootloader_hardware_init(void) esp_rom_spiflash_fix_dummylen(1, 1); #endif -//TODO: [ESP32C61] IDF-9276 -#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!"); -#else - ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!"); -#endif + /* Enable analog i2c master clock */ + SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-9274 Remove this? + SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M); } static inline void bootloader_ana_reset_config(void) diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt index 759952944c..7ce5ce6653 100644 --- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt @@ -18,7 +18,7 @@ if(NOT BOOTLOADER_BUILD) endif() -# TODO: [ESP32C61] IDF-9250, [ESP32C61] IDF-9276 +# TODO: [ESP32C61] IDF-9250 if(CONFIG_IDF_TARGET_ESP32C61) list(REMOVE_ITEM srcs "pmu_param.c" diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index e5e00f6047..a3fd389478 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -63,6 +63,10 @@ config ESP_ROM_HAS_SPI_FLASH bool default y +config ESP_ROM_WITHOUT_REGI2C + bool + default y + config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index ba64361270..341dec7b83 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -21,8 +21,7 @@ #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver -// TODO: [ESP32C61] IDF-9276, still should be true, temp commented -// #define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c new file mode 100644 index 0000000000..daffbd513e --- /dev/null +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/pmu_reg.h" // TODO: IDF-9249 Can be removed +#include "modem/modem_lpcon_reg.h" + +#define REGI2C_BIAS_MST_SEL (BIT(8)) +#define REGI2C_BBPLL_MST_SEL (BIT(9)) +#define REGI2C_ULP_CAL_MST_SEL (BIT(10)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(11)) +#define REGI2C_DIG_REG_MST_SEL (BIT(12)) + +#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_ANA_MST_ANA_CONF1_M) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ + +#define REGI2C_BBPLL (0x66) +#define REGI2C_BBPLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_ULP_CAL (0x61) +#define REGI2C_ULP_CAL_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 + +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + uint32_t i2c_sel = 0; + + REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-9249 Move to pmu_init() + REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-9249 Move to pmu_init() + + /* Before config I2C register, enable corresponding slave. */ + switch (block) { + case REGI2C_BBPLL : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + break; + case REGI2C_BIAS : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + break; + case REGI2C_DIG_REG: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + break; + case REGI2C_ULP_CAL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + break; + case REGI2C_SAR_I2C: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + break; + } + + return (uint8_t)(i2c_sel ? 0: 1); +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + return ret; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + return ret; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h index dcc2f6fe18..dbd84d1dd2 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -15,8 +15,6 @@ extern "C" { #endif -// TODO: [ESP32C61] IDF-9276, inherit from c6 - /** * @brief Start BBPLL self-calibration */ diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h index 4089e68b3e..6e38d22574 100644 --- a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h @@ -14,89 +14,89 @@ extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -124,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -146,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2210310 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h index d0f6d4c843..0f28b3a7a3 100644 --- a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,89 +14,89 @@ extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -124,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -146,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index d5e20a3715..c1669c6086 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -47,6 +47,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_REG_I2C_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y diff --git a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h index 8e80288ead..08aea2d8c9 100644 --- a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h @@ -9,96 +9,94 @@ #include #include "soc/soc.h" -//TODO: [ESP32C61] IDF-9276, inherit from c6 - #ifdef __cplusplus extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -126,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -148,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2210310 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 4a6a58e388..226a2517f9 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -41,7 +41,7 @@ #define DR_REG_MODEM1_BASE 0x600AC000 #define DR_REG_MODEM_PWR0_BASE 0x600AD000 #define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 //TODO: [ESP32C61] IDF-9276, from verify +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 47ac1eed8b..527b2d1ccb 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -61,7 +61,7 @@ #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314 // \#define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236 // \#define SOC_MODEM_CLOCK_SUPPORTED 1 -// \#define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9276 +#define SOC_REG_I2C_SUPPORTED 1 // \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 // \#define SOC_ETM_SUPPORTED 0