diff --git a/components/hal/esp32c5/include/hal/lp_timer_ll.h b/components/hal/esp32c5/include/hal/lp_timer_ll.h
index cac0a289b5..6e8b35d6af 100644
--- a/components/hal/esp32c5/include/hal/lp_timer_ll.h
+++ b/components/hal/esp32c5/include/hal/lp_timer_ll.h
@@ -73,6 +73,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
     dev->lp_int_clr.val = mask;
 }
 
+FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
+{
+    dev->lp_int_ena.main_timer_lp_int_ena = enable;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c6/include/hal/lp_timer_ll.h b/components/hal/esp32c6/include/hal/lp_timer_ll.h
index 080555bd89..a43a57a684 100644
--- a/components/hal/esp32c6/include/hal/lp_timer_ll.h
+++ b/components/hal/esp32c6/include/hal/lp_timer_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -73,6 +73,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
     dev->lp_int_clr.val = mask;
 }
 
+FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
+{
+    dev->lp_int_en.alarm = enable;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c61/include/hal/lp_timer_ll.h b/components/hal/esp32c61/include/hal/lp_timer_ll.h
index 1817542336..291b0b3bd7 100644
--- a/components/hal/esp32c61/include/hal/lp_timer_ll.h
+++ b/components/hal/esp32c61/include/hal/lp_timer_ll.h
@@ -73,6 +73,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
     dev->lp_int_clr.val = mask;
 }
 
+FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
+{
+    dev->lp_int_ena.main_timer_lp_int_ena = enable;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/include/hal/lp_timer_ll.h b/components/hal/esp32h2/include/hal/lp_timer_ll.h
index c8e6e2a054..d36788f15c 100644
--- a/components/hal/esp32h2/include/hal/lp_timer_ll.h
+++ b/components/hal/esp32h2/include/hal/lp_timer_ll.h
@@ -57,6 +57,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *de
     dev->int_clr.overflow = 1;
 }
 
+FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
+{
+    dev->lp_int_en.alarm = enable;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/lp_timer_ll.h b/components/hal/esp32p4/include/hal/lp_timer_ll.h
index 45e8ad3fa8..8ebe6d041c 100644
--- a/components/hal/esp32p4/include/hal/lp_timer_ll.h
+++ b/components/hal/esp32p4/include/hal/lp_timer_ll.h
@@ -73,6 +73,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
     dev->lp_int_clr.val = mask;
 }
 
+FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
+{
+    dev->lp_int_ena.main_timer_lp_int_ena = enable;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
index 48ab1529ba..6279136e8c 100644
--- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
+++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
@@ -104,6 +104,20 @@ void ulp_lp_core_sw_intr_enable(bool enable);
  */
 void ulp_lp_core_sw_intr_clear(void);
 
+#if SOC_LP_TIMER_SUPPORTED
+/**
+ * @brief Enable the LP Timer interrupt
+ *
+ */
+void ulp_lp_core_lp_timer_intr_enable(bool enable);
+
+/**
+ * @brief Clear the interrupt status for the LP Timer interrupt
+ *
+ */
+void ulp_lp_core_lp_timer_intr_clear(void);
+#endif
+
 /**
  * @brief Puts the CPU into a wait state until an interrupt is triggered
  *
diff --git a/components/ulp/lp_core/lp_core/lp_core_utils.c b/components/ulp/lp_core/lp_core/lp_core_utils.c
index 7bada098ca..ddf391a17d 100644
--- a/components/ulp/lp_core/lp_core/lp_core_utils.c
+++ b/components/ulp/lp_core/lp_core/lp_core_utils.c
@@ -191,6 +191,18 @@ void ulp_lp_core_sw_intr_clear(void)
     pmu_ll_lp_clear_sw_intr_status(&PMU);
 }
 
+#if SOC_LP_TIMER_SUPPORTED
+void ulp_lp_core_lp_timer_intr_enable(bool enable)
+{
+    lp_timer_ll_lp_alarm_intr_enable(&LP_TIMER, enable);
+}
+
+void ulp_lp_core_lp_timer_intr_clear(void)
+{
+    lp_timer_ll_clear_lp_alarm_intr_status(&LP_TIMER);
+}
+#endif
+
 void ulp_lp_core_wait_for_intr(void)
 {
     asm volatile("wfi");