refactor(lpperi): compatible refactor for H2 ECO5

components/esp_system/port/cpu_start.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -53,6 +53,7 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/cache.h"
 #include "esp_memprot.h"
+#include "soc/lpperi_struct.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/cache.h"
 #include "esp32c2/rom/secure_boot.h"
@@ -451,6 +452,13 @@ void IRAM_ATTR call_start_cpu0(void)
     }
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32H2
+    // Some modules' register layout are not binary compatible among the different chip revisions,
+    // they will be wrapped into a new compatible instance which will point to the correct register address according to the revision.
+    // To ensure the compatible instance is initialized before used, the initialization is done after BBS is cleared
+    lpperi_compatible_reg_addr_init();
+#endif
+
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
     do_multicore_settings();