From 5b00d1f396635af3b50df6d73b186153ab3c17c3 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 16 Feb 2023 16:22:34 +0800 Subject: [PATCH] efuse: Update efuses for esp32 esp32c2 esp32c3 esp32s2 esp32s3 --- components/efuse/esp32/esp_efuse_table.c | 1057 +++- components/efuse/esp32/esp_efuse_table.csv | 204 +- .../efuse/esp32/include/esp_efuse_table.h | 178 +- components/efuse/esp32c2/esp_efuse_table.c | 665 ++- components/efuse/esp32c2/esp_efuse_table.csv | 193 +- .../efuse/esp32c2/include/esp_efuse_table.h | 73 +- components/efuse/esp32c3/esp_efuse_table.c | 1487 ++++-- components/efuse/esp32c3/esp_efuse_table.csv | 356 +- .../efuse/esp32c3/include/esp_efuse_table.h | 192 +- components/efuse/esp32s2/esp_efuse_table.c | 1363 +++-- components/efuse/esp32s2/esp_efuse_table.csv | 361 +- .../efuse/esp32s2/include/esp_efuse_table.h | 196 +- components/efuse/esp32s3/esp_efuse_table.c | 1822 +++++-- components/efuse/esp32s3/esp_efuse_table.csv | 410 +- .../efuse/esp32s3/include/esp_efuse_table.h | 213 +- components/hal/esp32/include/hal/efuse_ll.h | 74 +- components/hal/esp32c2/include/hal/efuse_ll.h | 12 +- components/hal/esp32c3/include/hal/efuse_ll.h | 6 +- components/hal/esp32s2/include/hal/efuse_ll.h | 28 +- components/hal/esp32s3/include/hal/efuse_ll.h | 16 +- components/soc/esp32/include/soc/efuse_defs.h | 51 + components/soc/esp32/include/soc/efuse_reg.h | 2327 +++++---- .../soc/esp32/include/soc/efuse_struct.h | 1336 ++++- .../soc/esp32c2/include/soc/efuse_defs.h | 17 + .../soc/esp32c2/include/soc/efuse_reg.h | 347 +- .../soc/esp32c2/include/soc/efuse_struct.h | 171 +- .../soc/esp32c3/include/soc/efuse_defs.h | 17 + .../soc/esp32c3/include/soc/efuse_reg.h | 4200 ++++++++------- .../soc/esp32c3/include/soc/efuse_struct.h | 2880 ++++++++-- .../soc/esp32s2/include/soc/efuse_defs.h | 17 + .../soc/esp32s2/include/soc/efuse_reg.h | 4622 +++++++++-------- .../soc/esp32s2/include/soc/efuse_struct.h | 2954 +++++++++-- .../soc/esp32s3/include/soc/efuse_defs.h | 39 + .../soc/esp32s3/include/soc/efuse_reg.h | 4329 +++++++++------ .../soc/esp32s3/include/soc/efuse_struct.h | 2985 +++++++++-- 35 files changed, 24034 insertions(+), 11164 deletions(-) create mode 100644 components/soc/esp32/include/soc/efuse_defs.h create mode 100644 components/soc/esp32c2/include/soc/efuse_defs.h create mode 100644 components/soc/esp32c3/include/soc/efuse_defs.h create mode 100644 components/soc/esp32s2/include/soc/efuse_defs.h create mode 100644 components/soc/esp32s3/include/soc/efuse_defs.h diff --git a/components/efuse/esp32/esp_efuse_table.c b/components/efuse/esp32/esp_efuse_table.c index c02ab77fa1..e436effa57 100644 --- a/components/efuse/esp32/esp_efuse_table.c +++ b/components/efuse/esp32/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table c5ac3aa2d3a97d98ced4f4fccf48c328 +// md5_digest_table 2e197b7b14eec62fa5bdf94c6d71e87a // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -26,414 +26,961 @@ _Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not matc _Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files."); _Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files."); -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK0, 72, 8}, // Factory MAC addr [0], - {EFUSE_BLK0, 64, 8}, // Factory MAC addr [1], - {EFUSE_BLK0, 56, 8}, // Factory MAC addr [2], - {EFUSE_BLK0, 48, 8}, // Factory MAC addr [3], - {EFUSE_BLK0, 40, 8}, // Factory MAC addr [4], - {EFUSE_BLK0, 32, 8}, // Factory MAC addr [5], -}; - -static const esp_efuse_desc_t MAC_FACTORY_CRC[] = { - {EFUSE_BLK0, 80, 8}, // CRC8 for factory MAC address, -}; - -static const esp_efuse_desc_t MAC_CUSTOM_CRC[] = { - {EFUSE_BLK3, 0, 8}, // CRC8 for custom MAC address., -}; - -static const esp_efuse_desc_t MAC_CUSTOM[] = { - {EFUSE_BLK3, 8, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t MAC_CUSTOM_VER[] = { - {EFUSE_BLK3, 184, 8}, // Custom MAC version, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY[] = { - {EFUSE_BLK2, 0, MAX_BLK_LEN}, // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128), -}; - -static const esp_efuse_desc_t ABS_DONE_0[] = { - {EFUSE_BLK0, 196, 1}, // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0, -}; - -static const esp_efuse_desc_t ABS_DONE_1[] = { - {EFUSE_BLK0, 197, 1}, // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1, -}; - -static const esp_efuse_desc_t ENCRYPT_FLASH_KEY[] = { - {EFUSE_BLK1, 0, MAX_BLK_LEN}, // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128), -}; - -static const esp_efuse_desc_t ENCRYPT_CONFIG[] = { - {EFUSE_BLK0, 188, 4}, // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M, -}; - -static const esp_efuse_desc_t DISABLE_DL_ENCRYPT[] = { - {EFUSE_BLK0, 199, 1}, // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT., -}; - -static const esp_efuse_desc_t DISABLE_DL_DECRYPT[] = { - {EFUSE_BLK0, 200, 1}, // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT., -}; - -static const esp_efuse_desc_t DISABLE_DL_CACHE[] = { - {EFUSE_BLK0, 201, 1}, // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE., -}; - -static const esp_efuse_desc_t FLASH_CRYPT_CNT[] = { - {EFUSE_BLK0, 20, 7}, // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT., -}; - -static const esp_efuse_desc_t DISABLE_JTAG[] = { - {EFUSE_BLK0, 198, 1}, // Disable JTAG. EFUSE_RD_DISABLE_JTAG., -}; - -static const esp_efuse_desc_t CONSOLE_DEBUG_DISABLE[] = { - {EFUSE_BLK0, 194, 1}, // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE., -}; - -static const esp_efuse_desc_t UART_DOWNLOAD_DIS[] = { - {EFUSE_BLK0, 27, 1}, // Disable UART download mode. Valid for ESP32 V3 and newer, -}; - static const esp_efuse_desc_t WR_DIS[] = { {EFUSE_BLK0, 0, 16}, // [] Efuse write disable mask, }; -static const esp_efuse_desc_t WR_DIS_EFUSE_RD_DISABLE[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for EFUSE_RD_DISABLE, +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_WR_DIS[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of WR_DIS, }; static const esp_efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] = { - {EFUSE_BLK0, 2, 1}, // Flash encrypt. Write protection FLASH_CRYPT_CNT, + {EFUSE_BLK0, 2, 1}, // [] wr_dis of FLASH_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_UART_DOWNLOAD_DIS[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of UART_DOWNLOAD_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_MAC_CRC[] = { + {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_APP_CPU[] = { + {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BT[] = { + {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT, }; static const esp_efuse_desc_t WR_DIS_DIS_CACHE[] = { - {EFUSE_BLK0, 3, 1}, // [] wr_dis of DIS_CACHE, + {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE, }; -static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 7, 1}, // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1, +static const esp_efuse_desc_t WR_DIS_VOL_LEVEL_HP_INV[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VOL_LEVEL_HP_INV, }; -static const esp_efuse_desc_t WR_DIS_BLK2[] = { - {EFUSE_BLK0, 8, 1}, // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2, +static const esp_efuse_desc_t WR_DIS_CLK8M_FREQ[] = { + {EFUSE_BLK0, 4, 1}, // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ, }; -static const esp_efuse_desc_t WR_DIS_BLK3[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3, +static const esp_efuse_desc_t WR_DIS_ADC_VREF[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of ADC_VREF, }; -static const esp_efuse_desc_t RD_DIS_BLK1[] = { - {EFUSE_BLK0, 16, 1}, // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1, +static const esp_efuse_desc_t WR_DIS_XPD_SDIO_REG[] = { + {EFUSE_BLK0, 5, 1}, // [] wr_dis of XPD_SDIO_REG, }; -static const esp_efuse_desc_t RD_DIS_BLK2[] = { - {EFUSE_BLK0, 17, 1}, // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2, +static const esp_efuse_desc_t WR_DIS_XPD_SDIO_TIEH[] = { + {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH, }; -static const esp_efuse_desc_t RD_DIS_BLK3[] = { - {EFUSE_BLK0, 18, 1}, // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3, +static const esp_efuse_desc_t WR_DIS_XPD_SDIO_FORCE[] = { + {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE, }; -static const esp_efuse_desc_t CHIP_VER_DIS_APP_CPU[] = { - {EFUSE_BLK0, 96, 1}, // EFUSE_RD_CHIP_VER_DIS_APP_CPU, +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK, }; -static const esp_efuse_desc_t CHIP_VER_DIS_BT[] = { - {EFUSE_BLK0, 97, 1}, // EFUSE_RD_CHIP_VER_DIS_BT, +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q, }; -static const esp_efuse_desc_t CHIP_VER_PKG[] = { - {EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG least significant bits, - {EFUSE_BLK0, 98, 1}, // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit, +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_D, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CS0[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK1[] = { + {EFUSE_BLK0, 7, 1}, // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK2[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK3[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.BLK3] wr_dis of BLOCK3, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC_CRC[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_TP_LOW[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_LOW, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_TP_HIGH[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_HIGH, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_TP_LOW[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_LOW, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_TP_HIGH[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_HIGH, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_MAC_VERSION[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK3_PART_RESERVE[] = { + {EFUSE_BLK0, 10, 1}, // [] wr_dis of BLK3_PART_RESERVE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CRYPT_CONFIG[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG, +}; + +static const esp_efuse_desc_t WR_DIS_CODING_SCHEME[] = { + {EFUSE_BLK0, 10, 1}, // [] wr_dis of CODING_SCHEME, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_STATUS[] = { + {EFUSE_BLK0, 10, 1}, // [] wr_dis of KEY_STATUS, +}; + +static const esp_efuse_desc_t WR_DIS_ABS_DONE_0[] = { + {EFUSE_BLK0, 12, 1}, // [] wr_dis of ABS_DONE_0, +}; + +static const esp_efuse_desc_t WR_DIS_ABS_DONE_1[] = { + {EFUSE_BLK0, 13, 1}, // [] wr_dis of ABS_DONE_1, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_DISABLE[] = { + {EFUSE_BLK0, 14, 1}, // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE, +}; + +static const esp_efuse_desc_t WR_DIS_CONSOLE_DEBUG_DISABLE[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of CONSOLE_DEBUG_DISABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_DL_ENCRYPT[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_DL_DECRYPT[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_DECRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_DL_CACHE[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_CACHE, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 16, 4}, // [] Disable reading from BlOCK1-3, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK1[] = { + {EFUSE_BLK0, 16, 1}, // [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK2[] = { + {EFUSE_BLK0, 17, 1}, // [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK3[] = { + {EFUSE_BLK0, 18, 1}, // [RD_DIS.BLK3] rd_dis of BLOCK3, +}; + +static const esp_efuse_desc_t RD_DIS_CUSTOM_MAC_CRC[] = { + {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC, +}; + +static const esp_efuse_desc_t RD_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_TP_LOW[] = { + {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_LOW, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_TP_HIGH[] = { + {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_HIGH, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_TP_LOW[] = { + {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_LOW, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_TP_HIGH[] = { + {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_HIGH, +}; + +static const esp_efuse_desc_t RD_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] rd_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t RD_DIS_MAC_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION, +}; + +static const esp_efuse_desc_t RD_DIS_BLK3_PART_RESERVE[] = { + {EFUSE_BLK0, 19, 1}, // [] rd_dis of BLK3_PART_RESERVE, +}; + +static const esp_efuse_desc_t RD_DIS_FLASH_CRYPT_CONFIG[] = { + {EFUSE_BLK0, 19, 1}, // [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG, +}; + +static const esp_efuse_desc_t RD_DIS_CODING_SCHEME[] = { + {EFUSE_BLK0, 19, 1}, // [] rd_dis of CODING_SCHEME, +}; + +static const esp_efuse_desc_t RD_DIS_KEY_STATUS[] = { + {EFUSE_BLK0, 19, 1}, // [] rd_dis of KEY_STATUS, +}; + +static const esp_efuse_desc_t FLASH_CRYPT_CNT[] = { + {EFUSE_BLK0, 20, 7}, // [] Flash encryption is enabled if this field has an odd number of bits set, +}; + +static const esp_efuse_desc_t UART_DOWNLOAD_DIS[] = { + {EFUSE_BLK0, 27, 1}, // [] Disable UART download mode. Valid for ESP32 V3 and newer; only, +}; + +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK0, 72, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK0, 64, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK0, 56, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK0, 48, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK0, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK0, 32, 8}, // [MAC_FACTORY] MAC address, +}; + +static const esp_efuse_desc_t MAC_CRC[] = { + {EFUSE_BLK0, 80, 8}, // [MAC_FACTORY_CRC] CRC8 for MAC address, +}; + +static const esp_efuse_desc_t DISABLE_APP_CPU[] = { + {EFUSE_BLK0, 96, 1}, // [CHIP_VER_DIS_APP_CPU] Disables APP CPU, +}; + +static const esp_efuse_desc_t DISABLE_BT[] = { + {EFUSE_BLK0, 97, 1}, // [CHIP_VER_DIS_BT] Disables Bluetooth, +}; + +static const esp_efuse_desc_t CHIP_PACKAGE_4BIT[] = { + {EFUSE_BLK0, 98, 1}, // [CHIP_VER_PKG_4BIT] Chip package identifier #4bit, +}; + +static const esp_efuse_desc_t DIS_CACHE[] = { + {EFUSE_BLK0, 99, 1}, // [CHIP_VER_DIS_CACHE] Disables cache, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK0, 100, 5}, // [] read for SPI_pad_config_hd, +}; + +static const esp_efuse_desc_t CHIP_PACKAGE[] = { + {EFUSE_BLK0, 105, 3}, // [CHIP_VER_PKG] Chip package identifier, }; static const esp_efuse_desc_t CHIP_CPU_FREQ_LOW[] = { - {EFUSE_BLK0, 108, 1}, // EFUSE_RD_CHIP_CPU_FREQ_LOW, + {EFUSE_BLK0, 108, 1}, // [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise, }; static const esp_efuse_desc_t CHIP_CPU_FREQ_RATED[] = { - {EFUSE_BLK0, 109, 1}, // EFUSE_RD_CHIP_CPU_FREQ_RATED, + {EFUSE_BLK0, 109, 1}, // [] If set; the ESP32's maximum CPU frequency has been rated, +}; + +static const esp_efuse_desc_t BLK3_PART_RESERVE[] = { + {EFUSE_BLK0, 110, 1}, // [] BLOCK3 partially served for ADC calibration data, }; static const esp_efuse_desc_t CHIP_VER_REV1[] = { - {EFUSE_BLK0, 111, 1}, // EFUSE_RD_CHIP_VER_REV1, + {EFUSE_BLK0, 111, 1}, // [] bit is set to 1 for rev1 silicon, }; -static const esp_efuse_desc_t CHIP_VER_REV2[] = { - {EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2, +static const esp_efuse_desc_t CLK8M_FREQ[] = { + {EFUSE_BLK0, 128, 8}, // [CK8M_FREQ] 8MHz clock freq override, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK0, 184, 2}, // WAFER_VERSION_MINOR, +static const esp_efuse_desc_t ADC_VREF[] = { + {EFUSE_BLK0, 136, 5}, // [] True ADC reference voltage, }; static const esp_efuse_desc_t XPD_SDIO_REG[] = { - {EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG, + {EFUSE_BLK0, 142, 1}, // [] read for XPD_SDIO_REG, }; -static const esp_efuse_desc_t SDIO_TIEH[] = { - {EFUSE_BLK0, 143, 1}, // EFUSE_RD_SDIO_TIEH, +static const esp_efuse_desc_t XPD_SDIO_TIEH[] = { + {EFUSE_BLK0, 143, 1}, // [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"}, }; -static const esp_efuse_desc_t SDIO_FORCE[] = { - {EFUSE_BLK0, 144, 1}, // EFUSE_RD_SDIO_FORCE, +static const esp_efuse_desc_t XPD_SDIO_FORCE[] = { + {EFUSE_BLK0, 144, 1}, // [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset, }; -static const esp_efuse_desc_t ADC_VREF_AND_SDIO_DREF[] = { - {EFUSE_BLK0, 136, 6}, // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1], +static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 160, 5}, // [] Override SD_CLK pad (GPIO6/SPICLK), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 165, 5}, // [] Override SD_DATA_0 pad (GPIO7/SPIQ), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 170, 5}, // [] Override SD_DATA_1 pad (GPIO8/SPID), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CS0[] = { + {EFUSE_BLK0, 175, 5}, // [] Override SD_CMD pad (GPIO11/SPICS0), +}; + +static const esp_efuse_desc_t CHIP_VER_REV2[] = { + {EFUSE_BLK0, 180, 1}, // [], +}; + +static const esp_efuse_desc_t VOL_LEVEL_HP_INV[] = { + {EFUSE_BLK0, 182, 2}, // [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO), +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 184, 2}, // [], +}; + +static const esp_efuse_desc_t FLASH_CRYPT_CONFIG[] = { + {EFUSE_BLK0, 188, 4}, // [ENCRYPT_CONFIG] Flash encryption config (key tweak bits), +}; + +static const esp_efuse_desc_t CODING_SCHEME[] = { + {EFUSE_BLK0, 192, 2}, // [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"}, +}; + +static const esp_efuse_desc_t CONSOLE_DEBUG_DISABLE[] = { + {EFUSE_BLK0, 194, 1}, // [] Disable ROM BASIC interpreter fallback, +}; + +static const esp_efuse_desc_t DISABLE_SDIO_HOST[] = { + {EFUSE_BLK0, 195, 1}, // [], +}; + +static const esp_efuse_desc_t ABS_DONE_0[] = { + {EFUSE_BLK0, 196, 1}, // [] Secure boot V1 is enabled for bootloader image, +}; + +static const esp_efuse_desc_t ABS_DONE_1[] = { + {EFUSE_BLK0, 197, 1}, // [] Secure boot V2 is enabled for bootloader image, +}; + +static const esp_efuse_desc_t JTAG_DISABLE[] = { + {EFUSE_BLK0, 198, 1}, // [DISABLE_JTAG] Disable JTAG, +}; + +static const esp_efuse_desc_t DISABLE_DL_ENCRYPT[] = { + {EFUSE_BLK0, 199, 1}, // [] Disable flash encryption in UART bootloader, +}; + +static const esp_efuse_desc_t DISABLE_DL_DECRYPT[] = { + {EFUSE_BLK0, 200, 1}, // [] Disable flash decryption in UART bootloader, +}; + +static const esp_efuse_desc_t DISABLE_DL_CACHE[] = { + {EFUSE_BLK0, 201, 1}, // [] Disable flash cache in UART bootloader, +}; + +static const esp_efuse_desc_t KEY_STATUS[] = { + {EFUSE_BLK0, 202, 1}, // [] Usage of efuse block 3 (reserved), +}; + +static const esp_efuse_desc_t BLOCK1[] = { + {EFUSE_BLK1, 0, MAX_BLK_LEN}, // [ENCRYPT_FLASH_KEY] Flash encryption key, +}; + +static const esp_efuse_desc_t BLOCK2[] = { + {EFUSE_BLK2, 0, MAX_BLK_LEN}, // [SECURE_BOOT_KEY] Security boot key, +}; + +static const esp_efuse_desc_t CUSTOM_MAC_CRC[] = { + {EFUSE_BLK3, 0, 8}, // [MAC_CUSTOM_CRC] CRC8 for custom MAC address, +}; + +static const esp_efuse_desc_t MAC_CUSTOM[] = { + {EFUSE_BLK3, 8, 48}, // [MAC_CUSTOM] Custom MAC address, }; static const esp_efuse_desc_t ADC1_TP_LOW[] = { - {EFUSE_BLK3, 96, 7}, // TP_REG EFUSE_RD_ADC1_TP_LOW, -}; - -static const esp_efuse_desc_t ADC2_TP_LOW[] = { - {EFUSE_BLK3, 112, 7}, // TP_REG EFUSE_RD_ADC2_TP_LOW, + {EFUSE_BLK3, 96, 7}, // [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, }; static const esp_efuse_desc_t ADC1_TP_HIGH[] = { - {EFUSE_BLK3, 103, 9}, // TP_REG EFUSE_RD_ADC1_TP_HIGH, + {EFUSE_BLK3, 103, 9}, // [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, +}; + +static const esp_efuse_desc_t ADC2_TP_LOW[] = { + {EFUSE_BLK3, 112, 7}, // [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, }; static const esp_efuse_desc_t ADC2_TP_HIGH[] = { - {EFUSE_BLK3, 119, 9}, // TP_REG EFUSE_RD_ADC2_TP_HIGH, + {EFUSE_BLK3, 119, 9}, // [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK3, 128, 32}, // Secure version for anti-rollback, + {EFUSE_BLK3, 128, 32}, // [] Secure version for anti-rollback, +}; + +static const esp_efuse_desc_t MAC_VERSION[] = { + {EFUSE_BLK3, 184, 8}, // [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"}, }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[] = { - &MAC_FACTORY_CRC[0], // CRC8 for factory MAC address - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[] = { - &MAC_CUSTOM_CRC[0], // CRC8 for custom MAC address. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[] = { - &MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[] = { - &MAC_CUSTOM_VER[0], // Custom MAC version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[] = { - &SECURE_BOOT_KEY[0], // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[] = { - &ABS_DONE_0[0], // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[] = { - &ABS_DONE_1[0], // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[] = { - &ENCRYPT_FLASH_KEY[0], // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[] = { - &ENCRYPT_CONFIG[0], // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[] = { - &DISABLE_DL_ENCRYPT[0], // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[] = { - &DISABLE_DL_DECRYPT[0], // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[] = { - &DISABLE_DL_CACHE[0], // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[] = { - &FLASH_CRYPT_CNT[0], // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[] = { - &DISABLE_JTAG[0], // Disable JTAG. EFUSE_RD_DISABLE_JTAG. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = { - &CONSOLE_DEBUG_DISABLE[0], // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[] = { - &UART_DOWNLOAD_DIS[0], // Disable UART download mode. Valid for ESP32 V3 and newer - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { &WR_DIS[0], // [] Efuse write disable mask NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[] = { - &WR_DIS_EFUSE_RD_DISABLE[0], // Write protection for EFUSE_RD_DISABLE +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WR_DIS[] = { + &WR_DIS_WR_DIS[0], // [] wr_dis of WR_DIS NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] = { - &WR_DIS_FLASH_CRYPT_CNT[0], // Flash encrypt. Write protection FLASH_CRYPT_CNT + &WR_DIS_FLASH_CRYPT_CNT[0], // [] wr_dis of FLASH_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_DOWNLOAD_DIS[] = { + &WR_DIS_UART_DOWNLOAD_DIS[0], // [] wr_dis of UART_DOWNLOAD_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_CRC[] = { + &WR_DIS_MAC_CRC[0], // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_APP_CPU[] = { + &WR_DIS_DISABLE_APP_CPU[0], // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BT[] = { + &WR_DIS_DISABLE_BT[0], // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[] = { - &WR_DIS_DIS_CACHE[0], // [] wr_dis of DIS_CACHE + &WR_DIS_DIS_CACHE[0], // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VOL_LEVEL_HP_INV[] = { + &WR_DIS_VOL_LEVEL_HP_INV[0], // [] wr_dis of VOL_LEVEL_HP_INV NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[] = { - &WR_DIS_BLK2[0], // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CLK8M_FREQ[] = { + &WR_DIS_CLK8M_FREQ[0], // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[] = { - &WR_DIS_BLK3[0], // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_VREF[] = { + &WR_DIS_ADC_VREF[0], // [] wr_dis of ADC_VREF NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[] = { - &RD_DIS_BLK1[0], // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_REG[] = { + &WR_DIS_XPD_SDIO_REG[0], // [] wr_dis of XPD_SDIO_REG NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[] = { - &RD_DIS_BLK2[0], // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH[] = { + &WR_DIS_XPD_SDIO_TIEH[0], // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[] = { - &RD_DIS_BLK3[0], // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE[] = { + &WR_DIS_XPD_SDIO_FORCE[0], // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] = { - &CHIP_VER_DIS_APP_CPU[0], // EFUSE_RD_CHIP_VER_DIS_APP_CPU +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[] = { + &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK NULL }; -const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[] = { - &CHIP_VER_DIS_BT[0], // EFUSE_RD_CHIP_VER_DIS_BT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[] = { + &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q NULL }; -const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[] = { - &CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG least significant bits - &CHIP_VER_PKG[1], // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[] = { + &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS0[] = { + &WR_DIS_SPI_PAD_CONFIG_CS0[0], // [] wr_dis of SPI_PAD_CONFIG_CS0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK1[] = { + &WR_DIS_BLOCK1[0], // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK2[] = { + &WR_DIS_BLOCK2[0], // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK3[] = { + &WR_DIS_BLOCK3[0], // [WR_DIS.BLK3] wr_dis of BLOCK3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC[] = { + &WR_DIS_CUSTOM_MAC_CRC[0], // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_LOW[] = { + &WR_DIS_ADC1_TP_LOW[0], // [] wr_dis of ADC1_TP_LOW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_HIGH[] = { + &WR_DIS_ADC1_TP_HIGH[0], // [] wr_dis of ADC1_TP_HIGH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_LOW[] = { + &WR_DIS_ADC2_TP_LOW[0], // [] wr_dis of ADC2_TP_LOW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_HIGH[] = { + &WR_DIS_ADC2_TP_HIGH[0], // [] wr_dis of ADC2_TP_HIGH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_VERSION[] = { + &WR_DIS_MAC_VERSION[0], // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3_PART_RESERVE[] = { + &WR_DIS_BLK3_PART_RESERVE[0], // [] wr_dis of BLK3_PART_RESERVE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG[] = { + &WR_DIS_FLASH_CRYPT_CONFIG[0], // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CODING_SCHEME[] = { + &WR_DIS_CODING_SCHEME[0], // [] wr_dis of CODING_SCHEME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_STATUS[] = { + &WR_DIS_KEY_STATUS[0], // [] wr_dis of KEY_STATUS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_0[] = { + &WR_DIS_ABS_DONE_0[0], // [] wr_dis of ABS_DONE_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_1[] = { + &WR_DIS_ABS_DONE_1[0], // [] wr_dis of ABS_DONE_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_DISABLE[] = { + &WR_DIS_JTAG_DISABLE[0], // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CONSOLE_DEBUG_DISABLE[] = { + &WR_DIS_CONSOLE_DEBUG_DISABLE[0], // [] wr_dis of CONSOLE_DEBUG_DISABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_ENCRYPT[] = { + &WR_DIS_DISABLE_DL_ENCRYPT[0], // [] wr_dis of DISABLE_DL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_DECRYPT[] = { + &WR_DIS_DISABLE_DL_DECRYPT[0], // [] wr_dis of DISABLE_DL_DECRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_CACHE[] = { + &WR_DIS_DISABLE_DL_CACHE[0], // [] wr_dis of DISABLE_DL_CACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // [] Disable reading from BlOCK1-3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK1[] = { + &RD_DIS_BLOCK1[0], // [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK2[] = { + &RD_DIS_BLOCK2[0], // [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK3[] = { + &RD_DIS_BLOCK3[0], // [RD_DIS.BLK3] rd_dis of BLOCK3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC[] = { + &RD_DIS_CUSTOM_MAC_CRC[0], // [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC[] = { + &RD_DIS_CUSTOM_MAC[0], // [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_LOW[] = { + &RD_DIS_ADC1_TP_LOW[0], // [] rd_dis of ADC1_TP_LOW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_HIGH[] = { + &RD_DIS_ADC1_TP_HIGH[0], // [] rd_dis of ADC1_TP_HIGH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_LOW[] = { + &RD_DIS_ADC2_TP_LOW[0], // [] rd_dis of ADC2_TP_LOW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_HIGH[] = { + &RD_DIS_ADC2_TP_HIGH[0], // [] rd_dis of ADC2_TP_HIGH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SECURE_VERSION[] = { + &RD_DIS_SECURE_VERSION[0], // [] rd_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_MAC_VERSION[] = { + &RD_DIS_MAC_VERSION[0], // [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3_PART_RESERVE[] = { + &RD_DIS_BLK3_PART_RESERVE[0], // [] rd_dis of BLK3_PART_RESERVE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG[] = { + &RD_DIS_FLASH_CRYPT_CONFIG[0], // [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CODING_SCHEME[] = { + &RD_DIS_CODING_SCHEME[0], // [] rd_dis of CODING_SCHEME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY_STATUS[] = { + &RD_DIS_KEY_STATUS[0], // [] rd_dis of KEY_STATUS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[] = { + &FLASH_CRYPT_CNT[0], // [] Flash encryption is enabled if this field has an odd number of bits set + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[] = { + &UART_DOWNLOAD_DIS[0], // [] Disable UART download mode. Valid for ESP32 V3 and newer; only + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_CRC[] = { + &MAC_CRC[0], // [MAC_FACTORY_CRC] CRC8 for MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_APP_CPU[] = { + &DISABLE_APP_CPU[0], // [CHIP_VER_DIS_APP_CPU] Disables APP CPU + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BT[] = { + &DISABLE_BT[0], // [CHIP_VER_DIS_BT] Disables Bluetooth + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE_4BIT[] = { + &CHIP_PACKAGE_4BIT[0], // [CHIP_VER_PKG_4BIT] Chip package identifier #4bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_CACHE[] = { + &DIS_CACHE[0], // [CHIP_VER_DIS_CACHE] Disables cache + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[] = { + &SPI_PAD_CONFIG_HD[0], // [] read for SPI_pad_config_hd + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE[] = { + &CHIP_PACKAGE[0], // [CHIP_VER_PKG] Chip package identifier NULL }; const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[] = { - &CHIP_CPU_FREQ_LOW[0], // EFUSE_RD_CHIP_CPU_FREQ_LOW + &CHIP_CPU_FREQ_LOW[0], // [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise NULL }; const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[] = { - &CHIP_CPU_FREQ_RATED[0], // EFUSE_RD_CHIP_CPU_FREQ_RATED + &CHIP_CPU_FREQ_RATED[0], // [] If set; the ESP32's maximum CPU frequency has been rated + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK3_PART_RESERVE[] = { + &BLK3_PART_RESERVE[0], // [] BLOCK3 partially served for ADC calibration data NULL }; const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[] = { - &CHIP_VER_REV1[0], // EFUSE_RD_CHIP_VER_REV1 + &CHIP_VER_REV1[0], // [] bit is set to 1 for rev1 silicon NULL }; -const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = { - &CHIP_VER_REV2[0], // EFUSE_RD_CHIP_VER_REV2 +const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[] = { + &CLK8M_FREQ[0], // [CK8M_FREQ] 8MHz clock freq override NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR +const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF[] = { + &ADC_VREF[0], // [] True ADC reference voltage NULL }; const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = { - &XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG + &XPD_SDIO_REG[0], // [] read for XPD_SDIO_REG NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[] = { - &SDIO_TIEH[0], // EFUSE_RD_SDIO_TIEH +const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_TIEH[] = { + &XPD_SDIO_TIEH[0], // [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[] = { - &SDIO_FORCE[0], // EFUSE_RD_SDIO_FORCE +const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_FORCE[] = { + &XPD_SDIO_FORCE[0], // [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] = { - &ADC_VREF_AND_SDIO_DREF[0], // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1] +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { + &SPI_PAD_CONFIG_CLK[0], // [] Override SD_CLK pad (GPIO6/SPICLK) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[] = { + &SPI_PAD_CONFIG_Q[0], // [] Override SD_DATA_0 pad (GPIO7/SPIQ) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[] = { + &SPI_PAD_CONFIG_D[0], // [] Override SD_DATA_1 pad (GPIO8/SPID) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS0[] = { + &SPI_PAD_CONFIG_CS0[0], // [] Override SD_CMD pad (GPIO11/SPICS0) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = { + &CHIP_VER_REV2[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VOL_LEVEL_HP_INV[] = { + &VOL_LEVEL_HP_INV[0], // [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CONFIG[] = { + &FLASH_CRYPT_CONFIG[0], // [ENCRYPT_CONFIG] Flash encryption config (key tweak bits) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CODING_SCHEME[] = { + &CODING_SCHEME[0], // [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = { + &CONSOLE_DEBUG_DISABLE[0], // [] Disable ROM BASIC interpreter fallback + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_SDIO_HOST[] = { + &DISABLE_SDIO_HOST[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[] = { + &ABS_DONE_0[0], // [] Secure boot V1 is enabled for bootloader image + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[] = { + &ABS_DONE_1[0], // [] Secure boot V2 is enabled for bootloader image + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_DISABLE[] = { + &JTAG_DISABLE[0], // [DISABLE_JTAG] Disable JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[] = { + &DISABLE_DL_ENCRYPT[0], // [] Disable flash encryption in UART bootloader + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[] = { + &DISABLE_DL_DECRYPT[0], // [] Disable flash decryption in UART bootloader + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[] = { + &DISABLE_DL_CACHE[0], // [] Disable flash cache in UART bootloader + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_STATUS[] = { + &KEY_STATUS[0], // [] Usage of efuse block 3 (reserved) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLOCK1[] = { + &BLOCK1[0], // [ENCRYPT_FLASH_KEY] Flash encryption key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLOCK2[] = { + &BLOCK2[0], // [SECURE_BOOT_KEY] Security boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_CRC[] = { + &CUSTOM_MAC_CRC[0], // [MAC_CUSTOM_CRC] CRC8 for custom MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[] = { + &MAC_CUSTOM[0], // [MAC_CUSTOM] Custom MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[] = { - &ADC1_TP_LOW[0], // TP_REG EFUSE_RD_ADC1_TP_LOW - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[] = { - &ADC2_TP_LOW[0], // TP_REG EFUSE_RD_ADC2_TP_LOW + &ADC1_TP_LOW[0], // [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[] = { - &ADC1_TP_HIGH[0], // TP_REG EFUSE_RD_ADC1_TP_HIGH + &ADC1_TP_HIGH[0], // [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[] = { + &ADC2_TP_LOW[0], // [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[] = { - &ADC2_TP_HIGH[0], // TP_REG EFUSE_RD_ADC2_TP_HIGH + &ADC2_TP_HIGH[0], // [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version for anti-rollback + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_VERSION[] = { + &MAC_VERSION[0], // [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"} NULL }; diff --git a/components/efuse/esp32/esp_efuse_table.csv b/components/efuse/esp32/esp_efuse_table.csv index 95ed0a0113..d02ffb8886 100644 --- a/components/efuse/esp32/esp_efuse_table.csv +++ b/components/efuse/esp32/esp_efuse_table.csv @@ -1,95 +1,123 @@ + # field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..-) | # -# | EFUSE_BLK1 | |MAX_BLK_LEN*| # -# | EFUSE_BLK2 | | | # -# | EFUSE_BLK3) | | | # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # ########################################################################## -# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" +# After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# Factory MAC address # -####################### -MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0] -, EFUSE_BLK0, 64, 8, Factory MAC addr [1] -, EFUSE_BLK0, 56, 8, Factory MAC addr [2] -, EFUSE_BLK0, 48, 8, Factory MAC addr [3] -, EFUSE_BLK0, 40, 8, Factory MAC addr [4] -, EFUSE_BLK0, 32, 8, Factory MAC addr [5] -MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address +# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4 -# Custom MAC address # -###################### -MAC_CUSTOM_CRC, EFUSE_BLK3, 0, 8, CRC8 for custom MAC address. -MAC_CUSTOM, EFUSE_BLK3, 8, 48, Custom MAC -MAC_CUSTOM_VER, EFUSE_BLK3, 184, 8, Custom MAC version - -# Security boot # -################# -SECURE_BOOT_KEY, EFUSE_BLK2, 0, MAX_BLK_LEN, Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) -ABS_DONE_0, EFUSE_BLK0, 196, 1, Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0 -ABS_DONE_1, EFUSE_BLK0, 197, 1, Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1 - -# Flash encrypt # -################# -ENCRYPT_FLASH_KEY, EFUSE_BLK1, 0, MAX_BLK_LEN, Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) -ENCRYPT_CONFIG, EFUSE_BLK0, 188, 4, Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M - -DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT. -DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT. -DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE. -FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT. - -# Misc Security # -DISABLE_JTAG, EFUSE_BLK0, 198, 1, Disable JTAG. EFUSE_RD_DISABLE_JTAG. -CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE. -UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, Disable UART download mode. Valid for ESP32 V3 and newer, only. - -# Write protection # -#################### -WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask -WR_DIS.EFUSE_RD_DISABLE,EFUSE_BLK0, 0, 1, Write protection for EFUSE_RD_DISABLE -WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, Flash encrypt. Write protection FLASH_CRYPT_CNT, UART_DOWNLOAD_DIS. EFUSE_WR_DIS_FLASH_CRYPT_CNT -WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_CACHE -WR_DIS.BLK1, EFUSE_BLK0, 7, 1, Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1 -WR_DIS.BLK2, EFUSE_BLK0, 8, 1, Security boot. Write protection security key. EFUSE_WR_DIS_BLK2 -WR_DIS.BLK3, EFUSE_BLK0, 9, 1, Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3 - -# Read protection # -################### -RD_DIS_BLK1, EFUSE_BLK0, 16, 1, Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1 -RD_DIS_BLK2, EFUSE_BLK0, 17, 1, Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2 -RD_DIS_BLK3, EFUSE_BLK0, 18, 1, Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3 - -# Chip info # -############# -CHIP_VER_DIS_APP_CPU, EFUSE_BLK0, 96, 1, EFUSE_RD_CHIP_VER_DIS_APP_CPU -CHIP_VER_DIS_BT, EFUSE_BLK0, 97, 1, EFUSE_RD_CHIP_VER_DIS_BT -CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG least significant bits -, EFUSE_BLK0, 98, 1, EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit -CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW -CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED -CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1 -CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2 -WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, WAFER_VERSION_MINOR -XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG -SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH -SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE - -#SDIO_DREFH, EFUSE_BLK0, 136, 2, EFUSE_RD_SDIO_DREFH -#SDIO_DREFM, EFUSE_BLK0, 138, 2, EFUSE_RD_SDIO_DREFM -#SDIO_DREFL, EFUSE_BLK0, 140, 2, EFUSE_RD_SDIO_DREFL - -# esp_adc_cal # -############### -ADC_VREF_AND_SDIO_DREF, EFUSE_BLK0, 136, 6, EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1], SDIO_DREFM[2 3], SDIO_DREFL[4 5] ) -ADC1_TP_LOW, EFUSE_BLK3, 96, 7, TP_REG EFUSE_RD_ADC1_TP_LOW -ADC2_TP_LOW, EFUSE_BLK3, 112, 7, TP_REG EFUSE_RD_ADC2_TP_LOW -ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, TP_REG EFUSE_RD_ADC1_TP_HIGH -ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, TP_REG EFUSE_RD_ADC2_TP_HIGH - -# anti-rollback # -################# -SECURE_VERSION, EFUSE_BLK3, 128, 32, Secure version for anti-rollback +WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS +WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS +WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT +WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_DIS +WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC +WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU +WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT +WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE +WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV +WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ +WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF +WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG +WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH +WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE +WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CLK +WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q +WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D +WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CS0 +WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1 +WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2 +WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOCK3 +WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW +WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH +WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW +WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION +WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION +WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESERVE +WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG +WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME +WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS +WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0 +WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1 +WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE +WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_DISABLE +WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCRYPT +WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECRYPT +WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE +RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOCK1-3 +RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1 +RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2 +RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOCK3 +RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC +RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC +RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW +RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH +RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW +RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH +RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION +RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION +RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESERVE +RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG +RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME +RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS +FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabled if this field has an odd number of bits set +UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only +MAC, EFUSE_BLK0, 72, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK0, 64, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK0, 56, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK0, 48, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK0, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK0, 32, 8, [MAC_FACTORY] MAC address +MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for MAC address +DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU +DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables Bluetooth +CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit +DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disables cache +SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd +CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package identifier +CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise +CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maximum CPU frequency has been rated +BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served for ADC calibration data +CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 silicon +CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq override +ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage +XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG +XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"} +XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset +SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO6/SPICLK) +SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (GPIO7/SPIQ) +SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (GPIO8/SPID) +SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO11/SPICS0) +CHIP_VER_REV2, EFUSE_BLK0, 180, 1, [] +VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) +WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, [] +FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits) +CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"} +CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpreter fallback +DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, [] +ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled for bootloader image +ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled for bootloader image +JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG +DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption in UART bootloader +DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption in UART bootloader +DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UART bootloader +KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (reserved) +BLOCK1, EFUSE_BLK1, 0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key +BLOCK2, EFUSE_BLK2, 0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key +CUSTOM_MAC_CRC, EFUSE_BLK3, 0, 8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address +MAC_CUSTOM, EFUSE_BLK3, 8, 48, [MAC_CUSTOM] Custom MAC address +ADC1_TP_LOW, EFUSE_BLK3, 96, 7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE +ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE +ADC2_TP_LOW, EFUSE_BLK3, 112, 7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE +ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE +SECURE_VERSION, EFUSE_BLK3, 128, 32, [] Secure version for anti-rollback +MAC_VERSION, EFUSE_BLK3, 184, 8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"} diff --git a/components/efuse/esp32/include/esp_efuse_table.h b/components/efuse/esp32/include/esp_efuse_table.h index 2433d4b87a..89e51532bf 100644 --- a/components/efuse/esp32/include/esp_efuse_table.h +++ b/components/efuse/esp32/include/esp_efuse_table.h @@ -10,57 +10,163 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table c5ac3aa2d3a97d98ced4f4fccf48c328 +// md5_digest_table 2e197b7b14eec62fa5bdf94c6d71e87a // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +#define ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE ESP_EFUSE_WR_DIS_RD_DIS +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_DOWNLOAD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_CRC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY_CRC ESP_EFUSE_WR_DIS_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_APP_CPU[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_APP_CPU ESP_EFUSE_WR_DIS_DISABLE_APP_CPU +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BT[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_BT ESP_EFUSE_WR_DIS_DISABLE_BT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[]; +#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_CACHE ESP_EFUSE_WR_DIS_DIS_CACHE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VOL_LEVEL_HP_INV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CLK8M_FREQ[]; +#define ESP_EFUSE_WR_DIS_CK8M_FREQ ESP_EFUSE_WR_DIS_CLK8M_FREQ +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_VREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_REG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH[]; +#define ESP_EFUSE_WR_DIS_SDIO_TIEH ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE[]; +#define ESP_EFUSE_WR_DIS_SDIO_FORCE ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK1[]; +#define ESP_EFUSE_WR_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_WR_DIS_BLOCK1 +#define ESP_EFUSE_WR_DIS_BLK1 ESP_EFUSE_WR_DIS_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK2[]; +#define ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY ESP_EFUSE_WR_DIS_BLOCK2 +#define ESP_EFUSE_WR_DIS_BLK2 ESP_EFUSE_WR_DIS_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK3[]; +#define ESP_EFUSE_WR_DIS_BLK3 ESP_EFUSE_WR_DIS_BLOCK3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_CRC ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_VERSION[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_VER ESP_EFUSE_WR_DIS_MAC_VERSION +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3_PART_RESERVE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_WR_DIS_ENCRYPT_CONFIG ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_STATUS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_DISABLE[]; +#define ESP_EFUSE_WR_DIS_DISABLE_JTAG ESP_EFUSE_WR_DIS_JTAG_DISABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CONSOLE_DEBUG_DISABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_DECRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_CACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK1[]; +#define ESP_EFUSE_RD_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_RD_DIS_BLOCK1 +#define ESP_EFUSE_RD_DIS_BLK1 ESP_EFUSE_RD_DIS_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK2[]; +#define ESP_EFUSE_RD_DIS_SECURE_BOOT_KEY ESP_EFUSE_RD_DIS_BLOCK2 +#define ESP_EFUSE_RD_DIS_BLK2 ESP_EFUSE_RD_DIS_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK3[]; +#define ESP_EFUSE_RD_DIS_BLK3 ESP_EFUSE_RD_DIS_BLOCK3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_CRC ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM ESP_EFUSE_RD_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_MAC_VERSION[]; +#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_VER ESP_EFUSE_RD_DIS_MAC_VERSION +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3_PART_RESERVE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_RD_DIS_ENCRYPT_CONFIG ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY_STATUS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CRC[]; +#define ESP_EFUSE_MAC_FACTORY_CRC ESP_EFUSE_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_APP_CPU[]; +#define ESP_EFUSE_CHIP_VER_DIS_APP_CPU ESP_EFUSE_DISABLE_APP_CPU +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BT[]; +#define ESP_EFUSE_CHIP_VER_DIS_BT ESP_EFUSE_DISABLE_BT +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE_4BIT[]; +#define ESP_EFUSE_CHIP_VER_PKG_4BIT ESP_EFUSE_CHIP_PACKAGE_4BIT +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CACHE[]; +#define ESP_EFUSE_CHIP_VER_DIS_CACHE ESP_EFUSE_DIS_CACHE +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE[]; +#define ESP_EFUSE_CHIP_VER_PKG ESP_EFUSE_CHIP_PACKAGE +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK3_PART_RESERVE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[]; +#define ESP_EFUSE_CK8M_FREQ ESP_EFUSE_CLK8M_FREQ +extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_TIEH[]; +#define ESP_EFUSE_SDIO_TIEH ESP_EFUSE_XPD_SDIO_TIEH +extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_FORCE[]; +#define ESP_EFUSE_SDIO_FORCE ESP_EFUSE_XPD_SDIO_FORCE +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VOL_LEVEL_HP_INV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CONFIG[]; +#define ESP_EFUSE_ENCRYPT_CONFIG ESP_EFUSE_FLASH_CRYPT_CONFIG +extern const esp_efuse_desc_t* ESP_EFUSE_CODING_SCHEME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_SDIO_HOST[]; extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[]; extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_DISABLE[]; +#define ESP_EFUSE_DISABLE_JTAG ESP_EFUSE_JTAG_DISABLE extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_STATUS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1[]; +#define ESP_EFUSE_ENCRYPT_FLASH_KEY ESP_EFUSE_BLOCK1 +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2[]; +#define ESP_EFUSE_SECURE_BOOT_KEY ESP_EFUSE_BLOCK2 +extern const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_CRC[]; +#define ESP_EFUSE_MAC_CUSTOM_CRC ESP_EFUSE_CUSTOM_MAC_CRC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_VERSION[]; +#define ESP_EFUSE_MAC_CUSTOM_VER ESP_EFUSE_MAC_VERSION #ifdef __cplusplus } diff --git a/components/efuse/esp32c2/esp_efuse_table.c b/components/efuse/esp32c2/esp_efuse_table.c index a518074239..2ede33886d 100644 --- a/components/efuse/esp32c2/esp_efuse_table.c +++ b/components/efuse/esp32c2/esp_efuse_table.c @@ -9,251 +9,391 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 2216d0ff3e0f4e8803f85711b5cc2829 +// md5_digest_table 439495cbc35dc68d7566e05ac3dbb248 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 8}, // Write protection, + {EFUSE_BLK0, 0, 8}, // [] Disable programming of individual eFuses, }; static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS, + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 1, 1}, // Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE, +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of WDT_DELAY_SEL, }; -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN, +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN, + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW, +static const esp_efuse_desc_t WR_DIS_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of XTS_KEY_LENGTH_256, }; -static const esp_efuse_desc_t WR_DIS_BLK0_RESERVED[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for BLK0_RESERVED, +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SECURE_BOOT_EN, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for EFUSE_BLK1. SYS_DATA_PART0, +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of UART_PRINT_CONTROL, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART2, +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of FORCE_SEND_RESUME, }; -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for EFUSE_BLK3. whole KEY0, +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC_USED[] = { + {EFUSE_BLK0, 4, 1}, // [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 5, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 6, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of OCODE, +}; + +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of TEMP_CALIB, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_DBIAS_HVT[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of DIG_DBIAS_HVT, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_LDO_SLP_DBIAS2[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of DIG_LDO_SLP_DBIAS2, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_LDO_SLP_DBIAS26[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of DIG_LDO_SLP_DBIAS26, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_LDO_ACT_DBIAS26[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of DIG_LDO_ACT_DBIAS26, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_LDO_ACT_STEPD10[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of DIG_LDO_ACT_STEPD10, +}; + +static const esp_efuse_desc_t WR_DIS_RTC_LDO_SLP_DBIAS13[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of RTC_LDO_SLP_DBIAS13, +}; + +static const esp_efuse_desc_t WR_DIS_RTC_LDO_SLP_DBIAS29[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of RTC_LDO_SLP_DBIAS29, +}; + +static const esp_efuse_desc_t WR_DIS_RTC_LDO_SLP_DBIAS31[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of RTC_LDO_SLP_DBIAS31, +}; + +static const esp_efuse_desc_t WR_DIS_RTC_LDO_ACT_DBIAS31[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of RTC_LDO_ACT_DBIAS31, +}; + +static const esp_efuse_desc_t WR_DIS_RTC_LDO_ACT_DBIAS13[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of RTC_LDO_ACT_DBIAS13, +}; + +static const esp_efuse_desc_t WR_DIS_ADC_CALIBRATION_3[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of ADC_CALIBRATION_3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 7, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 2}, // Read protection, + {EFUSE_BLK0, 32, 2}, // [] Disable reading from BlOCK3, }; static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 2}, // Read protection for EFUSE_BLK3. KEY0, + {EFUSE_BLK0, 32, 2}, // [] Read protection for EFUSE_BLK3. KEY0, }; static const esp_efuse_desc_t RD_DIS_KEY0_LOW[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK3. KEY0 lower 128-bit key, + {EFUSE_BLK0, 32, 1}, // [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key, }; static const esp_efuse_desc_t RD_DIS_KEY0_HI[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK3. KEY0 higher 128-bit key, + {EFUSE_BLK0, 33, 1}, // [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 34, 2}, // RTC WDT timeout threshold, + {EFUSE_BLK0, 34, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 36, 1}, // Hardware Disable JTAG permanently, + {EFUSE_BLK0, 36, 1}, // [] Set this bit to disable pad jtag, }; static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 37, 1}, // Disable ICache in Download mode, + {EFUSE_BLK0, 37, 1}, // [] The bit be set to disable icache in download mode, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 38, 1}, // Disable flash encryption in Download boot mode, + {EFUSE_BLK0, 38, 1}, // [] The bit be set to disable manual encryption, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 39, 3}, // Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable, + {EFUSE_BLK0, 39, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t XTS_KEY_LENGTH_256[] = { - {EFUSE_BLK0, 42, 1}, // Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3, + {EFUSE_BLK0, 42, 1}, // [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"}, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 43, 2}, // Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled, + {EFUSE_BLK0, 43, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 45, 1}, // Force ROM code to send an SPI flash resume command during SPI boot, + {EFUSE_BLK0, 45, 1}, // [] Set this bit to force ROM code to send a resume command during SPI boot, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 46, 1}, // Disable all download boot modes, + {EFUSE_BLK0, 46, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7), }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 47, 1}, // Disable direct_boot mode, + {EFUSE_BLK0, 47, 1}, // [] This bit set means disable direct_boot mode, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 48, 1}, // Enable secure UART download mode, + {EFUSE_BLK0, 48, 1}, // [] Set this bit to enable secure UART download mode, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 49, 4}, // Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms, + {EFUSE_BLK0, 49, 4}, // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 53, 1}, // Enable secure boot, + {EFUSE_BLK0, 53, 1}, // [] The bit be set to enable secure boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 54, 4}, // Secure version for anti-rollback, + {EFUSE_BLK0, 54, 4}, // [] Secure version for anti-rollback, }; -static const esp_efuse_desc_t ENABLE_CUSTOM_MAC[] = { - {EFUSE_BLK0, 58, 1}, // True if MAC_CUSTOM is burned, +static const esp_efuse_desc_t CUSTOM_MAC_USED[] = { + {EFUSE_BLK0, 58, 1}, // [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 59, 1}, // Disables check of wafer version major, + {EFUSE_BLK0, 59, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 60, 1}, // Disables check of blk version major, + {EFUSE_BLK0, 60, 1}, // [] Disables check of blk version major, }; static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK1, 0, 88}, // User data block, + {EFUSE_BLK1, 0, 88}, // [] User data block, }; static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK1, 0, 48}, // Custom MAC addr, + {EFUSE_BLK1, 0, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC address, }; -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK2, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK2, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK2, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK2, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK2, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK2, 0, 8}, // Factory MAC addr [5], +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK2, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK2, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK2, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK2, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK2, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK2, 0, 8}, // [MAC_FACTORY] MAC address, }; static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK2, 48, 4}, // WAFER_VERSION_MINOR, + {EFUSE_BLK2, 48, 4}, // [] WAFER_VERSION_MINOR, }; static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK2, 52, 2}, // WAFER_VERSION_MAJOR, + {EFUSE_BLK2, 52, 2}, // [] WAFER_VERSION_MAJOR, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK2, 54, 3}, // EFUSE_PKG_VERSION, + {EFUSE_BLK2, 54, 3}, // [] EFUSE_PKG_VERSION, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK2, 57, 3}, // BLK_VERSION_MINOR, + {EFUSE_BLK2, 57, 3}, // [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"}, }; static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 60, 2}, // BLK_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK3, 0, 256}, // [256bit FE key] or [128bit FE key and 128key SB key] or [user data], -}; - -static const esp_efuse_desc_t KEY0_FE_256BIT[] = { - {EFUSE_BLK3, 0, 256}, // [256bit FE key], -}; - -static const esp_efuse_desc_t KEY0_FE_128BIT[] = { - {EFUSE_BLK3, 0, 128}, // [128bit FE key], -}; - -static const esp_efuse_desc_t KEY0_SB_128BIT[] = { - {EFUSE_BLK3, 128, 128}, // [128bit SB key], + {EFUSE_BLK2, 60, 2}, // [] Major version of BLOCK2, }; static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 62, 7}, // OCode, + {EFUSE_BLK2, 62, 7}, // [] OCode, }; static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 69, 9}, // Temperature calibration data, + {EFUSE_BLK2, 69, 9}, // [] Temperature calibration data, }; static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 78, 8}, // ADC1 init code at atten0, + {EFUSE_BLK2, 78, 8}, // [] ADC1 init code at atten0, }; static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 86, 5}, // ADC1 init code at atten3, + {EFUSE_BLK2, 86, 5}, // [] ADC1 init code at atten3, }; static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 91, 8}, // ADC1 calibration voltage at atten0, + {EFUSE_BLK2, 91, 8}, // [] ADC1 calibration voltage at atten0, }; static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 99, 6}, // ADC1 calibration voltage at atten3, + {EFUSE_BLK2, 99, 6}, // [] ADC1 calibration voltage at atten3, }; static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { - {EFUSE_BLK2, 105, 5}, // BLOCK2 digital dbias when hvt, + {EFUSE_BLK2, 105, 5}, // [] BLOCK2 digital dbias when hvt, }; static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS2[] = { - {EFUSE_BLK2, 110, 7}, // BLOCK2 DIG_LDO_DBG0_DBIAS2, + {EFUSE_BLK2, 110, 7}, // [] BLOCK2 DIG_LDO_DBG0_DBIAS2, }; static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS26[] = { - {EFUSE_BLK2, 117, 8}, // BLOCK2 DIG_LDO_DBG0_DBIAS26, + {EFUSE_BLK2, 117, 8}, // [] BLOCK2 DIG_LDO_DBG0_DBIAS26, }; static const esp_efuse_desc_t DIG_LDO_ACT_DBIAS26[] = { - {EFUSE_BLK2, 125, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS26, + {EFUSE_BLK2, 125, 6}, // [] BLOCK2 DIG_LDO_ACT_DBIAS26, }; static const esp_efuse_desc_t DIG_LDO_ACT_STEPD10[] = { - {EFUSE_BLK2, 131, 4}, // BLOCK2 DIG_LDO_ACT_STEPD10, + {EFUSE_BLK2, 131, 4}, // [] BLOCK2 DIG_LDO_ACT_STEPD10, }; static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS13[] = { - {EFUSE_BLK2, 135, 7}, // BLOCK2 DIG_LDO_SLP_DBIAS13, + {EFUSE_BLK2, 135, 7}, // [] BLOCK2 DIG_LDO_SLP_DBIAS13, }; static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS29[] = { - {EFUSE_BLK2, 142, 9}, // BLOCK2 DIG_LDO_SLP_DBIAS29, + {EFUSE_BLK2, 142, 9}, // [] BLOCK2 DIG_LDO_SLP_DBIAS29, }; static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS31[] = { - {EFUSE_BLK2, 151, 6}, // BLOCK2 DIG_LDO_SLP_DBIAS31, + {EFUSE_BLK2, 151, 6}, // [] BLOCK2 DIG_LDO_SLP_DBIAS31, }; static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS31[] = { - {EFUSE_BLK2, 157, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS31, + {EFUSE_BLK2, 157, 6}, // [] BLOCK2 DIG_LDO_ACT_DBIAS31, }; static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS13[] = { - {EFUSE_BLK2, 163, 8}, // BLOCK2 DIG_LDO_ACT_DBIAS13, + {EFUSE_BLK2, 163, 8}, // [] BLOCK2 DIG_LDO_ACT_DBIAS13, +}; + +static const esp_efuse_desc_t ADC_CALIBRATION_3[] = { + {EFUSE_BLK2, 192, 11}, // [] Store the bit [86:96] of ADC calibration data, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption, +}; + +static const esp_efuse_desc_t KEY0_FE_256BIT[] = { + {EFUSE_BLK3, 0, 256}, // [] 256bit FE key, +}; + +static const esp_efuse_desc_t KEY0_FE_128BIT[] = { + {EFUSE_BLK3, 0, 128}, // [] 128bit FE key, +}; + +static const esp_efuse_desc_t KEY0_SB_128BIT[] = { + {EFUSE_BLK3, 128, 128}, // [] 128bit SB key, }; @@ -261,301 +401,476 @@ static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS13[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection + &WR_DIS[0], // [] Disable programming of individual eFuses NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[] = { + &WR_DIS_XTS_KEY_LENGTH_256[0], // [] wr_dis of XTS_KEY_LENGTH_256 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK0_RESERVED[] = { - &WR_DIS_BLK0_RESERVED[0], // Write protection for BLK0_RESERVED +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART0[] = { - &WR_DIS_SYS_DATA_PART0[0], // Write protection for EFUSE_BLK1. SYS_DATA_PART0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK3. whole KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_USED[] = { + &WR_DIS_CUSTOM_MAC_USED[0], // [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[] = { + &WR_DIS_DIG_DBIAS_HVT[0], // [] wr_dis of DIG_DBIAS_HVT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS2[] = { + &WR_DIS_DIG_LDO_SLP_DBIAS2[0], // [] wr_dis of DIG_LDO_SLP_DBIAS2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS26[] = { + &WR_DIS_DIG_LDO_SLP_DBIAS26[0], // [] wr_dis of DIG_LDO_SLP_DBIAS26 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_DBIAS26[] = { + &WR_DIS_DIG_LDO_ACT_DBIAS26[0], // [] wr_dis of DIG_LDO_ACT_DBIAS26 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_STEPD10[] = { + &WR_DIS_DIG_LDO_ACT_STEPD10[0], // [] wr_dis of DIG_LDO_ACT_STEPD10 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS13[] = { + &WR_DIS_RTC_LDO_SLP_DBIAS13[0], // [] wr_dis of RTC_LDO_SLP_DBIAS13 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS29[] = { + &WR_DIS_RTC_LDO_SLP_DBIAS29[0], // [] wr_dis of RTC_LDO_SLP_DBIAS29 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS31[] = { + &WR_DIS_RTC_LDO_SLP_DBIAS31[0], // [] wr_dis of RTC_LDO_SLP_DBIAS31 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS31[] = { + &WR_DIS_RTC_LDO_ACT_DBIAS31[0], // [] wr_dis of RTC_LDO_ACT_DBIAS31 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS13[] = { + &WR_DIS_RTC_LDO_ACT_DBIAS13[0], // [] wr_dis of RTC_LDO_ACT_DBIAS13 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIBRATION_3[] = { + &WR_DIS_ADC_CALIBRATION_3[0], // [] wr_dis of ADC_CALIBRATION_3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection + &RD_DIS[0], // [] Disable reading from BlOCK3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK3. KEY0 + &RD_DIS_KEY0[0], // [] Read protection for EFUSE_BLK3. KEY0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0_LOW[] = { - &RD_DIS_KEY0_LOW[0], // Read protection for EFUSE_BLK3. KEY0 lower 128-bit key + &RD_DIS_KEY0_LOW[0], // [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0_HI[] = { - &RD_DIS_KEY0_HI[0], // Read protection for EFUSE_BLK3. KEY0 higher 128-bit key + &RD_DIS_KEY0_HI[0], // [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // RTC WDT timeout threshold + &WDT_DELAY_SEL[0], // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // Hardware Disable JTAG permanently + &DIS_PAD_JTAG[0], // [] Set this bit to disable pad jtag NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable ICache in Download mode + &DIS_DOWNLOAD_ICACHE[0], // [] The bit be set to disable icache in download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption in Download boot mode + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] The bit be set to disable manual encryption NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[] = { - &XTS_KEY_LENGTH_256[0], // Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3 + &XTS_KEY_LENGTH_256[0], // [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled + &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send an SPI flash resume command during SPI boot + &FORCE_SEND_RESUME[0], // [] Set this bit to force ROM code to send a resume command during SPI boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disable all download boot modes + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct_boot mode + &DIS_DIRECT_BOOT[0], // [] This bit set means disable direct_boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable secure UART download mode + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable secure UART download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms + &FLASH_TPUW[0], // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Enable secure boot + &SECURE_BOOT_EN[0], // [] The bit be set to enable secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version for anti-rollback NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ENABLE_CUSTOM_MAC[] = { - &ENABLE_CUSTOM_MAC[0], // True if MAC_CUSTOM is burned +const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_USED[] = { + &CUSTOM_MAC_USED[0], // [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data block + &USER_DATA[0], // [] User data block NULL }; const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC addr + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC address NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR + &WAFER_VERSION_MINOR[0], // [] WAFER_VERSION_MINOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR + &WAFER_VERSION_MAJOR[0], // [] WAFER_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // EFUSE_PKG_VERSION + &PKG_VERSION[0], // [] EFUSE_PKG_VERSION NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR + &BLK_VERSION_MINOR[0], // [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // [256bit FE key] or [128bit FE key and 128key SB key] or [user data] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[] = { - &KEY0_FE_256BIT[0], // [256bit FE key] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[] = { - &KEY0_FE_128BIT[0], // [128bit FE key] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[] = { - &KEY0_SB_128BIT[0], // [128bit SB key] + &BLK_VERSION_MAJOR[0], // [] Major version of BLOCK2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // OCode + &OCODE[0], // [] OCode NULL }; const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data + &TEMP_CALIB[0], // [] Temperature calibration data NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 + &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 + &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 + &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 + &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { - &DIG_DBIAS_HVT[0], // BLOCK2 digital dbias when hvt + &DIG_DBIAS_HVT[0], // [] BLOCK2 digital dbias when hvt NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS2[] = { - &DIG_LDO_SLP_DBIAS2[0], // BLOCK2 DIG_LDO_DBG0_DBIAS2 + &DIG_LDO_SLP_DBIAS2[0], // [] BLOCK2 DIG_LDO_DBG0_DBIAS2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS26[] = { - &DIG_LDO_SLP_DBIAS26[0], // BLOCK2 DIG_LDO_DBG0_DBIAS26 + &DIG_LDO_SLP_DBIAS26[0], // [] BLOCK2 DIG_LDO_DBG0_DBIAS26 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_DBIAS26[] = { - &DIG_LDO_ACT_DBIAS26[0], // BLOCK2 DIG_LDO_ACT_DBIAS26 + &DIG_LDO_ACT_DBIAS26[0], // [] BLOCK2 DIG_LDO_ACT_DBIAS26 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_STEPD10[] = { - &DIG_LDO_ACT_STEPD10[0], // BLOCK2 DIG_LDO_ACT_STEPD10 + &DIG_LDO_ACT_STEPD10[0], // [] BLOCK2 DIG_LDO_ACT_STEPD10 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS13[] = { - &RTC_LDO_SLP_DBIAS13[0], // BLOCK2 DIG_LDO_SLP_DBIAS13 + &RTC_LDO_SLP_DBIAS13[0], // [] BLOCK2 DIG_LDO_SLP_DBIAS13 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[] = { - &RTC_LDO_SLP_DBIAS29[0], // BLOCK2 DIG_LDO_SLP_DBIAS29 + &RTC_LDO_SLP_DBIAS29[0], // [] BLOCK2 DIG_LDO_SLP_DBIAS29 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[] = { - &RTC_LDO_SLP_DBIAS31[0], // BLOCK2 DIG_LDO_SLP_DBIAS31 + &RTC_LDO_SLP_DBIAS31[0], // [] BLOCK2 DIG_LDO_SLP_DBIAS31 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[] = { - &RTC_LDO_ACT_DBIAS31[0], // BLOCK2 DIG_LDO_ACT_DBIAS31 + &RTC_LDO_ACT_DBIAS31[0], // [] BLOCK2 DIG_LDO_ACT_DBIAS31 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[] = { - &RTC_LDO_ACT_DBIAS13[0], // BLOCK2 DIG_LDO_ACT_DBIAS13 + &RTC_LDO_ACT_DBIAS13[0], // [] BLOCK2 DIG_LDO_ACT_DBIAS13 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_3[] = { + &ADC_CALIBRATION_3[0], // [] Store the bit [86:96] of ADC calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[] = { + &KEY0_FE_256BIT[0], // [] 256bit FE key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[] = { + &KEY0_FE_128BIT[0], // [] 128bit FE key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[] = { + &KEY0_SB_128BIT[0], // [] 128bit SB key NULL }; diff --git a/components/efuse/esp32c2/esp_efuse_table.csv b/components/efuse/esp32c2/esp_efuse_table.csv index 7334923b2e..ce0583b040 100644 --- a/components/efuse/esp32c2/esp_efuse_table.csv +++ b/components/efuse/esp32c2/esp_efuse_table.csv @@ -1,99 +1,112 @@ + # field_name, | efuse_block, | bit_start, | bit_count, |comment # # | (EFUSE_BLK0 | (0..255) | (1-256) | # # | EFUSE_BLK1 | | | # -# | EFUSE_BLK3) | | | # +# | ...) | | | # ########################################################################## # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" +# After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 8, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS - WR_DIS.GROUP_1, EFUSE_BLK0, 1, 1, Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE - WR_DIS.GROUP_2, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN - WR_DIS.GROUP_3, EFUSE_BLK0, 3, 1, Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW - WR_DIS.BLK0_RESERVED, EFUSE_BLK0, 4, 1, Write protection for BLK0_RESERVED - WR_DIS.SYS_DATA_PART0, EFUSE_BLK0, 5, 1, Write protection for EFUSE_BLK1. SYS_DATA_PART0 - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 6, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART2 - WR_DIS.KEY0, EFUSE_BLK0, 7, 1, Write protection for EFUSE_BLK3. whole KEY0 - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 2, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 2, Read protection for EFUSE_BLK3. KEY0 - RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK3. KEY0 lower 128-bit key - RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK3. KEY0 higher 128-bit key +# This file was generated by regtools.py based on the efuses.yaml file with the version: 897499b0349a608b895d467abbcf006b - WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, RTC WDT timeout threshold - DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, Hardware Disable JTAG permanently - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, Disable ICache in Download mode - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, Disable flash encryption in Download boot mode - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable - XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3 - UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled - FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, Force ROM code to send an SPI flash resume command during SPI boot - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, Disable all download boot modes - DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, Disable direct_boot mode - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, Enable secure UART download mode - FLASH_TPUW, EFUSE_BLK0, 49, 4, Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms - SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, Enable secure boot - SECURE_VERSION, EFUSE_BLK0, 54, 4, Secure version for anti-rollback - ENABLE_CUSTOM_MAC, EFUSE_BLK0, 58, 1, True if MAC_CUSTOM is burned - DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, Disables check of wafer version major - DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, Disables check of blk version major - - -# USER_DATA BLOCK# - System configuration -####################### - USER_DATA, EFUSE_BLK1, 0, 88, User data block - USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, Custom MAC addr - - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - # EFUSE_RD_BLK2_DATA0_REG - MAC_FACTORY, EFUSE_BLK2, 40, 8, Factory MAC addr [0] - , EFUSE_BLK2, 32, 8, Factory MAC addr [1] - , EFUSE_BLK2, 24, 8, Factory MAC addr [2] - , EFUSE_BLK2, 16, 8, Factory MAC addr [3] - , EFUSE_BLK2, 8, 8, Factory MAC addr [4] - , EFUSE_BLK2, 0, 8, Factory MAC addr [5] - - # EFUSE_RD_BLK2_DATA1_REG - # mac_id_high 16 bits - WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, WAFER_VERSION_MINOR - WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, WAFER_VERSION_MAJOR - PKG_VERSION, EFUSE_BLK2, 54, 3, EFUSE_PKG_VERSION - BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, BLK_VERSION_MINOR - BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, BLK_VERSION_MAJOR - - # EFUSE_RD_BLK2_DATA2_REG - - -################ -KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data] -KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key] -KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key] -KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key] - -# AUTO CONFIG DIG&RTC DBIAS# -################ -OCODE, EFUSE_BLK2, 62, 7, OCode -TEMP_CALIB, EFUSE_BLK2, 69, 9, Temperature calibration data -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 91, 8, ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 99, 6, ADC1 calibration voltage at atten3 -DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt -DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, BLOCK2 DIG_LDO_DBG0_DBIAS2 -DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, BLOCK2 DIG_LDO_DBG0_DBIAS26 -DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26 -DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10 -RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, BLOCK2 DIG_LDO_SLP_DBIAS13 -RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, BLOCK2 DIG_LDO_SLP_DBIAS29 -RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, BLOCK2 DIG_LDO_SLP_DBIAS31 -RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31 -RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, BLOCK2 DIG_LDO_ACT_DBIAS13 +WR_DIS, EFUSE_BLK0, 0, 8, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 1, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 2, 1, [] wr_dis of XTS_KEY_LENGTH_256 +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 3, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 3, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DIRECT_BOOT +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 3, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 3, 1, [] wr_dis of FLASH_TPUW +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 4, 1, [] wr_dis of SECURE_VERSION +WR_DIS.CUSTOM_MAC_USED, EFUSE_BLK0, 4, 1, [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 5, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.MAC, EFUSE_BLK0, 6, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.PKG_VERSION, EFUSE_BLK0, 6, 1, [] wr_dis of PKG_VERSION +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.OCODE, EFUSE_BLK0, 6, 1, [] wr_dis of OCODE +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 6, 1, [] wr_dis of TEMP_CALIB +WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 +WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 +WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 +WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 +WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_DBIAS_HVT +WR_DIS.DIG_LDO_SLP_DBIAS2, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS2 +WR_DIS.DIG_LDO_SLP_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS26 +WR_DIS.DIG_LDO_ACT_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_DBIAS26 +WR_DIS.DIG_LDO_ACT_STEPD10, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_STEPD10 +WR_DIS.RTC_LDO_SLP_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS13 +WR_DIS.RTC_LDO_SLP_DBIAS29, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS29 +WR_DIS.RTC_LDO_SLP_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS31 +WR_DIS.RTC_LDO_ACT_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS31 +WR_DIS.RTC_LDO_ACT_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS13 +WR_DIS.ADC_CALIBRATION_3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC_CALIBRATION_3 +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 7, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +RD_DIS, EFUSE_BLK0, 32, 2, [] Disable reading from BlOCK3 +RD_DIS.KEY0, EFUSE_BLK0, 32, 2, [] Read protection for EFUSE_BLK3. KEY0 +RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key +RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key +WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, [] Set this bit to disable pad jtag +DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, [] The bit be set to disable icache in download mode +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, [] The bit be set to disable manual encryption +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"} +UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} +FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, [] Set this bit to force ROM code to send a resume command during SPI boot +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7) +DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, [] This bit set means disable direct_boot mode +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, [] Set this bit to enable secure UART download mode +FLASH_TPUW, EFUSE_BLK0, 49, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value +SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, [] The bit be set to enable secure boot +SECURE_VERSION, EFUSE_BLK0, 54, 4, [] Secure version for anti-rollback +CUSTOM_MAC_USED, EFUSE_BLK0, 58, 1, [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, [] Disables check of blk version major +USER_DATA, EFUSE_BLK1, 0, 88, [] User data block +USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address +MAC, EFUSE_BLK2, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK2, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK2, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK2, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK2, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK2, 0, 8, [MAC_FACTORY] MAC address +WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, [] WAFER_VERSION_MINOR +WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, [] WAFER_VERSION_MAJOR +PKG_VERSION, EFUSE_BLK2, 54, 3, [] EFUSE_PKG_VERSION +BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"} +BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, [] Major version of BLOCK2 +OCODE, EFUSE_BLK2, 62, 7, [] OCode +TEMP_CALIB, EFUSE_BLK2, 69, 9, [] Temperature calibration data +ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, [] ADC1 init code at atten0 +ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, [] ADC1 init code at atten3 +ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 91, 8, [] ADC1 calibration voltage at atten0 +ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 99, 6, [] ADC1 calibration voltage at atten3 +DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, [] BLOCK2 digital dbias when hvt +DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, [] BLOCK2 DIG_LDO_DBG0_DBIAS2 +DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, [] BLOCK2 DIG_LDO_DBG0_DBIAS26 +DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS26 +DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, [] BLOCK2 DIG_LDO_ACT_STEPD10 +RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, [] BLOCK2 DIG_LDO_SLP_DBIAS13 +RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, [] BLOCK2 DIG_LDO_SLP_DBIAS29 +RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, [] BLOCK2 DIG_LDO_SLP_DBIAS31 +RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS31 +RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, [] BLOCK2 DIG_LDO_ACT_DBIAS13 +ADC_CALIBRATION_3, EFUSE_BLK2, 192, 11, [] Store the bit [86:96] of ADC calibration data +KEY0, EFUSE_BLK3, 0, 256, [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption +KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [] 256bit FE key +KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [] 128bit FE key +KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [] 128bit SB key diff --git a/components/efuse/esp32c2/include/esp_efuse_table.h b/components/efuse/esp32c2/include/esp_efuse_table.h index 7cac756bcf..95192320dd 100644 --- a/components/efuse/esp32c2/include/esp_efuse_table.h +++ b/components/efuse/esp32c2/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 2216d0ff3e0f4e8803f85711b5cc2829 +// md5_digest_table 439495cbc35dc68d7566e05ac3dbb248 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,14 +19,53 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK0_RESERVED[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_USED[]; +#define ESP_EFUSE_WR_DIS_ENABLE_CUSTOM_MAC ESP_EFUSE_WR_DIS_CUSTOM_MAC_USED +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS26[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_DBIAS26[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_STEPD10[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS13[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS29[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS31[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS31[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS13[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIBRATION_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0_LOW[]; @@ -45,21 +84,21 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_CUSTOM_MAC[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_USED[]; +#define ESP_EFUSE_ENABLE_CUSTOM_MAC ESP_EFUSE_CUSTOM_MAC_USED extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[]; extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; @@ -76,6 +115,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[]; extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[]; extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[]; extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[]; #ifdef __cplusplus } diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index b25e14c1a8..0b00b5d22b 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -9,500 +9,711 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 2bf0cfccdc9e055a493d80400a248794 +// md5_digest_table 661eec06c4c442af5baa0c947029db74 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, }; static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, }; -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, }; -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, }; -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, }; -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, }; -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, }; -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, }; -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_ERR_RST_ENABLE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of ERR_RST_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_K_RTC_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_K_DIG_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_DIG_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_V_RTC_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_RTC_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_V_DIG_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_DIG_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_DBIAS_HVT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DIG_DBIAS_HVT, +}; + +static const esp_efuse_desc_t WR_DIS_THRES_HVT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of THRES_HVT, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, }; static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, }; -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, }; -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, }; -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, }; -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, }; -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, }; -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, }; -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, }; -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, }; -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, + {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, + {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable function of usb switch to jtag in module of usb device, }; static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, + {EFUSE_BLK0, 42, 1}, // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7), }; -static const esp_efuse_desc_t DIS_USB_DEVICE[] = { - {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE, +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 43, 1}, // [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"}, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, + {EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download mode, }; -static const esp_efuse_desc_t DIS_CAN[] = { - {EFUSE_BLK0, 46, 1}, // Disable CAN function, +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable CAN function, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., + {EFUSE_BLK0, 47, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., + {EFUSE_BLK0, 48, 3}, // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., + {EFUSE_BLK0, 51, 1}, // [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., -}; - -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., + {EFUSE_BLK0, 52, 1}, // [] Set this bit to disable flash encryption when in download boot modes, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, + {EFUSE_BLK0, 57, 1}, // [] Set this bit to exchange USB D+ and D- pins, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, -}; - -static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { - {EFUSE_BLK0, 59, 2}, // Enable btlc gpio, -}; - -static const esp_efuse_desc_t POWERGLITCH_EN[] = { - {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function, -}; - -static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = { - {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch, + {EFUSE_BLK0, 58, 1}, // [] Set this bit to vdd spi pin function as gpio, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, + {EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, + {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of Key0, }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of Key1, }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of Key2, }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of Key3, }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of Key4, }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of Key5, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, + {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, + {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable revoking aggressive secure boot, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, + {EFUSE_BLK0, 124, 4}, // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, + {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, + {EFUSE_BLK0, 129, 1}, // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable usb serial jtag print during rom boot, + {EFUSE_BLK0, 130, 1}, // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Disable download through USB-Serial-JTAG, + {EFUSE_BLK0, 132, 1}, // [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, + {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., + {EFUSE_BLK0, 134, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, + {EFUSE_BLK0, 141, 1}, // [] Set this bit to force ROM code to send a resume command during SPI boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, + {EFUSE_BLK0, 142, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature), }; static const esp_efuse_desc_t ERR_RST_ENABLE[] = { - {EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers, + {EFUSE_BLK0, 159, 1}, // [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"}, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, + {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, + {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major, }; -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, + {EFUSE_BLK1, 48, 6}, // [] SPI PAD CLK, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK1, 54, 6}, // [] SPI PAD Q(D1), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +static const esp_efuse_desc_t SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK1, 60, 6}, // [] SPI PAD D(D0), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, + {EFUSE_BLK1, 66, 6}, // [] SPI PAD CS, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK1, 72, 6}, // [] SPI PAD HD(D3), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK1, 78, 6}, // [] SPI PAD WP(D2), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, + {EFUSE_BLK1, 84, 6}, // [] SPI PAD DQS, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, + {EFUSE_BLK1, 90, 6}, // [] SPI PAD D4, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, + {EFUSE_BLK1, 96, 6}, // [] SPI PAD D5, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, + {EFUSE_BLK1, 102, 6}, // [] SPI PAD D6, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, + {EFUSE_BLK1, 108, 6}, // [] SPI PAD D7, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, - {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, +static const esp_efuse_desc_t WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK1, 114, 3}, // [] WAFER_VERSION_MINOR least significant bits, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3, + {EFUSE_BLK1, 117, 3}, // [] Package version, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 131, 9}, // Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 140, 8}, // ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, -}; - -static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, -}; - -static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, -}; - -static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, -}; - -static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, -}; - -static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, -}; - -static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, -}; - -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, + {EFUSE_BLK1, 120, 3}, // [] BLK_VERSION_MINOR, }; static const esp_efuse_desc_t K_RTC_LDO[] = { - {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO, + {EFUSE_BLK1, 135, 7}, // [] BLOCK1 K_RTC_LDO, }; static const esp_efuse_desc_t K_DIG_LDO[] = { - {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO, + {EFUSE_BLK1, 142, 7}, // [] BLOCK1 K_DIG_LDO, }; static const esp_efuse_desc_t V_RTC_DBIAS20[] = { - {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20, + {EFUSE_BLK1, 149, 8}, // [] BLOCK1 voltage of rtc dbias20, }; static const esp_efuse_desc_t V_DIG_DBIAS20[] = { - {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20, + {EFUSE_BLK1, 157, 8}, // [] BLOCK1 voltage of digital dbias20, }; static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { - {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt, + {EFUSE_BLK1, 165, 5}, // [] BLOCK1 digital dbias when hvt, }; static const esp_efuse_desc_t THRES_HVT[] = { - {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt, + {EFUSE_BLK1, 170, 10}, // [] BLOCK1 pvt threshold when hvt, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK1, 183, 1}, // [] WAFER_VERSION_MINOR most significant bit, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // [] WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"}, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 131, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 140, 8}, // [] ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 148, 10}, // [] ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 158, 10}, // [] ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 168, 10}, // [] ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 178, 10}, // [] ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 188, 10}, // [] ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 198, 10}, // [] ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 208, 10}, // [] ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 218, 10}, // [] ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC address, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), }; @@ -510,12 +721,12 @@ static const esp_efuse_desc_t THRES_HVT[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection + &WR_DIS[0], // [] Disable programming of individual eFuses NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS NULL }; @@ -524,598 +735,862 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { + &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ERR_RST_ENABLE[] = { + &WR_DIS_ERR_RST_ENABLE[0], // [] wr_dis of ERR_RST_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[] = { + &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[] = { + &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[] = { + &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[] = { + &WR_DIS_SPI_PAD_CONFIG_CS[0], // [] wr_dis of SPI_PAD_CONFIG_CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[] = { + &WR_DIS_SPI_PAD_CONFIG_HD[0], // [] wr_dis of SPI_PAD_CONFIG_HD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[] = { + &WR_DIS_SPI_PAD_CONFIG_WP[0], // [] wr_dis of SPI_PAD_CONFIG_WP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[] = { + &WR_DIS_SPI_PAD_CONFIG_DQS[0], // [] wr_dis of SPI_PAD_CONFIG_DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[] = { + &WR_DIS_SPI_PAD_CONFIG_D4[0], // [] wr_dis of SPI_PAD_CONFIG_D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[] = { + &WR_DIS_SPI_PAD_CONFIG_D5[0], // [] wr_dis of SPI_PAD_CONFIG_D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[] = { + &WR_DIS_SPI_PAD_CONFIG_D6[0], // [] wr_dis of SPI_PAD_CONFIG_D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[] = { + &WR_DIS_SPI_PAD_CONFIG_D7[0], // [] wr_dis of SPI_PAD_CONFIG_D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[] = { + &WR_DIS_WAFER_VERSION_MINOR_LO[0], // [] wr_dis of WAFER_VERSION_MINOR_LO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[] = { + &WR_DIS_K_RTC_LDO[0], // [] wr_dis of K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[] = { + &WR_DIS_K_DIG_LDO[0], // [] wr_dis of K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[] = { + &WR_DIS_V_RTC_DBIAS20[0], // [] wr_dis of V_RTC_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[] = { + &WR_DIS_V_DIG_DBIAS20[0], // [] wr_dis of V_DIG_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[] = { + &WR_DIS_DIG_DBIAS_HVT[0], // [] wr_dis of DIG_DBIAS_HVT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_THRES_HVT[] = { + &WR_DIS_THRES_HVT[0], // [] wr_dis of THRES_HVT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[] = { + &WR_DIS_WAFER_VERSION_MINOR_HI[0], // [] wr_dis of WAFER_VERSION_MINOR_HI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = { + &WR_DIS_VDD_SPI_AS_GPIO[0], // [] wr_dis of VDD_SPI_AS_GPIO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection + &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache + &DIS_ICACHE[0], // [] Set this bit to disable Icache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // Disable USB JTAG + &DIS_USB_JTAG[0], // [] Set this bit to disable function of usb switch to jtag in module of usb device NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode + &DIS_DOWNLOAD_ICACHE[0], // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = { - &DIS_USB_DEVICE[0], // Disable USB_DEVICE +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { + &DIS_USB_SERIAL_JTAG[0], // [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + &DIS_FORCE_DOWNLOAD[0], // [] Set this bit to disable the function that forces chip into download mode NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { - &DIS_CAN[0], // Disable CAN function +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [DIS_CAN] Set this bit to disable CAN function NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + &JTAG_SEL_ENABLE[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + &SOFT_DIS_JTAG[0], // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. + &DIS_PAD_JTAG[0], // [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Set this bit to disable flash encryption when in download boot modes NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins + &USB_EXCHG_PINS[0], // [] Set this bit to exchange USB D+ and D- pins NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { - &BTLC_GPIO_ENABLE[0], // Enable btlc gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { - &POWERGLITCH_EN[0], // Set this bit to enable power glitch function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = { - &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch + &VDD_SPI_AS_GPIO[0], // [] Set this bit to vdd spi pin function as gpio NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + &WDT_DELAY_SEL[0], // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Purpose of Key0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Purpose of Key1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Purpose of Key2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Purpose of Key3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Purpose of Key4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Purpose of Key5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable + &SECURE_BOOT_EN[0], // [] Set this bit to enable secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Set this bit to enable revoking aggressive secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + &FLASH_TPUW[0], // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct boot mode + &DIS_DIRECT_BOOT[0], // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Disable usb serial jtag print during rom boot + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Disable download through USB-Serial-JTAG + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable secure UART download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. + &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + &FORCE_SEND_RESUME[0], // [] Set this bit to force ROM code to send a resume command during SPI boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version (used by ESP-IDF anti-rollback feature) NULL }; const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = { - &ERR_RST_ENABLE[0], // Use BLOCK0 to check error record registers + &ERR_RST_ENABLE[0], // [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + &SPI_PAD_CONFIG_CLK[0], // [] SPI PAD CLK NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[] = { + &SPI_PAD_CONFIG_Q[0], // [] SPI PAD Q(D1) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[] = { + &SPI_PAD_CONFIG_D[0], // [] SPI PAD D(D0) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + &SPI_PAD_CONFIG_CS[0], // [] SPI PAD CS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[] = { + &SPI_PAD_CONFIG_HD[0], // [] SPI PAD HD(D3) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[] = { + &SPI_PAD_CONFIG_WP[0], // [] SPI PAD WP(D2) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + &SPI_PAD_CONFIG_DQS[0], // [] SPI PAD DQS NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + &SPI_PAD_CONFIG_D4[0], // [] SPI PAD D4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + &SPI_PAD_CONFIG_D5[0], // [] SPI PAD D5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + &SPI_PAD_CONFIG_D6[0], // [] SPI PAD D6 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + &SPI_PAD_CONFIG_D7[0], // [] SPI PAD D7 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits - &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[] = { + &WAFER_VERSION_MINOR_LO[0], // [] WAFER_VERSION_MINOR least significant bits NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version 0:ESP32C3 + &PKG_VERSION[0], // [] Package version NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { - &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + &K_RTC_LDO[0], // [] BLOCK1 K_RTC_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { - &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + &K_DIG_LDO[0], // [] BLOCK1 K_DIG_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { - &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + &V_RTC_DBIAS20[0], // [] BLOCK1 voltage of rtc dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { - &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + &V_DIG_DBIAS20[0], // [] BLOCK1 voltage of digital dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { - &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + &DIG_DBIAS_HVT[0], // [] BLOCK1 digital dbias when hvt NULL }; const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = { - &THRES_HVT[0], // BLOCK1 pvt threshold when hvt + &THRES_HVT[0], // [] BLOCK1 pvt threshold when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[] = { + &WAFER_VERSION_MINOR_HI[0], // [] WAFER_VERSION_MINOR most significant bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) NULL }; diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index 9430ae73e6..0863c42fdc 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -1,178 +1,192 @@ + # field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..-) | # -# | EFUSE_BLK1 | |MAX_BLK_LEN*| # -# | ... | | | # -# | EFUSE_BLK10)| | | # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # ########################################################################## -# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" +# After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 +# This file was generated by regtools.py based on the efuses.yaml file with the version: a85f874ae2b6538ca48b7c3db4a79531 - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode - DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function - JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. - USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins - VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio - BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio - POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function - POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch - - # EFUSE_RD_REPEAT_DATA1_REG # - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. - FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback - ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check. - - # EFUSE_RD_REPEAT_DATA4_REG # - DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major - DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major - - -# MAC_SPI_SYS BLOCK# -####################### - # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2 - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - - # RD_MAC_SPI_SYS_3 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits - , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit - # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 - BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR - - # RD_MAC_SPI_SYS_5 - # WAFER_VERSION_MINOR most significant bit - WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - # RD_SYS_PART1_DATA0 - rd_sys_part1_data3 - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - - # RD_SYS_PART1_DATA4 - BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 - TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 140, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 - - # RD_SYS_PART1_DATA5 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration - -# AUTO CONFIG DIG&RTC DBIAS# -################ -K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO -K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO -V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 -V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 -DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt -THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.ERR_RST_ENABLE, EFUSE_BLK0, 19, 1, [] wr_dis of ERR_RST_ENABLE +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK +WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q +WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D +WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS +WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD +WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP +WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS +WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 +WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 +WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 +WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 +WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO +WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO +WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 +WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20 +WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT +WR_DIS.THRES_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of THRES_HVT +WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE +WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 +WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 +WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 +WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 +WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 +WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 +WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 +WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache +DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device +DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) +DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"} +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode +DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins +VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Set this bit to vdd spi pin function as gpio +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} +FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot +SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature) +ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"} +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI PAD CLK +SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI PAD Q(D1) +SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI PAD D(D0) +SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI PAD CS +SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI PAD HD(D3) +SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI PAD WP(D2) +SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI PAD DQS +SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI PAD D4 +SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI PAD D5 +SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI PAD D6 +SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI PAD D7 +WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits +PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version +BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR +K_RTC_LDO, EFUSE_BLK1, 135, 7, [] BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 142, 7, [] BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, [] BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, [] BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, [] BLOCK1 digital dbias when hvt +THRES_HVT, EFUSE_BLK1, 170, 10, [] BLOCK1 pvt threshold when hvt +WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit +WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"} +TEMP_CALIB, EFUSE_BLK2, 131, 9, [] Temperature calibration data +OCODE, EFUSE_BLK2, 140, 8, [] ADC OCode +ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, [] ADC1 init code at atten0 +ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, [] ADC1 init code at atten1 +ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, [] ADC1 init code at atten2 +ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, [] ADC1 init code at atten3 +ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, [] ADC1 calibration voltage at atten0 +ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, [] ADC1 calibration voltage at atten1 +ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, [] ADC1 calibration voltage at atten2 +ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, [] ADC1 calibration voltage at atten3 +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index 00b24634b9..ecee5f3c1d 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 2bf0cfccdc9e055a493d80400a248794 +// md5_digest_table 661eec06c4c442af5baa0c947029db74 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -20,74 +20,166 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ERR_RST_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_THRES_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; @@ -95,21 +187,29 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; @@ -124,20 +224,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/components/efuse/esp32s2/esp_efuse_table.c b/components/efuse/esp32s2/esp_efuse_table.c index 2a1928894d..b29e1b86e2 100644 --- a/components/efuse/esp32s2/esp_efuse_table.c +++ b/components/efuse/esp32s2/esp_efuse_table.c @@ -9,460 +9,791 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 10aa3ea5c0748be491a49b2b2d889166 +// md5_digest_table 42c79ddff54c8f03645a832a69f60af2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, }; static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT, + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +static const esp_efuse_desc_t WR_DIS_DIS_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DCACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL, +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_DCACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_BOOT_REMAP[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_BOOT_REMAP, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SOFT_DIS_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_HARD_DIS_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of HARD_DIS_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_XPD[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_XPD, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_TIEH[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_FORCE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_FORCE, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, }; -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, }; -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, }; -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, }; -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, }; -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, }; -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_LEGACY_SPI_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_LEGACY_SPI_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CHANNEL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CHANNEL, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_PIN_POWER_SELECTION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of PIN_POWER_SELECTION, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO, }; static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t WR_DIS_ADC_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC_CALIB, }; -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MINOR, }; -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, }; -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A10H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A10H, }; -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A11H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A11H, }; -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A12H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A12H, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A13H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A13H, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A20H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A20H, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A21H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A21H, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A22H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A22H, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A23H[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A23H, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A10L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A10L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A11L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A11L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A12L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A12L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A13L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A13L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A20L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A20L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A21L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A21L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A22L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A22L, +}; + +static const esp_efuse_desc_t WR_DIS_RTCCALIB_V1IDX_A23L[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A23L, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS, + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXT_PHY_ENABLE[] = { + {EFUSE_BLK0, 30, 1}, // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_USB_FORCE_NOPERSIST[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_FORCE_NOPERSIST, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK0_VERSION[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of BLOCK0_VERSION, }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, }; -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, }; -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, }; -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, }; -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, }; -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, + {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache, }; static const esp_efuse_desc_t DIS_DCACHE[] = { - {EFUSE_BLK0, 41, 1}, // Disable Dcace, + {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable Dcache, }; static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 42, 1}, // [] Disables Icache when SoC is in Download mode, }; static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = { - {EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 43, 1}, // [] Disables Dcache when SoC is in Download mode, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, + {EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download mode, }; static const esp_efuse_desc_t DIS_USB[] = { - {EFUSE_BLK0, 45, 1}, // Disable USB function, + {EFUSE_BLK0, 45, 1}, // [] Set this bit to disable USB OTG function, }; -static const esp_efuse_desc_t DIS_CAN[] = { - {EFUSE_BLK0, 46, 1}, // Disable CAN function, +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable the TWAI Controller function, }; static const esp_efuse_desc_t DIS_BOOT_REMAP[] = { - {EFUSE_BLK0, 47, 1}, // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function, + {EFUSE_BLK0, 47, 1}, // [] Disables capability to Remap RAM to ROM address space, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 49, 1}, // Software disable jtag jtag can be activated again by hmac module, + {EFUSE_BLK0, 49, 1}, // [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral, }; static const esp_efuse_desc_t HARD_DIS_JTAG[] = { - {EFUSE_BLK0, 50, 1}, // Hardware disable jtag permanently disable jtag function, + {EFUSE_BLK0, 50, 1}, // [] Hardware disables JTAG permanently, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 51, 1}, // Disable flash encrypt function, + {EFUSE_BLK0, 51, 1}, // [] Disables flash encryption when in download boot modes, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 56, 1}, // Exchange D+ D- pins, + {EFUSE_BLK0, 56, 1}, // [] Set this bit to exchange USB D+ and D- pins, }; static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = { - {EFUSE_BLK0, 57, 1}, // Enable external PHY, + {EFUSE_BLK0, 57, 1}, // [EXT_PHY_ENABLE] Set this bit to enable external USB PHY, +}; + +static const esp_efuse_desc_t USB_FORCE_NOPERSIST[] = { + {EFUSE_BLK0, 58, 1}, // [] If set; forces USB BVALID to 1, }; static const esp_efuse_desc_t BLOCK0_VERSION[] = { - {EFUSE_BLK0, 59, 2}, // BLOCK0 efuse version, + {EFUSE_BLK0, 59, 2}, // [] BLOCK0 efuse version, }; static const esp_efuse_desc_t VDD_SPI_XPD[] = { - {EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up, + {EFUSE_BLK0, 68, 1}, // [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on, }; static const esp_efuse_desc_t VDD_SPI_TIEH[] = { - {EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda, + {EFUSE_BLK0, 69, 1}, // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}, }; static const esp_efuse_desc_t VDD_SPI_FORCE[] = { - {EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI, + {EFUSE_BLK0, 70, 1}, // [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, + {EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, + {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of KEY0, }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of KEY1, }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of KEY2, }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of KEY3, }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of KEY4, }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of KEY5, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, + {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, + {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable aggressive secure boot key revocation mode, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, + {EFUSE_BLK0, 124, 4}, // [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, + {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable all download boot modes, }; static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, + {EFUSE_BLK0, 129, 1}, // [] Set this bit to disable Legacy SPI boot mode, }; static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = { - {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1, + {EFUSE_BLK0, 130, 1}, // [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"}, }; static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Disable download through USB, + {EFUSE_BLK0, 132, 1}, // [] Set this bit to disable use of USB OTG in UART download boot mode, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, + {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode (read/write flash only), }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., + {EFUSE_BLK0, 134, 2}, // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}, }; static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { - {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., + {EFUSE_BLK0, 136, 1}, // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}, }; static const esp_efuse_desc_t FLASH_TYPE[] = { - {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, + {EFUSE_BLK0, 137, 1}, // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 138, 1}, // Force ROM code to send a resume command during SPI boot, + {EFUSE_BLK0, 138, 1}, // [] If set; forces ROM code to send an SPI flash resume command during SPI boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback, + {EFUSE_BLK0, 139, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature), }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, + {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, + {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major, }; -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, + {EFUSE_BLK1, 48, 6}, // [] SPI_PAD_configure CLK, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK1, 54, 6}, // [] SPI_PAD_configure Q(D1), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +static const esp_efuse_desc_t SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK1, 60, 6}, // [] SPI_PAD_configure D(D0), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, + {EFUSE_BLK1, 66, 6}, // [] SPI_PAD_configure CS, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK1, 72, 6}, // [] SPI_PAD_configure HD(D3), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK1, 78, 6}, // [] SPI_PAD_configure WP(D2), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, + {EFUSE_BLK1, 84, 6}, // [] SPI_PAD_configure DQS, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, + {EFUSE_BLK1, 90, 6}, // [] SPI_PAD_configure D4, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, + {EFUSE_BLK1, 96, 6}, // [] SPI_PAD_configure D5, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, + {EFUSE_BLK1, 102, 6}, // [] SPI_PAD_configure D6, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, + {EFUSE_BLK1, 108, 6}, // [] SPI_PAD_configure D7, }; static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 114, 2}, // WAFER_VERSION_MAJOR, + {EFUSE_BLK1, 114, 2}, // [] WAFER_VERSION_MAJOR, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 132, 3}, // WAFER_VERSION_MINOR least significant bits, - {EFUSE_BLK1, 116, 1}, // WAFER_VERSION_MINOR most significant bit, +static const esp_efuse_desc_t WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK1, 116, 1}, // [] WAFER_VERSION_MINOR most significant bit, }; static const esp_efuse_desc_t FLASH_VERSION[] = { - {EFUSE_BLK1, 117, 4}, // Flash_version, + {EFUSE_BLK1, 117, 4}, // [] Flash version, }; static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 121, 2}, // BLK_VERSION_MAJOR, + {EFUSE_BLK1, 121, 2}, // [] BLK_VERSION_MAJOR, }; static const esp_efuse_desc_t PSRAM_VERSION[] = { - {EFUSE_BLK1, 124, 4}, // PSRAM version, + {EFUSE_BLK1, 124, 4}, // [] PSRAM version, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 128, 4}, // Package version, + {EFUSE_BLK1, 128, 4}, // [] Package version, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK1, 132, 3}, // [] WAFER_VERSION_MINOR least significant bits, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t ADC_CALIB[] = { + {EFUSE_BLK2, 128, 4}, // [] 4 bit of ADC calibration, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK2, 132, 3}, // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2, + {EFUSE_BLK2, 132, 3}, // [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"}, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 135, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A10H[] = { + {EFUSE_BLK2, 144, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A11H[] = { + {EFUSE_BLK2, 152, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A12H[] = { + {EFUSE_BLK2, 160, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A13H[] = { + {EFUSE_BLK2, 168, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A20H[] = { + {EFUSE_BLK2, 176, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A21H[] = { + {EFUSE_BLK2, 184, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A22H[] = { + {EFUSE_BLK2, 192, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A23H[] = { + {EFUSE_BLK2, 200, 8}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A10L[] = { + {EFUSE_BLK2, 208, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A11L[] = { + {EFUSE_BLK2, 214, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A12L[] = { + {EFUSE_BLK2, 220, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A13L[] = { + {EFUSE_BLK2, 226, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A20L[] = { + {EFUSE_BLK2, 232, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A21L[] = { + {EFUSE_BLK2, 238, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A22L[] = { + {EFUSE_BLK2, 244, 6}, // [], +}; + +static const esp_efuse_desc_t RTCCALIB_V1IDX_A23L[] = { + {EFUSE_BLK2, 250, 6}, // [], }; static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, }; static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, }; static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, }; static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, }; static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, }; static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, }; static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, }; static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, }; static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), }; @@ -470,17 +801,12 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection + &WR_DIS[0], // [] Disable programming of individual eFuses NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = { - &WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS NULL }; @@ -489,543 +815,962 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[] = { + &WR_DIS_DIS_DCACHE[0], // [] wr_dis of DIS_DCACHE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + &WR_DIS_DIS_DOWNLOAD_DCACHE[0], // [] wr_dis of DIS_DOWNLOAD_DCACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB[] = { + &WR_DIS_DIS_USB[0], // [] wr_dis of DIS_USB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_BOOT_REMAP[] = { + &WR_DIS_DIS_BOOT_REMAP[0], // [] wr_dis of DIS_BOOT_REMAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HARD_DIS_JTAG[] = { + &WR_DIS_HARD_DIS_JTAG[0], // [] wr_dis of HARD_DIS_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[] = { + &WR_DIS_VDD_SPI_XPD[0], // [] wr_dis of VDD_SPI_XPD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[] = { + &WR_DIS_VDD_SPI_TIEH[0], // [] wr_dis of VDD_SPI_TIEH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[] = { + &WR_DIS_VDD_SPI_FORCE[0], // [] wr_dis of VDD_SPI_FORCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT[] = { + &WR_DIS_DIS_LEGACY_SPI_BOOT[0], // [] wr_dis of DIS_LEGACY_SPI_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL[] = { + &WR_DIS_UART_PRINT_CHANNEL[0], // [] wr_dis of UART_PRINT_CHANNEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[] = { + &WR_DIS_PIN_POWER_SELECTION[0], // [] wr_dis of PIN_POWER_SELECTION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = { + &WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[] = { + &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[] = { + &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[] = { + &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[] = { + &WR_DIS_SPI_PAD_CONFIG_CS[0], // [] wr_dis of SPI_PAD_CONFIG_CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[] = { + &WR_DIS_SPI_PAD_CONFIG_HD[0], // [] wr_dis of SPI_PAD_CONFIG_HD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[] = { + &WR_DIS_SPI_PAD_CONFIG_WP[0], // [] wr_dis of SPI_PAD_CONFIG_WP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[] = { + &WR_DIS_SPI_PAD_CONFIG_DQS[0], // [] wr_dis of SPI_PAD_CONFIG_DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[] = { + &WR_DIS_SPI_PAD_CONFIG_D4[0], // [] wr_dis of SPI_PAD_CONFIG_D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[] = { + &WR_DIS_SPI_PAD_CONFIG_D5[0], // [] wr_dis of SPI_PAD_CONFIG_D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[] = { + &WR_DIS_SPI_PAD_CONFIG_D6[0], // [] wr_dis of SPI_PAD_CONFIG_D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[] = { + &WR_DIS_SPI_PAD_CONFIG_D7[0], // [] wr_dis of SPI_PAD_CONFIG_D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[] = { + &WR_DIS_WAFER_VERSION_MINOR_HI[0], // [] wr_dis of WAFER_VERSION_MINOR_HI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VERSION[] = { + &WR_DIS_FLASH_VERSION[0], // [] wr_dis of FLASH_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VERSION[] = { + &WR_DIS_PSRAM_VERSION[0], // [] wr_dis of PSRAM_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[] = { + &WR_DIS_WAFER_VERSION_MINOR_LO[0], // [] wr_dis of WAFER_VERSION_MINOR_LO NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIB[] = { + &WR_DIS_ADC_CALIB[0], // [] wr_dis of ADC_CALIB NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10H[] = { + &WR_DIS_RTCCALIB_V1IDX_A10H[0], // [] wr_dis of RTCCALIB_V1IDX_A10H NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11H[] = { + &WR_DIS_RTCCALIB_V1IDX_A11H[0], // [] wr_dis of RTCCALIB_V1IDX_A11H NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12H[] = { + &WR_DIS_RTCCALIB_V1IDX_A12H[0], // [] wr_dis of RTCCALIB_V1IDX_A12H NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13H[] = { + &WR_DIS_RTCCALIB_V1IDX_A13H[0], // [] wr_dis of RTCCALIB_V1IDX_A13H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20H[] = { + &WR_DIS_RTCCALIB_V1IDX_A20H[0], // [] wr_dis of RTCCALIB_V1IDX_A20H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21H[] = { + &WR_DIS_RTCCALIB_V1IDX_A21H[0], // [] wr_dis of RTCCALIB_V1IDX_A21H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22H[] = { + &WR_DIS_RTCCALIB_V1IDX_A22H[0], // [] wr_dis of RTCCALIB_V1IDX_A22H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23H[] = { + &WR_DIS_RTCCALIB_V1IDX_A23H[0], // [] wr_dis of RTCCALIB_V1IDX_A23H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10L[] = { + &WR_DIS_RTCCALIB_V1IDX_A10L[0], // [] wr_dis of RTCCALIB_V1IDX_A10L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11L[] = { + &WR_DIS_RTCCALIB_V1IDX_A11L[0], // [] wr_dis of RTCCALIB_V1IDX_A11L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12L[] = { + &WR_DIS_RTCCALIB_V1IDX_A12L[0], // [] wr_dis of RTCCALIB_V1IDX_A12L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13L[] = { + &WR_DIS_RTCCALIB_V1IDX_A13L[0], // [] wr_dis of RTCCALIB_V1IDX_A13L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20L[] = { + &WR_DIS_RTCCALIB_V1IDX_A20L[0], // [] wr_dis of RTCCALIB_V1IDX_A20L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21L[] = { + &WR_DIS_RTCCALIB_V1IDX_A21L[0], // [] wr_dis of RTCCALIB_V1IDX_A21L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22L[] = { + &WR_DIS_RTCCALIB_V1IDX_A22L[0], // [] wr_dis of RTCCALIB_V1IDX_A22L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23L[] = { + &WR_DIS_RTCCALIB_V1IDX_A23L[0], // [] wr_dis of RTCCALIB_V1IDX_A23L + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { - &WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[] = { + &WR_DIS_USB_EXT_PHY_ENABLE[0], // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_FORCE_NOPERSIST[] = { + &WR_DIS_USB_FORCE_NOPERSIST[0], // [] wr_dis of USB_FORCE_NOPERSIST + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK0_VERSION[] = { + &WR_DIS_BLOCK0_VERSION[0], // [] wr_dis of BLOCK0_VERSION NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection + &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache + &DIS_ICACHE[0], // [] Set this bit to disable Icache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = { - &DIS_DCACHE[0], // Disable Dcace + &DIS_DCACHE[0], // [] Set this bit to disable Dcache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_ICACHE[0], // [] Disables Icache when SoC is in Download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = { - &DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_DCACHE[0], // [] Disables Dcache when SoC is in Download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + &DIS_FORCE_DOWNLOAD[0], // [] Set this bit to disable the function that forces chip into download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { - &DIS_USB[0], // Disable USB function + &DIS_USB[0], // [] Set this bit to disable USB OTG function NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { - &DIS_CAN[0], // Disable CAN function +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [DIS_CAN] Set this bit to disable the TWAI Controller function NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[] = { - &DIS_BOOT_REMAP[0], // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function + &DIS_BOOT_REMAP[0], // [] Disables capability to Remap RAM to ROM address space NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Software disable jtag jtag can be activated again by hmac module + &SOFT_DIS_JTAG[0], // [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral NULL }; const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = { - &HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function + &HARD_DIS_JTAG[0], // [] Hardware disables JTAG permanently NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Disables flash encryption when in download boot modes NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins + &USB_EXCHG_PINS[0], // [] Set this bit to exchange USB D+ and D- pins NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = { - &USB_EXT_PHY_ENABLE[0], // Enable external PHY + &USB_EXT_PHY_ENABLE[0], // [EXT_PHY_ENABLE] Set this bit to enable external USB PHY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_FORCE_NOPERSIST[] = { + &USB_FORCE_NOPERSIST[0], // [] If set; forces USB BVALID to 1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[] = { - &BLOCK0_VERSION[0], // BLOCK0 efuse version + &BLOCK0_VERSION[0], // [] BLOCK0 efuse version NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = { - &VDD_SPI_XPD[0], // VDD_SPI regulator power up + &VDD_SPI_XPD[0], // [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = { - &VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda + &VDD_SPI_TIEH[0], // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = { - &VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI + &VDD_SPI_FORCE[0], // [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + &WDT_DELAY_SEL[0], // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Purpose of KEY0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Purpose of KEY1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Purpose of KEY2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Purpose of KEY3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Purpose of KEY4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Purpose of KEY5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable + &SECURE_BOOT_EN[0], // [] Set this bit to enable secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Set this bit to enable aggressive secure boot key revocation mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + &FLASH_TPUW[0], // [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable all download boot modes NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = { - &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 + &DIS_LEGACY_SPI_BOOT[0], // [] Set this bit to disable Legacy SPI boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = { - &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1 + &UART_PRINT_CHANNEL[0], // [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { - &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB + &DIS_USB_DOWNLOAD_MODE[0], // [] Set this bit to disable use of USB OTG in UART download boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable secure UART download mode (read/write flash only) NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. + &UART_PRINT_CONTROL[0], // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { - &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + &PIN_POWER_SELECTION[0], // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { - &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line + &FLASH_TYPE[0], // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + &FORCE_SEND_RESUME[0], // [] If set; forces ROM code to send an SPI flash resume command during SPI boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version (used by ESP-IDF anti-rollback feature) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + &SPI_PAD_CONFIG_CLK[0], // [] SPI_PAD_configure CLK NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[] = { + &SPI_PAD_CONFIG_Q[0], // [] SPI_PAD_configure Q(D1) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[] = { + &SPI_PAD_CONFIG_D[0], // [] SPI_PAD_configure D(D0) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + &SPI_PAD_CONFIG_CS[0], // [] SPI_PAD_configure CS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[] = { + &SPI_PAD_CONFIG_HD[0], // [] SPI_PAD_configure HD(D3) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[] = { + &SPI_PAD_CONFIG_WP[0], // [] SPI_PAD_configure WP(D2) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + &SPI_PAD_CONFIG_DQS[0], // [] SPI_PAD_configure DQS NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + &SPI_PAD_CONFIG_D4[0], // [] SPI_PAD_configure D4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + &SPI_PAD_CONFIG_D5[0], // [] SPI_PAD_configure D5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + &SPI_PAD_CONFIG_D6[0], // [] SPI_PAD_configure D6 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + &SPI_PAD_CONFIG_D7[0], // [] SPI_PAD_configure D7 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR + &WAFER_VERSION_MAJOR[0], // [] WAFER_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits - &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[] = { + &WAFER_VERSION_MINOR_HI[0], // [] WAFER_VERSION_MINOR most significant bit NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = { - &FLASH_VERSION[0], // Flash_version + &FLASH_VERSION[0], // [] Flash version NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[] = { - &PSRAM_VERSION[0], // PSRAM version + &PSRAM_VERSION[0], // [] PSRAM version NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[] = { + &WAFER_VERSION_MINOR_LO[0], // [] WAFER_VERSION_MINOR least significant bits NULL }; const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIB[] = { + &ADC_CALIB[0], // [] 4 bit of ADC calibration NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10H[] = { + &RTCCALIB_V1IDX_A10H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11H[] = { + &RTCCALIB_V1IDX_A11H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12H[] = { + &RTCCALIB_V1IDX_A12H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13H[] = { + &RTCCALIB_V1IDX_A13H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20H[] = { + &RTCCALIB_V1IDX_A20H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21H[] = { + &RTCCALIB_V1IDX_A21H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22H[] = { + &RTCCALIB_V1IDX_A22H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23H[] = { + &RTCCALIB_V1IDX_A23H[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10L[] = { + &RTCCALIB_V1IDX_A10L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11L[] = { + &RTCCALIB_V1IDX_A11L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12L[] = { + &RTCCALIB_V1IDX_A12L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13L[] = { + &RTCCALIB_V1IDX_A13L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20L[] = { + &RTCCALIB_V1IDX_A20L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21L[] = { + &RTCCALIB_V1IDX_A21L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22L[] = { + &RTCCALIB_V1IDX_A22L[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23L[] = { + &RTCCALIB_V1IDX_A23L[0], // [] NULL }; const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data + &USER_DATA[0], // [BLOCK_USR_DATA] User data NULL }; const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data + &KEY0[0], // [BLOCK_KEY0] Key0 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data + &KEY1[0], // [BLOCK_KEY1] Key1 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data + &KEY2[0], // [BLOCK_KEY2] Key2 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data + &KEY3[0], // [BLOCK_KEY3] Key3 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data + &KEY4[0], // [BLOCK_KEY4] Key4 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data + &KEY5[0], // [BLOCK_KEY5] Key5 or user data NULL }; const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) NULL }; diff --git a/components/efuse/esp32s2/esp_efuse_table.csv b/components/efuse/esp32s2/esp_efuse_table.csv index 27ed54a8c1..529dbce73f 100644 --- a/components/efuse/esp32s2/esp_efuse_table.csv +++ b/components/efuse/esp32s2/esp_efuse_table.csv @@ -1,163 +1,212 @@ + # field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..-) | # -# | EFUSE_BLK1 | |MAX_BLK_LEN*| # -# | ... | | | # -# | EFUSE_BLK10)| | | # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # ########################################################################## -# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" +# After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2 - WR_DIS.DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT - WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 - WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS +# This file was generated by regtools.py based on the efuses.yaml file with the version: 888a61f6f500d9c7ee0aa32016b0bee7 - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 - DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function - DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function - DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function - SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, Software disable jtag jtag can be activated again by hmac module - HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, Hardware disable jtag permanently disable jtag function - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode - USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, Exchange D+ D- pins - USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, Enable external PHY - BLOCK0_VERSION, EFUSE_BLK0, 59, 2, BLOCK0 efuse version - - # EFUSE_RD_REPEAT_DATA1_REG # - VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up - VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda - VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 - UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1 - DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. - PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. - FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line - FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback - - # EFUSE_RD_REPEAT_DATA4_REG # - DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major - DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major - - -# MAC_SPI_8M_SYS BLOCK# -####################### - # RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2 - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - - # RD_MAC_SPI_8M_3 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR - WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits - , EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit - # WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4 - FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version - BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR - PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version - - # RD_MAC_SPI_8M_4 - PKG_VERSION, EFUSE_BLK1, 128, 4, Package version - # WAFER_VERSION_MINOR least significant bits - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - # RD_SYS_DATA0 - RD_SYS_DATA3 - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - - # RD_SYS_DATA4 - BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.DIS_USB, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.DIS_BOOT_REMAP, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_BOOT_REMAP +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of SOFT_DIS_JTAG +WR_DIS.HARD_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of HARD_DIS_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD +WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH +WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_LEGACY_SPI_BOOT +WR_DIS.UART_PRINT_CHANNEL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CHANNEL +WR_DIS.DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION +WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK +WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q +WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D +WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS +WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD +WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP +WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS +WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 +WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 +WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 +WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI +WR_DIS.FLASH_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VERSION +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.PSRAM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VERSION +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.ADC_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of ADC_CALIB +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.RTCCALIB_V1IDX_A10H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10H +WR_DIS.RTCCALIB_V1IDX_A11H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11H +WR_DIS.RTCCALIB_V1IDX_A12H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12H +WR_DIS.RTCCALIB_V1IDX_A13H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13H +WR_DIS.RTCCALIB_V1IDX_A20H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20H +WR_DIS.RTCCALIB_V1IDX_A21H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21H +WR_DIS.RTCCALIB_V1IDX_A22H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22H +WR_DIS.RTCCALIB_V1IDX_A23H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23H +WR_DIS.RTCCALIB_V1IDX_A10L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10L +WR_DIS.RTCCALIB_V1IDX_A11L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11L +WR_DIS.RTCCALIB_V1IDX_A12L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12L +WR_DIS.RTCCALIB_V1IDX_A13L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13L +WR_DIS.RTCCALIB_V1IDX_A20L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20L +WR_DIS.RTCCALIB_V1IDX_A21L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21L +WR_DIS.RTCCALIB_V1IDX_A22L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22L +WR_DIS.RTCCALIB_V1IDX_A23L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23L +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE +WR_DIS.USB_FORCE_NOPERSIST, EFUSE_BLK0, 30, 1, [] wr_dis of USB_FORCE_NOPERSIST +WR_DIS.BLOCK0_VERSION, EFUSE_BLK0, 30, 1, [] wr_dis of BLOCK0_VERSION +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache +DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache +DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Disables Icache when SoC is in Download mode +DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Disables Dcache when SoC is in Download mode +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode +DIS_USB, EFUSE_BLK0, 45, 1, [] Set this bit to disable USB OTG function +DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable the TWAI Controller function +DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, [] Disables capability to Remap RAM to ROM address space +SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral +HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, [] Hardware disables JTAG permanently +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, [] Disables flash encryption when in download boot modes +USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, [] Set this bit to exchange USB D+ and D- pins +USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, [EXT_PHY_ENABLE] Set this bit to enable external USB PHY +USB_FORCE_NOPERSIST, EFUSE_BLK0, 58, 1, [] If set; forces USB BVALID to 1 +BLOCK0_VERSION, EFUSE_BLK0, 59, 2, [] BLOCK0 efuse version +VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on +VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} +VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of KEY0 +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of KEY1 +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of KEY2 +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of KEY3 +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of KEY4 +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of KEY5 +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable aggressive secure boot key revocation mode +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable all download boot modes +DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable Legacy SPI boot mode +UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"} +DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable use of USB OTG in UART download boot mode +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode (read/write flash only) +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} +PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} +FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} +FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, [] If set; forces ROM code to send an SPI flash resume command during SPI boot +SECURE_VERSION, EFUSE_BLK0, 139, 16, [] Secure version (used by ESP-IDF anti-rollback feature) +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK +SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1) +SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0) +SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS +SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3) +SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2) +SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS +SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4 +SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5 +SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6 +SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7 +WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, [] WAFER_VERSION_MAJOR +WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 116, 1, [] WAFER_VERSION_MINOR most significant bit +FLASH_VERSION, EFUSE_BLK1, 117, 4, [] Flash version +BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, [] BLK_VERSION_MAJOR +PSRAM_VERSION, EFUSE_BLK1, 124, 4, [] PSRAM version +PKG_VERSION, EFUSE_BLK1, 128, 4, [] Package version +WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 132, 3, [] WAFER_VERSION_MINOR least significant bits +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +ADC_CALIB, EFUSE_BLK2, 128, 4, [] 4 bit of ADC calibration +BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"} +TEMP_CALIB, EFUSE_BLK2, 135, 9, [] Temperature calibration data +RTCCALIB_V1IDX_A10H, EFUSE_BLK2, 144, 8, [] +RTCCALIB_V1IDX_A11H, EFUSE_BLK2, 152, 8, [] +RTCCALIB_V1IDX_A12H, EFUSE_BLK2, 160, 8, [] +RTCCALIB_V1IDX_A13H, EFUSE_BLK2, 168, 8, [] +RTCCALIB_V1IDX_A20H, EFUSE_BLK2, 176, 8, [] +RTCCALIB_V1IDX_A21H, EFUSE_BLK2, 184, 8, [] +RTCCALIB_V1IDX_A22H, EFUSE_BLK2, 192, 8, [] +RTCCALIB_V1IDX_A23H, EFUSE_BLK2, 200, 8, [] +RTCCALIB_V1IDX_A10L, EFUSE_BLK2, 208, 6, [] +RTCCALIB_V1IDX_A11L, EFUSE_BLK2, 214, 6, [] +RTCCALIB_V1IDX_A12L, EFUSE_BLK2, 220, 6, [] +RTCCALIB_V1IDX_A13L, EFUSE_BLK2, 226, 6, [] +RTCCALIB_V1IDX_A20L, EFUSE_BLK2, 232, 6, [] +RTCCALIB_V1IDX_A21L, EFUSE_BLK2, 238, 6, [] +RTCCALIB_V1IDX_A22L, EFUSE_BLK2, 244, 6, [] +RTCCALIB_V1IDX_A23L, EFUSE_BLK2, 250, 6, [] +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32s2/include/esp_efuse_table.h b/components/efuse/esp32s2/include/esp_efuse_table.h index 46d67dc029..957e041d74 100644 --- a/components/efuse/esp32s2/include/esp_efuse_table.h +++ b/components/efuse/esp32s2/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 10aa3ea5c0748be491a49b2b2d889166 +// md5_digest_table 42c79ddff54c8f03645a832a69f60af2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,56 +19,148 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_BOOT_REMAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_FORCE_NOPERSIST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK0_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_USB_FORCE_NOPERSIST[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; @@ -79,11 +171,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; @@ -99,35 +197,65 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIB[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22L[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23L[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index 064c5066d8..85bb0d2900 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -9,568 +9,871 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 770b2130715648e4649be150765d72f9 +// md5_digest_table 7f80667718451ae522bb4d60ced03d49 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, }; static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +static const esp_efuse_desc_t WR_DIS_DIS_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DCACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL, +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_DCACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_APP_CPU[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_APP_CPU, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_STRAP_JTAG_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of STRAP_JTAG_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of USB_PHY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_XPD[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_XPD, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_TIEH[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_FORCE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_FORCE, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, }; -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, }; -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, }; -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, }; -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, }; -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, }; -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_PIN_POWER_SELECTION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of PIN_POWER_SELECTION, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_K_RTC_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_K_DIG_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_DIG_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_V_RTC_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_RTC_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_V_DIG_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_DIG_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_DBIAS_HVT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DIG_DBIAS_HVT, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN3, }; static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, }; -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, }; -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, }; -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, }; -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS, + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXT_PHY_ENABLE[] = { + {EFUSE_BLK0, 30, 1}, // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, }; -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, }; -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, }; -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, }; -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, }; -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, + {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache, }; static const esp_efuse_desc_t DIS_DCACHE[] = { - {EFUSE_BLK0, 41, 1}, // Disable Dcace, + {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable Dcache, }; static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 42, 1}, // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = { - {EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 43, 1}, // [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, + {EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download mode, }; -static const esp_efuse_desc_t DIS_USB[] = { - {EFUSE_BLK0, 45, 1}, // Disable USB function, +static const esp_efuse_desc_t DIS_USB_OTG[] = { + {EFUSE_BLK0, 45, 1}, // [DIS_USB] Set this bit to disable USB function, }; -static const esp_efuse_desc_t DIS_CAN[] = { - {EFUSE_BLK0, 46, 1}, // Disable CAN function, +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable CAN function, }; static const esp_efuse_desc_t DIS_APP_CPU[] = { - {EFUSE_BLK0, 47, 1}, // Disables APP CPU, + {EFUSE_BLK0, 47, 1}, // [] Disable app cpu, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral, + {EFUSE_BLK0, 48, 3}, // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module, }; -static const esp_efuse_desc_t HARD_DIS_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Hardware disable jtag permanently disable jtag function, +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // Disable flash encrypt function, + {EFUSE_BLK0, 52, 1}, // [] Set this bit to disable flash encryption when in download boot modes, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, + {EFUSE_BLK0, 57, 1}, // [] Set this bit to exchange USB D+ and D- pins, }; static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = { - {EFUSE_BLK0, 58, 1}, // Enable external PHY, -}; - -static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { - {EFUSE_BLK0, 59, 2}, // Enables BTLC GPIO, + {EFUSE_BLK0, 58, 1}, // [EXT_PHY_ENABLE] Set this bit to enable external PHY, }; static const esp_efuse_desc_t VDD_SPI_XPD[] = { - {EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up, + {EFUSE_BLK0, 68, 1}, // [] SPI regulator power up signal, }; static const esp_efuse_desc_t VDD_SPI_TIEH[] = { - {EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda, + {EFUSE_BLK0, 69, 1}, // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}, }; static const esp_efuse_desc_t VDD_SPI_FORCE[] = { - {EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI, + {EFUSE_BLK0, 70, 1}, // [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, + {EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, + {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of Key0, }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of Key1, }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of Key2, }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of Key3, }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of Key4, }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of Key5, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, + {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, + {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable revoking aggressive secure boot, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 118, 1}, // Set to disable usb_serial_jtag-to-jtag function, + {EFUSE_BLK0, 118, 1}, // [] Set this bit to disable function of usb switch to jtag in module of usb device, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 119, 1}, // Set to disable usb_serial_jtag module, + {EFUSE_BLK0, 119, 1}, // [DIS_USB_DEVICE] Set this bit to disable usb device, }; static const esp_efuse_desc_t STRAP_JTAG_SEL[] = { - {EFUSE_BLK0, 120, 1}, // Enable selection between usb_to_jtag or pad_to_jtag through gpio10, + {EFUSE_BLK0, 120, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, }; static const esp_efuse_desc_t USB_PHY_SEL[] = { - {EFUSE_BLK0, 121, 1}, // Select internal/external PHY for USB OTG and usb_serial_jtag, + {EFUSE_BLK0, 121, 1}, // [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, + {EFUSE_BLK0, 124, 4}, // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, + {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, + {EFUSE_BLK0, 129, 1}, // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable usb serial jtag print during rom boot, + {EFUSE_BLK0, 130, 1}, // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}, }; static const esp_efuse_desc_t FLASH_ECC_MODE[] = { - {EFUSE_BLK0, 131, 1}, // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode, + {EFUSE_BLK0, 131, 1}, // [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Set this bit to disable download through USB-Serial-JTAG, + {EFUSE_BLK0, 132, 1}, // [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, + {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., + {EFUSE_BLK0, 134, 2}, // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}, }; static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { - {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., + {EFUSE_BLK0, 136, 1}, // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}, }; static const esp_efuse_desc_t FLASH_TYPE[] = { - {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, + {EFUSE_BLK0, 137, 1}, // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}, }; static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = { - {EFUSE_BLK0, 138, 2}, // Sets the size of flash page, + {EFUSE_BLK0, 138, 2}, // [] Set Flash page size, }; static const esp_efuse_desc_t FLASH_ECC_EN[] = { - {EFUSE_BLK0, 140, 1}, // Enables ECC in Flash boot mode, + {EFUSE_BLK0, 140, 1}, // [] Set 1 to enable ECC for flash boot, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, + {EFUSE_BLK0, 141, 1}, // [] Set this bit to force ROM code to send a resume command during SPI boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, + {EFUSE_BLK0, 142, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature), }; static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 159, 1}, // Set this bit to disable download through USB-OTG, + {EFUSE_BLK0, 159, 1}, // [] Set this bit to disable download through USB-OTG, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, + {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, + {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major, }; -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, + {EFUSE_BLK1, 48, 6}, // [] SPI_PAD_configure CLK, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK1, 54, 6}, // [] SPI_PAD_configure Q(D1), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +static const esp_efuse_desc_t SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK1, 60, 6}, // [] SPI_PAD_configure D(D0), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, + {EFUSE_BLK1, 66, 6}, // [] SPI_PAD_configure CS, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK1, 72, 6}, // [] SPI_PAD_configure HD(D3), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK1, 78, 6}, // [] SPI_PAD_configure WP(D2), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, + {EFUSE_BLK1, 84, 6}, // [] SPI_PAD_configure DQS, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, + {EFUSE_BLK1, 90, 6}, // [] SPI_PAD_configure D4, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, + {EFUSE_BLK1, 96, 6}, // [] SPI_PAD_configure D5, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, + {EFUSE_BLK1, 102, 6}, // [] SPI_PAD_configure D6, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, + {EFUSE_BLK1, 108, 6}, // [] SPI_PAD_configure D7, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, - {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, +static const esp_efuse_desc_t WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK1, 114, 3}, // [] WAFER_VERSION_MINOR least significant bits, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 3}, // Package version, + {EFUSE_BLK1, 117, 3}, // [] Package version, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK1, 186, 6}, // ADC2 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 132, 9}, // Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 141, 8}, // ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 149, 8}, // ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 157, 6}, // ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 163, 6}, // ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 169, 6}, // ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 175, 8}, // ADC2 init code at atten0, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 183, 6}, // ADC2 init code at atten1, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 189, 6}, // ADC2 init code at atten2, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 195, 6}, // ADC2 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 201, 8}, // ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 209, 8}, // ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 217, 8}, // ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 225, 8}, // ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 233, 8}, // ADC2 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 241, 7}, // ADC2 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 248, 7}, // ADC2 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, -}; - -static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, -}; - -static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, -}; - -static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, -}; - -static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, -}; - -static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, -}; - -static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, -}; - -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, + {EFUSE_BLK1, 120, 3}, // [] BLK_VERSION_MINOR, }; static const esp_efuse_desc_t K_RTC_LDO[] = { - {EFUSE_BLK1, 141, 7}, // BLOCK1 K_RTC_LDO, + {EFUSE_BLK1, 141, 7}, // [] BLOCK1 K_RTC_LDO, }; static const esp_efuse_desc_t K_DIG_LDO[] = { - {EFUSE_BLK1, 148, 7}, // BLOCK1 K_DIG_LDO, + {EFUSE_BLK1, 148, 7}, // [] BLOCK1 K_DIG_LDO, }; static const esp_efuse_desc_t V_RTC_DBIAS20[] = { - {EFUSE_BLK1, 155, 8}, // BLOCK1 voltage of rtc dbias20, + {EFUSE_BLK1, 155, 8}, // [] BLOCK1 voltage of rtc dbias20, }; static const esp_efuse_desc_t V_DIG_DBIAS20[] = { - {EFUSE_BLK1, 163, 8}, // BLOCK1 voltage of digital dbias20, + {EFUSE_BLK1, 163, 8}, // [] BLOCK1 voltage of digital dbias20, }; static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { - {EFUSE_BLK1, 171, 5}, // BLOCK1 digital dbias when hvt, + {EFUSE_BLK1, 171, 5}, // [] BLOCK1 digital dbias when hvt, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK1, 183, 1}, // [] WAFER_VERSION_MINOR most significant bit, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // [] WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK1, 186, 6}, // [] ADC2 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 132, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 141, 8}, // [] ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 149, 8}, // [] ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 157, 6}, // [] ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 163, 6}, // [] ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 169, 6}, // [] ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 175, 8}, // [] ADC2 init code at atten0, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 183, 6}, // [] ADC2 init code at atten1, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 189, 6}, // [] ADC2 init code at atten2, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 195, 6}, // [] ADC2 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 201, 8}, // [] ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 209, 8}, // [] ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 217, 8}, // [] ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 225, 8}, // [] ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 233, 8}, // [] ADC2 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 241, 7}, // [] ADC2 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 248, 7}, // [] ADC2 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), }; @@ -578,12 +881,12 @@ static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection + &WR_DIS[0], // [] Disable programming of individual eFuses NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS NULL }; @@ -592,683 +895,1062 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[] = { + &WR_DIS_DIS_DCACHE[0], // [] wr_dis of DIS_DCACHE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + &WR_DIS_DIS_DOWNLOAD_DCACHE[0], // [] wr_dis of DIS_DOWNLOAD_DCACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[] = { + &WR_DIS_DIS_USB_OTG[0], // [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[] = { + &WR_DIS_DIS_APP_CPU[0], // [] wr_dis of DIS_APP_CPU + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[] = { + &WR_DIS_STRAP_JTAG_SEL[0], // [] wr_dis of STRAP_JTAG_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = { + &WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[] = { + &WR_DIS_VDD_SPI_XPD[0], // [] wr_dis of VDD_SPI_XPD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[] = { + &WR_DIS_VDD_SPI_TIEH[0], // [] wr_dis of VDD_SPI_TIEH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[] = { + &WR_DIS_VDD_SPI_FORCE[0], // [] wr_dis of VDD_SPI_FORCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[] = { + &WR_DIS_FLASH_ECC_MODE[0], // [] wr_dis of FLASH_ECC_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[] = { + &WR_DIS_PIN_POWER_SELECTION[0], // [] wr_dis of PIN_POWER_SELECTION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = { + &WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[] = { + &WR_DIS_FLASH_PAGE_SIZE[0], // [] wr_dis of FLASH_PAGE_SIZE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = { + &WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[] = { + &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[] = { + &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[] = { + &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[] = { + &WR_DIS_SPI_PAD_CONFIG_CS[0], // [] wr_dis of SPI_PAD_CONFIG_CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[] = { + &WR_DIS_SPI_PAD_CONFIG_HD[0], // [] wr_dis of SPI_PAD_CONFIG_HD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[] = { + &WR_DIS_SPI_PAD_CONFIG_WP[0], // [] wr_dis of SPI_PAD_CONFIG_WP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[] = { + &WR_DIS_SPI_PAD_CONFIG_DQS[0], // [] wr_dis of SPI_PAD_CONFIG_DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[] = { + &WR_DIS_SPI_PAD_CONFIG_D4[0], // [] wr_dis of SPI_PAD_CONFIG_D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[] = { + &WR_DIS_SPI_PAD_CONFIG_D5[0], // [] wr_dis of SPI_PAD_CONFIG_D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[] = { + &WR_DIS_SPI_PAD_CONFIG_D6[0], // [] wr_dis of SPI_PAD_CONFIG_D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[] = { + &WR_DIS_SPI_PAD_CONFIG_D7[0], // [] wr_dis of SPI_PAD_CONFIG_D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[] = { + &WR_DIS_WAFER_VERSION_MINOR_LO[0], // [] wr_dis of WAFER_VERSION_MINOR_LO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[] = { + &WR_DIS_K_RTC_LDO[0], // [] wr_dis of K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[] = { + &WR_DIS_K_DIG_LDO[0], // [] wr_dis of K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[] = { + &WR_DIS_V_RTC_DBIAS20[0], // [] wr_dis of V_RTC_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[] = { + &WR_DIS_V_DIG_DBIAS20[0], // [] wr_dis of V_DIG_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[] = { + &WR_DIS_DIG_DBIAS_HVT[0], // [] wr_dis of DIG_DBIAS_HVT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[] = { + &WR_DIS_WAFER_VERSION_MINOR_HI[0], // [] wr_dis of WAFER_VERSION_MINOR_HI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { - &WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[] = { + &WR_DIS_USB_EXT_PHY_ENABLE[0], // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection + &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache + &DIS_ICACHE[0], // [] Set this bit to disable Icache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = { - &DIS_DCACHE[0], // Disable Dcace + &DIS_DCACHE[0], // [] Set this bit to disable Dcache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_ICACHE[0], // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = { - &DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_DCACHE[0], // [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + &DIS_FORCE_DOWNLOAD[0], // [] Set this bit to disable the function that forces chip into download mode NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { - &DIS_USB[0], // Disable USB function +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[] = { + &DIS_USB_OTG[0], // [DIS_USB] Set this bit to disable USB function NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { - &DIS_CAN[0], // Disable CAN function +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [DIS_CAN] Set this bit to disable CAN function NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[] = { - &DIS_APP_CPU[0], // Disables APP CPU + &DIS_APP_CPU[0], // [] Disable app cpu NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral + &SOFT_DIS_JTAG[0], // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module NULL }; -const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = { - &HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Set this bit to disable flash encryption when in download boot modes NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins + &USB_EXCHG_PINS[0], // [] Set this bit to exchange USB D+ and D- pins NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = { - &USB_EXT_PHY_ENABLE[0], // Enable external PHY - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { - &BTLC_GPIO_ENABLE[0], // Enables BTLC GPIO + &USB_EXT_PHY_ENABLE[0], // [EXT_PHY_ENABLE] Set this bit to enable external PHY NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = { - &VDD_SPI_XPD[0], // VDD_SPI regulator power up + &VDD_SPI_XPD[0], // [] SPI regulator power up signal NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = { - &VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda + &VDD_SPI_TIEH[0], // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = { - &VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI + &VDD_SPI_FORCE[0], // [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + &WDT_DELAY_SEL[0], // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Purpose of Key0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Purpose of Key1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Purpose of Key2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Purpose of Key3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Purpose of Key4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Purpose of Key5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable + &SECURE_BOOT_EN[0], // [] Set this bit to enable secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Set this bit to enable revoking aggressive secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // Set to disable usb_serial_jtag-to-jtag function + &DIS_USB_JTAG[0], // [] Set this bit to disable function of usb switch to jtag in module of usb device NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { - &DIS_USB_SERIAL_JTAG[0], // Set to disable usb_serial_jtag module + &DIS_USB_SERIAL_JTAG[0], // [DIS_USB_DEVICE] Set this bit to disable usb device NULL }; const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[] = { - &STRAP_JTAG_SEL[0], // Enable selection between usb_to_jtag or pad_to_jtag through gpio10 + &STRAP_JTAG_SEL[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = { - &USB_PHY_SEL[0], // Select internal/external PHY for USB OTG and usb_serial_jtag + &USB_PHY_SEL[0], // [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + &FLASH_TPUW[0], // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct boot mode + &DIS_DIRECT_BOOT[0], // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Disable usb serial jtag print during rom boot + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = { - &FLASH_ECC_MODE[0], // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode + &FLASH_ECC_MODE[0], // [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Set this bit to disable download through USB-Serial-JTAG + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable secure UART download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. + &UART_PRINT_CONTROL[0], // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { - &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + &PIN_POWER_SELECTION[0], // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { - &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line + &FLASH_TYPE[0], // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = { - &FLASH_PAGE_SIZE[0], // Sets the size of flash page + &FLASH_PAGE_SIZE[0], // [] Set Flash page size NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = { - &FLASH_ECC_EN[0], // Enables ECC in Flash boot mode + &FLASH_ECC_EN[0], // [] Set 1 to enable ECC for flash boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + &FORCE_SEND_RESUME[0], // [] Set this bit to force ROM code to send a resume command during SPI boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version (used by ESP-IDF anti-rollback feature) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = { - &DIS_USB_OTG_DOWNLOAD_MODE[0], // Set this bit to disable download through USB-OTG + &DIS_USB_OTG_DOWNLOAD_MODE[0], // [] Set this bit to disable download through USB-OTG NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + &SPI_PAD_CONFIG_CLK[0], // [] SPI_PAD_configure CLK NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[] = { + &SPI_PAD_CONFIG_Q[0], // [] SPI_PAD_configure Q(D1) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[] = { + &SPI_PAD_CONFIG_D[0], // [] SPI_PAD_configure D(D0) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + &SPI_PAD_CONFIG_CS[0], // [] SPI_PAD_configure CS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[] = { + &SPI_PAD_CONFIG_HD[0], // [] SPI_PAD_configure HD(D3) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[] = { + &SPI_PAD_CONFIG_WP[0], // [] SPI_PAD_configure WP(D2) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + &SPI_PAD_CONFIG_DQS[0], // [] SPI_PAD_configure DQS NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + &SPI_PAD_CONFIG_D4[0], // [] SPI_PAD_configure D4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + &SPI_PAD_CONFIG_D5[0], // [] SPI_PAD_configure D5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + &SPI_PAD_CONFIG_D6[0], // [] SPI_PAD_configure D6 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + &SPI_PAD_CONFIG_D7[0], // [] SPI_PAD_configure D7 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits - &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[] = { + &WAFER_VERSION_MINOR_LO[0], // [] WAFER_VERSION_MINOR least significant bits NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version + &PKG_VERSION[0], // [] Package version NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[] = { - &ADC2_CAL_VOL_ATTEN3[0], // ADC2 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[] = { - &ADC2_INIT_CODE_ATTEN0[0], // ADC2 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[] = { - &ADC2_INIT_CODE_ATTEN1[0], // ADC2 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[] = { - &ADC2_INIT_CODE_ATTEN2[0], // ADC2 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[] = { - &ADC2_INIT_CODE_ATTEN3[0], // ADC2 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[] = { - &ADC2_CAL_VOL_ATTEN0[0], // ADC2 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[] = { - &ADC2_CAL_VOL_ATTEN1[0], // ADC2 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[] = { - &ADC2_CAL_VOL_ATTEN2[0], // ADC2 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { - &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + &K_RTC_LDO[0], // [] BLOCK1 K_RTC_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { - &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + &K_DIG_LDO[0], // [] BLOCK1 K_DIG_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { - &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + &V_RTC_DBIAS20[0], // [] BLOCK1 voltage of rtc dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { - &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + &V_DIG_DBIAS20[0], // [] BLOCK1 voltage of digital dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { - &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + &DIG_DBIAS_HVT[0], // [] BLOCK1 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[] = { + &WAFER_VERSION_MINOR_HI[0], // [] WAFER_VERSION_MINOR most significant bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[] = { + &ADC2_CAL_VOL_ATTEN3[0], // [] ADC2 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[] = { + &ADC2_INIT_CODE_ATTEN0[0], // [] ADC2 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[] = { + &ADC2_INIT_CODE_ATTEN1[0], // [] ADC2 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[] = { + &ADC2_INIT_CODE_ATTEN2[0], // [] ADC2 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[] = { + &ADC2_INIT_CODE_ATTEN3[0], // [] ADC2 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[] = { + &ADC2_CAL_VOL_ATTEN0[0], // [] ADC2 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[] = { + &ADC2_CAL_VOL_ATTEN1[0], // [] ADC2 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[] = { + &ADC2_CAL_VOL_ATTEN2[0], // [] ADC2 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) NULL }; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index 9d48b9d1d3..9f995a13a1 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -1,194 +1,232 @@ + # field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..256) | # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # # | EFUSE_BLK1 | | | # -# | ... | | | # -# | EFUSE_BLK10)| | | # +# | ...) | | | # ########################################################################## # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" +# After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 - WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS +# This file was generated by regtools.py based on the efuses.yaml file with the version: 6925129eca795b8b087d31be539740ec - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 - DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function - DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function - DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral - HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode - USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins - USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY - BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO - - # EFUSE_RD_REPEAT_DATA1_REG # - VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up - VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda - VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - DIS_USB_JTAG, EFUSE_BLK0, 118, 1, Set to disable usb_serial_jtag-to-jtag function - DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, Set to disable usb_serial_jtag module - STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, Enable selection between usb_to_jtag or pad_to_jtag through gpio10 - USB_PHY_SEL, EFUSE_BLK0, 121, 1, Select internal/external PHY for USB OTG and usb_serial_jtag - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot - FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Set this bit to disable download through USB-Serial-JTAG - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. - PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. - FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line - FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page - FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode - FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback - DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG - - # EFUSE_RD_REPEAT_DATA4_REG # - DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major - DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major - - -# MAC_SPI_8M_SYS BLOCK# -####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - - # RD_MAC_SPI_SYS_3 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits - , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit - # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version - BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR - - # RD_MAC_SPI_SYS_5 - # WAFER_VERSION_MINOR most significant bit - WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR - ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3 - - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - # RD_SYS_PART1_DATA0 - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - - # RD_SYS_PART1_DATA4 - BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware - TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 141, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1 - - # RD_SYS_PART1_DATA5 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3 - ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0 - ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1 - ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2 - ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3 - ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0 - ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1 - ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration - -# AUTO CONFIG DIG&RTC DBIAS# -################ -K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO -K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO -V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 -V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 -DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG +WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL +WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL +WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD +WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH +WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION +WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE +WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE +WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK +WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q +WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D +WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS +WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD +WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP +WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS +WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 +WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 +WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 +WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 +WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO +WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO +WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 +WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20 +WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT +WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3 +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE +WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 +WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 +WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 +WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 +WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0 +WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1 +WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2 +WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3 +WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 +WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 +WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 +WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 +WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0 +WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1 +WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2 +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache +DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache +DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) +DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7) +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode +DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function +DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function +DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins +USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY +VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal +VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} +VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot +DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device +DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device +STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 +USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"} +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} +FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} +PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} +FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} +FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size +FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot +FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot +SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature) +DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK +SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1) +SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0) +SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS +SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3) +SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2) +SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS +SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4 +SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5 +SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6 +SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7 +WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits +PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version +BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR +K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt +WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit +WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR +ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3 +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} +TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data +OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode +ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0 +ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1 +ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2 +ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3 +ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0 +ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1 +ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2 +ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3 +ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0 +ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1 +ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2 +ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3 +ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0 +ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1 +ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2 +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index ca89951ee0..f34fce781a 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 770b2130715648e4649be150765d72f9 +// md5_digest_table 7f80667718451ae522bb4d60ced03d49 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -20,54 +20,165 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[]; +#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; +#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[]; @@ -77,23 +188,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; @@ -105,21 +226,28 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; @@ -142,19 +270,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/components/hal/esp32/include/hal/efuse_ll.h b/components/hal/esp32/include/hal/efuse_ll.h index 9cb76f0040..17cdd2b133 100644 --- a/components/hal/esp32/include/hal/efuse_ll.h +++ b/components/hal/esp32/include/hal/efuse_ll.h @@ -23,97 +23,95 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); + return EFUSE.blk0_rdata0.rd_flash_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return REG_READ(EFUSE_BLK0_RDATA1_REG); + return EFUSE.blk0_rdata1.rd_mac; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF; + return EFUSE.blk0_rdata2.rd_mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0); + return EFUSE.blk0_rdata6.rd_abs_done_0; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1); + return EFUSE.blk0_rdata6.rd_abs_done_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE); + return EFUSE.blk0_rdata4.rd_xpd_sdio_force; } __attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG); + return EFUSE.blk0_rdata4.rd_xpd_sdio_reg; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH); + return EFUSE.blk0_rdata4.rd_xpd_sdio_tieh; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH); + return (EFUSE.blk0_rdata4.val >> 8) & 0x3; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM); + return (EFUSE.blk0_rdata4.val >> 10) & 0x3; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL); + return (EFUSE.blk0_rdata4.val >> 12) & 0x3; } __attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE); + return EFUSE.blk0_rdata3.rd_blk3_part_reserve; } __attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED); + return EFUSE.blk0_rdata3.rd_chip_cpu_freq_rated; } __attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW); + return EFUSE.blk0_rdata3.rd_chip_cpu_freq_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); - uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); - return (pkg_version_4bit << 3) | pkg_version; + return (EFUSE.blk0_rdata3.rd_chip_package_4bit << 3) | EFUSE.blk0_rdata3.rd_chip_package; } // use efuse_hal_get_major_chip_version() to get full major chip version __attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1); + return EFUSE.blk0_rdata3.rd_chip_ver_rev1; } // use efuse_hal_get_major_chip_version() to get full major chip version __attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2); + return EFUSE.blk0_rdata5.rd_chip_ver_rev2; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR); + return EFUSE.blk0_rdata5.rd_wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -123,47 +121,47 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver __attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); + return EFUSE.blk0_rdata6.rd_coding_scheme; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); + return EFUSE.blk0_rdata3.rd_disable_app_cpu; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void) { - return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT); + return EFUSE.blk0_rdata3.rd_disable_bt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV); + return EFUSE.blk0_rdata5.rd_vol_level_hp_inv; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void) { - return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF); + return EFUSE.blk0_rdata4.rd_adc_vref; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW); + return EFUSE.blk3_rdata3.rd_adc1_tp_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW); + return EFUSE.blk3_rdata3.rd_adc2_tp_low; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH); + return EFUSE.blk3_rdata3.rd_adc1_tp_high; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void) { - return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH); + return EFUSE.blk3_rdata3.rd_adc2_tp_high; } __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsigned block) @@ -171,7 +169,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi if (block == 0 || block > 4) { return false; } - uint32_t error_reg = REG_GET_FIELD(EFUSE_DEC_STATUS_REG, EFUSE_DEC_WARNINGS); + uint32_t error_reg = EFUSE.dec_status.dec_warnings; return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0; } @@ -179,42 +177,42 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi __attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void) { - return REG_READ(EFUSE_CMD_REG); + return EFUSE.cmd.val; } __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) { - REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); + EFUSE.cmd.read_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void) { - REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD); + EFUSE.cmd.pgm_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value) { - REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value); + EFUSE.dac_conf.dac_clk_div = value; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value) { - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value); + EFUSE.clk.clk_sel0 = value; } __attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value) { - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value); + EFUSE.clk.clk_sel1 = value; } /******************* eFuse control functions *************************/ diff --git a/components/hal/esp32c2/include/hal/efuse_ll.h b/components/hal/esp32c2/include/hal/efuse_ll.h index fe3a0d8217..51b5ca883d 100644 --- a/components/hal/esp32c2/include/hal/efuse_ll.h +++ b/components/hal/esp32c2/include/hal/efuse_ll.h @@ -22,7 +22,7 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return EFUSE.rd_repeat_data0.spi_boot_encrypt_decrypt_cnt; + return EFUSE.rd_repeat_data0.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) @@ -32,12 +32,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_blk2_data0.blk2_data0; + return EFUSE.rd_blk2_data0.mac; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_blk2_data1.mac_id_high; + return EFUSE.rd_blk2_data1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) @@ -85,7 +85,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) { // OCODE, EFUSE_BLK2, 62, 7, OCode - return (EFUSE.rd_blk2_data2.ocode_hi << 2) + EFUSE.rd_blk2_data1.ocode_low; + return (EFUSE.rd_blk2_data2.ocode_1 << 2) + EFUSE.rd_blk2_data1.ocode; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) @@ -109,7 +109,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_slp_d __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_dbias26(void) { // DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26 - return (EFUSE.rd_blk2_data4.dig_ldo_act_dbias26_hi << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26_low; + return (EFUSE.rd_blk2_data4.dig_ldo_act_dbias26_1 << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_stepd10(void) @@ -139,7 +139,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_slp_d __attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias31(void) { // RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31 - return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_hi << 3) + EFUSE.rd_blk2_data4.rtc_ldo_act_dbias31_low; + return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_1 << 3) + EFUSE.rd_blk2_data4.rtc_ldo_act_dbias31; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias13(void) diff --git a/components/hal/esp32c3/include/hal/efuse_ll.h b/components/hal/esp32c3/include/hal/efuse_ll.h index ee1deaf1ea..b6fcf1bb6b 100644 --- a/components/hal/esp32c3/include/hal/efuse_ll.h +++ b/components/hal/esp32c3/include/hal/efuse_ll.h @@ -32,7 +32,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_sys_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) @@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -114,7 +114,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) { // EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 - return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_hi << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20_low; + return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_1 << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) diff --git a/components/hal/esp32s2/include/hal/efuse_ll.h b/components/hal/esp32s2/include/hal/efuse_ll.h index 147bde79bf..ccfb01fb03 100644 --- a/components/hal/esp32s2/include/hal/efuse_ll.h +++ b/components/hal/esp32s2/include/hal/efuse_ll.h @@ -32,12 +32,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_8m_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_spi_8m_1.mac_1; + return EFUSE.rd_mac_spi_sys_1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) @@ -48,13 +48,13 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return EFUSE.rd_mac_spi_8m_3.wafer_version_major; + return EFUSE.rd_mac_spi_sys_3.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_3.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_4.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -64,12 +64,12 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return EFUSE.rd_mac_spi_8m_3.blk_version_major; + return EFUSE.rd_mac_spi_sys_3.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return EFUSE.rd_sys_data4.blk_version_minor; + return EFUSE.rd_sys_part1_data4.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) @@ -79,37 +79,37 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return EFUSE.rd_mac_spi_8m_4.pkg_version; + return EFUSE.rd_mac_spi_sys_4.pkg_version; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) { - return EFUSE.rd_repeat_data1.sdio_force; + return EFUSE.rd_repeat_data1.vdd_spi_force; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) { - return EFUSE.rd_repeat_data1.sdio_tieh; + return EFUSE.rd_repeat_data1.vdd_spi_tieh; } __attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void) { - return EFUSE.rd_repeat_data1.sdio_xpd; + return EFUSE.rd_repeat_data1.vdd_spi_xpd; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) { - return EFUSE.rd_repeat_data1.sdio_drefl; + return EFUSE.rd_repeat_data1.vdd_spi_drefl; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) { - return EFUSE.rd_repeat_data1.sdio_drefm; + return EFUSE.rd_repeat_data1.vdd_spi_drefm; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) { - return EFUSE.rd_repeat_data0.sdio_drefh; + return EFUSE.rd_repeat_data0.vdd_spi_drefh; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) @@ -117,7 +117,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) // OCODE1, BLOCK2, 128, 4, (#4 reg, pos 0) // OCODE2, BLOCK2, 144, 3, (#4 reg, pos 16) // OCODE = (ocode2 << 4) + ocode1 - return (EFUSE.rd_sys_data4.ocode_hi << 4) + EFUSE.rd_sys_data4.ocode_low; + return (((EFUSE.rd_sys_part1_data4.val >> 16) & 0x7) << 4) + (EFUSE.rd_sys_part1_data4.val & 0xF); } /******************* eFuse control functions *************************/ diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h index 7e2b6bb789..19bb37734a 100644 --- a/components/hal/esp32s3/include/hal/efuse_ll.h +++ b/components/hal/esp32s3/include/hal/efuse_ll.h @@ -22,32 +22,32 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt; + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - return EFUSE.rd_repeat_data1.reg_wdt_delay_sel; + return EFUSE.rd_repeat_data1.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) { - return EFUSE.rd_repeat_data3.reg_flash_type; + return EFUSE.rd_repeat_data3.flash_type; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_sys_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_spi_sys_1.reg_mac_1; + return EFUSE.rd_mac_spi_sys_1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - return EFUSE.rd_repeat_data2.reg_secure_boot_en; + return EFUSE.rd_repeat_data2.secure_boot_en; } // use efuse_hal_get_major_chip_version() to get major chip version @@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -108,7 +108,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(voi __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void) { // EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 - return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_hi << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20_low; + return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_1 << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) diff --git a/components/soc/esp32/include/soc/efuse_defs.h b/components/soc/esp32/include/soc/efuse_defs.h new file mode 100644 index 0000000000..182e5f0a20 --- /dev/null +++ b/components/soc/esp32/include/soc/efuse_defs.h @@ -0,0 +1,51 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/* Write disable bits */ +#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +/* Read disable bits for efuse blocks 1-3 */ +#define EFUSE_RD_DIS_BLK1 (1<<16) +#define EFUSE_RD_DIS_BLK2 (1<<17) +#define EFUSE_RD_DIS_BLK3 (1<<18) + +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ +#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h index f687938a52..f8c9e01806 100644 --- a/components/soc/esp32/include/soc/efuse_reg.h +++ b/components/soc/esp32/include/soc/efuse_reg.h @@ -1,1181 +1,1394 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ +#pragma once +#include +#include "soc/soc.h" +#include "efuse_defs.h" +#ifdef __cplusplus +extern "C" { +#endif -#include "soc.h" -#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ -/*description: read for flash_crypt_cnt*/ -#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F -#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) -#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F -#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 -/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: read for efuse_rd_disable*/ -#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F -#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) -#define EFUSE_RD_EFUSE_RD_DIS_V 0xF -#define EFUSE_RD_EFUSE_RD_DIS_S 16 - -/* Read disable bits for efuse blocks 1-3 */ -#define EFUSE_RD_DIS_BLK1 (1<<16) -#define EFUSE_RD_DIS_BLK2 (1<<17) -#define EFUSE_RD_DIS_BLK3 (1<<18) -/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS - in efuse block 0 -*/ -#define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) - -/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: read for efuse_wr_disable*/ -#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF -#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) -#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF +/** EFUSE_BLK0_RDATA0_REG register */ +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_RD_EFUSE_WR_DIS : R; bitpos: [15:0]; default: 0; + * read for efuse_wr_disable + */ +#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFFU +#define EFUSE_RD_EFUSE_WR_DIS_M (EFUSE_RD_EFUSE_WR_DIS_V << EFUSE_RD_EFUSE_WR_DIS_S) +#define EFUSE_RD_EFUSE_WR_DIS_V 0x0000FFFFU #define EFUSE_RD_EFUSE_WR_DIS_S 0 +/** EFUSE_RD_EFUSE_RD_DIS : R; bitpos: [19:16]; default: 0; + * read for efuse_rd_disable + */ +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000FU +#define EFUSE_RD_EFUSE_RD_DIS_M (EFUSE_RD_EFUSE_RD_DIS_V << EFUSE_RD_EFUSE_RD_DIS_S) +#define EFUSE_RD_EFUSE_RD_DIS_V 0x0000000FU +#define EFUSE_RD_EFUSE_RD_DIS_S 16 +/** EFUSE_RD_FLASH_CRYPT_CNT : R; bitpos: [26:20]; default: 0; + * read for flash_crypt_cnt + */ +#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007FU +#define EFUSE_RD_FLASH_CRYPT_CNT_M (EFUSE_RD_FLASH_CRYPT_CNT_V << EFUSE_RD_FLASH_CRYPT_CNT_S) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x0000007FU +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 +/** EFUSE_RD_UART_DOWNLOAD_DIS : R; bitpos: [27]; default: 0; + * Disable UART download mode. Valid for ESP32 V3 and newer, only + */ +#define EFUSE_RD_UART_DOWNLOAD_DIS (BIT(27)) +#define EFUSE_RD_UART_DOWNLOAD_DIS_M (EFUSE_RD_UART_DOWNLOAD_DIS_V << EFUSE_RD_UART_DOWNLOAD_DIS_S) +#define EFUSE_RD_UART_DOWNLOAD_DIS_V 0x00000001U +#define EFUSE_RD_UART_DOWNLOAD_DIS_S 27 +/** EFUSE_RESERVED_0_28 : R; bitpos: [31:28]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_28 0x0000000FU +#define EFUSE_RESERVED_0_28_M (EFUSE_RESERVED_0_28_V << EFUSE_RESERVED_0_28_S) +#define EFUSE_RESERVED_0_28_V 0x0000000FU +#define EFUSE_RESERVED_0_28_S 28 -/* Write disable bits */ -#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ -#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) -#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ -#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ -#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ -#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ -#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ -#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ -#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ -#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ -#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ -#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ +/** EFUSE_BLK0_RDATA1_REG register */ +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_RD_MAC : R; bitpos: [31:0]; default: 0; + * MAC address + */ +#define EFUSE_RD_MAC 0xFFFFFFFFU +#define EFUSE_RD_MAC_M (EFUSE_RD_MAC_V << EFUSE_RD_MAC_S) +#define EFUSE_RD_MAC_V 0xFFFFFFFFU +#define EFUSE_RD_MAC_S 0 -#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: read for low 32bit WIFI_MAC_Address*/ -#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 +/** EFUSE_BLK0_RDATA2_REG register */ +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_RD_MAC_1 : R; bitpos: [15:0]; default: 0; + * MAC address + */ +#define EFUSE_RD_MAC_1 0x0000FFFFU +#define EFUSE_RD_MAC_1_M (EFUSE_RD_MAC_1_V << EFUSE_RD_MAC_1_S) +#define EFUSE_RD_MAC_1_V 0x0000FFFFU +#define EFUSE_RD_MAC_1_S 0 +/** EFUSE_RD_MAC_CRC : R; bitpos: [23:16]; default: 0; + * CRC8 for MAC address + */ +#define EFUSE_RD_MAC_CRC 0x000000FFU +#define EFUSE_RD_MAC_CRC_M (EFUSE_RD_MAC_CRC_V << EFUSE_RD_MAC_CRC_S) +#define EFUSE_RD_MAC_CRC_V 0x000000FFU +#define EFUSE_RD_MAC_CRC_S 16 +/** EFUSE_RD_RESERVE_0_88 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_88 0x000000FFU +#define EFUSE_RD_RESERVE_0_88_M (EFUSE_RD_RESERVE_0_88_V << EFUSE_RD_RESERVE_0_88_S) +#define EFUSE_RD_RESERVE_0_88_V 0x000000FFU +#define EFUSE_RD_RESERVE_0_88_S 24 -#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: read for high 24bit WIFI_MAC_Address*/ -#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 - -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: bit is set to 1 for rev1 silicon*/ -#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) -#define EFUSE_RD_CHIP_VER_REV1_V 0x1 -#define EFUSE_RD_CHIP_VER_REV1_S 15 -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ -/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 -/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If set, the ESP32's maximum CPU frequency has been rated*/ -#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 -/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ -#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 -/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: least significant bits of chip package */ -#define EFUSE_RD_CHIP_VER_PKG 0x00000007 -#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) -#define EFUSE_RD_CHIP_VER_PKG_V 0x7 -#define EFUSE_RD_CHIP_VER_PKG_S 9 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ -#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 -/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_hd*/ -#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F +/** EFUSE_BLK0_RDATA3_REG register */ +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_RD_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ +#define EFUSE_RD_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_RD_DISABLE_APP_CPU_M (EFUSE_RD_DISABLE_APP_CPU_V << EFUSE_RD_DISABLE_APP_CPU_S) +#define EFUSE_RD_DISABLE_APP_CPU_V 0x00000001U +#define EFUSE_RD_DISABLE_APP_CPU_S 0 +/** EFUSE_RD_DISABLE_BT : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ +#define EFUSE_RD_DISABLE_BT (BIT(1)) +#define EFUSE_RD_DISABLE_BT_M (EFUSE_RD_DISABLE_BT_V << EFUSE_RD_DISABLE_BT_S) +#define EFUSE_RD_DISABLE_BT_V 0x00000001U +#define EFUSE_RD_DISABLE_BT_S 1 +/** EFUSE_RD_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ +#define EFUSE_RD_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_M (EFUSE_RD_CHIP_PACKAGE_4BIT_V << EFUSE_RD_CHIP_PACKAGE_4BIT_S) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_V 0x00000001U +#define EFUSE_RD_CHIP_PACKAGE_4BIT_S 2 +/** EFUSE_RD_DIS_CACHE : R; bitpos: [3]; default: 0; + * Disables cache + */ +#define EFUSE_RD_DIS_CACHE (BIT(3)) +#define EFUSE_RD_DIS_CACHE_M (EFUSE_RD_DIS_CACHE_V << EFUSE_RD_DIS_CACHE_S) +#define EFUSE_RD_DIS_CACHE_V 0x00000001U +#define EFUSE_RD_DIS_CACHE_S 3 +/** EFUSE_RD_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; + * read for SPI_pad_config_hd + */ +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M (EFUSE_RD_SPI_PAD_CONFIG_HD_V << EFUSE_RD_SPI_PAD_CONFIG_HD_S) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x0000001FU #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 -/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: most significant bit of chip package */ -#define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) -#define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) -#define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 -#define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 -/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 -/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 +/** EFUSE_RD_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ +#define EFUSE_RD_CHIP_PACKAGE 0x00000007U +#define EFUSE_RD_CHIP_PACKAGE_M (EFUSE_RD_CHIP_PACKAGE_V << EFUSE_RD_CHIP_PACKAGE_S) +#define EFUSE_RD_CHIP_PACKAGE_V 0x00000007U +#define EFUSE_RD_CHIP_PACKAGE_S 9 +/** EFUSE_RD_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M (EFUSE_RD_CHIP_CPU_FREQ_LOW_V << EFUSE_RD_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x00000001U +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 +/** EFUSE_RD_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ +#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M (EFUSE_RD_CHIP_CPU_FREQ_RATED_V << EFUSE_RD_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x00000001U +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 +/** EFUSE_RD_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M (EFUSE_RD_BLK3_PART_RESERVE_V << EFUSE_RD_BLK3_PART_RESERVE_S) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x00000001U +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 +/** EFUSE_RD_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M (EFUSE_RD_CHIP_VER_REV1_V << EFUSE_RD_CHIP_VER_REV1_S) +#define EFUSE_RD_CHIP_VER_REV1_V 0x00000001U +#define EFUSE_RD_CHIP_VER_REV1_S 15 +/** EFUSE_RD_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_112 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_112_M (EFUSE_RD_RESERVE_0_112_V << EFUSE_RD_RESERVE_0_112_S) +#define EFUSE_RD_RESERVE_0_112_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_112_S 16 -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: read for sdio_force*/ -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: read for SDIO_TIEH*/ -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: read for XPD_SDIO_REG*/ -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 -/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ -/*description: True ADC reference voltage */ -#define EFUSE_RD_ADC_VREF 0x0000001F -#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) -#define EFUSE_RD_ADC_VREF_V 0x1F +/** EFUSE_BLK0_RDATA4_REG register */ +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_RD_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ +#define EFUSE_RD_CLK8M_FREQ 0x000000FFU +#define EFUSE_RD_CLK8M_FREQ_M (EFUSE_RD_CLK8M_FREQ_V << EFUSE_RD_CLK8M_FREQ_S) +#define EFUSE_RD_CLK8M_FREQ_V 0x000000FFU +#define EFUSE_RD_CLK8M_FREQ_S 0 +/** EFUSE_RD_ADC_VREF : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ +#define EFUSE_RD_ADC_VREF 0x0000001FU +#define EFUSE_RD_ADC_VREF_M (EFUSE_RD_ADC_VREF_V << EFUSE_RD_ADC_VREF_S) +#define EFUSE_RD_ADC_VREF_V 0x0000001FU #define EFUSE_RD_ADC_VREF_S 8 -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer - * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore - * SDIO_DREFH/M/L is only available in older versions of ESP32 */ -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 -/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_RD_CK8M_FREQ 0x000000FF -#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) -#define EFUSE_RD_CK8M_FREQ_V 0xFF -#define EFUSE_RD_CK8M_FREQ_S 0 +/** EFUSE_RD_RESERVE_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_141 (BIT(13)) +#define EFUSE_RD_RESERVE_0_141_M (EFUSE_RD_RESERVE_0_141_V << EFUSE_RD_RESERVE_0_141_S) +#define EFUSE_RD_RESERVE_0_141_V 0x00000001U +#define EFUSE_RD_RESERVE_0_141_S 13 +/** EFUSE_RD_XPD_SDIO_REG : R; bitpos: [14]; default: 0; + * read for XPD_SDIO_REG + */ +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (EFUSE_RD_XPD_SDIO_REG_V << EFUSE_RD_XPD_SDIO_REG_S) +#define EFUSE_RD_XPD_SDIO_REG_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_REG_S 14 +/** EFUSE_RD_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ +#define EFUSE_RD_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_XPD_SDIO_TIEH_M (EFUSE_RD_XPD_SDIO_TIEH_V << EFUSE_RD_XPD_SDIO_TIEH_S) +#define EFUSE_RD_XPD_SDIO_TIEH_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_TIEH_S 15 +/** EFUSE_RD_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ +#define EFUSE_RD_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_XPD_SDIO_FORCE_M (EFUSE_RD_XPD_SDIO_FORCE_V << EFUSE_RD_XPD_SDIO_FORCE_S) +#define EFUSE_RD_XPD_SDIO_FORCE_V 0x00000001U +#define EFUSE_RD_XPD_SDIO_FORCE_S 16 +/** EFUSE_RD_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_145 0x00007FFFU +#define EFUSE_RD_RESERVE_0_145_M (EFUSE_RD_RESERVE_0_145_V << EFUSE_RD_RESERVE_0_145_S) +#define EFUSE_RD_RESERVE_0_145_V 0x00007FFFU +#define EFUSE_RD_RESERVE_0_145_S 17 -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: read for flash_crypt_config*/ -#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F -#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF -#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_RD_WAFER_VERSION_MINOR: RO; bitpos:[25:24]; */ -/*descritpion: Wafer version minor*/ -#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003 -#define EFUSE_RD_WAFER_VERSION_MINOR_M ((EFUSE_RD_WAFER_VERSION_MINOR_V)<<(EFUSE_RD_WAFER_VERSION_MINOR_S)) -#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x03 -#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ -/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. -0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */ -#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) -#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S)) -#define EFUSE_RD_CHIP_VER_REV2_V 0x1 -#define EFUSE_RD_CHIP_VER_REV2_S 20 -/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_cs0*/ -#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 -/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_d*/ -#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 -/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_q*/ -#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F -#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 -/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: read for SPI_pad_config_clk*/ -#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F +/** EFUSE_BLK0_RDATA5_REG register */ +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_RD_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; + * read for SPI_pad_config_clk + */ +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M (EFUSE_RD_SPI_PAD_CONFIG_CLK_V << EFUSE_RD_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x0000001FU #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 +/** EFUSE_RD_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; + * read for SPI_pad_config_q + */ +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M (EFUSE_RD_SPI_PAD_CONFIG_Q_V << EFUSE_RD_SPI_PAD_CONFIG_Q_S) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 +/** EFUSE_RD_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; + * read for SPI_pad_config_d + */ +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_D_M (EFUSE_RD_SPI_PAD_CONFIG_D_V << EFUSE_RD_SPI_PAD_CONFIG_D_S) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 +/** EFUSE_RD_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; + * read for SPI_pad_config_cs0 + */ +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M (EFUSE_RD_SPI_PAD_CONFIG_CS0_V << EFUSE_RD_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x0000001FU +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 +/** EFUSE_RD_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ +#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_RD_CHIP_VER_REV2_M (EFUSE_RD_CHIP_VER_REV2_V << EFUSE_RD_CHIP_VER_REV2_S) +#define EFUSE_RD_CHIP_VER_REV2_V 0x00000001U +#define EFUSE_RD_CHIP_VER_REV2_S 20 +/** EFUSE_RD_RESERVE_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_181 (BIT(21)) +#define EFUSE_RD_RESERVE_0_181_M (EFUSE_RD_RESERVE_0_181_V << EFUSE_RD_RESERVE_0_181_S) +#define EFUSE_RD_RESERVE_0_181_V 0x00000001U +#define EFUSE_RD_RESERVE_0_181_S 21 +/** EFUSE_RD_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x00000003U +#define EFUSE_RD_VOL_LEVEL_HP_INV_M (EFUSE_RD_VOL_LEVEL_HP_INV_V << EFUSE_RD_VOL_LEVEL_HP_INV_S) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x00000003U +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 +/** EFUSE_RD_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ +#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003U +#define EFUSE_RD_WAFER_VERSION_MINOR_M (EFUSE_RD_WAFER_VERSION_MINOR_V << EFUSE_RD_WAFER_VERSION_MINOR_S) +#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x00000003U +#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 +/** EFUSE_RD_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_186 0x00000003U +#define EFUSE_RD_RESERVE_0_186_M (EFUSE_RD_RESERVE_0_186_V << EFUSE_RD_RESERVE_0_186_S) +#define EFUSE_RD_RESERVE_0_186_V 0x00000003U +#define EFUSE_RD_RESERVE_0_186_S 26 +/** EFUSE_RD_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; + * read for flash_crypt_config + */ +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000FU +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M (EFUSE_RD_FLASH_CRYPT_CONFIG_V << EFUSE_RD_FLASH_CRYPT_CONFIG_S) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0x0000000FU +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: read for key_status*/ -#define EFUSE_RD_KEY_STATUS (BIT(10)) -#define EFUSE_RD_KEY_STATUS_M (BIT(10)) -#define EFUSE_RD_KEY_STATUS_V 0x1 -#define EFUSE_RD_KEY_STATUS_S 10 -/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: read for download_dis_cache*/ -#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_RD_DISABLE_DL_CACHE_S 9 -/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: read for download_dis_decrypt*/ -#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 -/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: read for download_dis_encrypt*/ -#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 -/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: read for JTAG_disable*/ -#define EFUSE_RD_DISABLE_JTAG (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_V 0x1 -#define EFUSE_RD_DISABLE_JTAG_S 6 -/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: read for abstract_done_1*/ -#define EFUSE_RD_ABS_DONE_1 (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_V 0x1 -#define EFUSE_RD_ABS_DONE_1_S 5 -/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: read for abstract_done_0*/ -#define EFUSE_RD_ABS_DONE_0 (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_V 0x1 -#define EFUSE_RD_ABS_DONE_0_S 4 -/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 -/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: read for console_debug_disable*/ -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: read for coding_scheme*/ -#define EFUSE_RD_CODING_SCHEME 0x00000003 -#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) -#define EFUSE_RD_CODING_SCHEME_V 0x3 +/** EFUSE_BLK0_RDATA6_REG register */ +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_RD_CODING_SCHEME : R; bitpos: [1:0]; default: 0; + * read for coding_scheme + */ +#define EFUSE_RD_CODING_SCHEME 0x00000003U +#define EFUSE_RD_CODING_SCHEME_M (EFUSE_RD_CODING_SCHEME_V << EFUSE_RD_CODING_SCHEME_S) +#define EFUSE_RD_CODING_SCHEME_V 0x00000003U #define EFUSE_RD_CODING_SCHEME_S 0 +/** EFUSE_RD_CONSOLE_DEBUG_DISABLE : R; bitpos: [2]; default: 0; + * read for console_debug_disable + */ +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (EFUSE_RD_CONSOLE_DEBUG_DISABLE_V << EFUSE_RD_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x00000001U +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 +/** EFUSE_RD_DISABLE_SDIO_HOST : R; bitpos: [3]; default: 0; */ +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (EFUSE_RD_DISABLE_SDIO_HOST_V << EFUSE_RD_DISABLE_SDIO_HOST_S) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x00000001U +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 +/** EFUSE_RD_ABS_DONE_0 : R; bitpos: [4]; default: 0; + * read for abstract_done_0 + */ +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (EFUSE_RD_ABS_DONE_0_V << EFUSE_RD_ABS_DONE_0_S) +#define EFUSE_RD_ABS_DONE_0_V 0x00000001U +#define EFUSE_RD_ABS_DONE_0_S 4 +/** EFUSE_RD_ABS_DONE_1 : R; bitpos: [5]; default: 0; + * read for abstract_done_1 + */ +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (EFUSE_RD_ABS_DONE_1_V << EFUSE_RD_ABS_DONE_1_S) +#define EFUSE_RD_ABS_DONE_1_V 0x00000001U +#define EFUSE_RD_ABS_DONE_1_S 5 +/** EFUSE_RD_JTAG_DISABLE : R; bitpos: [6]; default: 0; + * Disable JTAG + */ +#define EFUSE_RD_JTAG_DISABLE (BIT(6)) +#define EFUSE_RD_JTAG_DISABLE_M (EFUSE_RD_JTAG_DISABLE_V << EFUSE_RD_JTAG_DISABLE_S) +#define EFUSE_RD_JTAG_DISABLE_V 0x00000001U +#define EFUSE_RD_JTAG_DISABLE_S 6 +/** EFUSE_RD_DISABLE_DL_ENCRYPT : R; bitpos: [7]; default: 0; + * read for download_dis_encrypt + */ +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (EFUSE_RD_DISABLE_DL_ENCRYPT_V << EFUSE_RD_DISABLE_DL_ENCRYPT_S) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 +/** EFUSE_RD_DISABLE_DL_DECRYPT : R; bitpos: [8]; default: 0; + * read for download_dis_decrypt + */ +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (EFUSE_RD_DISABLE_DL_DECRYPT_V << EFUSE_RD_DISABLE_DL_DECRYPT_S) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 +/** EFUSE_RD_DISABLE_DL_CACHE : R; bitpos: [9]; default: 0; + * read for download_dis_cache + */ +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (EFUSE_RD_DISABLE_DL_CACHE_V << EFUSE_RD_DISABLE_DL_CACHE_S) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x00000001U +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 +/** EFUSE_RD_KEY_STATUS : R; bitpos: [10]; default: 0; + * read for key_status + */ +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (EFUSE_RD_KEY_STATUS_V << EFUSE_RD_KEY_STATUS_S) +#define EFUSE_RD_KEY_STATUS_V 0x00000001U +#define EFUSE_RD_KEY_STATUS_S 10 +/** EFUSE_RD_RESERVE_0_203 : RW; bitpos: [31:11]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_203 0x001FFFFFU +#define EFUSE_RD_RESERVE_0_203_M (EFUSE_RD_RESERVE_0_203_V << EFUSE_RD_RESERVE_0_203_S) +#define EFUSE_RD_RESERVE_0_203_V 0x001FFFFFU +#define EFUSE_RD_RESERVE_0_203_S 11 -#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 -#define EFUSE_CODING_SCHEME_VAL_34 0x1 -#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 - -#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) -/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ -/*description: program for flash_crypt_cnt*/ -#define EFUSE_FLASH_CRYPT_CNT 0x0000007F -#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) -#define EFUSE_FLASH_CRYPT_CNT_V 0x7F -#define EFUSE_FLASH_CRYPT_CNT_S 20 -/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: program for efuse_rd_disable*/ -#define EFUSE_RD_DIS 0x0000000F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0xF -#define EFUSE_RD_DIS_S 16 -/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: program for efuse_wr_disable*/ -#define EFUSE_WR_DIS 0x0000FFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFF +/** EFUSE_BLK0_WDATA0_REG register */ +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_WR_DIS : RW; bitpos: [15:0]; default: 0; + * program for efuse_wr_disable + */ +#define EFUSE_WR_DIS 0x0000FFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0x0000FFFFU #define EFUSE_WR_DIS_S 0 +/** EFUSE_RD_DIS : RW; bitpos: [19:16]; default: 0; + * program for efuse_rd_disable + */ +#define EFUSE_RD_DIS 0x0000000FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000000FU +#define EFUSE_RD_DIS_S 16 +/** EFUSE_FLASH_CRYPT_CNT : RW; bitpos: [26:20]; default: 0; + * program for flash_crypt_cnt + */ +#define EFUSE_FLASH_CRYPT_CNT 0x0000007FU +#define EFUSE_FLASH_CRYPT_CNT_M (EFUSE_FLASH_CRYPT_CNT_V << EFUSE_FLASH_CRYPT_CNT_S) +#define EFUSE_FLASH_CRYPT_CNT_V 0x0000007FU +#define EFUSE_FLASH_CRYPT_CNT_S 20 -#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: program for low 32bit WIFI_MAC_Address*/ -#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF -#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +/** EFUSE_BLK0_WDATA1_REG register */ +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_WIFI_MAC_CRC_LOW : RW; bitpos: [31:0]; default: 0; + * program for low 32bit WIFI_MAC_Address + */ +#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFFU +#define EFUSE_WIFI_MAC_CRC_LOW_M (EFUSE_WIFI_MAC_CRC_LOW_V << EFUSE_WIFI_MAC_CRC_LOW_S) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFFU #define EFUSE_WIFI_MAC_CRC_LOW_S 0 -#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: program for high 24bit WIFI_MAC_Address*/ -#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF -#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +/** EFUSE_BLK0_WDATA2_REG register */ +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_WIFI_MAC_CRC_HIGH : RW; bitpos: [23:0]; default: 0; + * program for high 24bit WIFI_MAC_Address + */ +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFFU +#define EFUSE_WIFI_MAC_CRC_HIGH_M (EFUSE_WIFI_MAC_CRC_HIGH_V << EFUSE_WIFI_MAC_CRC_HIGH_S) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0x00FFFFFFU #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 -#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) -#define EFUSE_CHIP_VER_REV1_V 0x1 -#define EFUSE_CHIP_VER_REV1_S 15 -/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ -/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ -#define EFUSE_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) -#define EFUSE_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_BLK3_PART_RESERVE_S 14 -/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If set, the ESP32's maximum CPU frequency has been rated*/ -#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 -/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ -#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 -/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: least significant bits of chip package */ -#define EFUSE_CHIP_VER_PKG 0x00000007 -#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) -#define EFUSE_CHIP_VER_PKG_V 0x7 -#define EFUSE_CHIP_VER_PKG_S 9 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 -#define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 -/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_hd*/ -#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F +/** EFUSE_BLK0_WDATA3_REG register */ +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ +#define EFUSE_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_DISABLE_APP_CPU_M (EFUSE_DISABLE_APP_CPU_V << EFUSE_DISABLE_APP_CPU_S) +#define EFUSE_DISABLE_APP_CPU_V 0x00000001U +#define EFUSE_DISABLE_APP_CPU_S 0 +/** EFUSE_DISABLE_BT : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ +#define EFUSE_DISABLE_BT (BIT(1)) +#define EFUSE_DISABLE_BT_M (EFUSE_DISABLE_BT_V << EFUSE_DISABLE_BT_S) +#define EFUSE_DISABLE_BT_V 0x00000001U +#define EFUSE_DISABLE_BT_S 1 +/** EFUSE_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ +#define EFUSE_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_CHIP_PACKAGE_4BIT_M (EFUSE_CHIP_PACKAGE_4BIT_V << EFUSE_CHIP_PACKAGE_4BIT_S) +#define EFUSE_CHIP_PACKAGE_4BIT_V 0x00000001U +#define EFUSE_CHIP_PACKAGE_4BIT_S 2 +/** EFUSE_DIS_CACHE : R; bitpos: [3]; default: 0; + * Disables cache + */ +#define EFUSE_DIS_CACHE (BIT(3)) +#define EFUSE_DIS_CACHE_M (EFUSE_DIS_CACHE_V << EFUSE_DIS_CACHE_S) +#define EFUSE_DIS_CACHE_V 0x00000001U +#define EFUSE_DIS_CACHE_S 3 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; + * program for SPI_pad_config_hd + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000001FU #define EFUSE_SPI_PAD_CONFIG_HD_S 4 -/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: most significant bit of chip package */ -#define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) -#define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) -#define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 -#define EFUSE_CHIP_VER_PKG_4BIT_S 2 -/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_CHIP_VER_DIS_BT_S 1 -/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 +/** EFUSE_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ +#define EFUSE_CHIP_PACKAGE 0x00000007U +#define EFUSE_CHIP_PACKAGE_M (EFUSE_CHIP_PACKAGE_V << EFUSE_CHIP_PACKAGE_S) +#define EFUSE_CHIP_PACKAGE_V 0x00000007U +#define EFUSE_CHIP_PACKAGE_S 9 +/** EFUSE_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M (EFUSE_CHIP_CPU_FREQ_LOW_V << EFUSE_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x00000001U +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 +/** EFUSE_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M (EFUSE_CHIP_CPU_FREQ_RATED_V << EFUSE_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x00000001U +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 +/** EFUSE_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M (EFUSE_BLK3_PART_RESERVE_V << EFUSE_BLK3_PART_RESERVE_S) +#define EFUSE_BLK3_PART_RESERVE_V 0x00000001U +#define EFUSE_BLK3_PART_RESERVE_S 14 +/** EFUSE_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M (EFUSE_CHIP_VER_REV1_V << EFUSE_CHIP_VER_REV1_S) +#define EFUSE_CHIP_VER_REV1_V 0x00000001U +#define EFUSE_CHIP_VER_REV1_S 15 +/** EFUSE_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_112 0x0000FFFFU +#define EFUSE_RESERVE_0_112_M (EFUSE_RESERVE_0_112_V << EFUSE_RESERVE_0_112_S) +#define EFUSE_RESERVE_0_112_V 0x0000FFFFU +#define EFUSE_RESERVE_0_112_S 16 -#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) -/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: program for sdio_force*/ -#define EFUSE_SDIO_FORCE (BIT(16)) -#define EFUSE_SDIO_FORCE_M (BIT(16)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 16 -/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: program for SDIO_TIEH*/ -#define EFUSE_SDIO_TIEH (BIT(15)) -#define EFUSE_SDIO_TIEH_M (BIT(15)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 15 -/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: program for XPD_SDIO_REG*/ -#define EFUSE_XPD_SDIO_REG (BIT(14)) -#define EFUSE_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_XPD_SDIO_REG_V 0x1 -#define EFUSE_XPD_SDIO_REG_S 14 -/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ -/*description: True ADC reference voltage */ -#define EFUSE_ADC_VREF 0x0000001F -#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) -#define EFUSE_ADC_VREF_V 0x1F +/** EFUSE_BLK0_WDATA4_REG register */ +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ +#define EFUSE_CLK8M_FREQ 0x000000FFU +#define EFUSE_CLK8M_FREQ_M (EFUSE_CLK8M_FREQ_V << EFUSE_CLK8M_FREQ_S) +#define EFUSE_CLK8M_FREQ_V 0x000000FFU +#define EFUSE_CLK8M_FREQ_S 0 +/** EFUSE_ADC_VREF : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ +#define EFUSE_ADC_VREF 0x0000001FU +#define EFUSE_ADC_VREF_M (EFUSE_ADC_VREF_V << EFUSE_ADC_VREF_S) +#define EFUSE_ADC_VREF_V 0x0000001FU #define EFUSE_ADC_VREF_S 8 -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer - * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore - * SDIO_DREFH/M/L is only available in older versions of ESP32 */ -/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 12 -/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 10 -/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 8 -/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define EFUSE_CK8M_FREQ 0x000000FF -#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) -#define EFUSE_CK8M_FREQ_V 0xFF -#define EFUSE_CK8M_FREQ_S 0 +/** EFUSE_RESERVE_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_141 (BIT(13)) +#define EFUSE_RESERVE_0_141_M (EFUSE_RESERVE_0_141_V << EFUSE_RESERVE_0_141_S) +#define EFUSE_RESERVE_0_141_V 0x00000001U +#define EFUSE_RESERVE_0_141_S 13 +/** EFUSE_XPD_SDIO_REG : R; bitpos: [14]; default: 0; + * program for XPD_SDIO_REG + */ +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (EFUSE_XPD_SDIO_REG_V << EFUSE_XPD_SDIO_REG_S) +#define EFUSE_XPD_SDIO_REG_V 0x00000001U +#define EFUSE_XPD_SDIO_REG_S 14 +/** EFUSE_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ +#define EFUSE_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_XPD_SDIO_TIEH_M (EFUSE_XPD_SDIO_TIEH_V << EFUSE_XPD_SDIO_TIEH_S) +#define EFUSE_XPD_SDIO_TIEH_V 0x00000001U +#define EFUSE_XPD_SDIO_TIEH_S 15 +/** EFUSE_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ +#define EFUSE_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_XPD_SDIO_FORCE_M (EFUSE_XPD_SDIO_FORCE_V << EFUSE_XPD_SDIO_FORCE_S) +#define EFUSE_XPD_SDIO_FORCE_V 0x00000001U +#define EFUSE_XPD_SDIO_FORCE_S 16 +/** EFUSE_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_145 0x00007FFFU +#define EFUSE_RESERVE_0_145_M (EFUSE_RESERVE_0_145_V << EFUSE_RESERVE_0_145_S) +#define EFUSE_RESERVE_0_145_V 0x00007FFFU +#define EFUSE_RESERVE_0_145_S 17 -#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: program for flash_crypt_config*/ -#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F -#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF -#define EFUSE_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ -/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) - BIT[27] is the sign bit, 0: + , 1: - - BIT[26:24] is the difference value, unit: 0.017V - volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ -#define EFUSE_DIG_VOL_L6 0x0F -#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_DIG_VOL_L6_V 0x0F -#define EFUSE_DIG_VOL_L6_S 24 -/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ -/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. -0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ -#define EFUSE_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ -/* Deprecated */ -#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ -#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ -#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ -#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ -/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_cs0*/ -#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 -/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_d*/ -#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) -#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_D_S 10 -/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_q*/ -#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F -#define EFUSE_SPI_PAD_CONFIG_Q_S 5 -/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: program for SPI_pad_config_clk*/ -#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F -#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F +/** EFUSE_BLK0_WDATA5_REG register */ +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; + * program for SPI_pad_config_clk + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000001FU #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; + * program for SPI_pad_config_q + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; + * program for SPI_pad_config_d + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_D_S 10 +/** EFUSE_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; + * program for SPI_pad_config_cs0 + */ +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CS0_M (EFUSE_SPI_PAD_CONFIG_CS0_V << EFUSE_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x0000001FU +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 +/** EFUSE_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ +#define EFUSE_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_CHIP_VER_REV2_M (EFUSE_CHIP_VER_REV2_V << EFUSE_CHIP_VER_REV2_S) +#define EFUSE_CHIP_VER_REV2_V 0x00000001U +#define EFUSE_CHIP_VER_REV2_S 20 +/** EFUSE_RESERVE_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_181 (BIT(21)) +#define EFUSE_RESERVE_0_181_M (EFUSE_RESERVE_0_181_V << EFUSE_RESERVE_0_181_S) +#define EFUSE_RESERVE_0_181_V 0x00000001U +#define EFUSE_RESERVE_0_181_S 21 +/** EFUSE_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ +#define EFUSE_VOL_LEVEL_HP_INV 0x00000003U +#define EFUSE_VOL_LEVEL_HP_INV_M (EFUSE_VOL_LEVEL_HP_INV_V << EFUSE_VOL_LEVEL_HP_INV_S) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x00000003U +#define EFUSE_VOL_LEVEL_HP_INV_S 22 +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ +#define EFUSE_WAFER_VERSION_MINOR 0x00000003U +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MINOR_S 24 +/** EFUSE_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RESERVE_0_186 0x00000003U +#define EFUSE_RESERVE_0_186_M (EFUSE_RESERVE_0_186_V << EFUSE_RESERVE_0_186_S) +#define EFUSE_RESERVE_0_186_V 0x00000003U +#define EFUSE_RESERVE_0_186_S 26 +/** EFUSE_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; + * program for flash_crypt_config + */ +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000FU +#define EFUSE_FLASH_CRYPT_CONFIG_M (EFUSE_FLASH_CRYPT_CONFIG_V << EFUSE_FLASH_CRYPT_CONFIG_S) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0x0000000FU +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 -#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: program for key_status*/ -#define EFUSE_KEY_STATUS (BIT(10)) -#define EFUSE_KEY_STATUS_M (BIT(10)) -#define EFUSE_KEY_STATUS_V 0x1 -#define EFUSE_KEY_STATUS_S 10 -/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: program for download_dis_cache*/ -#define EFUSE_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_DISABLE_DL_CACHE_S 9 -/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: program for download_dis_decrypt*/ -#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_DISABLE_DL_DECRYPT_S 8 -/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: program for download_dis_encrypt*/ -#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_DISABLE_DL_ENCRYPT_S 7 -/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: program for JTAG_disable*/ -#define EFUSE_DISABLE_JTAG (BIT(6)) -#define EFUSE_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_DISABLE_JTAG_V 0x1 -#define EFUSE_DISABLE_JTAG_S 6 -/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: program for abstract_done_1*/ -#define EFUSE_ABS_DONE_1 (BIT(5)) -#define EFUSE_ABS_DONE_1_M (BIT(5)) -#define EFUSE_ABS_DONE_1_V 0x1 -#define EFUSE_ABS_DONE_1_S 5 -/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: program for abstract_done_0*/ -#define EFUSE_ABS_DONE_0 (BIT(4)) -#define EFUSE_ABS_DONE_0_M (BIT(4)) -#define EFUSE_ABS_DONE_0_V 0x1 -#define EFUSE_ABS_DONE_0_S 4 -/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_DISABLE_SDIO_HOST_S 3 -/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: program for console_debug_disable*/ -#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: program for coding_scheme*/ -#define EFUSE_CODING_SCHEME 0x00000003 -#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) -#define EFUSE_CODING_SCHEME_V 0x3 +/** EFUSE_BLK0_WDATA6_REG register */ +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_CODING_SCHEME : RW; bitpos: [1:0]; default: 0; + * program for coding_scheme + */ +#define EFUSE_CODING_SCHEME 0x00000003U +#define EFUSE_CODING_SCHEME_M (EFUSE_CODING_SCHEME_V << EFUSE_CODING_SCHEME_S) +#define EFUSE_CODING_SCHEME_V 0x00000003U #define EFUSE_CODING_SCHEME_S 0 +/** EFUSE_CONSOLE_DEBUG_DISABLE : RW; bitpos: [2]; default: 0; + * program for console_debug_disable + */ +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (EFUSE_CONSOLE_DEBUG_DISABLE_V << EFUSE_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x00000001U +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 +/** EFUSE_DISABLE_SDIO_HOST : RW; bitpos: [3]; default: 0; */ +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (EFUSE_DISABLE_SDIO_HOST_V << EFUSE_DISABLE_SDIO_HOST_S) +#define EFUSE_DISABLE_SDIO_HOST_V 0x00000001U +#define EFUSE_DISABLE_SDIO_HOST_S 3 +/** EFUSE_ABS_DONE_0 : RW; bitpos: [4]; default: 0; + * program for abstract_done_0 + */ +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (EFUSE_ABS_DONE_0_V << EFUSE_ABS_DONE_0_S) +#define EFUSE_ABS_DONE_0_V 0x00000001U +#define EFUSE_ABS_DONE_0_S 4 +/** EFUSE_ABS_DONE_1 : RW; bitpos: [5]; default: 0; + * program for abstract_done_1 + */ +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (EFUSE_ABS_DONE_1_V << EFUSE_ABS_DONE_1_S) +#define EFUSE_ABS_DONE_1_V 0x00000001U +#define EFUSE_ABS_DONE_1_S 5 +/** EFUSE_DISABLE_JTAG : RW; bitpos: [6]; default: 0; + * program for JTAG_disable + */ +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (EFUSE_DISABLE_JTAG_V << EFUSE_DISABLE_JTAG_S) +#define EFUSE_DISABLE_JTAG_V 0x00000001U +#define EFUSE_DISABLE_JTAG_S 6 +/** EFUSE_DISABLE_DL_ENCRYPT : RW; bitpos: [7]; default: 0; + * program for download_dis_encrypt + */ +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (EFUSE_DISABLE_DL_ENCRYPT_V << EFUSE_DISABLE_DL_ENCRYPT_S) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x00000001U +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 +/** EFUSE_DISABLE_DL_DECRYPT : RW; bitpos: [8]; default: 0; + * program for download_dis_decrypt + */ +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (EFUSE_DISABLE_DL_DECRYPT_V << EFUSE_DISABLE_DL_DECRYPT_S) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x00000001U +#define EFUSE_DISABLE_DL_DECRYPT_S 8 +/** EFUSE_DISABLE_DL_CACHE : RW; bitpos: [9]; default: 0; + * program for download_dis_cache + */ +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (EFUSE_DISABLE_DL_CACHE_V << EFUSE_DISABLE_DL_CACHE_S) +#define EFUSE_DISABLE_DL_CACHE_V 0x00000001U +#define EFUSE_DISABLE_DL_CACHE_S 9 +/** EFUSE_KEY_STATUS : RW; bitpos: [10]; default: 0; + * program for key_status + */ +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (EFUSE_KEY_STATUS_V << EFUSE_KEY_STATUS_S) +#define EFUSE_KEY_STATUS_V 0x00000001U +#define EFUSE_KEY_STATUS_S 10 -#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT0 0xFFFFFFFF -#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) -#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT0_S 0 +/** EFUSE_BLK1_RDATA0_REG register */ +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_RD_BLOCK1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_M (EFUSE_RD_BLOCK1_V << EFUSE_RD_BLOCK1_S) +#define EFUSE_RD_BLOCK1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_S 0 -#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) -/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT1 0xFFFFFFFF -#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) -#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT1_S 0 +/** EFUSE_BLK1_RDATA1_REG register */ +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_RD_BLOCK1_1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_1_M (EFUSE_RD_BLOCK1_1_V << EFUSE_RD_BLOCK1_1_S) +#define EFUSE_RD_BLOCK1_1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_1_S 0 -#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT2 0xFFFFFFFF -#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) -#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT2_S 0 +/** EFUSE_BLK1_RDATA2_REG register */ +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RD_BLOCK1_2 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_2_M (EFUSE_RD_BLOCK1_2_V << EFUSE_RD_BLOCK1_2_S) +#define EFUSE_RD_BLOCK1_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_2_S 0 -#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT3 0xFFFFFFFF -#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) -#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT3_S 0 +/** EFUSE_BLK1_RDATA3_REG register */ +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_RD_BLOCK1_3 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_3 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_3_M (EFUSE_RD_BLOCK1_3_V << EFUSE_RD_BLOCK1_3_S) +#define EFUSE_RD_BLOCK1_3_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_3_S 0 -#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT4 0xFFFFFFFF -#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) -#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT4_S 0 +/** EFUSE_BLK1_RDATA4_REG register */ +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_RD_BLOCK1_4 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_4 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_4_M (EFUSE_RD_BLOCK1_4_V << EFUSE_RD_BLOCK1_4_S) +#define EFUSE_RD_BLOCK1_4_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_4_S 0 -#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) -/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT5 0xFFFFFFFF -#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) -#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT5_S 0 +/** EFUSE_BLK1_RDATA5_REG register */ +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_RD_BLOCK1_5 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_5 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_5_M (EFUSE_RD_BLOCK1_5_V << EFUSE_RD_BLOCK1_5_S) +#define EFUSE_RD_BLOCK1_5_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_5_S 0 -#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT6 0xFFFFFFFF -#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) -#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT6_S 0 +/** EFUSE_BLK1_RDATA6_REG register */ +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_RD_BLOCK1_6 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_6 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_6_M (EFUSE_RD_BLOCK1_6_V << EFUSE_RD_BLOCK1_6_S) +#define EFUSE_RD_BLOCK1_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_6_S 0 -#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK1*/ -#define EFUSE_BLK1_DOUT7 0xFFFFFFFF -#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) -#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK1_DOUT7_S 0 +/** EFUSE_BLK1_RDATA7_REG register */ +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RD_BLOCK1_7 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ +#define EFUSE_RD_BLOCK1_7 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_7_M (EFUSE_RD_BLOCK1_7_V << EFUSE_RD_BLOCK1_7_S) +#define EFUSE_RD_BLOCK1_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK1_7_S 0 -#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT0 0xFFFFFFFF -#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) -#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT0_S 0 +/** EFUSE_BLK2_RDATA0_REG register */ +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_RD_BLOCK2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_M (EFUSE_RD_BLOCK2_V << EFUSE_RD_BLOCK2_S) +#define EFUSE_RD_BLOCK2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_S 0 -#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) -/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT1 0xFFFFFFFF -#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) -#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT1_S 0 +/** EFUSE_BLK2_RDATA1_REG register */ +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_RD_BLOCK2_1 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_1 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_1_M (EFUSE_RD_BLOCK2_1_V << EFUSE_RD_BLOCK2_1_S) +#define EFUSE_RD_BLOCK2_1_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_1_S 0 -#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT2 0xFFFFFFFF -#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) -#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT2_S 0 +/** EFUSE_BLK2_RDATA2_REG register */ +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_RD_BLOCK2_2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_2 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_2_M (EFUSE_RD_BLOCK2_2_V << EFUSE_RD_BLOCK2_2_S) +#define EFUSE_RD_BLOCK2_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_2_S 0 -#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT3 0xFFFFFFFF -#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) -#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT3_S 0 +/** EFUSE_BLK2_RDATA3_REG register */ +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_RD_BLOCK2_3 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_3 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_3_M (EFUSE_RD_BLOCK2_3_V << EFUSE_RD_BLOCK2_3_S) +#define EFUSE_RD_BLOCK2_3_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_3_S 0 -#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT4 0xFFFFFFFF -#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) -#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT4_S 0 +/** EFUSE_BLK2_RDATA4_REG register */ +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_RD_BLOCK2_4 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_4 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_4_M (EFUSE_RD_BLOCK2_4_V << EFUSE_RD_BLOCK2_4_S) +#define EFUSE_RD_BLOCK2_4_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_4_S 0 -#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) -/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT5 0xFFFFFFFF -#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) -#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT5_S 0 +/** EFUSE_BLK2_RDATA5_REG register */ +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_RD_BLOCK2_5 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_5 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_5_M (EFUSE_RD_BLOCK2_5_V << EFUSE_RD_BLOCK2_5_S) +#define EFUSE_RD_BLOCK2_5_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_5_S 0 -#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT6 0xFFFFFFFF -#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) -#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT6_S 0 +/** EFUSE_BLK2_RDATA6_REG register */ +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_RD_BLOCK2_6 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_6 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_6_M (EFUSE_RD_BLOCK2_6_V << EFUSE_RD_BLOCK2_6_S) +#define EFUSE_RD_BLOCK2_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_6_S 0 -#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK2*/ -#define EFUSE_BLK2_DOUT7 0xFFFFFFFF -#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) -#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK2_DOUT7_S 0 +/** EFUSE_BLK2_RDATA7_REG register */ +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_RD_BLOCK2_7 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ +#define EFUSE_RD_BLOCK2_7 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_7_M (EFUSE_RD_BLOCK2_7_V << EFUSE_RD_BLOCK2_7_S) +#define EFUSE_RD_BLOCK2_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLOCK2_7_S 0 -#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT0 0xFFFFFFFF -#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) -#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT0_S 0 +/** EFUSE_BLK3_RDATA0_REG register */ +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_RD_CUSTOM_MAC_CRC : R; bitpos: [7:0]; default: 0; + * CRC8 for custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC_CRC 0x000000FFU +#define EFUSE_RD_CUSTOM_MAC_CRC_M (EFUSE_RD_CUSTOM_MAC_CRC_V << EFUSE_RD_CUSTOM_MAC_CRC_S) +#define EFUSE_RD_CUSTOM_MAC_CRC_V 0x000000FFU +#define EFUSE_RD_CUSTOM_MAC_CRC_S 0 +/** EFUSE_RD_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_M (EFUSE_RD_CUSTOM_MAC_V << EFUSE_RD_CUSTOM_MAC_S) +#define EFUSE_RD_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_S 8 -#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) -/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT1 0xFFFFFFFF -#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) -#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT1_S 0 +/** EFUSE_BLK3_RDATA1_REG register */ +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_RD_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ +#define EFUSE_RD_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_1_M (EFUSE_RD_CUSTOM_MAC_1_V << EFUSE_RD_CUSTOM_MAC_1_S) +#define EFUSE_RD_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_RD_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_56 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_56 0x000000FFU +#define EFUSE_RESERVED_3_56_M (EFUSE_RESERVED_3_56_V << EFUSE_RESERVED_3_56_S) +#define EFUSE_RESERVED_3_56_V 0x000000FFU +#define EFUSE_RESERVED_3_56_S 24 -#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT2 0xFFFFFFFF -#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) -#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT2_S 0 +/** EFUSE_BLK3_RDATA2_REG register */ +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_RD_BLK3_RESERVED_2 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_2 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_2_M (EFUSE_RD_BLK3_RESERVED_2_V << EFUSE_RD_BLK3_RESERVED_2_S) +#define EFUSE_RD_BLK3_RESERVED_2_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_2_S 0 -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration - * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ -#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT3 0xFFFFFFFF -#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) -#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT3_S 0 -/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ -/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC2_TP_HIGH 0x1FF -#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) -#define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF -#define EFUSE_RD_ADC2_TP_HIGH_S 23 -/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ -/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC2_TP_LOW 0x7F -#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) -#define EFUSE_RD_ADC2_TP_LOW_V 0x7F -#define EFUSE_RD_ADC2_TP_LOW_S 16 -/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ -/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC1_TP_HIGH 0x1FF -#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) -#define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF -#define EFUSE_RD_ADC1_TP_HIGH_S 7 -/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ -/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_ADC1_TP_LOW 0x7F -#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) -#define EFUSE_RD_ADC1_TP_LOW_V 0x7F +/** EFUSE_BLK3_RDATA3_REG register */ +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_RD_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC1_TP_LOW 0x0000007FU +#define EFUSE_RD_ADC1_TP_LOW_M (EFUSE_RD_ADC1_TP_LOW_V << EFUSE_RD_ADC1_TP_LOW_S) +#define EFUSE_RD_ADC1_TP_LOW_V 0x0000007FU #define EFUSE_RD_ADC1_TP_LOW_S 0 +/** EFUSE_RD_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC1_TP_HIGH 0x000001FFU +#define EFUSE_RD_ADC1_TP_HIGH_M (EFUSE_RD_ADC1_TP_HIGH_V << EFUSE_RD_ADC1_TP_HIGH_S) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x000001FFU +#define EFUSE_RD_ADC1_TP_HIGH_S 7 +/** EFUSE_RD_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC2_TP_LOW 0x0000007FU +#define EFUSE_RD_ADC2_TP_LOW_M (EFUSE_RD_ADC2_TP_LOW_V << EFUSE_RD_ADC2_TP_LOW_S) +#define EFUSE_RD_ADC2_TP_LOW_V 0x0000007FU +#define EFUSE_RD_ADC2_TP_LOW_S 16 +/** EFUSE_RD_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_RD_ADC2_TP_HIGH 0x000001FFU +#define EFUSE_RD_ADC2_TP_HIGH_M (EFUSE_RD_ADC2_TP_HIGH_V << EFUSE_RD_ADC2_TP_HIGH_S) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x000001FFU +#define EFUSE_RD_ADC2_TP_HIGH_S 23 -#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT4 0xFFFFFFFF -#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) -#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT4_S 0 -/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ -/*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_RD_CAL_RESERVED 0x0000FFFF -#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) -#define EFUSE_RD_CAL_RESERVED_V 0xFFFF -#define EFUSE_RD_CAL_RESERVED_S 0 +/** EFUSE_BLK3_RDATA4_REG register */ +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_RD_SECURE_VERSION : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ +#define EFUSE_RD_SECURE_VERSION 0xFFFFFFFFU +#define EFUSE_RD_SECURE_VERSION_M (EFUSE_RD_SECURE_VERSION_V << EFUSE_RD_SECURE_VERSION_S) +#define EFUSE_RD_SECURE_VERSION_V 0xFFFFFFFFU +#define EFUSE_RD_SECURE_VERSION_S 0 -#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) -/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT5 0xFFFFFFFF -#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) -#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT5_S 0 +/** EFUSE_BLK3_RDATA5_REG register */ +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_RESERVED_3_160 : R; bitpos: [23:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_160 0x00FFFFFFU +#define EFUSE_RESERVED_3_160_M (EFUSE_RESERVED_3_160_V << EFUSE_RESERVED_3_160_S) +#define EFUSE_RESERVED_3_160_V 0x00FFFFFFU +#define EFUSE_RESERVED_3_160_S 0 +/** EFUSE_RD_MAC_VERSION : R; bitpos: [31:24]; default: 0; + * Custom MAC version + */ +#define EFUSE_RD_MAC_VERSION 0x000000FFU +#define EFUSE_RD_MAC_VERSION_M (EFUSE_RD_MAC_VERSION_V << EFUSE_RD_MAC_VERSION_S) +#define EFUSE_RD_MAC_VERSION_V 0x000000FFU +#define EFUSE_RD_MAC_VERSION_S 24 -#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT6 0xFFFFFFFF -#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) -#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT6_S 0 +/** EFUSE_BLK3_RDATA6_REG register */ +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_RD_BLK3_RESERVED_6 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_6 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_6_M (EFUSE_RD_BLK3_RESERVED_6_V << EFUSE_RD_BLK3_RESERVED_6_S) +#define EFUSE_RD_BLK3_RESERVED_6_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_6_S 0 -#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: read for BLOCK3*/ -#define EFUSE_BLK3_DOUT7 0xFFFFFFFF -#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) -#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF -#define EFUSE_BLK3_DOUT7_S 0 +/** EFUSE_BLK3_RDATA7_REG register */ +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RD_BLK3_RESERVED_7 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ +#define EFUSE_RD_BLK3_RESERVED_7 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_7_M (EFUSE_RD_BLK3_RESERVED_7_V << EFUSE_RD_BLK3_RESERVED_7_S) +#define EFUSE_RD_BLK3_RESERVED_7_V 0xFFFFFFFFU +#define EFUSE_RD_BLK3_RESERVED_7_S 0 -#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN0 0xFFFFFFFF -#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) -#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA0_REG register */ +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_BLK1_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN0 0xFFFFFFFFU +#define EFUSE_BLK1_DIN0_M (EFUSE_BLK1_DIN0_V << EFUSE_BLK1_DIN0_S) +#define EFUSE_BLK1_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN0_S 0 -#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) -/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN1 0xFFFFFFFF -#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) -#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA1_REG register */ +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_BLK1_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN1 0xFFFFFFFFU +#define EFUSE_BLK1_DIN1_M (EFUSE_BLK1_DIN1_V << EFUSE_BLK1_DIN1_S) +#define EFUSE_BLK1_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN1_S 0 -#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) -/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN2 0xFFFFFFFF -#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) -#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA2_REG register */ +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_BLK1_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN2 0xFFFFFFFFU +#define EFUSE_BLK1_DIN2_M (EFUSE_BLK1_DIN2_V << EFUSE_BLK1_DIN2_S) +#define EFUSE_BLK1_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN2_S 0 -#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) -/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN3 0xFFFFFFFF -#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) -#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA3_REG register */ +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_BLK1_DIN3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN3 0xFFFFFFFFU +#define EFUSE_BLK1_DIN3_M (EFUSE_BLK1_DIN3_V << EFUSE_BLK1_DIN3_S) +#define EFUSE_BLK1_DIN3_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN3_S 0 -#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) -/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN4 0xFFFFFFFF -#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) -#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA4_REG register */ +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_BLK1_DIN4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN4 0xFFFFFFFFU +#define EFUSE_BLK1_DIN4_M (EFUSE_BLK1_DIN4_V << EFUSE_BLK1_DIN4_S) +#define EFUSE_BLK1_DIN4_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN4_S 0 -#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) -/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN5 0xFFFFFFFF -#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) -#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA5_REG register */ +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_BLK1_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN5 0xFFFFFFFFU +#define EFUSE_BLK1_DIN5_M (EFUSE_BLK1_DIN5_V << EFUSE_BLK1_DIN5_S) +#define EFUSE_BLK1_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN5_S 0 -#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) -/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN6 0xFFFFFFFF -#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) -#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA6_REG register */ +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_BLK1_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN6 0xFFFFFFFFU +#define EFUSE_BLK1_DIN6_M (EFUSE_BLK1_DIN6_V << EFUSE_BLK1_DIN6_S) +#define EFUSE_BLK1_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN6_S 0 -#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) -/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK1*/ -#define EFUSE_BLK1_DIN7 0xFFFFFFFF -#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) -#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK1_WDATA7_REG register */ +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_BLK1_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ +#define EFUSE_BLK1_DIN7 0xFFFFFFFFU +#define EFUSE_BLK1_DIN7_M (EFUSE_BLK1_DIN7_V << EFUSE_BLK1_DIN7_S) +#define EFUSE_BLK1_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK1_DIN7_S 0 -#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) -/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN0 0xFFFFFFFF -#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) -#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA0_REG register */ +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_BLK2_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN0 0xFFFFFFFFU +#define EFUSE_BLK2_DIN0_M (EFUSE_BLK2_DIN0_V << EFUSE_BLK2_DIN0_S) +#define EFUSE_BLK2_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN0_S 0 -#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) -/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN1 0xFFFFFFFF -#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) -#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA1_REG register */ +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_BLK2_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN1 0xFFFFFFFFU +#define EFUSE_BLK2_DIN1_M (EFUSE_BLK2_DIN1_V << EFUSE_BLK2_DIN1_S) +#define EFUSE_BLK2_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN1_S 0 -#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) -/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN2 0xFFFFFFFF -#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) -#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA2_REG register */ +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_BLK2_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN2 0xFFFFFFFFU +#define EFUSE_BLK2_DIN2_M (EFUSE_BLK2_DIN2_V << EFUSE_BLK2_DIN2_S) +#define EFUSE_BLK2_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN2_S 0 -#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) -/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN3 0xFFFFFFFF -#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) -#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA3_REG register */ +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_BLK2_DIN3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN3 0xFFFFFFFFU +#define EFUSE_BLK2_DIN3_M (EFUSE_BLK2_DIN3_V << EFUSE_BLK2_DIN3_S) +#define EFUSE_BLK2_DIN3_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN3_S 0 -#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) -/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN4 0xFFFFFFFF -#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) -#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA4_REG register */ +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_BLK2_DIN4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN4 0xFFFFFFFFU +#define EFUSE_BLK2_DIN4_M (EFUSE_BLK2_DIN4_V << EFUSE_BLK2_DIN4_S) +#define EFUSE_BLK2_DIN4_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN4_S 0 -#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) -/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN5 0xFFFFFFFF -#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) -#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA5_REG register */ +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_BLK2_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN5 0xFFFFFFFFU +#define EFUSE_BLK2_DIN5_M (EFUSE_BLK2_DIN5_V << EFUSE_BLK2_DIN5_S) +#define EFUSE_BLK2_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN5_S 0 -#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) -/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN6 0xFFFFFFFF -#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) -#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA6_REG register */ +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_BLK2_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN6 0xFFFFFFFFU +#define EFUSE_BLK2_DIN6_M (EFUSE_BLK2_DIN6_V << EFUSE_BLK2_DIN6_S) +#define EFUSE_BLK2_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN6_S 0 -#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) -/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK2*/ -#define EFUSE_BLK2_DIN7 0xFFFFFFFF -#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) -#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK2_WDATA7_REG register */ +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_BLK2_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ +#define EFUSE_BLK2_DIN7 0xFFFFFFFFU +#define EFUSE_BLK2_DIN7_M (EFUSE_BLK2_DIN7_V << EFUSE_BLK2_DIN7_S) +#define EFUSE_BLK2_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK2_DIN7_S 0 -#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) -/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN0 0xFFFFFFFF -#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) -#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA0_REG register */ +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_BLK3_DIN0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN0 0xFFFFFFFFU +#define EFUSE_BLK3_DIN0_M (EFUSE_BLK3_DIN0_V << EFUSE_BLK3_DIN0_S) +#define EFUSE_BLK3_DIN0_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN0_S 0 -#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) -/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN1 0xFFFFFFFF -#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) -#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA1_REG register */ +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_BLK3_DIN1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN1 0xFFFFFFFFU +#define EFUSE_BLK3_DIN1_M (EFUSE_BLK3_DIN1_V << EFUSE_BLK3_DIN1_S) +#define EFUSE_BLK3_DIN1_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN1_S 0 -#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) -/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN2 0xFFFFFFFF -#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) -#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA2_REG register */ +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_BLK3_DIN2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN2 0xFFFFFFFFU +#define EFUSE_BLK3_DIN2_M (EFUSE_BLK3_DIN2_V << EFUSE_BLK3_DIN2_S) +#define EFUSE_BLK3_DIN2_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN2_S 0 -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration - * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ -#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) -/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN3 0xFFFFFFFF -#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) -#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF -#define EFUSE_BLK3_DIN3_S 0 -/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ -/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC2_TP_HIGH 0x1FF -#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) -#define EFUSE_ADC2_TP_HIGH_V 0x1FF -#define EFUSE_ADC2_TP_HIGH_S 23 -/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ -/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC2_TP_LOW 0x7F -#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) -#define EFUSE_ADC2_TP_LOW_V 0x7F -#define EFUSE_ADC2_TP_LOW_S 16 -/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ -/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC1_TP_HIGH 0x1FF -#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) -#define EFUSE_ADC1_TP_HIGH_V 0x1FF -#define EFUSE_ADC1_TP_HIGH_S 7 -/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ -/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ -#define EFUSE_ADC1_TP_LOW 0x7F -#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) -#define EFUSE_ADC1_TP_LOW_V 0x7F +/** EFUSE_BLK3_WDATA3_REG register */ +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC1_TP_LOW 0x0000007FU +#define EFUSE_ADC1_TP_LOW_M (EFUSE_ADC1_TP_LOW_V << EFUSE_ADC1_TP_LOW_S) +#define EFUSE_ADC1_TP_LOW_V 0x0000007FU #define EFUSE_ADC1_TP_LOW_S 0 +/** EFUSE_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC1_TP_HIGH 0x000001FFU +#define EFUSE_ADC1_TP_HIGH_M (EFUSE_ADC1_TP_HIGH_V << EFUSE_ADC1_TP_HIGH_S) +#define EFUSE_ADC1_TP_HIGH_V 0x000001FFU +#define EFUSE_ADC1_TP_HIGH_S 7 +/** EFUSE_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC2_TP_LOW 0x0000007FU +#define EFUSE_ADC2_TP_LOW_M (EFUSE_ADC2_TP_LOW_V << EFUSE_ADC2_TP_LOW_S) +#define EFUSE_ADC2_TP_LOW_V 0x0000007FU +#define EFUSE_ADC2_TP_LOW_S 16 +/** EFUSE_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ +#define EFUSE_ADC2_TP_HIGH 0x000001FFU +#define EFUSE_ADC2_TP_HIGH_M (EFUSE_ADC2_TP_HIGH_V << EFUSE_ADC2_TP_HIGH_S) +#define EFUSE_ADC2_TP_HIGH_V 0x000001FFU +#define EFUSE_ADC2_TP_HIGH_S 23 -#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) -/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN4 0xFFFFFFFF -#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) -#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF -#define EFUSE_BLK3_DIN4_S 0 -/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ -/*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ -#define EFUSE_CAL_RESERVED 0x0000FFFF -#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) -#define EFUSE_CAL_RESERVED_V 0xFFFF -#define EFUSE_CAL_RESERVED_S 0 +/** EFUSE_BLK3_WDATA4_REG register */ +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_SECURE_VERSION : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ +#define EFUSE_SECURE_VERSION 0xFFFFFFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0xFFFFFFFFU +#define EFUSE_SECURE_VERSION_S 0 -#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) -/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN5 0xFFFFFFFF -#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) -#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA5_REG register */ +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_BLK3_DIN5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN5 0xFFFFFFFFU +#define EFUSE_BLK3_DIN5_M (EFUSE_BLK3_DIN5_V << EFUSE_BLK3_DIN5_S) +#define EFUSE_BLK3_DIN5_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN5_S 0 -#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) -/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN6 0xFFFFFFFF -#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) -#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA6_REG register */ +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_BLK3_DIN6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN6 0xFFFFFFFFU +#define EFUSE_BLK3_DIN6_M (EFUSE_BLK3_DIN6_V << EFUSE_BLK3_DIN6_S) +#define EFUSE_BLK3_DIN6_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN6_S 0 -#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) -/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: program for BLOCK3*/ -#define EFUSE_BLK3_DIN7 0xFFFFFFFF -#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) -#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF +/** EFUSE_BLK3_WDATA7_REG register */ +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_BLK3_DIN7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ +#define EFUSE_BLK3_DIN7 0xFFFFFFFFU +#define EFUSE_BLK3_DIN7_M (EFUSE_BLK3_DIN7_V << EFUSE_BLK3_DIN7_S) +#define EFUSE_BLK3_DIN7_V 0xFFFFFFFFU #define EFUSE_BLK3_DIN7_S 0 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ -/*description: efuse timing configure*/ -#define EFUSE_CLK_SEL1 0x000000FF -#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) -#define EFUSE_CLK_SEL1_V 0xFF -#define EFUSE_CLK_SEL1_S 8 -/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ -/*description: efuse timing configure*/ -#define EFUSE_CLK_SEL0 0x000000FF -#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) -#define EFUSE_CLK_SEL0_V 0xFF +/** EFUSE_CLK_REG register */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_CLK_SEL0 : RW; bitpos: [7:0]; default: 82; + * efuse timing configure + */ +#define EFUSE_CLK_SEL0 0x000000FFU +#define EFUSE_CLK_SEL0_M (EFUSE_CLK_SEL0_V << EFUSE_CLK_SEL0_S) +#define EFUSE_CLK_SEL0_V 0x000000FFU #define EFUSE_CLK_SEL0_S 0 +/** EFUSE_CLK_SEL1 : RW; bitpos: [15:8]; default: 64; + * efuse timing configure + */ +#define EFUSE_CLK_SEL1 0x000000FFU +#define EFUSE_CLK_SEL1_M (EFUSE_CLK_SEL1_V << EFUSE_CLK_SEL1_S) +#define EFUSE_CLK_SEL1_V 0x000000FFU +#define EFUSE_CLK_SEL1_S 8 +/** EFUSE_CLK_EN : RW; bitpos: [16]; default: 0; */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) -/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: */ -#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 -#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: efuse operation code*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_OP_CODE : RW; bitpos: [15:0]; default: 0; + * efuse operation code + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 +/** EFUSE_FORCE_NO_WR_RD_DIS : RW; bitpos: [16]; default: 1; */ +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (EFUSE_FORCE_NO_WR_RD_DIS_V << EFUSE_FORCE_NO_WR_RD_DIS_S) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x00000001U +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_DEBUG 0xFFFFFFFF -#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) -#define EFUSE_DEBUG_V 0xFFFFFFFF +/** EFUSE_STATUS_REG register */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_DEBUG : R; bitpos: [31:0]; default: 0; */ +#define EFUSE_DEBUG 0xFFFFFFFFU +#define EFUSE_DEBUG_M (EFUSE_DEBUG_V << EFUSE_DEBUG_S) +#define EFUSE_DEBUG_V 0xFFFFFFFFU #define EFUSE_DEBUG_S 0 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: command for program*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: command for read*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_READ_CMD : RW; bitpos: [0]; default: 0; + * command for read + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : RW; bitpos: [1]; default: 0; + * command for program + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt raw status*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt raw status*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_READ_DONE_INT_RAW : R; bitpos: [0]; default: 0; + * read done interrupt raw status + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R; bitpos: [1]; default: 0; + * program done interrupt raw status + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt status*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt status*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_READ_DONE_INT_ST : R; bitpos: [0]; default: 0; + * read done interrupt status + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : R; bitpos: [1]; default: 0; + * program done interrupt status + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt enable*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt enable*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_READ_DONE_INT_ENA : RW; bitpos: [0]; default: 0; + * read done interrupt enable + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : RW; bitpos: [1]; default: 0; + * program done interrupt enable + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program done interrupt clear*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: read done interrupt clear*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_READ_DONE_INT_CLR : W; bitpos: [0]; default: 0; + * read done interrupt clear + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : W; bitpos: [1]; default: 0; + * program done interrupt clear + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ -/*description: efuse timing configure*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_DAC_CLK_DIV : RW; bitpos: [7:0]; default: 40; + * efuse timing configure + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : RW; bitpos: [8]; default: 0; */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 -#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) -/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ -/*description: the decode result of 3/4 coding scheme has warning*/ -#define EFUSE_DEC_WARNINGS 0x00000FFF -#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) -#define EFUSE_DEC_WARNINGS_V 0xFFF +/** EFUSE_DEC_STATUS_REG register */ +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_DEC_WARNINGS : R; bitpos: [11:0]; default: 0; + * the decode result of 3/4 coding scheme has warning + */ +#define EFUSE_DEC_WARNINGS 0x00000FFFU +#define EFUSE_DEC_WARNINGS_M (EFUSE_DEC_WARNINGS_V << EFUSE_DEC_WARNINGS_S) +#define EFUSE_DEC_WARNINGS_V 0x00000FFFU #define EFUSE_DEC_WARNINGS_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ -/*description: */ -#define EFUSE_DATE 0xFFFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFFF +/** EFUSE_DATE_REG register */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : RW; bitpos: [31:0]; default: 369370624; */ +#define EFUSE_DATE 0xFFFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xFFFFFFFFU #define EFUSE_DATE_S 0 - - - -#endif /*_SOC_EFUSE_REG_H_ */ +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/efuse_struct.h b/components/soc/esp32/include/soc/efuse_struct.h index 246572e40f..f8d78500a3 100644 --- a/components/soc/esp32/include/soc/efuse_struct.h +++ b/components/soc/esp32/include/soc/efuse_struct.h @@ -1,106 +1,1276 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ +#pragma once -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t blk0_rdata0; - uint32_t blk0_rdata1; - uint32_t blk0_rdata2; - uint32_t blk0_rdata3; - uint32_t blk0_rdata4; - uint32_t blk0_rdata5; - uint32_t blk0_rdata6; +/** Type of blk0_rdata0 register */ +typedef union { + struct { + /** rd_efuse_wr_dis : R; bitpos: [15:0]; default: 0; + * read for efuse_wr_disable + */ + uint32_t rd_efuse_wr_dis:16; + /** rd_efuse_rd_dis : R; bitpos: [19:16]; default: 0; + * read for efuse_rd_disable + */ + uint32_t rd_efuse_rd_dis:4; + /** rd_flash_crypt_cnt : R; bitpos: [26:20]; default: 0; + * read for flash_crypt_cnt + */ + uint32_t rd_flash_crypt_cnt:7; + /** rd_uart_download_dis : R; bitpos: [27]; default: 0; + * Disable UART download mode. Valid for ESP32 V3 and newer, only + */ + uint32_t rd_uart_download_dis:1; + /** reserved_0_28 : R; bitpos: [31:28]; default: 0; + * reserved + */ + uint32_t reserved_0_28:4; + }; + uint32_t val; +} efuse_blk0_rdata0_reg_t; - uint32_t blk0_wdata0; - uint32_t blk0_wdata1; - uint32_t blk0_wdata2; - uint32_t blk0_wdata3; - uint32_t blk0_wdata4; - uint32_t blk0_wdata5; - uint32_t blk0_wdata6; +/** Type of blk0_rdata1 register */ +typedef union { + struct { + /** rd_mac : R; bitpos: [31:0]; default: 0; + * MAC address + */ + uint32_t rd_mac:32; + }; + uint32_t val; +} efuse_blk0_rdata1_reg_t; - uint32_t blk1_rdata0; - uint32_t blk1_rdata1; - uint32_t blk1_rdata2; - uint32_t blk1_rdata3; - uint32_t blk1_rdata4; - uint32_t blk1_rdata5; - uint32_t blk1_rdata6; - uint32_t blk1_rdata7; +/** Type of blk0_rdata2 register */ +typedef union { + struct { + /** rd_mac_1 : R; bitpos: [15:0]; default: 0; + * MAC address + */ + uint32_t rd_mac_1:16; + /** rd_mac_crc : R; bitpos: [23:16]; default: 0; + * CRC8 for MAC address + */ + uint32_t rd_mac_crc:8; + /** rd_reserve_0_88 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_88:8; + }; + uint32_t val; +} efuse_blk0_rdata2_reg_t; - uint32_t blk2_rdata0; - uint32_t blk2_rdata1; - uint32_t blk2_rdata2; - uint32_t blk2_rdata3; - uint32_t blk2_rdata4; - uint32_t blk2_rdata5; - uint32_t blk2_rdata6; - uint32_t blk2_rdata7; +/** Type of blk0_rdata3 register */ +typedef union { + struct { + /** rd_disable_app_cpu : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ + uint32_t rd_disable_app_cpu:1; + /** rd_disable_bt : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ + uint32_t rd_disable_bt:1; + /** rd_chip_package_4bit : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ + uint32_t rd_chip_package_4bit:1; + /** rd_dis_cache : R; bitpos: [3]; default: 0; + * Disables cache + */ + uint32_t rd_dis_cache:1; + /** rd_spi_pad_config_hd : R; bitpos: [8:4]; default: 0; + * read for SPI_pad_config_hd + */ + uint32_t rd_spi_pad_config_hd:5; + /** rd_chip_package : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ + uint32_t rd_chip_package:3; + /** rd_chip_cpu_freq_low : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ + uint32_t rd_chip_cpu_freq_low:1; + /** rd_chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ + uint32_t rd_chip_cpu_freq_rated:1; + /** rd_blk3_part_reserve : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ + uint32_t rd_blk3_part_reserve:1; + /** rd_chip_ver_rev1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ + uint32_t rd_chip_ver_rev1:1; + /** rd_reserve_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_112:16; + }; + uint32_t val; +} efuse_blk0_rdata3_reg_t; - uint32_t blk3_rdata0; - uint32_t blk3_rdata1; - uint32_t blk3_rdata2; - uint32_t blk3_rdata3; - uint32_t blk3_rdata4; - uint32_t blk3_rdata5; - uint32_t blk3_rdata6; - uint32_t blk3_rdata7; +/** Type of blk0_rdata4 register */ +typedef union { + struct { + /** rd_clk8m_freq : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ + uint32_t rd_clk8m_freq:8; + /** rd_adc_vref : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ + uint32_t rd_adc_vref:5; + /** rd_reserve_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_141:1; + /** rd_xpd_sdio_reg : R; bitpos: [14]; default: 0; + * read for XPD_SDIO_REG + */ + uint32_t rd_xpd_sdio_reg:1; + /** rd_xpd_sdio_tieh : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ + uint32_t rd_xpd_sdio_tieh:1; + /** rd_xpd_sdio_force : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ + uint32_t rd_xpd_sdio_force:1; + /** rd_reserve_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_145:15; + }; + uint32_t val; +} efuse_blk0_rdata4_reg_t; - uint32_t blk1_wdata0; - uint32_t blk1_wdata1; - uint32_t blk1_wdata2; - uint32_t blk1_wdata3; - uint32_t blk1_wdata4; - uint32_t blk1_wdata5; - uint32_t blk1_wdata6; - uint32_t blk1_wdata7; +/** Type of blk0_rdata5 register */ +typedef union { + struct { + /** rd_spi_pad_config_clk : R; bitpos: [4:0]; default: 0; + * read for SPI_pad_config_clk + */ + uint32_t rd_spi_pad_config_clk:5; + /** rd_spi_pad_config_q : R; bitpos: [9:5]; default: 0; + * read for SPI_pad_config_q + */ + uint32_t rd_spi_pad_config_q:5; + /** rd_spi_pad_config_d : R; bitpos: [14:10]; default: 0; + * read for SPI_pad_config_d + */ + uint32_t rd_spi_pad_config_d:5; + /** rd_spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; + * read for SPI_pad_config_cs0 + */ + uint32_t rd_spi_pad_config_cs0:5; + /** rd_chip_ver_rev2 : R; bitpos: [20]; default: 0; */ + uint32_t rd_chip_ver_rev2:1; + /** rd_reserve_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_181:1; + /** rd_vol_level_hp_inv : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + uint32_t rd_vol_level_hp_inv:2; + /** rd_wafer_version_minor : R; bitpos: [25:24]; default: 0; */ + uint32_t rd_wafer_version_minor:2; + /** rd_reserve_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_186:2; + /** rd_flash_crypt_config : R; bitpos: [31:28]; default: 0; + * read for flash_crypt_config + */ + uint32_t rd_flash_crypt_config:4; + }; + uint32_t val; +} efuse_blk0_rdata5_reg_t; - uint32_t blk2_wdata0; - uint32_t blk2_wdata1; - uint32_t blk2_wdata2; - uint32_t blk2_wdata3; - uint32_t blk2_wdata4; - uint32_t blk2_wdata5; - uint32_t blk2_wdata6; - uint32_t blk2_wdata7; +/** Type of blk0_rdata6 register */ +typedef union { + struct { + /** rd_coding_scheme : R; bitpos: [1:0]; default: 0; + * read for coding_scheme + */ + uint32_t rd_coding_scheme:2; + /** rd_console_debug_disable : R; bitpos: [2]; default: 0; + * read for console_debug_disable + */ + uint32_t rd_console_debug_disable:1; + /** rd_disable_sdio_host : R; bitpos: [3]; default: 0; */ + uint32_t rd_disable_sdio_host:1; + /** rd_abs_done_0 : R; bitpos: [4]; default: 0; + * read for abstract_done_0 + */ + uint32_t rd_abs_done_0:1; + /** rd_abs_done_1 : R; bitpos: [5]; default: 0; + * read for abstract_done_1 + */ + uint32_t rd_abs_done_1:1; + /** rd_jtag_disable : R; bitpos: [6]; default: 0; + * Disable JTAG + */ + uint32_t rd_jtag_disable:1; + /** rd_disable_dl_encrypt : R; bitpos: [7]; default: 0; + * read for download_dis_encrypt + */ + uint32_t rd_disable_dl_encrypt:1; + /** rd_disable_dl_decrypt : R; bitpos: [8]; default: 0; + * read for download_dis_decrypt + */ + uint32_t rd_disable_dl_decrypt:1; + /** rd_disable_dl_cache : R; bitpos: [9]; default: 0; + * read for download_dis_cache + */ + uint32_t rd_disable_dl_cache:1; + /** rd_key_status : R; bitpos: [10]; default: 0; + * read for key_status + */ + uint32_t rd_key_status:1; + /** rd_reserve_0_203 : RW; bitpos: [31:11]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_203:21; + }; + uint32_t val; +} efuse_blk0_rdata6_reg_t; - uint32_t blk3_wdata0; - uint32_t blk3_wdata1; - uint32_t blk3_wdata2; - uint32_t blk3_wdata3; - uint32_t blk3_wdata4; - uint32_t blk3_wdata5; - uint32_t blk3_wdata6; - uint32_t blk3_wdata7; +/** Type of blk0_wdata0 register */ +typedef union { + struct { + /** wr_dis : RW; bitpos: [15:0]; default: 0; + * program for efuse_wr_disable + */ + uint32_t wr_dis:16; + /** rd_dis : RW; bitpos: [19:16]; default: 0; + * program for efuse_rd_disable + */ + uint32_t rd_dis:4; + /** flash_crypt_cnt : RW; bitpos: [26:20]; default: 0; + * program for flash_crypt_cnt + */ + uint32_t flash_crypt_cnt:7; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_blk0_wdata0_reg_t; - uint32_t clk; - uint32_t conf; - uint32_t status; - uint32_t cmd; - uint32_t int_raw; - uint32_t int_st; - uint32_t int_ena; - uint32_t int_clr; - uint32_t dac_conf; - uint32_t dec_status; - uint32_t reserve[55]; - uint32_t date; +/** Type of blk0_wdata1 register */ +typedef union { + struct { + /** wifi_mac_crc_low : RW; bitpos: [31:0]; default: 0; + * program for low 32bit WIFI_MAC_Address + */ + uint32_t wifi_mac_crc_low:32; + }; + uint32_t val; +} efuse_blk0_wdata1_reg_t; + +/** Type of blk0_wdata2 register */ +typedef union { + struct { + /** wifi_mac_crc_high : RW; bitpos: [23:0]; default: 0; + * program for high 24bit WIFI_MAC_Address + */ + uint32_t wifi_mac_crc_high:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_blk0_wdata2_reg_t; + +/** Type of blk0_wdata3 register */ +typedef union { + struct { + /** disable_app_cpu : R; bitpos: [0]; default: 0; + * Disables APP CPU + */ + uint32_t disable_app_cpu:1; + /** disable_bt : R; bitpos: [1]; default: 0; + * Disables Bluetooth + */ + uint32_t disable_bt:1; + /** chip_package_4bit : R; bitpos: [2]; default: 0; + * Chip package identifier #4bit + */ + uint32_t chip_package_4bit:1; + /** dis_cache : R; bitpos: [3]; default: 0; + * Disables cache + */ + uint32_t dis_cache:1; + /** spi_pad_config_hd : R; bitpos: [8:4]; default: 0; + * program for SPI_pad_config_hd + */ + uint32_t spi_pad_config_hd:5; + /** chip_package : RW; bitpos: [11:9]; default: 0; + * Chip package identifier + */ + uint32_t chip_package:3; + /** chip_cpu_freq_low : RW; bitpos: [12]; default: 0; + * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is + * rated for 160MHz. 240MHz otherwise + */ + uint32_t chip_cpu_freq_low:1; + /** chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; + * If set, the ESP32's maximum CPU frequency has been rated + */ + uint32_t chip_cpu_freq_rated:1; + /** blk3_part_reserve : RW; bitpos: [14]; default: 0; + * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + */ + uint32_t blk3_part_reserve:1; + /** chip_ver_rev1 : RW; bitpos: [15]; default: 0; + * bit is set to 1 for rev1 silicon + */ + uint32_t chip_ver_rev1:1; + /** reserve_0_112 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_112:16; + }; + uint32_t val; +} efuse_blk0_wdata3_reg_t; + +/** Type of blk0_wdata4 register */ +typedef union { + struct { + /** clk8m_freq : R; bitpos: [7:0]; default: 0; + * 8MHz clock freq override + */ + uint32_t clk8m_freq:8; + /** adc_vref : RW; bitpos: [12:8]; default: 0; + * True ADC reference voltage + */ + uint32_t adc_vref:5; + /** reserve_0_141 : RW; bitpos: [13]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_141:1; + /** xpd_sdio_reg : R; bitpos: [14]; default: 0; + * program for XPD_SDIO_REG + */ + uint32_t xpd_sdio_reg:1; + /** xpd_sdio_tieh : R; bitpos: [15]; default: 0; + * If XPD_SDIO_FORCE & XPD_SDIO_REG + */ + uint32_t xpd_sdio_tieh:1; + /** xpd_sdio_force : R; bitpos: [16]; default: 0; + * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset + */ + uint32_t xpd_sdio_force:1; + /** reserve_0_145 : RW; bitpos: [31:17]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_145:15; + }; + uint32_t val; +} efuse_blk0_wdata4_reg_t; + +/** Type of blk0_wdata5 register */ +typedef union { + struct { + /** spi_pad_config_clk : R; bitpos: [4:0]; default: 0; + * program for SPI_pad_config_clk + */ + uint32_t spi_pad_config_clk:5; + /** spi_pad_config_q : R; bitpos: [9:5]; default: 0; + * program for SPI_pad_config_q + */ + uint32_t spi_pad_config_q:5; + /** spi_pad_config_d : R; bitpos: [14:10]; default: 0; + * program for SPI_pad_config_d + */ + uint32_t spi_pad_config_d:5; + /** spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; + * program for SPI_pad_config_cs0 + */ + uint32_t spi_pad_config_cs0:5; + /** chip_ver_rev2 : R; bitpos: [20]; default: 0; */ + uint32_t chip_ver_rev2:1; + /** reserve_0_181 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_181:1; + /** vol_level_hp_inv : R; bitpos: [23:22]; default: 0; + * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM + * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + uint32_t vol_level_hp_inv:2; + /** wafer_version_minor : R; bitpos: [25:24]; default: 0; */ + uint32_t wafer_version_minor:2; + /** reserve_0_186 : RW; bitpos: [27:26]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t reserve_0_186:2; + /** flash_crypt_config : R; bitpos: [31:28]; default: 0; + * program for flash_crypt_config + */ + uint32_t flash_crypt_config:4; + }; + uint32_t val; +} efuse_blk0_wdata5_reg_t; + +/** Type of blk0_wdata6 register */ +typedef union { + struct { + /** coding_scheme : RW; bitpos: [1:0]; default: 0; + * program for coding_scheme + */ + uint32_t coding_scheme:2; + /** console_debug_disable : RW; bitpos: [2]; default: 0; + * program for console_debug_disable + */ + uint32_t console_debug_disable:1; + /** disable_sdio_host : RW; bitpos: [3]; default: 0; */ + uint32_t disable_sdio_host:1; + /** abs_done_0 : RW; bitpos: [4]; default: 0; + * program for abstract_done_0 + */ + uint32_t abs_done_0:1; + /** abs_done_1 : RW; bitpos: [5]; default: 0; + * program for abstract_done_1 + */ + uint32_t abs_done_1:1; + /** disable_jtag : RW; bitpos: [6]; default: 0; + * program for JTAG_disable + */ + uint32_t disable_jtag:1; + /** disable_dl_encrypt : RW; bitpos: [7]; default: 0; + * program for download_dis_encrypt + */ + uint32_t disable_dl_encrypt:1; + /** disable_dl_decrypt : RW; bitpos: [8]; default: 0; + * program for download_dis_decrypt + */ + uint32_t disable_dl_decrypt:1; + /** disable_dl_cache : RW; bitpos: [9]; default: 0; + * program for download_dis_cache + */ + uint32_t disable_dl_cache:1; + /** key_status : RW; bitpos: [10]; default: 0; + * program for key_status + */ + uint32_t key_status:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} efuse_blk0_wdata6_reg_t; + +/** Type of blk1_rdata0 register */ +typedef union { + struct { + /** rd_block1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1:32; + }; + uint32_t val; +} efuse_blk1_rdata0_reg_t; + +/** Type of blk1_rdata1 register */ +typedef union { + struct { + /** rd_block1_1 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_1:32; + }; + uint32_t val; +} efuse_blk1_rdata1_reg_t; + +/** Type of blk1_rdata2 register */ +typedef union { + struct { + /** rd_block1_2 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_2:32; + }; + uint32_t val; +} efuse_blk1_rdata2_reg_t; + +/** Type of blk1_rdata3 register */ +typedef union { + struct { + /** rd_block1_3 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_3:32; + }; + uint32_t val; +} efuse_blk1_rdata3_reg_t; + +/** Type of blk1_rdata4 register */ +typedef union { + struct { + /** rd_block1_4 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_4:32; + }; + uint32_t val; +} efuse_blk1_rdata4_reg_t; + +/** Type of blk1_rdata5 register */ +typedef union { + struct { + /** rd_block1_5 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_5:32; + }; + uint32_t val; +} efuse_blk1_rdata5_reg_t; + +/** Type of blk1_rdata6 register */ +typedef union { + struct { + /** rd_block1_6 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_6:32; + }; + uint32_t val; +} efuse_blk1_rdata6_reg_t; + +/** Type of blk1_rdata7 register */ +typedef union { + struct { + /** rd_block1_7 : R; bitpos: [31:0]; default: 0; + * Flash encryption key + */ + uint32_t rd_block1_7:32; + }; + uint32_t val; +} efuse_blk1_rdata7_reg_t; + +/** Type of blk2_rdata0 register */ +typedef union { + struct { + /** rd_block2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2:32; + }; + uint32_t val; +} efuse_blk2_rdata0_reg_t; + +/** Type of blk2_rdata1 register */ +typedef union { + struct { + /** rd_block2_1 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_1:32; + }; + uint32_t val; +} efuse_blk2_rdata1_reg_t; + +/** Type of blk2_rdata2 register */ +typedef union { + struct { + /** rd_block2_2 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_2:32; + }; + uint32_t val; +} efuse_blk2_rdata2_reg_t; + +/** Type of blk2_rdata3 register */ +typedef union { + struct { + /** rd_block2_3 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_3:32; + }; + uint32_t val; +} efuse_blk2_rdata3_reg_t; + +/** Type of blk2_rdata4 register */ +typedef union { + struct { + /** rd_block2_4 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_4:32; + }; + uint32_t val; +} efuse_blk2_rdata4_reg_t; + +/** Type of blk2_rdata5 register */ +typedef union { + struct { + /** rd_block2_5 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_5:32; + }; + uint32_t val; +} efuse_blk2_rdata5_reg_t; + +/** Type of blk2_rdata6 register */ +typedef union { + struct { + /** rd_block2_6 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_6:32; + }; + uint32_t val; +} efuse_blk2_rdata6_reg_t; + +/** Type of blk2_rdata7 register */ +typedef union { + struct { + /** rd_block2_7 : R; bitpos: [31:0]; default: 0; + * Security boot key + */ + uint32_t rd_block2_7:32; + }; + uint32_t val; +} efuse_blk2_rdata7_reg_t; + +/** Type of blk3_rdata0 register */ +typedef union { + struct { + /** rd_custom_mac_crc : R; bitpos: [7:0]; default: 0; + * CRC8 for custom MAC address + */ + uint32_t rd_custom_mac_crc:8; + /** rd_custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ + uint32_t rd_custom_mac:24; + }; + uint32_t val; +} efuse_blk3_rdata0_reg_t; + +/** Type of blk3_rdata1 register */ +typedef union { + struct { + /** rd_custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ + uint32_t rd_custom_mac_1:24; + /** reserved_3_56 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_56:8; + }; + uint32_t val; +} efuse_blk3_rdata1_reg_t; + +/** Type of blk3_rdata2 register */ +typedef union { + struct { + /** rd_blk3_reserved_2 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_2:32; + }; + uint32_t val; +} efuse_blk3_rdata2_reg_t; + +/** Type of blk3_rdata3 register */ +typedef union { + struct { + /** rd_adc1_tp_low : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc1_tp_low:7; + /** rd_adc1_tp_high : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc1_tp_high:9; + /** rd_adc2_tp_low : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc2_tp_low:7; + /** rd_adc2_tp_high : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t rd_adc2_tp_high:9; + }; + uint32_t val; +} efuse_blk3_rdata3_reg_t; + +/** Type of blk3_rdata4 register */ +typedef union { + struct { + /** rd_secure_version : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ + uint32_t rd_secure_version:32; + }; + uint32_t val; +} efuse_blk3_rdata4_reg_t; + +/** Type of blk3_rdata5 register */ +typedef union { + struct { + /** reserved_3_160 : R; bitpos: [23:0]; default: 0; + * reserved + */ + uint32_t reserved_3_160:24; + /** rd_mac_version : R; bitpos: [31:24]; default: 0; + * Custom MAC version + */ + uint32_t rd_mac_version:8; + }; + uint32_t val; +} efuse_blk3_rdata5_reg_t; + +/** Type of blk3_rdata6 register */ +typedef union { + struct { + /** rd_blk3_reserved_6 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_6:32; + }; + uint32_t val; +} efuse_blk3_rdata6_reg_t; + +/** Type of blk3_rdata7 register */ +typedef union { + struct { + /** rd_blk3_reserved_7 : R; bitpos: [31:0]; default: 0; + * read for BLOCK3 + */ + uint32_t rd_blk3_reserved_7:32; + }; + uint32_t val; +} efuse_blk3_rdata7_reg_t; + +/** Type of blk1_wdata0 register */ +typedef union { + struct { + /** blk1_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din0:32; + }; + uint32_t val; +} efuse_blk1_wdata0_reg_t; + +/** Type of blk1_wdata1 register */ +typedef union { + struct { + /** blk1_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din1:32; + }; + uint32_t val; +} efuse_blk1_wdata1_reg_t; + +/** Type of blk1_wdata2 register */ +typedef union { + struct { + /** blk1_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din2:32; + }; + uint32_t val; +} efuse_blk1_wdata2_reg_t; + +/** Type of blk1_wdata3 register */ +typedef union { + struct { + /** blk1_din3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din3:32; + }; + uint32_t val; +} efuse_blk1_wdata3_reg_t; + +/** Type of blk1_wdata4 register */ +typedef union { + struct { + /** blk1_din4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din4:32; + }; + uint32_t val; +} efuse_blk1_wdata4_reg_t; + +/** Type of blk1_wdata5 register */ +typedef union { + struct { + /** blk1_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din5:32; + }; + uint32_t val; +} efuse_blk1_wdata5_reg_t; + +/** Type of blk1_wdata6 register */ +typedef union { + struct { + /** blk1_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din6:32; + }; + uint32_t val; +} efuse_blk1_wdata6_reg_t; + +/** Type of blk1_wdata7 register */ +typedef union { + struct { + /** blk1_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK1 + */ + uint32_t blk1_din7:32; + }; + uint32_t val; +} efuse_blk1_wdata7_reg_t; + +/** Type of blk2_wdata0 register */ +typedef union { + struct { + /** blk2_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din0:32; + }; + uint32_t val; +} efuse_blk2_wdata0_reg_t; + +/** Type of blk2_wdata1 register */ +typedef union { + struct { + /** blk2_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din1:32; + }; + uint32_t val; +} efuse_blk2_wdata1_reg_t; + +/** Type of blk2_wdata2 register */ +typedef union { + struct { + /** blk2_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din2:32; + }; + uint32_t val; +} efuse_blk2_wdata2_reg_t; + +/** Type of blk2_wdata3 register */ +typedef union { + struct { + /** blk2_din3 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din3:32; + }; + uint32_t val; +} efuse_blk2_wdata3_reg_t; + +/** Type of blk2_wdata4 register */ +typedef union { + struct { + /** blk2_din4 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din4:32; + }; + uint32_t val; +} efuse_blk2_wdata4_reg_t; + +/** Type of blk2_wdata5 register */ +typedef union { + struct { + /** blk2_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din5:32; + }; + uint32_t val; +} efuse_blk2_wdata5_reg_t; + +/** Type of blk2_wdata6 register */ +typedef union { + struct { + /** blk2_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din6:32; + }; + uint32_t val; +} efuse_blk2_wdata6_reg_t; + +/** Type of blk2_wdata7 register */ +typedef union { + struct { + /** blk2_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK2 + */ + uint32_t blk2_din7:32; + }; + uint32_t val; +} efuse_blk2_wdata7_reg_t; + +/** Type of blk3_wdata0 register */ +typedef union { + struct { + /** blk3_din0 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din0:32; + }; + uint32_t val; +} efuse_blk3_wdata0_reg_t; + +/** Type of blk3_wdata1 register */ +typedef union { + struct { + /** blk3_din1 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din1:32; + }; + uint32_t val; +} efuse_blk3_wdata1_reg_t; + +/** Type of blk3_wdata2 register */ +typedef union { + struct { + /** blk3_din2 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din2:32; + }; + uint32_t val; +} efuse_blk3_wdata2_reg_t; + +/** Type of blk3_wdata3 register */ +typedef union { + struct { + /** adc1_tp_low : RW; bitpos: [6:0]; default: 0; + * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc1_tp_low:7; + /** adc1_tp_high : RW; bitpos: [15:7]; default: 0; + * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc1_tp_high:9; + /** adc2_tp_low : RW; bitpos: [22:16]; default: 0; + * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc2_tp_low:7; + /** adc2_tp_high : RW; bitpos: [31:23]; default: 0; + * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + */ + uint32_t adc2_tp_high:9; + }; + uint32_t val; +} efuse_blk3_wdata3_reg_t; + +/** Type of blk3_wdata4 register */ +typedef union { + struct { + /** secure_version : R; bitpos: [31:0]; default: 0; + * Secure version for anti-rollback + */ + uint32_t secure_version:32; + }; + uint32_t val; +} efuse_blk3_wdata4_reg_t; + +/** Type of blk3_wdata5 register */ +typedef union { + struct { + /** blk3_din5 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din5:32; + }; + uint32_t val; +} efuse_blk3_wdata5_reg_t; + +/** Type of blk3_wdata6 register */ +typedef union { + struct { + /** blk3_din6 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din6:32; + }; + uint32_t val; +} efuse_blk3_wdata6_reg_t; + +/** Type of blk3_wdata7 register */ +typedef union { + struct { + /** blk3_din7 : RW; bitpos: [31:0]; default: 0; + * program for BLOCK3 + */ + uint32_t blk3_din7:32; + }; + uint32_t val; +} efuse_blk3_wdata7_reg_t; + +/** Type of clk register */ +typedef union { + struct { + /** clk_sel0 : RW; bitpos: [7:0]; default: 82; + * efuse timing configure + */ + uint32_t clk_sel0:8; + /** clk_sel1 : RW; bitpos: [15:8]; default: 64; + * efuse timing configure + */ + uint32_t clk_sel1:8; + /** clk_en : RW; bitpos: [16]; default: 0; */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register */ +typedef union { + struct { + /** op_code : RW; bitpos: [15:0]; default: 0; + * efuse operation code + */ + uint32_t op_code:16; + /** force_no_wr_rd_dis : RW; bitpos: [16]; default: 1; */ + uint32_t force_no_wr_rd_dis:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register */ +typedef union { + struct { + /** debug : R; bitpos: [31:0]; default: 0; */ + uint32_t debug:32; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register */ +typedef union { + struct { + /** read_cmd : RW; bitpos: [0]; default: 0; + * command for read + */ + uint32_t read_cmd:1; + /** pgm_cmd : RW; bitpos: [1]; default: 0; + * command for program + */ + uint32_t pgm_cmd:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register */ +typedef union { + struct { + /** read_done_int_raw : R; bitpos: [0]; default: 0; + * read done interrupt raw status + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R; bitpos: [1]; default: 0; + * program done interrupt raw status + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register */ +typedef union { + struct { + /** read_done_int_st : R; bitpos: [0]; default: 0; + * read done interrupt status + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : R; bitpos: [1]; default: 0; + * program done interrupt status + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register */ +typedef union { + struct { + /** read_done_int_ena : RW; bitpos: [0]; default: 0; + * read done interrupt enable + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : RW; bitpos: [1]; default: 0; + * program done interrupt enable + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register */ +typedef union { + struct { + /** read_done_int_clr : W; bitpos: [0]; default: 0; + * read done interrupt clear + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : W; bitpos: [1]; default: 0; + * program done interrupt clear + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register */ +typedef union { + struct { + /** dac_clk_div : RW; bitpos: [7:0]; default: 40; + * efuse timing configure + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : RW; bitpos: [8]; default: 0; */ + uint32_t dac_clk_pad_sel:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of dec_status register */ +typedef union { + struct { + /** dec_warnings : R; bitpos: [11:0]; default: 0; + * the decode result of 3/4 coding scheme has warning + */ + uint32_t dec_warnings:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} efuse_dec_status_reg_t; + +/** Type of date register */ +typedef union { + struct { + /** date : RW; bitpos: [31:0]; default: 369370624; */ + uint32_t date:32; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_blk0_rdata0_reg_t blk0_rdata0; + volatile efuse_blk0_rdata1_reg_t blk0_rdata1; + volatile efuse_blk0_rdata2_reg_t blk0_rdata2; + volatile efuse_blk0_rdata3_reg_t blk0_rdata3; + volatile efuse_blk0_rdata4_reg_t blk0_rdata4; + volatile efuse_blk0_rdata5_reg_t blk0_rdata5; + volatile efuse_blk0_rdata6_reg_t blk0_rdata6; + volatile efuse_blk0_wdata0_reg_t blk0_wdata0; + volatile efuse_blk0_wdata1_reg_t blk0_wdata1; + volatile efuse_blk0_wdata2_reg_t blk0_wdata2; + volatile efuse_blk0_wdata3_reg_t blk0_wdata3; + volatile efuse_blk0_wdata4_reg_t blk0_wdata4; + volatile efuse_blk0_wdata5_reg_t blk0_wdata5; + volatile efuse_blk0_wdata6_reg_t blk0_wdata6; + volatile efuse_blk1_rdata0_reg_t blk1_rdata0; + volatile efuse_blk1_rdata1_reg_t blk1_rdata1; + volatile efuse_blk1_rdata2_reg_t blk1_rdata2; + volatile efuse_blk1_rdata3_reg_t blk1_rdata3; + volatile efuse_blk1_rdata4_reg_t blk1_rdata4; + volatile efuse_blk1_rdata5_reg_t blk1_rdata5; + volatile efuse_blk1_rdata6_reg_t blk1_rdata6; + volatile efuse_blk1_rdata7_reg_t blk1_rdata7; + volatile efuse_blk2_rdata0_reg_t blk2_rdata0; + volatile efuse_blk2_rdata1_reg_t blk2_rdata1; + volatile efuse_blk2_rdata2_reg_t blk2_rdata2; + volatile efuse_blk2_rdata3_reg_t blk2_rdata3; + volatile efuse_blk2_rdata4_reg_t blk2_rdata4; + volatile efuse_blk2_rdata5_reg_t blk2_rdata5; + volatile efuse_blk2_rdata6_reg_t blk2_rdata6; + volatile efuse_blk2_rdata7_reg_t blk2_rdata7; + volatile efuse_blk3_rdata0_reg_t blk3_rdata0; + volatile efuse_blk3_rdata1_reg_t blk3_rdata1; + volatile efuse_blk3_rdata2_reg_t blk3_rdata2; + volatile efuse_blk3_rdata3_reg_t blk3_rdata3; + volatile efuse_blk3_rdata4_reg_t blk3_rdata4; + volatile efuse_blk3_rdata5_reg_t blk3_rdata5; + volatile efuse_blk3_rdata6_reg_t blk3_rdata6; + volatile efuse_blk3_rdata7_reg_t blk3_rdata7; + volatile efuse_blk1_wdata0_reg_t blk1_wdata0; + volatile efuse_blk1_wdata1_reg_t blk1_wdata1; + volatile efuse_blk1_wdata2_reg_t blk1_wdata2; + volatile efuse_blk1_wdata3_reg_t blk1_wdata3; + volatile efuse_blk1_wdata4_reg_t blk1_wdata4; + volatile efuse_blk1_wdata5_reg_t blk1_wdata5; + volatile efuse_blk1_wdata6_reg_t blk1_wdata6; + volatile efuse_blk1_wdata7_reg_t blk1_wdata7; + volatile efuse_blk2_wdata0_reg_t blk2_wdata0; + volatile efuse_blk2_wdata1_reg_t blk2_wdata1; + volatile efuse_blk2_wdata2_reg_t blk2_wdata2; + volatile efuse_blk2_wdata3_reg_t blk2_wdata3; + volatile efuse_blk2_wdata4_reg_t blk2_wdata4; + volatile efuse_blk2_wdata5_reg_t blk2_wdata5; + volatile efuse_blk2_wdata6_reg_t blk2_wdata6; + volatile efuse_blk2_wdata7_reg_t blk2_wdata7; + volatile efuse_blk3_wdata0_reg_t blk3_wdata0; + volatile efuse_blk3_wdata1_reg_t blk3_wdata1; + volatile efuse_blk3_wdata2_reg_t blk3_wdata2; + volatile efuse_blk3_wdata3_reg_t blk3_wdata3; + volatile efuse_blk3_wdata4_reg_t blk3_wdata4; + volatile efuse_blk3_wdata5_reg_t blk3_wdata5; + volatile efuse_blk3_wdata6_reg_t blk3_wdata6; + volatile efuse_blk3_wdata7_reg_t blk3_wdata7; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_dec_status_reg_t dec_status; + uint32_t reserved_120[55]; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - -#endif /* _SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp32c2/include/soc/efuse_defs.h b/components/soc/esp32c2/include/soc/efuse_defs.h new file mode 100644 index 0000000000..55f3abff56 --- /dev/null +++ b/components/soc/esp32c2/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/include/soc/efuse_reg.h b/components/soc/esp32c2/include/soc/efuse_reg.h index ef8373fd8e..6f13f2a2ba 100644 --- a/components/soc/esp32c2/include/soc/efuse_reg.h +++ b/components/soc/esp32c2/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif @@ -154,6 +155,11 @@ extern "C" { #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) #define EFUSE_WR_DIS_V 0x000000FFU #define EFUSE_WR_DIS_S 0 +/** EFUSE_RESERVED_0_8 : RW; bitpos: [31:8]; default: 0; */ +#define EFUSE_RESERVED_0_8 0x00FFFFFFU +#define EFUSE_RESERVED_0_8_M (EFUSE_RESERVED_0_8_V << EFUSE_RESERVED_0_8_S) +#define EFUSE_RESERVED_0_8_V 0x00FFFFFFU +#define EFUSE_RESERVED_0_8_S 8 /** EFUSE_RD_REPEAT_DATA0_REG register * BLOCK0 data register 1. @@ -195,14 +201,14 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6 -/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO; bitpos: [9:7]; default: 0; +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [9:7]; default: 0; * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even * number of 1: disable. */ -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT 0x00000007U -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S) -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V 0x00000007U -#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S 7 +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 7 /** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0; * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, * XTS_AES use 128-bit eFuse data in BLOCK3. @@ -262,37 +268,72 @@ extern "C" { #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 21 -/** EFUSE_RPT4_RESERVED : RO; bitpos: [31:22]; default: 0; - * Reserved (used for four backups method). +/** EFUSE_SECURE_VERSION : R; bitpos: [25:22]; default: 0; + * Secure version for anti-rollback */ -#define EFUSE_RPT4_RESERVED 0x000003FFU -#define EFUSE_RPT4_RESERVED_M (EFUSE_RPT4_RESERVED_V << EFUSE_RPT4_RESERVED_S) -#define EFUSE_RPT4_RESERVED_V 0x000003FFU -#define EFUSE_RPT4_RESERVED_S 22 +#define EFUSE_SECURE_VERSION 0x0000000FU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000000FU +#define EFUSE_SECURE_VERSION_S 22 +/** EFUSE_CUSTOM_MAC_USED : R; bitpos: [26]; default: 0; + * True if MAC_CUSTOM is burned + */ +#define EFUSE_CUSTOM_MAC_USED (BIT(26)) +#define EFUSE_CUSTOM_MAC_USED_M (EFUSE_CUSTOM_MAC_USED_V << EFUSE_CUSTOM_MAC_USED_S) +#define EFUSE_CUSTOM_MAC_USED_V 0x00000001U +#define EFUSE_CUSTOM_MAC_USED_S 26 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [27]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(27)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 27 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [28]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(28)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 28 +/** EFUSE_RESERVED_0_61 : R; bitpos: [31:29]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_61 0x00000007U +#define EFUSE_RESERVED_0_61_M (EFUSE_RESERVED_0_61_V << EFUSE_RESERVED_0_61_S) +#define EFUSE_RESERVED_0_61_V 0x00000007U +#define EFUSE_RESERVED_0_61_S 29 /** EFUSE_RD_BLK1_DATA0_REG register * BLOCK1 data register 0. */ #define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_SYSTEM_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the bits [0:31] of system data. +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:0]; default: 0; + * Custom MAC address */ -#define EFUSE_SYSTEM_DATA0 0xFFFFFFFFU -#define EFUSE_SYSTEM_DATA0_M (EFUSE_SYSTEM_DATA0_V << EFUSE_SYSTEM_DATA0_S) -#define EFUSE_SYSTEM_DATA0_V 0xFFFFFFFFU -#define EFUSE_SYSTEM_DATA0_S 0 +#define EFUSE_CUSTOM_MAC 0xFFFFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0xFFFFFFFFU +#define EFUSE_CUSTOM_MAC_S 0 /** EFUSE_RD_BLK1_DATA1_REG register * BLOCK1 data register 1. */ #define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38) -/** EFUSE_SYSTEM_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the bits [32:63] of system data. +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [15:0]; default: 0; + * Custom MAC address */ -#define EFUSE_SYSTEM_DATA1 0xFFFFFFFFU -#define EFUSE_SYSTEM_DATA1_M (EFUSE_SYSTEM_DATA1_V << EFUSE_SYSTEM_DATA1_S) -#define EFUSE_SYSTEM_DATA1_V 0xFFFFFFFFU -#define EFUSE_SYSTEM_DATA1_S 0 +#define EFUSE_CUSTOM_MAC_1 0x0000FFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x0000FFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_1_48 : R; bitpos: [31:16]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_48 0x0000FFFFU +#define EFUSE_RESERVED_1_48_M (EFUSE_RESERVED_1_48_V << EFUSE_RESERVED_1_48_S) +#define EFUSE_RESERVED_1_48_V 0x0000FFFFU +#define EFUSE_RESERVED_1_48_S 16 /** EFUSE_RD_BLK1_DATA2_REG register * BLOCK1 data register 2. @@ -310,122 +351,227 @@ extern "C" { * Register 0 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40) -/** EFUSE_BLK2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Store the bit [0:31] of MAC. +/** EFUSE_MAC : R; bitpos: [31:0]; default: 0; + * MAC address */ -#define EFUSE_BLK2_DATA0 0xFFFFFFFFU -#define EFUSE_BLK2_DATA0_M (EFUSE_BLK2_DATA0_V << EFUSE_BLK2_DATA0_S) -#define EFUSE_BLK2_DATA0_V 0xFFFFFFFFU -#define EFUSE_BLK2_DATA0_S 0 +#define EFUSE_MAC 0xFFFFFFFFU +#define EFUSE_MAC_M (EFUSE_MAC_V << EFUSE_MAC_S) +#define EFUSE_MAC_V 0xFFFFFFFFU +#define EFUSE_MAC_S 0 /** EFUSE_RD_BLK2_DATA1_REG register * Register 1 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44) -/** EFUSE_MAC_ID_HIGH : RO; bitpos: [15:0]; default: 0; - * Store the bit [31:47] of MAC. +/** EFUSE_MAC_1 : R; bitpos: [15:0]; default: 0; + * MAC address */ -#define EFUSE_MAC_ID_HIGH 0x0000FFFFU -#define EFUSE_MAC_ID_HIGH_M (EFUSE_MAC_ID_HIGH_V << EFUSE_MAC_ID_HIGH_S) -#define EFUSE_MAC_ID_HIGH_V 0x0000FFFFU -#define EFUSE_MAC_ID_HIGH_S 0 -/** EFUSE_WAFER_VERSION : RO; bitpos: [18:16]; default: 0; - * Store wafer version. +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [19:16]; default: 0; + * WAFER_VERSION_MINOR */ -#define EFUSE_WAFER_VERSION 0x00000007U -#define EFUSE_WAFER_VERSION_M (EFUSE_WAFER_VERSION_V << EFUSE_WAFER_VERSION_S) -#define EFUSE_WAFER_VERSION_V 0x00000007U -#define EFUSE_WAFER_VERSION_S 16 -/** EFUSE_PKG_VERSION : RO; bitpos: [21:19]; default: 0; - * Store package version. +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 16 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [21:20]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 20 +/** EFUSE_PKG_VERSION : R; bitpos: [24:22]; default: 0; + * EFUSE_PKG_VERSION */ #define EFUSE_PKG_VERSION 0x00000007U #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) #define EFUSE_PKG_VERSION_V 0x00000007U -#define EFUSE_PKG_VERSION_S 19 -/** EFUSE_BLK2_EFUSE_VERSION : RO; bitpos: [24:22]; default: 0; - * Store efuse version. +#define EFUSE_PKG_VERSION_S 22 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [27:25]; default: 0; + * Minor version of BLOCK2 */ -#define EFUSE_BLK2_EFUSE_VERSION 0x00000007U -#define EFUSE_BLK2_EFUSE_VERSION_M (EFUSE_BLK2_EFUSE_VERSION_V << EFUSE_BLK2_EFUSE_VERSION_S) -#define EFUSE_BLK2_EFUSE_VERSION_V 0x00000007U -#define EFUSE_BLK2_EFUSE_VERSION_S 22 -/** EFUSE_RF_REF_I_BIAS_CONFIG : RO; bitpos: [28:25]; default: 0; - * Store rf configuration parameters. +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 25 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [29:28]; default: 0; + * Major version of BLOCK2 */ -#define EFUSE_RF_REF_I_BIAS_CONFIG 0x0000000FU -#define EFUSE_RF_REF_I_BIAS_CONFIG_M (EFUSE_RF_REF_I_BIAS_CONFIG_V << EFUSE_RF_REF_I_BIAS_CONFIG_S) -#define EFUSE_RF_REF_I_BIAS_CONFIG_V 0x0000000FU -#define EFUSE_RF_REF_I_BIAS_CONFIG_S 25 -/** EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO; bitpos: [31:29]; default: 0; - * Store the bit [0:2] of ido configuration parameters. +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 28 +/** EFUSE_OCODE : R; bitpos: [31:30]; default: 0; + * OCode */ -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW 0x00000007U -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M (EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V << EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S) -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V 0x00000007U -#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S 29 +#define EFUSE_OCODE 0x00000003U +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x00000003U +#define EFUSE_OCODE_S 30 /** EFUSE_RD_BLK2_DATA2_REG register * Register 2 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48) -/** EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO; bitpos: [26:0]; default: 0; - * Store the bit [3:29] of ido configuration parameters. +/** EFUSE_OCODE_1 : R; bitpos: [4:0]; default: 0; + * OCode */ -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH 0x07FFFFFFU -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M (EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V << EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S) -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V 0x07FFFFFFU -#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S 0 -/** EFUSE_PVT_LOW : RO; bitpos: [31:27]; default: 0; - * Store the bit [0:4] of pvt. +#define EFUSE_OCODE_1 0x0000001FU +#define EFUSE_OCODE_1_M (EFUSE_OCODE_1_V << EFUSE_OCODE_1_S) +#define EFUSE_OCODE_1_V 0x0000001FU +#define EFUSE_OCODE_1_S 0 +/** EFUSE_TEMP_CALIB : R; bitpos: [13:5]; default: 0; + * Temperature calibration data */ -#define EFUSE_PVT_LOW 0x0000001FU -#define EFUSE_PVT_LOW_M (EFUSE_PVT_LOW_V << EFUSE_PVT_LOW_S) -#define EFUSE_PVT_LOW_V 0x0000001FU -#define EFUSE_PVT_LOW_S 27 +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 5 +/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [21:14]; default: 0; + * ADC1 init code at atten0 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 14 +/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [26:22]; default: 0; + * ADC1 init code at atten3 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000001FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000001FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 22 +/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000001FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000001FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 27 /** EFUSE_RD_BLK2_DATA3_REG register * Register 3 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_PVT_HIGH : RO; bitpos: [9:0]; default: 0; - * Store the bit [5:14] of pvt. +/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration voltage at atten0 */ -#define EFUSE_PVT_HIGH 0x000003FFU -#define EFUSE_PVT_HIGH_M (EFUSE_PVT_HIGH_V << EFUSE_PVT_HIGH_S) -#define EFUSE_PVT_HIGH_V 0x000003FFU -#define EFUSE_PVT_HIGH_S 0 -/** EFUSE_ADC_CALIBRATION_0 : RO; bitpos: [31:10]; default: 0; - * Store the bit [0:21] of ADC calibration data. +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x00000007U +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x00000007U +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0 +/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:3]; default: 0; + * ADC1 calibration voltage at atten3 */ -#define EFUSE_ADC_CALIBRATION_0 0x003FFFFFU -#define EFUSE_ADC_CALIBRATION_0_M (EFUSE_ADC_CALIBRATION_0_V << EFUSE_ADC_CALIBRATION_0_S) -#define EFUSE_ADC_CALIBRATION_0_V 0x003FFFFFU -#define EFUSE_ADC_CALIBRATION_0_S 10 +#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 3 +/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [13:9]; default: 0; + * BLOCK2 digital dbias when hvt + */ +#define EFUSE_DIG_DBIAS_HVT 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) +#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_S 9 +/** EFUSE_DIG_LDO_SLP_DBIAS2 : R; bitpos: [20:14]; default: 0; + * BLOCK2 DIG_LDO_DBG0_DBIAS2 + */ +#define EFUSE_DIG_LDO_SLP_DBIAS2 0x0000007FU +#define EFUSE_DIG_LDO_SLP_DBIAS2_M (EFUSE_DIG_LDO_SLP_DBIAS2_V << EFUSE_DIG_LDO_SLP_DBIAS2_S) +#define EFUSE_DIG_LDO_SLP_DBIAS2_V 0x0000007FU +#define EFUSE_DIG_LDO_SLP_DBIAS2_S 14 +/** EFUSE_DIG_LDO_SLP_DBIAS26 : R; bitpos: [28:21]; default: 0; + * BLOCK2 DIG_LDO_DBG0_DBIAS26 + */ +#define EFUSE_DIG_LDO_SLP_DBIAS26 0x000000FFU +#define EFUSE_DIG_LDO_SLP_DBIAS26_M (EFUSE_DIG_LDO_SLP_DBIAS26_V << EFUSE_DIG_LDO_SLP_DBIAS26_S) +#define EFUSE_DIG_LDO_SLP_DBIAS26_V 0x000000FFU +#define EFUSE_DIG_LDO_SLP_DBIAS26_S 21 +/** EFUSE_DIG_LDO_ACT_DBIAS26 : R; bitpos: [31:29]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS26 + */ +#define EFUSE_DIG_LDO_ACT_DBIAS26 0x00000007U +#define EFUSE_DIG_LDO_ACT_DBIAS26_M (EFUSE_DIG_LDO_ACT_DBIAS26_V << EFUSE_DIG_LDO_ACT_DBIAS26_S) +#define EFUSE_DIG_LDO_ACT_DBIAS26_V 0x00000007U +#define EFUSE_DIG_LDO_ACT_DBIAS26_S 29 /** EFUSE_RD_BLK2_DATA4_REG register * Register 4 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_ADC_CALIBRATION_1 : RO; bitpos: [31:0]; default: 0; - * Store the bit [22:53] of ADC calibration data. +/** EFUSE_DIG_LDO_ACT_DBIAS26_1 : R; bitpos: [2:0]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS26 */ -#define EFUSE_ADC_CALIBRATION_1 0xFFFFFFFFU -#define EFUSE_ADC_CALIBRATION_1_M (EFUSE_ADC_CALIBRATION_1_V << EFUSE_ADC_CALIBRATION_1_S) -#define EFUSE_ADC_CALIBRATION_1_V 0xFFFFFFFFU -#define EFUSE_ADC_CALIBRATION_1_S 0 +#define EFUSE_DIG_LDO_ACT_DBIAS26_1 0x00000007U +#define EFUSE_DIG_LDO_ACT_DBIAS26_1_M (EFUSE_DIG_LDO_ACT_DBIAS26_1_V << EFUSE_DIG_LDO_ACT_DBIAS26_1_S) +#define EFUSE_DIG_LDO_ACT_DBIAS26_1_V 0x00000007U +#define EFUSE_DIG_LDO_ACT_DBIAS26_1_S 0 +/** EFUSE_DIG_LDO_ACT_STEPD10 : R; bitpos: [6:3]; default: 0; + * BLOCK2 DIG_LDO_ACT_STEPD10 + */ +#define EFUSE_DIG_LDO_ACT_STEPD10 0x0000000FU +#define EFUSE_DIG_LDO_ACT_STEPD10_M (EFUSE_DIG_LDO_ACT_STEPD10_V << EFUSE_DIG_LDO_ACT_STEPD10_S) +#define EFUSE_DIG_LDO_ACT_STEPD10_V 0x0000000FU +#define EFUSE_DIG_LDO_ACT_STEPD10_S 3 +/** EFUSE_RTC_LDO_SLP_DBIAS13 : R; bitpos: [13:7]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS13 + */ +#define EFUSE_RTC_LDO_SLP_DBIAS13 0x0000007FU +#define EFUSE_RTC_LDO_SLP_DBIAS13_M (EFUSE_RTC_LDO_SLP_DBIAS13_V << EFUSE_RTC_LDO_SLP_DBIAS13_S) +#define EFUSE_RTC_LDO_SLP_DBIAS13_V 0x0000007FU +#define EFUSE_RTC_LDO_SLP_DBIAS13_S 7 +/** EFUSE_RTC_LDO_SLP_DBIAS29 : R; bitpos: [22:14]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS29 + */ +#define EFUSE_RTC_LDO_SLP_DBIAS29 0x000001FFU +#define EFUSE_RTC_LDO_SLP_DBIAS29_M (EFUSE_RTC_LDO_SLP_DBIAS29_V << EFUSE_RTC_LDO_SLP_DBIAS29_S) +#define EFUSE_RTC_LDO_SLP_DBIAS29_V 0x000001FFU +#define EFUSE_RTC_LDO_SLP_DBIAS29_S 14 +/** EFUSE_RTC_LDO_SLP_DBIAS31 : R; bitpos: [28:23]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS31 + */ +#define EFUSE_RTC_LDO_SLP_DBIAS31 0x0000003FU +#define EFUSE_RTC_LDO_SLP_DBIAS31_M (EFUSE_RTC_LDO_SLP_DBIAS31_V << EFUSE_RTC_LDO_SLP_DBIAS31_S) +#define EFUSE_RTC_LDO_SLP_DBIAS31_V 0x0000003FU +#define EFUSE_RTC_LDO_SLP_DBIAS31_S 23 +/** EFUSE_RTC_LDO_ACT_DBIAS31 : R; bitpos: [31:29]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS31 + */ +#define EFUSE_RTC_LDO_ACT_DBIAS31 0x00000007U +#define EFUSE_RTC_LDO_ACT_DBIAS31_M (EFUSE_RTC_LDO_ACT_DBIAS31_V << EFUSE_RTC_LDO_ACT_DBIAS31_S) +#define EFUSE_RTC_LDO_ACT_DBIAS31_V 0x00000007U +#define EFUSE_RTC_LDO_ACT_DBIAS31_S 29 /** EFUSE_RD_BLK2_DATA5_REG register * Register 5 of BLOCK2. */ #define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_ADC_CALIBRATION_2 : RO; bitpos: [31:0]; default: 0; - * Store the bit [54:85] of ADC calibration data. +/** EFUSE_RTC_LDO_ACT_DBIAS31_1 : R; bitpos: [2:0]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS31 */ -#define EFUSE_ADC_CALIBRATION_2 0xFFFFFFFFU -#define EFUSE_ADC_CALIBRATION_2_M (EFUSE_ADC_CALIBRATION_2_V << EFUSE_ADC_CALIBRATION_2_S) -#define EFUSE_ADC_CALIBRATION_2_V 0xFFFFFFFFU -#define EFUSE_ADC_CALIBRATION_2_S 0 +#define EFUSE_RTC_LDO_ACT_DBIAS31_1 0x00000007U +#define EFUSE_RTC_LDO_ACT_DBIAS31_1_M (EFUSE_RTC_LDO_ACT_DBIAS31_1_V << EFUSE_RTC_LDO_ACT_DBIAS31_1_S) +#define EFUSE_RTC_LDO_ACT_DBIAS31_1_V 0x00000007U +#define EFUSE_RTC_LDO_ACT_DBIAS31_1_S 0 +/** EFUSE_RTC_LDO_ACT_DBIAS13 : R; bitpos: [10:3]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS13 + */ +#define EFUSE_RTC_LDO_ACT_DBIAS13 0x000000FFU +#define EFUSE_RTC_LDO_ACT_DBIAS13_M (EFUSE_RTC_LDO_ACT_DBIAS13_V << EFUSE_RTC_LDO_ACT_DBIAS13_S) +#define EFUSE_RTC_LDO_ACT_DBIAS13_V 0x000000FFU +#define EFUSE_RTC_LDO_ACT_DBIAS13_S 3 +/** EFUSE_RESERVED_2_171 : R; bitpos: [31:11]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_171 0x001FFFFFU +#define EFUSE_RESERVED_2_171_M (EFUSE_RESERVED_2_171_V << EFUSE_RESERVED_2_171_S) +#define EFUSE_RESERVED_2_171_V 0x001FFFFFU +#define EFUSE_RESERVED_2_171_S 11 /** EFUSE_RD_BLK2_DATA6_REG register * Register 6 of BLOCK2. @@ -749,9 +895,6 @@ extern "C" { #define EFUSE_CLK_EN_V 0x00000001U #define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - /** EFUSE_CONF_REG register * eFuse operation mode configuraiton register */ diff --git a/components/soc/esp32c2/include/soc/efuse_struct.h b/components/soc/esp32c2/include/soc/efuse_struct.h index c8de3d9991..c30ded3f9c 100644 --- a/components/soc/esp32c2/include/soc/efuse_struct.h +++ b/components/soc/esp32c2/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -165,7 +165,8 @@ typedef union { * Disable programming of individual eFuses. */ uint32_t wr_dis:8; - uint32_t reserved_8:24; + /** reserved_0_8 : RW; bitpos: [31:8]; default: 0; */ + uint32_t reserved_0_8:24; }; uint32_t val; } efuse_rd_wr_dis_reg_t; @@ -196,11 +197,11 @@ typedef union { * The bit be set to disable manual encryption. */ uint32_t dis_download_manual_encrypt:1; - /** spi_boot_encrypt_decrypt_cnt : RO; bitpos: [9:7]; default: 0; + /** spi_boot_crypt_cnt : RO; bitpos: [9:7]; default: 0; * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even * number of 1: disable. */ - uint32_t spi_boot_encrypt_decrypt_cnt:3; + uint32_t spi_boot_crypt_cnt:3; /** xts_key_length_256 : RO; bitpos: [10]; default: 0; * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, * XTS_AES use 128-bit eFuse data in BLOCK3. @@ -236,26 +237,26 @@ typedef union { * The bit be set to enable secure boot. */ uint32_t secure_boot_en:1; - /** secure_version : RO; bitpos: [25:22]; default: 0; - * Secure version for anti-rollback. + /** secure_version : R; bitpos: [25:22]; default: 0; + * Secure version for anti-rollback */ uint32_t secure_version:4; - /** enable_custom_mac : RO; bitpos: [26]; default: 0; - * True if custom_mac is burned. + /** custom_mac_used : R; bitpos: [26]; default: 0; + * True if MAC_CUSTOM is burned */ - uint32_t enable_custom_mac:1; - /** disable_wafer_version_major : RO; bitpos: [27]; default: 0; - * Disables check of wafer version major. + uint32_t custom_mac_used:1; + /** disable_wafer_version_major : R; bitpos: [27]; default: 0; + * Disables check of wafer version major */ uint32_t disable_wafer_version_major:1; - /** disable_blk_version_major : RO; bitpos: [28]; default: 0; - * Disables check of blk version major. + /** disable_blk_version_major : R; bitpos: [28]; default: 0; + * Disables check of blk version major */ uint32_t disable_blk_version_major:1; - /** rpt4_reserved : RO; bitpos: [31:29]; default: 0; - * Reserved (used for four backups method). + /** reserved_0_61 : R; bitpos: [31:29]; default: 0; + * reserved */ - uint32_t rpt4_reserved:3; + uint32_t reserved_0_61:3; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -265,10 +266,10 @@ typedef union { */ typedef union { struct { - /** system_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the bits [0:31] of system data. + /** custom_mac : R; bitpos: [31:0]; default: 0; + * Custom MAC address */ - uint32_t system_data0:32; + uint32_t custom_mac:32; }; uint32_t val; } efuse_rd_blk1_data0_reg_t; @@ -278,10 +279,14 @@ typedef union { */ typedef union { struct { - /** system_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the bits [32:63] of system data. + /** custom_mac_1 : R; bitpos: [15:0]; default: 0; + * Custom MAC address */ - uint32_t system_data1:32; + uint32_t custom_mac_1:16; + /** reserved_1_48 : R; bitpos: [31:16]; default: 0; + * reserved + */ + uint32_t reserved_1_48:16; }; uint32_t val; } efuse_rd_blk1_data1_reg_t; @@ -305,10 +310,10 @@ typedef union { */ typedef union { struct { - /** blk2_data0 : RO; bitpos: [31:0]; default: 0; - * Store the bit [0:31] of MAC. + /** mac : R; bitpos: [31:0]; default: 0; + * MAC address */ - uint32_t blk2_data0:32; + uint32_t mac:32; }; uint32_t val; } efuse_rd_blk2_data0_reg_t; @@ -318,34 +323,34 @@ typedef union { */ typedef union { struct { - /** mac_id_high : RO; bitpos: [15:0]; default: 0; - * Store the bit [31:47] of MAC. + /** mac_1 : R; bitpos: [15:0]; default: 0; + * MAC address */ - uint32_t mac_id_high:16; - /** wafer_version_minor : RO; bitpos: [19:16]; default: 0; - * Store wafer version minor. + uint32_t mac_1:16; + /** wafer_version_minor : R; bitpos: [19:16]; default: 0; + * WAFER_VERSION_MINOR */ uint32_t wafer_version_minor:4; - /** wafer_version_major : RO; bitpos: [21:20]; default: 0; - * Store wafer version major. + /** wafer_version_major : R; bitpos: [21:20]; default: 0; + * WAFER_VERSION_MAJOR */ uint32_t wafer_version_major:2; - /** pkg_version : RO; bitpos: [24:22]; default: 0; - * Store package version. + /** pkg_version : R; bitpos: [24:22]; default: 0; + * EFUSE_PKG_VERSION */ uint32_t pkg_version:3; - /** blk_version_minor : RO; bitpos: [27:25]; default: 0; - * Store blk 2 efuse version minor. + /** blk_version_minor : R; bitpos: [27:25]; default: 0; + * Minor version of BLOCK2 */ uint32_t blk_version_minor:3; - /** blk_version_major : RO; bitpos: [29:28]; default: 0; - * Store blk 2 efuse version major. + /** blk_version_major : R; bitpos: [29:28]; default: 0; + * Major version of BLOCK2 */ uint32_t blk_version_major:2; - /** ocode_lo : RO; bitpos: [31:30]; - * Store ocode. + /** ocode : R; bitpos: [31:30]; default: 0; + * OCode */ - uint32_t ocode_low:2; + uint32_t ocode:2; }; uint32_t val; } efuse_rd_blk2_data1_reg_t; @@ -355,18 +360,26 @@ typedef union { */ typedef union { struct { - /** ocode_hi : RO; bitpos: [4:0]; - * Store ocode. + /** ocode_1 : R; bitpos: [4:0]; default: 0; + * OCode */ - uint32_t ocode_hi:5; - /** ldo_vol_bias_config_high : RO; bitpos: [26:5]; default: 0; - * ido configuration parameters. + uint32_t ocode_1:5; + /** temp_calib : R; bitpos: [13:5]; default: 0; + * Temperature calibration data */ - uint32_t ldo_vol_bias_config_high:22; - /** pvt_low : RO; bitpos: [31:27]; default: 0; - * Store the bit [0:4] of pvt. + uint32_t temp_calib:9; + /** adc1_init_code_atten0 : R; bitpos: [21:14]; default: 0; + * ADC1 init code at atten0 */ - uint32_t pvt_low:5; + uint32_t adc1_init_code_atten0:8; + /** adc1_init_code_atten3 : R; bitpos: [26:22]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:5; + /** adc1_cal_vol_atten0 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:5; }; uint32_t val; } efuse_rd_blk2_data2_reg_t; @@ -376,11 +389,30 @@ typedef union { */ typedef union { struct { - uint32_t reserved1:9; + /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0_1:3; + /** adc1_cal_vol_atten3 : R; bitpos: [8:3]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:6; + /** dig_dbias_hvt : R; bitpos: [13:9]; default: 0; + * BLOCK2 digital dbias when hvt + */ uint32_t dig_dbias_hvt:5; + /** dig_ldo_slp_dbias2 : R; bitpos: [20:14]; default: 0; + * BLOCK2 DIG_LDO_DBG0_DBIAS2 + */ uint32_t dig_ldo_slp_dbias2:7; + /** dig_ldo_slp_dbias26 : R; bitpos: [28:21]; default: 0; + * BLOCK2 DIG_LDO_DBG0_DBIAS26 + */ uint32_t dig_ldo_slp_dbias26:8; - uint32_t dig_ldo_act_dbias26_low:3; + /** dig_ldo_act_dbias26 : R; bitpos: [31:29]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS26 + */ + uint32_t dig_ldo_act_dbias26:3; }; uint32_t val; } efuse_rd_blk2_data3_reg_t; @@ -390,12 +422,30 @@ typedef union { */ typedef union { struct { - uint32_t dig_ldo_act_dbias26_hi:3; + /** dig_ldo_act_dbias26_1 : R; bitpos: [2:0]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS26 + */ + uint32_t dig_ldo_act_dbias26_1:3; + /** dig_ldo_act_stepd10 : R; bitpos: [6:3]; default: 0; + * BLOCK2 DIG_LDO_ACT_STEPD10 + */ uint32_t dig_ldo_act_stepd10:4; + /** rtc_ldo_slp_dbias13 : R; bitpos: [13:7]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS13 + */ uint32_t rtc_ldo_slp_dbias13:7; + /** rtc_ldo_slp_dbias29 : R; bitpos: [22:14]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS29 + */ uint32_t rtc_ldo_slp_dbias29:9; + /** rtc_ldo_slp_dbias31 : R; bitpos: [28:23]; default: 0; + * BLOCK2 DIG_LDO_SLP_DBIAS31 + */ uint32_t rtc_ldo_slp_dbias31:6; - uint32_t rtc_ldo_act_dbias31_low:3; + /** rtc_ldo_act_dbias31 : R; bitpos: [31:29]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS31 + */ + uint32_t rtc_ldo_act_dbias31:3; }; uint32_t val; } efuse_rd_blk2_data4_reg_t; @@ -405,9 +455,18 @@ typedef union { */ typedef union { struct { - uint32_t rtc_ldo_act_dbias31_hi:3; + /** rtc_ldo_act_dbias31_1 : R; bitpos: [2:0]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS31 + */ + uint32_t rtc_ldo_act_dbias31_1:3; + /** rtc_ldo_act_dbias13 : R; bitpos: [10:3]; default: 0; + * BLOCK2 DIG_LDO_ACT_DBIAS13 + */ uint32_t rtc_ldo_act_dbias13:8; - uint32_t reserved2:21; + /** reserved_2_171 : R; bitpos: [31:11]; default: 0; + * reserved + */ + uint32_t reserved_2_171:21; }; uint32_t val; } efuse_rd_blk2_data5_reg_t; diff --git a/components/soc/esp32c3/include/soc/efuse_defs.h b/components/soc/esp32c3/include/soc/efuse_defs.h new file mode 100644 index 0000000000..55f3abff56 --- /dev/null +++ b/components/soc/esp32c3/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h index 0b612fd64f..29dafb6df5 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/include/soc/efuse_reg.h @@ -1,2015 +1,2623 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Disable programming of individual eFuses.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_POWER_GLITCH_DSENSE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Sample delay configuration of power glitch.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable power glitch function.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to vdd spi pin function as gpio.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange USB D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encryption when in download boot modes.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 - means disable ). JTAG can be enabled in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag - through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable TWAI function.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable usb device.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable function of usb switch to jtag in module of usb device.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of - 1: enable. even number of 1: disable.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold in unit of slow clock - cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF -#define EFUSE_RPT4_RESERVED2_S 0 +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - If the value is less than 15 the waiting time is the configurable value*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_V 0x1 -#define EFUSE_ERR_RST_ENABLE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature).*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : R/W ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Set the default UARTboot message output mode. 00: Enabled. 01: - Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB-Serial-JTAG.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Disable USB-Serial-JTAG print during rom boot.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable direct boot*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the seventh 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of POWER_GLITCH_DSENSE.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The value of POWERGLITCH_EN.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: The value of BTLC_GPIO_ENABLE.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_AS_GPIO.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The value of USB_EXCHG_PINS.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The value of DIS_PAD_JTAG.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The value of JTAG_SEL_ENABLE.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The value of DIS_TWAI.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_DEVICE.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_JTAG.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_RPT4_RESERVED6 : RO; bitpos: [13]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED6 (BIT(13)) +#define EFUSE_RPT4_RESERVED6_M (EFUSE_RPT4_RESERVED6_V << EFUSE_RPT4_RESERVED6_S) +#define EFUSE_RPT4_RESERVED6_V 0x00000001U +#define EFUSE_RPT4_RESERVED6_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Set this bit to vdd spi pin function as gpio. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; + * Enable btlc gpio. + */ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0; + * Set this bit to enable power glitch function. + */ +#define EFUSE_POWERGLITCH_EN (BIT(29)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 29 +/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0; + * Sample delay configuration of power glitch. + */ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED2 0x0000FFFFU +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000FFFFU #define EFUSE_RPT4_RESERVED2_S 0 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED3 0x0000000FU +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x0000000FU +#define EFUSE_RPT4_RESERVED3_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED0 0x0000003FU +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED0_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value; Otherwise, the waiting time is + * twice the configurable value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C) -/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_V 0x1 -#define EFUSE_ERR_RST_ENABLE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The value of DIS_DIRECT_BOOT.*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) +#define EFUSE_FLASH_ECC_MODE_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Disable UART download mode through USB-Serial-JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) +#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) +#define EFUSE_FLASH_ECC_EN_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_S 12 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 14 +/** EFUSE_RESERVED_0_158 : R; bitpos: [30]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_158 (BIT(30)) +#define EFUSE_RESERVED_0_158_M (EFUSE_RESERVED_0_158_V << EFUSE_RESERVED_0_158_S) +#define EFUSE_RESERVED_0_158_V 0x00000001U +#define EFUSE_RESERVED_0_158_S 30 +/** EFUSE_ERR_RST_ENABLE : R; bitpos: [31]; default: 0; + * Use BLOCK0 to check error record registers + */ +#define EFUSE_ERR_RST_ENABLE (BIT(31)) +#define EFUSE_ERR_RST_ENABLE_M (EFUSE_ERR_RST_ENABLE_V << EFUSE_ERR_RST_ENABLE_S) +#define EFUSE_ERR_RST_ENABLE_V 0x00000001U +#define EFUSE_ERR_RST_ENABLE_S 31 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * BLOCK1 data register 0. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * BLOCK1 data register 1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI PAD CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI PAD Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI PAD D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04C) -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI PAD D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI PAD CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI PAD HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI PAD WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI PAD DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI PAD D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Stores the fist 8 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x000000FF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0xFF -#define EFUSE_SYS_DATA_PART0_0_S 25 -/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: Package version 0:ESP32-C3 */ -#define EFUSE_PKG_VERSION 0x00000007 -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0x7 +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI PAD D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI PAD D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI PAD D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U #define EFUSE_PKG_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 24 +/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 0x0000001FU +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x0000001FU +#define EFUSE_RESERVED_1_123_S 27 -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register 4. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RESERVED_1_128 : R; bitpos: [6:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_128 0x0000007FU +#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S) +#define EFUSE_RESERVED_1_128_V 0x0000007FU +#define EFUSE_RESERVED_1_128_S 0 +/** EFUSE_K_RTC_LDO : R; bitpos: [13:7]; default: 0; + * BLOCK1 K_RTC_LDO + */ +#define EFUSE_K_RTC_LDO 0x0000007FU +#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) +#define EFUSE_K_RTC_LDO_V 0x0000007FU +#define EFUSE_K_RTC_LDO_S 7 +/** EFUSE_K_DIG_LDO : R; bitpos: [20:14]; default: 0; + * BLOCK1 K_DIG_LDO + */ +#define EFUSE_K_DIG_LDO 0x0000007FU +#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) +#define EFUSE_K_DIG_LDO_V 0x0000007FU +#define EFUSE_K_DIG_LDO_S 14 +/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [28:21]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20 0x000000FFU +#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) +#define EFUSE_V_RTC_DBIAS20_V 0x000000FFU +#define EFUSE_V_RTC_DBIAS20_S 21 +/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [31:29]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20 0x00000007U +#define EFUSE_V_DIG_DBIAS20_M (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S) +#define EFUSE_V_DIG_DBIAS20_V 0x00000007U +#define EFUSE_V_DIG_DBIAS20_S 29 -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * BLOCK1 data register 5. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_V_DIG_DBIAS20_1 : R; bitpos: [4:0]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20_1 0x0000001FU +#define EFUSE_V_DIG_DBIAS20_1_M (EFUSE_V_DIG_DBIAS20_1_V << EFUSE_V_DIG_DBIAS20_1_S) +#define EFUSE_V_DIG_DBIAS20_1_V 0x0000001FU +#define EFUSE_V_DIG_DBIAS20_1_S 0 +/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [9:5]; default: 0; + * BLOCK1 digital dbias when hvt + */ +#define EFUSE_DIG_DBIAS_HVT 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) +#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_S 5 +/** EFUSE_THRES_HVT : R; bitpos: [19:10]; default: 0; + * BLOCK1 pvt threshold when hvt + */ +#define EFUSE_THRES_HVT 0x000003FFU +#define EFUSE_THRES_HVT_M (EFUSE_THRES_HVT_V << EFUSE_THRES_HVT_S) +#define EFUSE_THRES_HVT_V 0x000003FFU +#define EFUSE_THRES_HVT_S 10 +/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_180 0x00000007U +#define EFUSE_RESERVED_1_180_M (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S) +#define EFUSE_RESERVED_1_180_V 0x00000007U +#define EFUSE_RESERVED_1_180_S 20 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(23)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 23 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 24 +/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_186 0x0000003FU +#define EFUSE_RESERVED_1_186_M (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S) +#define EFUSE_RESERVED_1_186_V 0x0000003FU +#define EFUSE_RESERVED_1_186_S 26 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 0 +/** EFUSE_RESERVED_2_130 : R; bitpos: [2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_130 (BIT(2)) +#define EFUSE_RESERVED_2_130_M (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S) +#define EFUSE_RESERVED_2_130_V 0x00000001U +#define EFUSE_RESERVED_2_130_S 2 +/** EFUSE_TEMP_CALIB : R; bitpos: [11:3]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 3 +/** EFUSE_OCODE : R; bitpos: [19:12]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 12 +/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [29:20]; default: 0; + * ADC1 init code at atten0 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 20 +/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:30]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x00000003U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x00000003U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 30 -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [7:0]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [17:8]; default: 0; + * ADC1 init code at atten2 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 8 +/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [27:18]; default: 0; + * ADC1 init code at atten3 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x000003FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 18 +/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:28]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 28 -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [5:0]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0 +/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [15:6]; default: 0; + * ADC1 calibration voltage at atten1 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 6 +/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [25:16]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 16 +/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x0000003FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 26 -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [3:0]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V 0x0000000FU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S 0 +/** EFUSE_RESERVED_2_228 : R; bitpos: [31:4]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_228 0x0FFFFFFFU +#define EFUSE_RESERVED_2_228_M (EFUSE_RESERVED_2_228_V << EFUSE_RESERVED_2_228_S) +#define EFUSE_RESERVED_2_228_V 0x0FFFFFFFU +#define EFUSE_RESERVED_2_228_S 4 -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0A0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0A4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0A8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0AC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0B0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0B4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0B8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0BC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0C0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0C4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0C8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0CC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0D0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0D4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0D8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0DC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0E0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0E4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0E8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0EC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0F0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0F4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0F8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0FC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 -/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If POWERGLITCH_EN is 1 then it indicates a programming error.*/ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 -#define EFUSE_POWERGLITCH_EN_ERR_S 29 -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/* EFUSE_VDD_SPI_AS_GPIO_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 23 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If DIS_TWAI is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_V 0x1 -#define EFUSE_DIS_TWAI_ERR_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED6_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If DIS_USB_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If DIS_ICACHE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * If DIS_USB_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0; + * If DIS_USB_DEVICE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DEVICE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_RPT4_RESERVED6_ERR : RO; bitpos: [13]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) +#define EFUSE_RPT4_RESERVED6_ERR_M (EFUSE_RPT4_RESERVED6_ERR_V << EFUSE_RPT4_RESERVED6_ERR_S) +#define EFUSE_RPT4_RESERVED6_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED6_ERR_S 13 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If DIS_CAN is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * If SOFT_DIS_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * If DIS_PAD_JTAG is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * If any bit in USB_DREFH is 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * If any bit in USB_DREFL is 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * If USB_EXCHG_PINS is 1, then it indicates a programming error. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. + */ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) +#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0; + * If POWERGLITCH_EN is 1, then it indicates a programming error. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 29 +/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. + */ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFF +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFFU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000FFFFU #define EFUSE_RPT4_RESERVED2_ERR_S 0 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED0_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3_ERR 0x0000000F -#define EFUSE_RPT4_RESERVED3_ERR_M ((EFUSE_RPT4_RESERVED3_ERR_V)<<(EFUSE_RPT4_RESERVED3_ERR_S)) -#define EFUSE_RPT4_RESERVED3_ERR_V 0xF -#define EFUSE_RPT4_RESERVED3_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR 0x0000000FU +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x0000000FU +#define EFUSE_RPT4_RESERVED3_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If SECURE_BOOT_EN is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000003FU +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000003FU +#define EFUSE_RPT4_RESERVED0_ERR_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in FLASH_TPUM is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Use BLOCK0 to check error record registers, 0 - without check.*/ -#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31)) -#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1 -#define EFUSE_ERR_RST_ENABLE_ERR_S 31 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_RPT4_RESERVED7_ERR : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED7_ERR_M ((EFUSE_RPT4_RESERVED7_ERR_V)<<(EFUSE_RPT4_RESERVED7_ERR_S)) -#define EFUSE_RPT4_RESERVED7_ERR_V 0x1F -#define EFUSE_RPT4_RESERVED7_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_RPT4_RESERVED8_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED8_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If DIS_DIRECT_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; + * If FLASH_ECC_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) +#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If PIN_POWER_SELECTION is 1, then it indicates a programming error. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If FLASH_TYPE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; + * If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 +/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; + * If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_ERR_S 12 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * If FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; + * If any bit in SECURE_VERSION is 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 14 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR 0x00000003U +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000003U +#define EFUSE_RPT4_RESERVED1_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED4_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY3_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key3 is reliable 1: - Means that programming key3 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY3_FAIL (BIT(31)) -#define EFUSE_KEY3_FAIL_M (BIT(31)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key2 is reliable 1: - Means that programming key2 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY2_FAIL (BIT(27)) -#define EFUSE_KEY2_FAIL_M (BIT(27)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key1 is reliable 1: - Means that programming key1 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY1_FAIL (BIT(23)) -#define EFUSE_KEY1_FAIL_M (BIT(23)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key0 is reliable 1: - Means that programming key0 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY0_FAIL (BIT(19)) -#define EFUSE_KEY0_FAIL_M (BIT(19)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of user data is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_USR_DATA_FAIL (BIT(15)) -#define EFUSE_USR_DATA_FAIL_M (BIT(15)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable - 1: Means that programming data of system part1 failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART1_FAIL (BIT(11)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(11)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable - 1: Means that programming MAC_SPI_8M failed and the number of error bytes is over 6.*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(7)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(7)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_RESERVED_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_RESERVED_FAIL (BIT(3)) +#define EFUSE_RESERVED_FAIL_M (EFUSE_RESERVED_FAIL_V << EFUSE_RESERVED_FAIL_S) +#define EFUSE_RESERVED_FAIL_V 0x00000001U +#define EFUSE_RESERVED_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(7)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(11)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(15)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY0_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(19)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY1_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(23)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY2_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(27)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY3_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(31)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_KEY5_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: - Means that programming KEY5 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY5_FAIL (BIT(7)) -#define EFUSE_KEY5_FAIL_M (BIT(7)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY4_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY4 is reliable 1: - Means that programming KEY4 failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY4_FAIL (BIT(3)) -#define EFUSE_KEY4_FAIL_M (BIT(3)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY4_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(3)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_KEY5_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(7)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register; + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU #define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007200 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index 230064321e..459c5483de 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -1,532 +1,2378 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/ - union { - struct { - uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t rpt4_reserved5: 1; /*Reserved*/ - uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ - uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ - uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/ - uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/ - uint32_t dis_can: 1; /*Set this bit to disable CAN function.*/ - uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t usb_drefh: 2; /*Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_drefl: 2; /*Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_exchg_pins: 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t vdd_spi_as_gpio: 1; /*Set this bit to vdd spi pin function as gpio.*/ - uint32_t btlc_gpio_enable: 2; /*Enable btlc gpio.*/ - uint32_t powerglitch_en: 1; /*Set this bit to enable power glitch function.*/ - uint32_t power_glitch_dsense: 2; /*Sample delay configuration of power glitch.*/ - }; - uint32_t val; - } pgm_data1; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved (used for four backups method).*/ - uint32_t wat_delay_sel: 2; /*Selects RTC watchdog timeout threshold in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t spi_boot_crypt_cnt: 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t secure_boot_key_revoke0: 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t secure_boot_key_revoke1: 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t secure_boot_key_revoke2: 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t key_purpose_0: 4; /*Purpose of Key0.*/ - uint32_t key_purpose_1: 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } pgm_data2; - union { - struct { - uint32_t key_purpose_2: 4; /*Purpose of Key2.*/ - uint32_t key_purpose_3: 4; /*Purpose of Key3.*/ - uint32_t key_purpose_4: 4; /*Purpose of Key4.*/ - uint32_t key_purpose_5: 4; /*Purpose of Key5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved (used for four backups method).*/ - uint32_t secure_boot_en: 1; /*Set this bit to enable secure boot.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t rpt4_reserved0: 6; /*Reserved (used for four backups method).*/ - uint32_t flash_tpuw: 4; /*Configures flash waiting time after power-up in unit of ms. If the value is less than 15 the waiting time is the configurable value*/ - }; - uint32_t val; - } pgm_data3; - union { - struct { - uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ - uint32_t dis_direct_boot: 1; /*Set this bit to disable direct boot.*/ - uint32_t dis_usb_serial_jtag_rom_print: 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t rpt4_reserved8: 1; /*Reserved (used for four backups method).*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download mode through USB-Serial-JTAG.*/ - uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/ - uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t rpt4_reserved1: 1; /*Reserved (used for four backups method).*/ - uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } pgm_data4; - union { - struct { - uint32_t rpt4_reserved4:24; /*Reserved (used for four backups method).*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } pgm_data5; - uint32_t pgm_data6; /*Register 6 that stores data to be programmed.*/ - uint32_t pgm_data7; /*Register 7 that stores data to be programmed.*/ - uint32_t pgm_check_value0; /*Register 0 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value1; /*Register 1 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value2; /*Register 2 that stores the RS code to be programmed.*/ - uint32_t rd_wr_dis; /*BLOCK0 data register $n.*/ - union { - struct { - uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t rpt4_reserved5: 1; /*Reserved*/ - uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ - uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ - uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ - uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/ - uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/ - uint32_t dis_usb: 1; /*The value of DIS_USB.*/ - uint32_t dis_can: 1; /*The value of DIS_CAN.*/ - uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/ - uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/ - uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/ - uint32_t dis_download_manual_encrypt: 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ - uint32_t usb_drefh: 2; /*The value of USB_DREFH.*/ - uint32_t usb_drefl: 2; /*The value of USB_DREFL.*/ - uint32_t usb_exchg_pins: 1; /*The value of USB_EXCHG_PINS.*/ - uint32_t vdd_spi_as_gpio: 1; /*The value of VDD_SPI_AS_GPIO.*/ - uint32_t btlc_gpio_enable: 2; /*The value of BTLC_GPIO_ENABLE.*/ - uint32_t powerglitch_en: 1; /*The value of POWERGLITCH_EN.*/ - uint32_t power_glitch_dsense: 2; /*The value of POWER_GLITCH_DSENSE.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved.*/ - uint32_t wdt_delay_sel: 2; /*The value of WDT_DELAY_SEL.*/ - uint32_t spi_boot_crypt_cnt: 3; /*The value of SPI_BOOT_CRYPT_CNT.*/ - uint32_t secure_boot_key_revoke0: 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/ - uint32_t secure_boot_key_revoke1: 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/ - uint32_t secure_boot_key_revoke2: 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/ - uint32_t key_purpose_0: 4; /*The value of KEY_PURPOSE_0.*/ - uint32_t key_purpose_1: 4; /*The value of KEY_PURPOSE_1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2: 4; /*The value of KEY_PURPOSE_2.*/ - uint32_t key_purpose_3: 4; /*The value of KEY_PURPOSE_3.*/ - uint32_t key_purpose_4: 4; /*The value of KEY_PURPOSE_4.*/ - uint32_t key_purpose_5: 4; /*The value of KEY_PURPOSE_5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved.*/ - uint32_t secure_boot_en: 1; /*The value of SECURE_BOOT_EN.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ - uint32_t rpt4_reserved0: 6; /*Reserved.*/ - uint32_t flash_tpuw: 4; /*The value of FLASH_TPUW.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot: 1; /*The value of DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print:1; /*The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ - uint32_t rpt4_reserved8: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*The value of dis_usb_serial_jtag_download_mode.*/ - uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/ - uint32_t rpt4_reserved7: 5; /*Reserved.*/ - uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/ - uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/ - uint32_t rpt4_reserved1: 1; /*Reserved.*/ - uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major: 1; - uint32_t disable_blk_version_major: 1; - uint32_t rpt4_reserved4:22; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t spi_pad_conf_0:16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version_minor_low: 3; - uint32_t pkg_version: 3; - uint32_t blk_version_minor:3; - uint32_t sys_data_part0_0: 5; - }; - uint32_t val; - } rd_mac_spi_sys_3; - union { - struct { - uint32_t reserved1: 7; - uint32_t k_rtc_ldo: 7; - uint32_t k_dig_ldo: 7; - uint32_t v_rtc_dbias20: 8; - uint32_t v_dig_dbias20_low: 3; - }; - uint32_t val; - } rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t v_dig_dbias20_hi: 5; - uint32_t dig_dbias_hvt: 5; - uint32_t reserved1: 13; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; - }; - uint32_t val; - } rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ - uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ - union { - struct { - uint32_t blk_version_major: 2; - uint32_t reserved1: 10; - uint32_t ocode: 8; - uint32_t reserved2: 12; - }; - uint32_t val; - } rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_usr_data0; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data1; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data2; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data3; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data4; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data5; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data6; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data7; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_key0_data0; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data1; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data2; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data3; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data4; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data5; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data6; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data7; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key1_data0; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data1; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data2; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data3; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data4; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data5; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data6; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data7; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key2_data0; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data1; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data2; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data3; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data4; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data5; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data6; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data7; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key3_data0; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data1; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data2; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data3; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data4; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data5; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data6; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data7; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key4_data0; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data1; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data2; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data3; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data4; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data5; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data6; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data7; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key5_data0; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data2; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data3; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data4; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data5; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data6; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data7; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data0; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data2; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data3; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data4; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data5; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data6; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data7; /*Register $n of BLOCK10 (system).*/ - union { - struct { - uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved5_err: 1; /*Reserved.*/ - uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ - uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ - uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/ - uint32_t dis_can_err: 1; /*If DIS_CAN is 1 then it indicates a programming error.*/ - uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ - uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ - uint32_t usb_drefh_err: 2; /*If any bit in USB_DREFH is 1 then it indicates a programming error.*/ - uint32_t usb_drefl_err: 2; /*If any bit in USB_DREFL is 1 then it indicates a programming error.*/ - uint32_t usb_exchg_pins_err: 1; /*If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ - uint32_t vdd_spi_as_gpio_err: 1; /*If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ - uint32_t btlc_gpio_enable_err: 2; /*If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ - uint32_t powerglitch_en_err: 1; /*If POWERGLITCH_EN is 1 then it indicates a programming error.*/ - uint32_t power_glitch_dsense_err: 2; /*If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t rpt4_reserved2_err: 16; /*Reserved.*/ - uint32_t wdt_delay_sel_err: 2; /*If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ - uint32_t spi_boot_crypt_cnt_err: 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke0_err: 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke1_err: 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke2_err: 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_0_err: 4; /*If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_1_err: 4; /*If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t key_purpose_2_err: 4; /*If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_3_err: 4; /*If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_4_err: 4; /*If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_5_err: 4; /*If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved3_err: 4; /*Reserved.*/ - uint32_t secure_boot_en_err: 1; /*If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ - uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved0_err: 6; /*Reserved.*/ - uint32_t flash_tpuw_err: 4; /*If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t dis_download_mode_err: 1; /*If the value is not zero then it indicates a programming error on DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot_err: 1; /*If the value is not zero then it indicates a programming error on DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print_err:1; /*If the value is not zero then it indicates a programming error on DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ - uint32_t rpt4_reserved8_err: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode_err: 1; /*If the value is not zero then it indicates a programming error on DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ - uint32_t enable_security_download_err: 1; /*If the value is not zero then it indicates a programming error on ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control_err: 2; /*If the value is not zero then it indicates a programming error on UART_PRINT_CONTROL.*/ - uint32_t rpt4_reserved7_err: 5; /*Reserved*/ - uint32_t force_send_resume_err: 1; /*If the value is not zero then it indicates a programming error on FORCE_SEND_RESUME.*/ - uint32_t secure_version_err: 16; /*If the value is not zero then it indicates a programming error on SECURE_VERSION.*/ - uint32_t rpt4_reserved1_err: 1; /*Reserved.*/ - uint32_t err_rst_enable_err: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t rpt4_reserved4_err:24; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t reserved3: 1; /*Reserved.*/ - uint32_t sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming MAC_SPI_8M failed and the number of error bytes is over 6.*/ - uint32_t usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming the data of system part1 failed and the number of error bytes is over 6.*/ - uint32_t key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t usr_data_fail: 1; /*0: Means no failure and that the data of user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key0_fail: 1; /*0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.*/ - uint32_t key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key1_fail: 1; /*0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.*/ - uint32_t key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key2_fail: 1; /*0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.*/ - uint32_t key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key3_fail: 1; /*0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key4_fail: 1; /*0: Means no failure and that the data of KEY4 is reliable 1: Means that programming KEY4 failed and the number of error bytes is over 6.*/ - uint32_t sys_part2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming KEY5 failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16:16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0: 24; /*Configures the setup time of read operation.*/ - uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t reserved0: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num:16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num:16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ + uint32_t dis_usb_jtag:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_icache:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** rpt4_reserved6 : RO; bitpos: [13]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved6:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Set this bit to vdd spi pin function as gpio. + */ + uint32_t vdd_spi_as_gpio:1; + /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; + * Enable btlc gpio. + */ + uint32_t btlc_gpio_enable:2; + /** powerglitch_en : RO; bitpos: [29]; default: 0; + * Set this bit to enable power glitch function. + */ + uint32_t powerglitch_en:1; + /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0; + * Sample delay configuration of power glitch. + */ + uint32_t power_glitch_dsense:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved2:16; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved3:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved0:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value; Otherwise, the waiting time is + * twice the configurable value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** flash_ecc_mode : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ + uint32_t flash_ecc_mode:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Disable UART download mode through USB-Serial-JTAG + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ + uint32_t flash_ecc_en:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** reserved_0_158 : R; bitpos: [30]; default: 0; + * reserved + */ + uint32_t reserved_0_158:1; + /** err_rst_enable : R; bitpos: [31]; default: 0; + * Use BLOCK0 to check error record registers + */ + uint32_t err_rst_enable:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI PAD CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI PAD Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI PAD D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI PAD D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI PAD CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI PAD HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI PAD WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI PAD DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI PAD D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI PAD D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI PAD D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI PAD D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** pkg_version : R; bitpos: [23:21]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** blk_version_minor : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ + uint32_t blk_version_minor:3; + /** reserved_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ +typedef union { + struct { + /** reserved_1_128 : R; bitpos: [6:0]; default: 0; + * reserved + */ + uint32_t reserved_1_128:7; + /** k_rtc_ldo : R; bitpos: [13:7]; default: 0; + * BLOCK1 K_RTC_LDO + */ + uint32_t k_rtc_ldo:7; + /** k_dig_ldo : R; bitpos: [20:14]; default: 0; + * BLOCK1 K_DIG_LDO + */ + uint32_t k_dig_ldo:7; + /** v_rtc_dbias20 : R; bitpos: [28:21]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20:8; + /** v_dig_dbias20 : R; bitpos: [31:29]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20:3; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ +typedef union { + struct { + /** v_dig_dbias20_1 : R; bitpos: [4:0]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20_1:5; + /** dig_dbias_hvt : R; bitpos: [9:5]; default: 0; + * BLOCK1 digital dbias when hvt + */ + uint32_t dig_dbias_hvt:5; + /** thres_hvt : R; bitpos: [19:10]; default: 0; + * BLOCK1 pvt threshold when hvt + */ + uint32_t thres_hvt:10; + /** reserved_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t reserved_1_180:3; + /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** wafer_version_major : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** reserved_1_186 : R; bitpos: [31:26]; default: 0; + * reserved + */ + uint32_t reserved_1_186:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** blk_version_major : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** reserved_2_130 : R; bitpos: [2]; default: 0; + * reserved + */ + uint32_t reserved_2_130:1; + /** temp_calib : R; bitpos: [11:3]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** ocode : R; bitpos: [19:12]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_init_code_atten0 : R; bitpos: [29:20]; default: 0; + * ADC1 init code at atten0 + */ + uint32_t adc1_init_code_atten0:10; + /** adc1_init_code_atten1 : R; bitpos: [31:30]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1:2; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_init_code_atten1_1 : R; bitpos: [7:0]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1_1:8; + /** adc1_init_code_atten2 : R; bitpos: [17:8]; default: 0; + * ADC1 init code at atten2 + */ + uint32_t adc1_init_code_atten2:10; + /** adc1_init_code_atten3 : R; bitpos: [27:18]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:10; + /** adc1_cal_vol_atten0 : R; bitpos: [31:28]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:4; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten0_1 : R; bitpos: [5:0]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0_1:6; + /** adc1_cal_vol_atten1 : R; bitpos: [15:6]; default: 0; + * ADC1 calibration voltage at atten1 + */ + uint32_t adc1_cal_vol_atten1:10; + /** adc1_cal_vol_atten2 : R; bitpos: [25:16]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2:10; + /** adc1_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:6; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten3_1 : R; bitpos: [3:0]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3_1:4; + /** reserved_2_228 : R; bitpos: [31:4]; default: 0; + * reserved + */ + uint32_t reserved_2_228:28; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC address + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC address + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * If any bit in RD_DIS is 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * If DIS_ICACHE is 1, then it indicates a programming error. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * If DIS_USB_JTAG is 1, then it indicates a programming error. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_usb_device_err : RO; bitpos: [11]; default: 0; + * If DIS_USB_DEVICE is 1, then it indicates a programming error. + */ + uint32_t dis_usb_device_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. + */ + uint32_t dis_force_download_err:1; + /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved6_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * If DIS_CAN is 1, then it indicates a programming error. + */ + uint32_t dis_can_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * If SOFT_DIS_JTAG is 1, then it indicates a programming error. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * If DIS_PAD_JTAG is 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * If any bit in USB_DREFH is 1, then it indicates a programming error. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * If any bit in USB_DREFL is 1, then it indicates a programming error. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * If USB_EXCHG_PINS is 1, then it indicates a programming error. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; + * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. + */ + uint32_t btlc_gpio_enable_err:2; + /** powerglitch_en_err : RO; bitpos: [29]; default: 0; + * If POWERGLITCH_EN is 1, then it indicates a programming error. + */ + uint32_t powerglitch_en_err:1; + /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0; + * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. + */ + uint32_t power_glitch_dsense_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err:16; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. + */ + uint32_t key_purpose_5_err:4; + /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * If SECURE_BOOT_EN is 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * If any bit in FLASH_TPUM is 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * If UART_PRINT_CHANNEL is 1, then it indicates a programming error. + */ + uint32_t uart_print_channel_err:1; + /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; + * If FLASH_ECC_MODE is 1, then it indicates a programming error. + */ + uint32_t flash_ecc_mode_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * If PIN_POWER_SELECTION is 1, then it indicates a programming error. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * If FLASH_TYPE is 1, then it indicates a programming error. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; + * If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; + * If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. + */ + uint32_t flash_ecc_en_err:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If FORCE_SEND_RESUME is 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * If any bit in SECURE_VERSION is 1, then it indicates a programming error. + */ + uint32_t secure_version_err:16; + /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** reserved_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t reserved_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** mac_spi_8m_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** sys_part1_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** usr_data_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key0_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key1_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key2_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key3_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key4_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** key5_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register; + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 33583616; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; uint32_t reserved_1f8; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/include/soc/efuse_defs.h b/components/soc/esp32s2/include/soc/efuse_defs.h new file mode 100644 index 0000000000..55f3abff56 --- /dev/null +++ b/components/soc/esp32s2/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2/include/soc/efuse_reg.h b/components/soc/esp32s2/include/soc/efuse_reg.h index bb369fa740..b742bfc37c 100644 --- a/components/soc/esp32s2/include/soc/efuse_reg.h +++ b/components/soc/esp32s2/include/soc/efuse_reg.h @@ -1,2313 +1,2749 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - +#pragma once +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Set this bit to disable eFuse programming.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_VDD_SPI_DREFH : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: SPI regulator high voltage reference.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : R/W ;bitpos:[29] ;default: 1'h0 ; */ -/*description: SPI regulator switches current limit mode.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3 -#define EFUSE_RPT4_RESERVED0_S 27 -/* EFUSE_USB_FORCE_NOPERSIST : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Force nopersist to 1.*/ -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: Set this bit to enable external PHY.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Set this bit to exchange D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: Set this bit to disable flash encrypt function (except in SPI/HSPI/Legacy_SPI - boot mode).*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Set this bit to disable JTAG in the soft way. JTAG can be enabled - in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit to disable programming eFuse through ATE mode.*/ -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_BOOT_REMAP : R/W ;bitpos:[15] ;default: 1'h0 ; */ -/*description: Set this bit to disable boot remap from RAM to ROM.*/ -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_S 15 -/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'h0 ; */ -/*description: Set this bit to disable CAN function.*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'h0 ; */ -/*description: Set this bit to disable USB function.*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'h0 ; */ -/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to disable Dcache.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_RD_DIS_KEY0 (1<<0) -#define EFUSE_RD_DIS_KEY1 (1<<1) -#define EFUSE_RD_DIS_KEY2 (1<<2) -#define EFUSE_RD_DIS_KEY3 (1<<3) -#define EFUSE_RD_DIS_KEY4 (1<<4) -#define EFUSE_RD_DIS_KEY5 (1<<5) -#define EFUSE_RD_DIS_SYS_DATA_PART2 (1<<6) +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Prevents SPI regulator from overshoot.*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Adds resistor from LDO output to ground. 0: no resistance*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: Tunes the current limit threshold of SPI regulator when tieh=0 - about 800 mA/(8+d).*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set SPI regulator to 1 to enable output current limit.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set SPI regulator to 0 to configure init[1:0]=0.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: SPI regulator output is short connected to VDD3P3_RTC_IO.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: SPI regulator power up signal.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: SPI regulator low voltage reference.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI regulator medium voltage reference.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 -#define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - When the value is 15 the waiting time is 30 ms.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3F -#define EFUSE_RPT4_RESERVED1_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Purpose of Key6. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0x1F -#define EFUSE_RPT4_RESERVED2_S 27 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: IDF secure version.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 11 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 10 -/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The type of the interfaced flash. 0: four data lines 1: eight data lines.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The type of UART print control.00: Forces to print.01: Controlled - by GPIO46 print at low level.10: Controlled by GPIO46 print at high level.11: Forces to disable print.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: Set this bit to enable security download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED3 : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: Set this bit to disable tiny basic console in ROM.*/ -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_V 0x1 -#define EFUSE_RPT4_RESERVED3_S 3 -/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Selectes UART print channel. 0: UART0*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0 0x000000FF -#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) -#define EFUSE_RPT1_RESERVED0_V 0xFF -#define EFUSE_RPT1_RESERVED0_S 24 -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_S 0 +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01c) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of pgm data 7.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_S 0 +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_S 0 +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_S 0 +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02c) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_WR_DIS_RD_DIS (1<<0) -#define EFUSE_WR_DIS_DIS_RTC_RAM_BOOT (1<<1) -#define EFUSE_WR_DIS_GROUP_1 (1<<2) -#define EFUSE_WR_DIS_GROUP_2 (1<<3) -#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT (1<<4) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0 (1<<5) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1 (1<<6) -#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2 (1<<7) -#define EFUSE_WR_DIS_KEY0_PURPOSE (1<<8) -#define EFUSE_WR_DIS_KEY1_PURPOSE (1<<9) -#define EFUSE_WR_DIS_KEY2_PURPOSE (1<<10) -#define EFUSE_WR_DIS_KEY3_PURPOSE (1<<11) -#define EFUSE_WR_DIS_KEY4_PURPOSE (1<<12) -#define EFUSE_WR_DIS_KEY5_PURPOSE (1<<13) -#define EFUSE_WR_DIS_SECURE_BOOT_EN (1<<15) -#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE (1<<16) -#define EFUSE_WR_DIS_GROUP_3 (1<<18) -#define EFUSE_WR_DIS_BLK1 (1<<20) -#define EFUSE_WR_DIS_SYS_DATA_PART1 (1<<21) -#define EFUSE_WR_DIS_USER_DATA (1<<22) -#define EFUSE_WR_DIS_KEY0 (1<<23) -#define EFUSE_WR_DIS_KEY1 (1<<24) -#define EFUSE_WR_DIS_KEY2 (1<<25) -#define EFUSE_WR_DIS_KEY3 (1<<26) -#define EFUSE_WR_DIS_KEY4 (1<<27) -#define EFUSE_WR_DIS_KEY5 (1<<28) -#define EFUSE_WR_DIS_SYS_DATA_PART2 (1<<29) -#define EFUSE_WR_DIS_USB_EXCHG_PINS (1<<30) - - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFH.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_MODECURLIM.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3 -#define EFUSE_RPT4_RESERVED0_S 27 -/* EFUSE_USB_FORCE_NOPERSIST : RO ;bitpos:[26] ;default: 1'h0 ; */ -/*description: The value of usb_force_nopersist*/ -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: The value of EXT_PHY_ENABLE.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : RO ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : RO ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: The value of HARD_DIS_JTAG.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : RO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: The value of DIS_EFUSE_ATE_WR.*/ -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_BOOT_REMAP : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: The value of DIS_BOOT_REMAP.*/ -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_S 15 -/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'h0 ; */ -/*description: The value of DIS_CAN.*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'h0 ; */ -/*description: The value of DIS_USB.*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'h0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_DCACHE.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of DIS_DCACHE.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F +/** EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Reserved. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001U +#define EFUSE_DIS_DCACHE_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB OTG function. + */ +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001U +#define EFUSE_DIS_USB_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable the TWAI Controller function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001U +#define EFUSE_DIS_BOOT_REMAP_S 15 +/** EFUSE_RPT4_RESERVED5 : RO; bitpos: [16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED5 (BIT(16)) +#define EFUSE_RPT4_RESERVED5_M (EFUSE_RPT4_RESERVED5_V << EFUSE_RPT4_RESERVED5_S) +#define EFUSE_RPT4_RESERVED5_V 0x00000001U +#define EFUSE_RPT4_RESERVED5_S 16 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated temporarily + * by HMAC peripheral. + */ +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001U +#define EFUSE_SOFT_DIS_JTAG_S 17 +/** EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001U +#define EFUSE_HARD_DIS_JTAG_S 18 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 +/** EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 20 +/** EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 22 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 24 +/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ +#define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_USB_EXT_PHY_ENABLE_M (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S) +#define EFUSE_USB_EXT_PHY_ENABLE_V 0x00000001U +#define EFUSE_USB_EXT_PHY_ENABLE_S 25 +/** EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001U +#define EFUSE_USB_FORCE_NOPERSIST_S 26 +/** EFUSE_BLOCK0_VERSION : R; bitpos: [28:27]; default: 0; + * BLOCK0 efuse version + */ +#define EFUSE_BLOCK0_VERSION 0x00000003U +#define EFUSE_BLOCK0_VERSION_M (EFUSE_BLOCK0_VERSION_V << EFUSE_BLOCK0_VERSION_S) +#define EFUSE_BLOCK0_VERSION_V 0x00000003U +#define EFUSE_BLOCK0_VERSION_S 27 +/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ +#define EFUSE_VDD_SPI_DREFH 0x00000003U +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The value of REG_VDD_SPI_DCAP.*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_INIT.*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: The value of VDD_SPI_DCURLIM.*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_ENCURLIM.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_EN_INIT.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_FORCE.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_TIEH.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of VDD_SPI_XPD.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFL.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFM.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 +/** EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ +#define EFUSE_VDD_SPI_DREFM 0x00000003U +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ +#define EFUSE_VDD_SPI_DREFL 0x00000003U +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_S 2 +/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. + */ +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_S 4 +/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V + * LDO. 1: VDD_SPI connects to VDD_RTC_IO. + */ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_S 5 +/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + */ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_S 6 +/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. + */ +#define EFUSE_VDD_SPI_INIT 0x00000003U +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_S 12 +/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ +#define EFUSE_VDD_SPI_DCAP 0x00000003U +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_S 14 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: + * 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock + * cycles. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled + * 1 or 3 bits are set in the eFuse, disabled otherwise. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3F -#define EFUSE_RPT4_RESERVED1_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'h0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_6.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ +#define EFUSE_KEY_PURPOSE_6 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED1 0x0000003FU +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003FU +#define EFUSE_RPT4_RESERVED1_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). When the + * value is 15, delay is 7.5 ms. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03c) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0x1F -#define EFUSE_RPT4_RESERVED2_S 27 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 11 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 10 -/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of FLASH_TYPE.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of PIN_POWER_SELECTION.*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of DIS_USB_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The value of RPT4_RESERVED4.*/ -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_V 0x1 -#define EFUSE_RPT4_RESERVED3_S 3 -/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The value of UART_PRINT_CHANNEL.*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The value of DIS_LEGACY_SPI_BOOT.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +/** EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 +/** EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0. 1: UART1. + */ +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_S 2 +/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB OTG in UART download boot mode. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 + * is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: + * VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 10 +/** EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 11 +/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED2 0x0000001FU +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001FU +#define EFUSE_RPT4_RESERVED2_S 27 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0 0x000000FF -#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) -#define EFUSE_RPT1_RESERVED0_V 0xFF -#define EFUSE_RPT1_RESERVED0_S 24 -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved ( four backup method ).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +/** EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04c) -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: PSRAM version */ -#define EFUSE_PSRAM_VERSION 0x0000000F -#define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S)) -#define EFUSE_PSRAM_VERSION_V 0xF -#define EFUSE_PSRAM_VERSION_S 28 -/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */ -/*description: Flash version */ -#define EFUSE_FLASH_VERSION 0x0000000F -#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S)) -#define EFUSE_FLASH_VERSION_V 0xF +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [19:18]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 18 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [20]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(20)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 20 +/** EFUSE_FLASH_VERSION : R; bitpos: [24:21]; default: 0; + * Flash version + */ +#define EFUSE_FLASH_VERSION 0x0000000FU +#define EFUSE_FLASH_VERSION_M (EFUSE_FLASH_VERSION_V << EFUSE_FLASH_VERSION_S) +#define EFUSE_FLASH_VERSION_V 0x0000000FU #define EFUSE_FLASH_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [26:25]; default: 0; + * BLK_VERSION_MAJOR + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 25 +/** EFUSE_RESERVED_1_123 : R; bitpos: [27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 (BIT(27)) +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x00000001U +#define EFUSE_RESERVED_1_123_S 27 +/** EFUSE_PSRAM_VERSION : R; bitpos: [31:28]; default: 0; + * PSRAM version + */ +#define EFUSE_PSRAM_VERSION 0x0000000FU +#define EFUSE_PSRAM_VERSION_M (EFUSE_PSRAM_VERSION_V << EFUSE_PSRAM_VERSION_S) +#define EFUSE_PSRAM_VERSION_V 0x0000000FU +#define EFUSE_PSRAM_VERSION_S 28 -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 4 -/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Package version */ -#define EFUSE_PKG_VERSION 0x0000000F -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0xF +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_PKG_VERSION : R; bitpos: [3:0]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x0000000FU +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x0000000FU #define EFUSE_PKG_VERSION_S 0 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [6:4]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 4 +/** EFUSE_RESERVED_1_135 : R; bitpos: [31:7]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_135 0x01FFFFFFU +#define EFUSE_RESERVED_1_135_M (EFUSE_RESERVED_1_135_V << EFUSE_RESERVED_1_135_S) +#define EFUSE_RESERVED_1_135_V 0x01FFFFFFU +#define EFUSE_RESERVED_1_135_S 7 -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05c) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06c) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_ADC_CALIB : R; bitpos: [3:0]; default: 0; + * 4 bit of ADC calibration + */ +#define EFUSE_ADC_CALIB 0x0000000FU +#define EFUSE_ADC_CALIB_M (EFUSE_ADC_CALIB_V << EFUSE_ADC_CALIB_S) +#define EFUSE_ADC_CALIB_V 0x0000000FU +#define EFUSE_ADC_CALIB_S 0 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [6:4]; default: 0; + * BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 4 +/** EFUSE_TEMP_CALIB : R; bitpos: [15:7]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 7 +/** EFUSE_RTCCALIB_V1IDX_A10H : R; bitpos: [23:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A10H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A10H_M (EFUSE_RTCCALIB_V1IDX_A10H_V << EFUSE_RTCCALIB_V1IDX_A10H_S) +#define EFUSE_RTCCALIB_V1IDX_A10H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A10H_S 16 +/** EFUSE_RTCCALIB_V1IDX_A11H : R; bitpos: [31:24]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A11H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A11H_M (EFUSE_RTCCALIB_V1IDX_A11H_V << EFUSE_RTCCALIB_V1IDX_A11H_S) +#define EFUSE_RTCCALIB_V1IDX_A11H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A11H_S 24 -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_RTCCALIB_V1IDX_A12H : R; bitpos: [7:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A12H_M (EFUSE_RTCCALIB_V1IDX_A12H_V << EFUSE_RTCCALIB_V1IDX_A12H_S) +#define EFUSE_RTCCALIB_V1IDX_A12H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A12H_S 0 +/** EFUSE_RTCCALIB_V1IDX_A13H : R; bitpos: [15:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A13H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A13H_M (EFUSE_RTCCALIB_V1IDX_A13H_V << EFUSE_RTCCALIB_V1IDX_A13H_S) +#define EFUSE_RTCCALIB_V1IDX_A13H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A13H_S 8 +/** EFUSE_RTCCALIB_V1IDX_A20H : R; bitpos: [23:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A20H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A20H_M (EFUSE_RTCCALIB_V1IDX_A20H_V << EFUSE_RTCCALIB_V1IDX_A20H_S) +#define EFUSE_RTCCALIB_V1IDX_A20H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A20H_S 16 +/** EFUSE_RTCCALIB_V1IDX_A21H : R; bitpos: [31:24]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A21H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A21H_M (EFUSE_RTCCALIB_V1IDX_A21H_V << EFUSE_RTCCALIB_V1IDX_A21H_S) +#define EFUSE_RTCCALIB_V1IDX_A21H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A21H_S 24 -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_RTCCALIB_V1IDX_A22H : R; bitpos: [7:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A22H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A22H_M (EFUSE_RTCCALIB_V1IDX_A22H_V << EFUSE_RTCCALIB_V1IDX_A22H_S) +#define EFUSE_RTCCALIB_V1IDX_A22H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A22H_S 0 +/** EFUSE_RTCCALIB_V1IDX_A23H : R; bitpos: [15:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A23H 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A23H_M (EFUSE_RTCCALIB_V1IDX_A23H_V << EFUSE_RTCCALIB_V1IDX_A23H_S) +#define EFUSE_RTCCALIB_V1IDX_A23H_V 0x000000FFU +#define EFUSE_RTCCALIB_V1IDX_A23H_S 8 +/** EFUSE_RTCCALIB_V1IDX_A10L : R; bitpos: [21:16]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A10L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A10L_M (EFUSE_RTCCALIB_V1IDX_A10L_V << EFUSE_RTCCALIB_V1IDX_A10L_S) +#define EFUSE_RTCCALIB_V1IDX_A10L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A10L_S 16 +/** EFUSE_RTCCALIB_V1IDX_A11L : R; bitpos: [27:22]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A11L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A11L_M (EFUSE_RTCCALIB_V1IDX_A11L_V << EFUSE_RTCCALIB_V1IDX_A11L_S) +#define EFUSE_RTCCALIB_V1IDX_A11L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A11L_S 22 +/** EFUSE_RTCCALIB_V1IDX_A12L : R; bitpos: [31:28]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12L 0x0000000FU +#define EFUSE_RTCCALIB_V1IDX_A12L_M (EFUSE_RTCCALIB_V1IDX_A12L_V << EFUSE_RTCCALIB_V1IDX_A12L_S) +#define EFUSE_RTCCALIB_V1IDX_A12L_V 0x0000000FU +#define EFUSE_RTCCALIB_V1IDX_A12L_S 28 -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_RTCCALIB_V1IDX_A12L_1 : R; bitpos: [1:0]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A12L_1 0x00000003U +#define EFUSE_RTCCALIB_V1IDX_A12L_1_M (EFUSE_RTCCALIB_V1IDX_A12L_1_V << EFUSE_RTCCALIB_V1IDX_A12L_1_S) +#define EFUSE_RTCCALIB_V1IDX_A12L_1_V 0x00000003U +#define EFUSE_RTCCALIB_V1IDX_A12L_1_S 0 +/** EFUSE_RTCCALIB_V1IDX_A13L : R; bitpos: [7:2]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A13L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A13L_M (EFUSE_RTCCALIB_V1IDX_A13L_V << EFUSE_RTCCALIB_V1IDX_A13L_S) +#define EFUSE_RTCCALIB_V1IDX_A13L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A13L_S 2 +/** EFUSE_RTCCALIB_V1IDX_A20L : R; bitpos: [13:8]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A20L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A20L_M (EFUSE_RTCCALIB_V1IDX_A20L_V << EFUSE_RTCCALIB_V1IDX_A20L_S) +#define EFUSE_RTCCALIB_V1IDX_A20L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A20L_S 8 +/** EFUSE_RTCCALIB_V1IDX_A21L : R; bitpos: [19:14]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A21L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A21L_M (EFUSE_RTCCALIB_V1IDX_A21L_V << EFUSE_RTCCALIB_V1IDX_A21L_S) +#define EFUSE_RTCCALIB_V1IDX_A21L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A21L_S 14 +/** EFUSE_RTCCALIB_V1IDX_A22L : R; bitpos: [25:20]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A22L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A22L_M (EFUSE_RTCCALIB_V1IDX_A22L_V << EFUSE_RTCCALIB_V1IDX_A22L_S) +#define EFUSE_RTCCALIB_V1IDX_A22L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A22L_S 20 +/** EFUSE_RTCCALIB_V1IDX_A23L : R; bitpos: [31:26]; default: 0; */ +#define EFUSE_RTCCALIB_V1IDX_A23L 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A23L_M (EFUSE_RTCCALIB_V1IDX_A23L_V << EFUSE_RTCCALIB_V1IDX_A23L_S) +#define EFUSE_RTCCALIB_V1IDX_A23L_V 0x0000003FU +#define EFUSE_RTCCALIB_V1IDX_A23L_S 26 -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07c) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08c) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09c) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0a0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0a4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0a8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ac) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0b0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0b4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0b8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0bc) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0c0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0c4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0c8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0cc) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0d0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0d4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0d8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0dc) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0e0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0e4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0e8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ec) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0f0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0f4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0f8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0fc) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'h0 ; */ -/*description: If VDD_SPI_MODECURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3 -#define EFUSE_RPT4_RESERVED0_ERR_S 27 -/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Record error infomation of the burning result of usb_force_nopersist.*/ -#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x1 -#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 -/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: If EXT_PHY_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[24] ;default: 1'h0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 24 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 22 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 -/* EFUSE_HARD_DIS_JTAG_ERR : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: If HARD_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_M (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_V 0x1 -#define EFUSE_HARD_DIS_JTAG_ERR_S 18 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[17] ;default: 1'h0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_M (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x1 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: If DIS_EFUSE_ATE_WR is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x1 -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 -/* EFUSE_DIS_BOOT_REMAP_ERR : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: If DIS_BOOT_REMAP is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_M (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x1 -#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 -/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'h0 ; */ -/*description: If DIS_CAN is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (BIT(14)) -#define EFUSE_DIS_CAN_ERR_V 0x1 -#define EFUSE_DIS_CAN_ERR_S 14 -/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'h0 ; */ -/*description: If DIS_USB is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (BIT(13)) -#define EFUSE_DIS_USB_ERR_V 0x1 -#define EFUSE_DIS_USB_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'h0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: If DIS_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DCACHE_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + */ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DCACHE_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + */ +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001U +#define EFUSE_DIS_USB_ERR_S 13 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + */ +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001U +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 +/** EFUSE_RPT4_RESERVED5_ERR : RO; bitpos: [16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + */ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(16)) +#define EFUSE_RPT4_RESERVED5_ERR_M (EFUSE_RPT4_RESERVED5_ERR_V << EFUSE_RPT4_RESERVED5_ERR_S) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED5_ERR_S 16 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 +/** EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + */ +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001U +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 20 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 22 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 +/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + */ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001U +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 +/** EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + */ +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001U +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_S 27 +/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + */ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 +/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + */ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DCAP is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 -/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x3 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: If any bit in VDD_SPI_DCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If VDD_SPI_ENCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: If VDD_SPI_EN_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 -/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: If VDD_SPI_FORCE is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 -/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: If VDD_SPI_TIEH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 -/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: If VDD_SPI_XPD is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x1 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 -/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 -/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + */ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_ERR_S 0 +/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + */ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 +/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + */ +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_ERR_S 4 +/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + */ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 +/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + */ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 +/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + */ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 +/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + */ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 +/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + */ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 +/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + */ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_S 12 +/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + */ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED1_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'h0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_6 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_M ((EFUSE_KEY_PURPOSE_6_ERR_V)<<(EFUSE_KEY_PURPOSE_6_ERR_S)) -#define EFUSE_KEY_PURPOSE_6_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_6_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + */ +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + */ +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003FU +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003FU +#define EFUSE_RPT4_RESERVED1_ERR_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x1F -#define EFUSE_RPT4_RESERVED2_ERR_S 27 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[26:11] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 11 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 -/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_V 0x1 -#define EFUSE_FLASH_TYPE_ERR_S 9 -/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: If RPT4_RESERVED3 is 1 then it indicates a programming error.*/ -#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_M (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED3_ERR_S 3 -/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + */ +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 11 +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001FU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001FU +#define EFUSE_RPT4_RESERVED2_ERR_S 27 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT1_RESERVED0_ERR : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT1_RESERVED0_ERR 0x000000FF -#define EFUSE_RPT1_RESERVED0_ERR_M ((EFUSE_RPT1_RESERVED0_ERR_V)<<(EFUSE_RPT1_RESERVED0_ERR_S)) -#define EFUSE_RPT1_RESERVED0_ERR_V 0xFF -#define EFUSE_RPT1_RESERVED0_ERR_S 24 -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved ( four backup method ).*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in RPT4_RESERVED4 is 1, there is a programming error in + * EFUSE_RPT4_RESERVED4. + */ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED4_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the user data is reliable*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that + * programming BLOCK1 data failed and the number of error bytes is over 5. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that + * programming BLOCK2 data failed and the number of error bytes is over 5. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that + * programming BLOCK3 data failed and the number of error bytes is over 5. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable. 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable. 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable. 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable. 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable. 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable*/ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable. 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that + * programming BLOCK10 data failed and the number of error bytes is over 5. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +/** EFUSE_CLK_REG register + * eFuse clock configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command. 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF -#define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: Configures the setup time of read operation.*/ -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) -#define EFUSE_TSUR_A_V 0xFF -#define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse of read operation.*/ -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) -#define EFUSE_TRD_V 0xFF -#define EFUSE_TRD_S 8 -/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of read operation.*/ -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) -#define EFUSE_THR_A_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ -/*description: Configures the length of pulse during programming 1 to eFuse.*/ -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) -#define EFUSE_TPGM_V 0xFFFF -#define EFUSE_TPGM_S 16 -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse during programming 0 to eFuse.*/ -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) -#define EFUSE_TPGM_INACTIVE_V 0xFF -#define EFUSE_TPGM_INACTIVE_S 8 -/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of programming operation.*/ -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) -#define EFUSE_THP_A_V 0xFF +/** EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU #define EFUSE_THP_A_S 0 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 8 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF -#define EFUSE_PWR_ON_NUM_S 8 -/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the setup time of programming operation.*/ -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) -#define EFUSE_TSUP_A_V 0xFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h19081100 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0xFFFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFFF +/** EFUSE_DATE_REG register + * Version control register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Version control register. + */ +#define EFUSE_DATE 0xFFFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xFFFFFFFFU #define EFUSE_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h index 705c47a412..88f99599f5 100644 --- a/components/soc/esp32s2/include/soc/efuse_struct.h +++ b/components/soc/esp32s2/include/soc/efuse_struct.h @@ -1,542 +1,2440 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; /**/ - union { - struct { - uint32_t rd_dis: 7; - uint32_t dis_rtc_ram_boot: 1; - uint32_t dis_icache: 1; - uint32_t dis_dcache: 1; - uint32_t dis_download_icache: 1; - uint32_t dis_download_dcache: 1; - uint32_t dis_force_download: 1; - uint32_t dis_usb: 1; - uint32_t dis_can: 1; - uint32_t dis_sdio_access: 1; - uint32_t dis_efuse_ate_wr: 1; - uint32_t soft_dis_jtag: 1; - uint32_t hard_dis_jtag: 1; - uint32_t dis_download_manual_encrypt: 1; - uint32_t usb_drefh: 2; - uint32_t usb_drefl: 2; - uint32_t usb_exchg_pins: 1; - uint32_t ext_phy_enable: 1; - uint32_t usb_force_b: 1; - uint32_t usb_dres: 2; - uint32_t sdio_modecurlim: 1; - uint32_t sdio_drefh: 2; - }; - uint32_t val; - } pgm_data1; - union { - struct { - uint32_t sdio_drefm: 2; - uint32_t sdio_drefl: 2; - uint32_t sdio_xpd: 1; - uint32_t sdio_tieh: 1; - uint32_t sdio_force: 1; - uint32_t sdio_en_init: 1; - uint32_t sdio_encurlim: 1; - uint32_t sdio_dcurlim: 3; - uint32_t sdio_init: 2; - uint32_t sdio_dcap: 2; - uint32_t wdt_delay_sel: 2; - uint32_t spi_boot_crypt_cnt: 3; - uint32_t secure_boot_key_revoke0: 1; - uint32_t secure_boot_key_revoke1: 1; - uint32_t secure_boot_key_revoke2: 1; - uint32_t key_purpose_0: 4; - uint32_t key_purpose_1: 4; - }; - uint32_t val; - } pgm_data2; - union { - struct { - uint32_t key_purpose_2: 4; - uint32_t key_purpose_3: 4; - uint32_t key_purpose_4: 4; - uint32_t key_purpose_5: 4; - uint32_t key_purpose_6: 4; - uint32_t secure_boot_en: 1; - uint32_t secure_boot_aggressive_revoke: 1; - uint32_t xtal_freq: 6; - uint32_t flash_tpuw: 4; - }; - uint32_t val; - } pgm_data3; - union { - struct { - uint32_t dis_download_mode: 1; - uint32_t dis_legacy_spi_boot: 1; - uint32_t uart_print_channel: 1; - uint32_t dis_tiny_basic: 1; - uint32_t dis_usb_download_mode: 1; - uint32_t enable_security_download: 1; - uint32_t uart_print_control: 2; - uint32_t reserve: 24; - }; - uint32_t val; - } pgm_data4; - union { - struct { - uint32_t chip_version:24; - uint32_t rs_data_23: 8; - }; - uint32_t val; - } pgm_data5; - uint32_t pgm_data6; /**/ - uint32_t pgm_data7; /**/ - uint32_t pgm_check_value0; /**/ - uint32_t pgm_check_value1; /**/ - uint32_t pgm_check_value2; /**/ - uint32_t rd_wr_dis; /**/ - union { - struct { - uint32_t rd_dis: 7; - uint32_t dis_rtc_ram_boot: 1; - uint32_t dis_icache: 1; - uint32_t dis_dcache: 1; - uint32_t dis_download_icache: 1; - uint32_t dis_download_dcache: 1; - uint32_t dis_force_download: 1; - uint32_t dis_usb: 1; - uint32_t dis_can: 1; - uint32_t dis_sdio_access: 1; - uint32_t dis_ate_wr: 1; - uint32_t soft_dis_jtag: 1; - uint32_t hard_dis_jtag: 1; - uint32_t dis_download_manual_encrypt: 1; - uint32_t usb_drefh: 2; - uint32_t usb_drefl: 2; - uint32_t usb_exchg_pins: 1; - uint32_t ext_phy_enable: 1; - uint32_t usb_force_b: 1; - uint32_t usb_dres: 2; - uint32_t sdio_modecurlim: 1; - uint32_t sdio_drefh: 2; - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t sdio_drefm: 2; - uint32_t sdio_drefl: 2; - uint32_t sdio_xpd: 1; - uint32_t sdio_tieh: 1; - uint32_t sdio_force: 1; - uint32_t sdio_en_init: 1; - uint32_t sdio_encurlim: 1; - uint32_t sdio_dcurlim: 3; - uint32_t sdio_init: 2; - uint32_t eufse_sdio_dcap: 2; - uint32_t wdt_delay_sel: 2; - uint32_t spi_boot_crypt_cnt: 3; - uint32_t secure_boot_key_revoke0: 1; - uint32_t secure_boot_key_revoke1: 1; - uint32_t secure_boot_key_revoke2: 1; - uint32_t key_purpose_0: 4; - uint32_t key_purpose_1: 4; - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2: 4; - uint32_t key_purpose_3: 4; - uint32_t key_purpose_4: 4; - uint32_t key_purpose_5: 4; - uint32_t key_purpose_6: 4; - uint32_t secure_boot_en: 1; - uint32_t secure_boot_aggressive_revoke: 1; - uint32_t xtal_freq: 6; - uint32_t flash_tpuw: 4; - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode: 1; - uint32_t dis_legacy_spi_boot: 1; - uint32_t uart_print_channel: 1; - uint32_t dis_tiny_basic: 1; - uint32_t dis_usb_download_mode: 1; - uint32_t enable_security_download: 1; - uint32_t uart_print_control: 2; - uint32_t reserve: 24; - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major: 1; - uint32_t disable_blk_version_major: 1; - uint32_t rpt4_reserved4:22; - uint32_t reserved24: 8; - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_8m_0; /**/ - union { - struct { - uint32_t mac_1: 16; - uint32_t spi_pad_conf_0:16; - }; - uint32_t val; - } rd_mac_spi_8m_1; - union { - struct { - uint32_t spi_pad_conf_1:20; - uint32_t clk8m_freq: 12; - }; - uint32_t val; - } rd_mac_spi_8m_2; - union { - struct { - uint32_t spi_pad_conf_2: 18; - uint32_t wafer_version_major: 2; - uint32_t wafer_version_minor_high: 1; // most significant bit - uint32_t reserve1: 4; - uint32_t blk_version_major: 2; - uint32_t reserve2: 5; - }; - uint32_t val; - } rd_mac_spi_8m_3; - union { - struct { - uint32_t pkg_version: 4; - uint32_t wafer_version_minor_low: 3; // least significant bits - uint32_t reserve: 25; - }; - uint32_t val; - } rd_mac_spi_8m_4; - uint32_t rd_mac_spi_8m_5; /**/ - uint32_t rd_sys_data0; /**/ - uint32_t rd_sys_data1; /**/ - uint32_t rd_sys_data2; /**/ - uint32_t rd_sys_data3; /**/ - union { - struct { - uint32_t ocode_low: 4; - uint32_t blk_version_minor : 3; - uint32_t reserved1: 9; - uint32_t ocode_hi: 3; - uint32_t reserved2: 13; - }; - uint32_t val; - } rd_sys_data4; /**/ - uint32_t rd_sys_data5; /**/ - uint32_t rd_sys_data6; /**/ - uint32_t rd_sys_data7; /**/ - uint32_t rd_usr_data0; /**/ - uint32_t rd_usr_data1; /**/ - uint32_t rd_usr_data2; /**/ - uint32_t rd_usr_data3; /**/ - uint32_t rd_usr_data4; /**/ - uint32_t rd_usr_data5; /**/ - uint32_t rd_usr_data6; /**/ - uint32_t rd_usr_data7; /**/ - uint32_t rd_key0_data0; /**/ - uint32_t rd_key0_data1; /**/ - uint32_t rd_key0_data2; /**/ - uint32_t rd_key0_data3; /**/ - uint32_t rd_key0_data4; /**/ - uint32_t rd_key0_data5; /**/ - uint32_t rd_key0_data6; /**/ - uint32_t rd_key0_data7; /**/ - uint32_t rd_key1_data0; /**/ - uint32_t rd_key1_data1; /**/ - uint32_t rd_key1_data2; /**/ - uint32_t rd_key1_data3; /**/ - uint32_t rd_key1_data4; /**/ - uint32_t rd_key1_data5; /**/ - uint32_t rd_key1_data6; /**/ - uint32_t rd_key1_data7; /**/ - uint32_t rd_key2_data0; /**/ - uint32_t rd_key2_data1; /**/ - uint32_t rd_key2_data2; /**/ - uint32_t rd_key2_data3; /**/ - uint32_t rd_key2_data4; /**/ - uint32_t rd_key2_data5; /**/ - uint32_t rd_key2_data6; /**/ - uint32_t rd_key2_data7; /**/ - uint32_t rd_key3_data0; /**/ - uint32_t rd_key3_data1; /**/ - uint32_t rd_key3_data2; /**/ - uint32_t rd_key3_data3; /**/ - uint32_t rd_key3_data4; /**/ - uint32_t rd_key3_data5; /**/ - uint32_t rd_key3_data6; /**/ - uint32_t rd_key3_data7; /**/ - uint32_t rd_key4_data0; /**/ - uint32_t rd_key4_data1; /**/ - uint32_t rd_key4_data2; /**/ - uint32_t rd_key4_data3; /**/ - uint32_t rd_key4_data4; /**/ - uint32_t rd_key4_data5; /**/ - uint32_t rd_key4_data6; /**/ - uint32_t rd_key4_data7; /**/ - uint32_t rd_key5_data0; /**/ - uint32_t rd_key5_data1; /**/ - uint32_t rd_key5_data2; /**/ - uint32_t rd_key5_data3; /**/ - uint32_t rd_key5_data4; /**/ - uint32_t rd_key5_data5; /**/ - uint32_t rd_key5_data6; /**/ - uint32_t rd_key5_data7; /**/ - uint32_t rd_key6_data0; /**/ - uint32_t rd_key6_data1; /**/ - uint32_t rd_key6_data2; /**/ - uint32_t rd_key6_data3; /**/ - uint32_t rd_key6_data4; /**/ - uint32_t rd_key6_data5; /**/ - uint32_t rd_key6_data6; /**/ - uint32_t rd_key6_data7; /**/ - union { - struct { - uint32_t rd_rd_dis_err: 7; - uint32_t rd_dis_rtc_ram_boot_err: 1; - uint32_t rd_dis_icache_err: 1; - uint32_t rd_dis_dcache_err: 1; - uint32_t rd_dis_download_icache_err: 1; - uint32_t rd_dis_download_dcache_err: 1; - uint32_t rd_dis_force_download: 1; - uint32_t rd_dis_usb_err: 1; - uint32_t rd_dis_can_err: 1; - uint32_t rd_dis_sdio_access_err: 1; - uint32_t rd_dis_efuse_ate_wr_err: 1; - uint32_t rd_soft_dis_jtag_err: 1; - uint32_t rd_hard_dis_jtag_err: 1; - uint32_t rd_dis_download_manual_encrypt_err: 1; - uint32_t rd_usb_drefh_err: 2; - uint32_t rd_usb_drefl_err: 2; - uint32_t rd_usb_exchg_pins_err: 1; - uint32_t rd_ext_phy_enable: 1; - uint32_t rd_usb_force: 1; - uint32_t rd_usb_dres_err: 2; - uint32_t rd_sdio_modecurlim_err: 1; - uint32_t rd_sdio_drefh_err: 2; - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t rd_sdio_drefm_err: 2; - uint32_t rd_sdio_drefl_err: 2; - uint32_t rd_sdio_xpd_err: 1; - uint32_t rd_sdio_tieh_err: 1; - uint32_t rd_sdio_force_err: 1; - uint32_t rd_sdio_en_init_err: 1; - uint32_t rd_sdio_encurlim_err: 1; - uint32_t rd_sdio_dcurlim_err: 3; - uint32_t rd_sdio_init_err: 2; - uint32_t rd_sdio_dcap_err: 2; - uint32_t rd_wdt_delay_sel_err: 2; - uint32_t rd_spi_boot_crypt_cnt_err: 3; - uint32_t rd_secure_boot_key_revoke0_err: 1; - uint32_t rd_secure_boot_key_revoke1_err: 1; - uint32_t rd_secure_boot_key_revoke2_err: 1; - uint32_t rd_key_purpose_0_err: 4; - uint32_t rd_key_purpose_1_err: 4; - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t rd_key_purpose_2_err: 4; - uint32_t rd_key_purpose_3_err: 4; - uint32_t rd_key_purpose_4_err: 4; - uint32_t rd_key_purpose_5_err: 4; - uint32_t rd_key_purpose_6_err: 4; - uint32_t rd_secure_boot_en_err: 1; - uint32_t rd_secure_boot_aggressive_revoke_err: 1; - uint32_t rd_xtal_freq_err: 6; - uint32_t rd_flash_tpuw_err: 4; - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t rd_dis_download_mode_err: 1; - uint32_t rd_dis_legacy_spi_boot_err: 1; - uint32_t rd_uart_print_channel: 1; - uint32_t rd_dis_tiny_basic: 1; - uint32_t rd_dis_usb_download_mode: 1; - uint32_t rd_enable_security_download: 1; - uint32_t rd_uart_print_control: 2; - uint32_t rd_reserve_err: 24; - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t rd_chip_version_err:24; - uint32_t reserved24: 8; - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t rd_mac_spi_8m_err_num: 3; - uint32_t rd_mac_spi_8m_fail: 1; - uint32_t rd_sys_err_num: 3; - uint32_t rd_sys_err_fail: 1; - uint32_t rd_usr_data_err_num: 3; - uint32_t rd_usr_data_fail: 1; - uint32_t rd_key0_err_num: 3; - uint32_t rd_key0_fail: 1; - uint32_t rd_key1_err_num: 3; - uint32_t rd_key1_fail: 1; - uint32_t rd_key2_err_num: 3; - uint32_t rd_key2_fail: 1; - uint32_t rd_key3_err_num: 3; - uint32_t rd_key3_fail: 1; - uint32_t rd_key4_err_num: 3; - uint32_t rd_key4_fail: 1; - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t rd_key5_err_num: 3; - uint32_t rd_key5_fail: 1; - uint32_t rd_key6_err_num: 3; - uint32_t rd_key6_fail: 1; - uint32_t reserved8: 24; - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_pd: 1; - uint32_t reserved1: 15; - uint32_t clk_en: 1; - uint32_t reserved17:15; - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; - uint32_t reserved16:16; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 3; - uint32_t otp_load_sw: 1; - uint32_t otp_vddq_c_sync2: 1; - uint32_t otp_strobe_sw: 1; - uint32_t otp_csb_sw: 1; - uint32_t otp_pgenb_sw: 1; - uint32_t otp_vddq_is_sw: 1; - uint32_t repeat_err_cnt: 8; - uint32_t reserved17: 15; - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; - uint32_t pgm_cmd: 1; - uint32_t blk_num: 4; - uint32_t reserved6: 26; - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; - uint32_t pgm_done: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; - uint32_t dac_clk_pad_sel: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t thr_a: 8; - uint32_t trd: 8; - uint32_t tsur_a: 8; - uint32_t read_init_num: 8; - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t thp_a: 8; - uint32_t tpgm_inactive: 8; - uint32_t tpgm: 16; - }; - uint32_t val; - } wr_tim_conf0; - union { - struct { - uint32_t tsup_a: 8; - uint32_t pwr_on_num:16; - uint32_t reserved24: 8; - }; - uint32_t val; - } wr_tim_conf1; - uint32_t reserved_1f8; - uint32_t date; /**/ +/** Group: PGM Data Registers */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Registers */ +/** Type of rd_wr_dis register + * Register 0 of BLOCK0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * Register 1 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Reserved. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_dcache : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + uint32_t dis_dcache:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + uint32_t dis_download_icache:1; + /** dis_download_dcache : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + uint32_t dis_download_dcache:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** dis_usb : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB OTG function. + */ + uint32_t dis_usb:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable the TWAI Controller function. + */ + uint32_t dis_twai:1; + /** dis_boot_remap : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + uint32_t dis_boot_remap:1; + /** rpt4_reserved5 : RO; bitpos: [16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved5:1; + /** soft_dis_jtag : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated temporarily + * by HMAC peripheral. + */ + uint32_t soft_dis_jtag:1; + /** hard_dis_jtag : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + uint32_t hard_dis_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** usb_ext_phy_enable : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + uint32_t usb_ext_phy_enable:1; + /** usb_force_nopersist : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + uint32_t usb_force_nopersist:1; + /** block0_version : R; bitpos: [28:27]; default: 0; + * BLOCK0 efuse version + */ + uint32_t block0_version:2; + /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + uint32_t vdd_spi_modecurlim:1; + /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + uint32_t vdd_spi_drefh:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * Register 2 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + uint32_t vdd_spi_drefm:2; + /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + uint32_t vdd_spi_drefl:2; + /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. + */ + uint32_t vdd_spi_xpd:1; + /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V + * LDO. 1: VDD_SPI connects to VDD_RTC_IO. + */ + uint32_t vdd_spi_tieh:1; + /** vdd_spi_force : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + */ + uint32_t vdd_spi_force:1; + /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + uint32_t vdd_spi_en_init:1; + /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + uint32_t vdd_spi_encurlim:1; + /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ + uint32_t vdd_spi_dcurlim:3; + /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. + */ + uint32_t vdd_spi_init:2; + /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + uint32_t vdd_spi_dcap:2; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: + * 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock + * cycles. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled + * 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * Register 3 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_5:4; + /** key_purpose_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + uint32_t key_purpose_6:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved1:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). When the + * value is 15, delay is 7.5 ms. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * Register 4 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + uint32_t dis_download_mode:1; + /** dis_legacy_spi_boot : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + uint32_t dis_legacy_spi_boot:1; + /** uart_print_channel : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0. 1: UART1. + */ + uint32_t uart_print_channel:1; + /** rpt4_reserved3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved3:1; + /** dis_usb_download_mode : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB OTG in UART download boot mode. + */ + uint32_t dis_usb_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 + * is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: + * VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + uint32_t flash_type:1; + /** force_send_resume : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** rpt4_reserved2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved2:5; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * Register 5 of BLOCK0. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * Register 0 of BLOCK1. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * Register 1 of BLOCK1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * Register 2 of BLOCK1. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * Register 3 of BLOCK1. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_major : R; bitpos: [19:18]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** wafer_version_minor_hi : R; bitpos: [20]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** flash_version : R; bitpos: [24:21]; default: 0; + * Flash version + */ + uint32_t flash_version:4; + /** blk_version_major : R; bitpos: [26:25]; default: 0; + * BLK_VERSION_MAJOR + */ + uint32_t blk_version_major:2; + /** reserved_1_123 : R; bitpos: [27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:1; + /** psram_version : R; bitpos: [31:28]; default: 0; + * PSRAM version + */ + uint32_t psram_version:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * Register 4 of BLOCK1. + */ +typedef union { + struct { + /** pkg_version : R; bitpos: [3:0]; default: 0; + * Package version + */ + uint32_t pkg_version:4; + /** wafer_version_minor_lo : R; bitpos: [6:4]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** reserved_1_135 : R; bitpos: [31:7]; default: 0; + * reserved + */ + uint32_t reserved_1_135:25; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * Register 5 of BLOCK1. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc_calib : R; bitpos: [3:0]; default: 0; + * 4 bit of ADC calibration + */ + uint32_t adc_calib:4; + /** blk_version_minor : R; bitpos: [6:4]; default: 0; + * BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + */ + uint32_t blk_version_minor:3; + /** temp_calib : R; bitpos: [15:7]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** rtccalib_v1idx_a10h : R; bitpos: [23:16]; default: 0; */ + uint32_t rtccalib_v1idx_a10h:8; + /** rtccalib_v1idx_a11h : R; bitpos: [31:24]; default: 0; */ + uint32_t rtccalib_v1idx_a11h:8; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a12h : R; bitpos: [7:0]; default: 0; */ + uint32_t rtccalib_v1idx_a12h:8; + /** rtccalib_v1idx_a13h : R; bitpos: [15:8]; default: 0; */ + uint32_t rtccalib_v1idx_a13h:8; + /** rtccalib_v1idx_a20h : R; bitpos: [23:16]; default: 0; */ + uint32_t rtccalib_v1idx_a20h:8; + /** rtccalib_v1idx_a21h : R; bitpos: [31:24]; default: 0; */ + uint32_t rtccalib_v1idx_a21h:8; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a22h : R; bitpos: [7:0]; default: 0; */ + uint32_t rtccalib_v1idx_a22h:8; + /** rtccalib_v1idx_a23h : R; bitpos: [15:8]; default: 0; */ + uint32_t rtccalib_v1idx_a23h:8; + /** rtccalib_v1idx_a10l : R; bitpos: [21:16]; default: 0; */ + uint32_t rtccalib_v1idx_a10l:6; + /** rtccalib_v1idx_a11l : R; bitpos: [27:22]; default: 0; */ + uint32_t rtccalib_v1idx_a11l:6; + /** rtccalib_v1idx_a12l : R; bitpos: [31:28]; default: 0; */ + uint32_t rtccalib_v1idx_a12l:4; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** rtccalib_v1idx_a12l_1 : R; bitpos: [1:0]; default: 0; */ + uint32_t rtccalib_v1idx_a12l_1:2; + /** rtccalib_v1idx_a13l : R; bitpos: [7:2]; default: 0; */ + uint32_t rtccalib_v1idx_a13l:6; + /** rtccalib_v1idx_a20l : R; bitpos: [13:8]; default: 0; */ + uint32_t rtccalib_v1idx_a20l:6; + /** rtccalib_v1idx_a21l : R; bitpos: [19:14]; default: 0; */ + uint32_t rtccalib_v1idx_a21l:6; + /** rtccalib_v1idx_a22l : R; bitpos: [25:20]; default: 0; */ + uint32_t rtccalib_v1idx_a22l:6; + /** rtccalib_v1idx_a23l : R; bitpos: [31:26]; default: 0; */ + uint32_t rtccalib_v1idx_a23l:6; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Error Status Registers */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_dcache_err : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + */ + uint32_t dis_dcache_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + */ + uint32_t dis_download_dcache_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** dis_usb_err : RO; bitpos: [13]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + */ + uint32_t dis_usb_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + */ + uint32_t dis_can_err:1; + /** dis_boot_remap_err : RO; bitpos: [15]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + */ + uint32_t dis_boot_remap_err:1; + /** rpt4_reserved5_err : RO; bitpos: [16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + */ + uint32_t rpt4_reserved5_err:1; + /** soft_dis_jtag_err : RO; bitpos: [17]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:1; + /** hard_dis_jtag_err : RO; bitpos: [18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + */ + uint32_t hard_dis_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [19]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [21:20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [23:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** ext_phy_enable_err : RO; bitpos: [25]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + */ + uint32_t ext_phy_enable_err:1; + /** usb_force_nopersist_err : RO; bitpos: [26]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + */ + uint32_t usb_force_nopersist_err:1; + /** rpt4_reserved0_err : RO; bitpos: [28:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + */ + uint32_t rpt4_reserved0_err:2; + /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + */ + uint32_t vdd_spi_modecurlim_err:1; + /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + */ + uint32_t vdd_spi_drefh_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + */ + uint32_t vdd_spi_drefm_err:2; + /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + */ + uint32_t vdd_spi_drefl_err:2; + /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + */ + uint32_t vdd_spi_xpd_err:1; + /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + */ + uint32_t vdd_spi_tieh_err:1; + /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + */ + uint32_t vdd_spi_force_err:1; + /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + */ + uint32_t vdd_spi_en_init_err:1; + /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + */ + uint32_t vdd_spi_encurlim_err:1; + /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + */ + uint32_t vdd_spi_dcurlim_err:3; + /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + */ + uint32_t vdd_spi_init_err:2; + /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + */ + uint32_t vdd_spi_dcap_err:2; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** key_purpose_6_err : RO; bitpos: [19:16]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + */ + uint32_t key_purpose_6_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Any bit equal to 1 denotes a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved1_err : RO; bitpos: [27:22]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + */ + uint32_t rpt4_reserved1_err:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + */ + uint32_t uart_print_channel_err:1; + /** rpt4_reserved3_err : RO; bitpos: [3]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + */ + uint32_t rpt4_reserved3_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + */ + uint32_t flash_type_err:1; + /** force_send_resume_err : RO; bitpos: [10]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [26:11]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + */ + uint32_t secure_version_err:16; + /** rpt4_reserved2_err : RO; bitpos: [31:27]; default: 0; + * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + */ + uint32_t rpt4_reserved2_err:5; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; + * If any bit in RPT4_RESERVED4 is 1, there is a programming error in + * EFUSE_RPT4_RESERVED4. + */ + uint32_t rpt4_reserved4_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that + * programming BLOCK1 data failed and the number of error bytes is over 5. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that + * programming BLOCK2 data failed and the number of error bytes is over 5. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that + * programming BLOCK3 data failed and the number of error bytes is over 5. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable. 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable. 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable. 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable. 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable. 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable. 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that + * programming BLOCK10 data failed and the number of error bytes is over 5. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Control/Status Registers */ +/** Type of clk register + * eFuse clock configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuration register. + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command. 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Configuration Registers */ +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf0 register + * Configuration register 0 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** thp_a : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + uint32_t thp_a:8; + /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + uint32_t tpgm_inactive:8; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf0_reg_t; + +/** Type of wr_tim_conf1 register + * Configuration register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configuration register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 419959040; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_date_reg_t date; } efuse_dev_t; + extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/efuse_defs.h b/components/soc/esp32s3/include/soc/efuse_defs.h new file mode 100644 index 0000000000..6c61b202b9 --- /dev/null +++ b/components/soc/esp32s3/include/soc/efuse_defs.h @@ -0,0 +1,39 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +// #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +//#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index 94e6851ae0..6b4119620b 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -1,1943 +1,2864 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" +#include "efuse_defs.h" #ifdef __cplusplus extern "C" { #endif -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S)) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S)) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S)) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) -/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 3rd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S)) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 4th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S)) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 5th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S)) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 6th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 7th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 1st 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 2nd 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Disable programming of individual eFuses..*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: SPI regulator high voltage reference..*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: SPI regulator switches current limit mode..*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio..*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_EXT_PHY_ENABLE : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable external PHY..*/ -#define EFUSE_EXT_PHY_ENABLE (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_M (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_S 26 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange USB D+ and D- pins..*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, s -tored in eFuse..*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, sto -red in eFuse..*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encryption when in download boot modes..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently..*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JT -AG can be enabled in HMAC module..*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_DIS_APP_CPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Disable app cpu..*/ -#define EFUSE_DIS_APP_CPU (BIT(15)) -#define EFUSE_DIS_APP_CPU_M (BIT(15)) -#define EFUSE_DIS_APP_CPU_V 0x1 -#define EFUSE_DIS_APP_CPU_S 15 -/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable CAN function..*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to disable USB function..*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, -6, 7)..*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6 -, 7)..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache..*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache..*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved */ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10..*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001U +#define EFUSE_DIS_DCACHE_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_DIS_USB_OTG : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ +#define EFUSE_DIS_USB_OTG (BIT(13)) +#define EFUSE_DIS_USB_OTG_M (EFUSE_DIS_USB_OTG_V << EFUSE_DIS_USB_OTG_S) +#define EFUSE_DIS_USB_OTG_V 0x00000001U +#define EFUSE_DIS_USB_OTG_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0; + * Disable app cpu. + */ +#define EFUSE_DIS_APP_CPU (BIT(15)) +#define EFUSE_DIS_APP_CPU_M (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S) +#define EFUSE_DIS_APP_CPU_V 0x00000001U +#define EFUSE_DIS_APP_CPU_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0; + * Set this bit to enable external PHY. + */ +#define EFUSE_USB_EXT_PHY_ENABLE (BIT(26)) +#define EFUSE_USB_EXT_PHY_ENABLE_M (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S) +#define EFUSE_USB_EXT_PHY_ENABLE_V 0x00000001U +#define EFUSE_USB_EXT_PHY_ENABLE_S 26 +/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; + * Bluetooth GPIO signal output security level control. + */ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) +#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_S 27 +/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ +#define EFUSE_VDD_SPI_DREFH 0x00000003U +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_S 30 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1..*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0..*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even n -umber of 1: disable..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1 -: 80000. 2: 160000. 3:320000..*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Prevents SPI regulator from overshoot..*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K..*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ -/*description: Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+ -d)..*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 1 to enable output current limit..*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 0 to configure init[1:0]=0..*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI..*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: SPI regulator output is short connected to VDD3P3_RTC_IO..*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: SPI regulator power up signal..*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: SPI regulator low voltage reference..*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI regulator medium voltage reference..*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ +#define EFUSE_VDD_SPI_DREFM 0x00000003U +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_S 0 +/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ +#define EFUSE_VDD_SPI_DREFL 0x00000003U +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_S 2 +/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * SPI regulator power up signal. + */ +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_S 4 +/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * SPI regulator output is short connected to VDD3P3_RTC_IO. + */ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_S 5 +/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + */ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_S 6 +/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + */ +#define EFUSE_VDD_SPI_INIT 0x00000003U +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_S 12 +/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ +#define EFUSE_VDD_SPI_DCAP 0x00000003U +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_S 14 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les -s than 15, the waiting time is the configurable value; Otherwise, the waiting ti -me is twice the configurable value..*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: Sample delay configuration of power glitch..*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 26 -/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to switch internal PHY and external PHY for USB OTG and USB Dev -ice. 0: internal PHY is assigned to USB Device while external PHY is assigned to - USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned -to USB Device..*/ -#define EFUSE_USB_PHY_SEL (BIT(25)) -#define EFUSE_USB_PHY_SEL_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_V 0x1 -#define EFUSE_USB_PHY_SEL_S 25 -/* EFUSE_STRAP_JTAG_SEL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through str -apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/ -#define EFUSE_STRAP_JTAG_SEL (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_M (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_V 0x1 -#define EFUSE_STRAP_JTAG_SEL_S 24 -/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to disable usb device..*/ -#define EFUSE_DIS_USB_DEVICE (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 23 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[22] ;default: 6'h0 ; */ -/*description: Set this bit to disable function of usb switch to jtag in module of usb device..*/ -#define EFUSE_DIS_USB_JTAG (BIT(22)) -#define EFUSE_DIS_USB_JTAG_M (BIT(22)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot..*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED0 0x0000000F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0xF -#define EFUSE_RPT4_RESERVED0_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5..*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4..*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3..*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2..*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ +#define EFUSE_RPT4_RESERVED0 0x0000000FU +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x0000000FU +#define EFUSE_RPT4_RESERVED0_S 16 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ +#define EFUSE_DIS_USB_JTAG (BIT(22)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 22 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [23]; default: 0; + * Set this bit to disable usb device. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(23)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 23 +/** EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ +#define EFUSE_STRAP_JTAG_SEL (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_M (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S) +#define EFUSE_STRAP_JTAG_SEL_V 0x00000001U +#define EFUSE_STRAP_JTAG_SEL_S 24 +/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; + * This bit is used to switch internal PHY and external PHY for USB OTG and USB + * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to + * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to + * USB Device. + */ +#define EFUSE_USB_PHY_SEL (BIT(25)) +#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) +#define EFUSE_USB_PHY_SEL_V 0x00000001U +#define EFUSE_USB_PHY_SEL_S 25 +/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0; + * Sample delay configuration of power glitch. + */ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_S 26 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C) -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB-OTG*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 31 -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 (BIT(30)) -#define EFUSE_RPT4_RESERVED1_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_V 0x1 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature)..*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set 1 to enable ECC for flash boot..*/ -#define EFUSE_FLASH_ECC_EN (BIT(12)) -#define EFUSE_FLASH_ECC_EN_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_V 0x1 -#define EFUSE_FLASH_ECC_EN_S 12 -/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: Set Flash page size..*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) -#define EFUSE_FLASH_PAGE_SIZE_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_S 10 -/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines..*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI..*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO -8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled..*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB-Seial-JTAG.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would - use 16to17 byte mode..*/ -#define EFUSE_FLASH_ECC_MODE (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_M (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_V 0x1 -#define EFUSE_FLASH_ECC_MODE_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Disable USB-Serial-JTAG print during rom boot.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable direct boot.*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7)..*/ +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Selectes the default UART print channel. 0: UART0. 1: UART1. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) +#define EFUSE_FLASH_ECC_MODE_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable UART download mode through USB. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_S 8 +/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 9 +/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) +#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_S 10 +/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ +#define EFUSE_FLASH_ECC_EN (BIT(12)) +#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) +#define EFUSE_FLASH_ECC_EN_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_S 12 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 14 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0; + * Set this bit to enable power glitch function. + */ +#define EFUSE_POWERGLITCH_EN (BIT(30)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 30 +/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : R; bitpos: [31]; default: 0; + * Set this bit to disable download through USB-OTG + */ +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(31)) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 31 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED2 0x00FFFFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED2_S 0 +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 +/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_0_162 0x003FFFFFU +#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) +#define EFUSE_RESERVED_0_162_V 0x003FFFFFU +#define EFUSE_RESERVED_0_162_S 2 -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address..*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * BLOCK1 data register 0. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF..*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address..*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * BLOCK1 data register 1. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CLK_S 16 +/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_Q_S 22 +/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU +#define EFUSE_SPI_PAD_CONFIG_D_S 28 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4C) +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register 2. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) /* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Stores the first part of SPI_PAD_CONF..*/ #define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) #define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ +#define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) +#define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U +#define EFUSE_SPI_PAD_CONFIG_D_1_S 0 +/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ +#define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) +#define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_CS_S 2 +/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_HD_S 8 +/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ +#define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) +#define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_WP_S 14 +/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ +#define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) +#define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_DQS_S 20 +/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ +#define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) +#define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D4_S 26 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the fist 14 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF..*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 21 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 24 +/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_123 0x0000001FU +#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) +#define EFUSE_RESERVED_1_123_V 0x0000001FU +#define EFUSE_RESERVED_1_123_S 27 -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register 4. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_RESERVED_1_128 : R; bitpos: [12:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_128 0x00001FFFU +#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S) +#define EFUSE_RESERVED_1_128_V 0x00001FFFU +#define EFUSE_RESERVED_1_128_S 0 +/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ +#define EFUSE_K_RTC_LDO 0x0000007FU +#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) +#define EFUSE_K_RTC_LDO_V 0x0000007FU +#define EFUSE_K_RTC_LDO_S 13 +/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ +#define EFUSE_K_DIG_LDO 0x0000007FU +#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) +#define EFUSE_K_DIG_LDO_V 0x0000007FU +#define EFUSE_K_DIG_LDO_S 20 +/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) +#define EFUSE_V_RTC_DBIAS20_V 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_S 27 -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * BLOCK1 data register 5. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_V_RTC_DBIAS20_1 : R; bitpos: [2:0]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20_1 0x00000007U +#define EFUSE_V_RTC_DBIAS20_1_M (EFUSE_V_RTC_DBIAS20_1_V << EFUSE_V_RTC_DBIAS20_1_S) +#define EFUSE_V_RTC_DBIAS20_1_V 0x00000007U +#define EFUSE_V_RTC_DBIAS20_1_S 0 +/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [10:3]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ +#define EFUSE_V_DIG_DBIAS20 0x000000FFU +#define EFUSE_V_DIG_DBIAS20_M (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S) +#define EFUSE_V_DIG_DBIAS20_V 0x000000FFU +#define EFUSE_V_DIG_DBIAS20_S 3 +/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [15:11]; default: 0; + * BLOCK1 digital dbias when hvt + */ +#define EFUSE_DIG_DBIAS_HVT 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) +#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU +#define EFUSE_DIG_DBIAS_HVT_S 11 +/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_176 0x0000007FU +#define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S) +#define EFUSE_RESERVED_1_176_V 0x0000007FU +#define EFUSE_RESERVED_1_176_S 16 +/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ +#define EFUSE_WAFER_VERSION_MINOR_HI (BIT(23)) +#define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) +#define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U +#define EFUSE_WAFER_VERSION_MINOR_HI_S 23 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 24 +/** EFUSE_ADC2_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0; + * ADC2 calibration voltage at atten3 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN3 0x0000003FU +#define EFUSE_ADC2_CAL_VOL_ATTEN3_M (EFUSE_ADC2_CAL_VOL_ATTEN3_V << EFUSE_ADC2_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN3_V 0x0000003FU +#define EFUSE_ADC2_CAL_VOL_ATTEN3_S 26 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register 0 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register 1 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register 2 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register 3 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register 4 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 0 +/** EFUSE_RESERVED_2_130 : R; bitpos: [3:2]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_130 0x00000003U +#define EFUSE_RESERVED_2_130_M (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S) +#define EFUSE_RESERVED_2_130_V 0x00000003U +#define EFUSE_RESERVED_2_130_S 2 +/** EFUSE_TEMP_CALIB : R; bitpos: [12:4]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 4 +/** EFUSE_OCODE : R; bitpos: [20:13]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 13 +/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [28:21]; default: 0; + * ADC1 init code at atten0 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU +#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 21 +/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:29]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 29 -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register 5 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [2:0]; default: 0; + * ADC1 init code at atten1 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x00000007U +#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [8:3]; default: 0; + * ADC1 init code at atten2 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 3 +/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [14:9]; default: 0; + * ADC1 init code at atten3 + */ +#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000003FU +#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 9 +/** EFUSE_ADC2_INIT_CODE_ATTEN0 : R; bitpos: [22:15]; default: 0; + * ADC2 init code at atten0 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN0 0x000000FFU +#define EFUSE_ADC2_INIT_CODE_ATTEN0_M (EFUSE_ADC2_INIT_CODE_ATTEN0_V << EFUSE_ADC2_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN0_V 0x000000FFU +#define EFUSE_ADC2_INIT_CODE_ATTEN0_S 15 +/** EFUSE_ADC2_INIT_CODE_ATTEN1 : R; bitpos: [28:23]; default: 0; + * ADC2 init code at atten1 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN1 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN1_M (EFUSE_ADC2_INIT_CODE_ATTEN1_V << EFUSE_ADC2_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN1_V 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN1_S 23 +/** EFUSE_ADC2_INIT_CODE_ATTEN2 : R; bitpos: [31:29]; default: 0; + * ADC2 init code at atten2 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN2 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_M (EFUSE_ADC2_INIT_CODE_ATTEN2_V << EFUSE_ADC2_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN2_V 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_S 29 -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register 6 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_ADC2_INIT_CODE_ATTEN2_1 : R; bitpos: [2:0]; default: 0; + * ADC2 init code at atten2 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_M (EFUSE_ADC2_INIT_CODE_ATTEN2_1_V << EFUSE_ADC2_INIT_CODE_ATTEN2_1_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_V 0x00000007U +#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_S 0 +/** EFUSE_ADC2_INIT_CODE_ATTEN3 : R; bitpos: [8:3]; default: 0; + * ADC2 init code at atten3 + */ +#define EFUSE_ADC2_INIT_CODE_ATTEN3 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN3_M (EFUSE_ADC2_INIT_CODE_ATTEN3_V << EFUSE_ADC2_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC2_INIT_CODE_ATTEN3_V 0x0000003FU +#define EFUSE_ADC2_INIT_CODE_ATTEN3_S 3 +/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; + * ADC1 calibration voltage at atten0 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 9 +/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [24:17]; default: 0; + * ADC1 calibration voltage at atten1 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 17 +/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x0000007FU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x0000007FU +#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 25 -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register 7 of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_ADC1_CAL_VOL_ATTEN2_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration voltage at atten2 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1 (BIT(0)) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_M (EFUSE_ADC1_CAL_VOL_ATTEN2_1_V << EFUSE_ADC1_CAL_VOL_ATTEN2_1_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_V 0x00000001U +#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_S 0 +/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:1]; default: 0; + * ADC1 calibration voltage at atten3 + */ +#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) +#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x000000FFU +#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 1 +/** EFUSE_ADC2_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; + * ADC2 calibration voltage at atten0 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN0 0x000000FFU +#define EFUSE_ADC2_CAL_VOL_ATTEN0_M (EFUSE_ADC2_CAL_VOL_ATTEN0_V << EFUSE_ADC2_CAL_VOL_ATTEN0_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN0_V 0x000000FFU +#define EFUSE_ADC2_CAL_VOL_ATTEN0_S 9 +/** EFUSE_ADC2_CAL_VOL_ATTEN1 : R; bitpos: [23:17]; default: 0; + * ADC2 calibration voltage at atten1 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN1 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN1_M (EFUSE_ADC2_CAL_VOL_ATTEN1_V << EFUSE_ADC2_CAL_VOL_ATTEN1_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN1_V 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN1_S 17 +/** EFUSE_ADC2_CAL_VOL_ATTEN2 : R; bitpos: [30:24]; default: 0; + * ADC2 calibration voltage at atten2 + */ +#define EFUSE_ADC2_CAL_VOL_ATTEN2 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN2_M (EFUSE_ADC2_CAL_VOL_ATTEN2_V << EFUSE_ADC2_CAL_VOL_ATTEN2_S) +#define EFUSE_ADC2_CAL_VOL_ATTEN2_V 0x0000007FU +#define EFUSE_ADC2_CAL_VOL_ATTEN2_S 24 +/** EFUSE_RESERVED_2_255 : R; bitpos: [31]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_255 (BIT(31)) +#define EFUSE_RESERVED_2_255_M (EFUSE_RESERVED_2_255_V << EFUSE_RESERVED_2_255_S) +#define EFUSE_RESERVED_2_255_V 0x00000001U +#define EFUSE_RESERVED_2_255_S 31 -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 +/** EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 +/** EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xA0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xA4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xA8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xAC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xB0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xB4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xB8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xBC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xC0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xC4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xC8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xCC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xD0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xD4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xD8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xDC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xE0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xE4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xE8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xEC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xF0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xF4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xF8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xFC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 0th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register 0 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 1st 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 2nd 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register 2 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 3rd 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register 3 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 4th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register 4 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 5th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register 5 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 6th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register 6 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the 7th 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register 7 of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 26 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 23 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_DIS_APP_CPU_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) -#define EFUSE_DIS_APP_CPU_ERR_M (BIT(15)) -#define EFUSE_DIS_APP_CPU_ERR_V 0x1 -#define EFUSE_DIS_APP_CPU_ERR_S 15 -/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (BIT(14)) -#define EFUSE_DIS_CAN_ERR_V 0x1 -#define EFUSE_DIS_CAN_ERR_S 14 -/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (BIT(13)) -#define EFUSE_DIS_USB_ERR_V 0x1 -#define EFUSE_DIS_USB_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_V 0x1 -#define EFUSE_DIS_DCACHE_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved*/ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DCACHE_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001U +#define EFUSE_DIS_USB_ERR_S 13 +/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001U +#define EFUSE_DIS_CAN_ERR_S 14 +/** EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) +#define EFUSE_DIS_APP_CPU_ERR_M (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S) +#define EFUSE_DIS_APP_CPU_ERR_V 0x00000001U +#define EFUSE_DIS_APP_CPU_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001U +#define EFUSE_EXT_PHY_ENABLE_ERR_S 26 +/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) +#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U +#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 +/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 +/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 -/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x3 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 -/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 -/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 -/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x1 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 -/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 -/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003U #define EFUSE_VDD_SPI_DREFM_ERR_S 0 +/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 +/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_XPD_ERR_S 4 +/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 +/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 +/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 +/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 +/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007U +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 +/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_INIT_ERR_S 12 +/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003U +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 -/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_V 0x1 -#define EFUSE_USB_PHY_SEL_ERR_S 25 -/* EFUSE_STRAP_JTAG_SEL_ERR : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_ERR_M (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x1 -#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 -/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_ERR_S 23 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[22] ;default: 6'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(22)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000000F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0xF -#define EFUSE_RPT4_RESERVED0_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000000FU +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000000FU +#define EFUSE_RPT4_RESERVED0_ERR_S 16 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 22 +/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DEVICE_ERR_S 23 +/** EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_ERR_M (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S) +#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x00000001U +#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 +/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) +#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) +#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U +#define EFUSE_USB_PHY_SEL_ERR_S 25 +/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set this bit to disable download through USB-OTG.*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (BIT(31)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 31 -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) -#define EFUSE_FLASH_ECC_EN_ERR_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_ERR_V 0x1 -#define EFUSE_FLASH_ECC_EN_ERR_S 12 -/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_ERR_M ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S)) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 -/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_V 0x1 -#define EFUSE_FLASH_TYPE_ERR_S 9 -/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_ERR_M (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_ERR_V 0x1 -#define EFUSE_FLASH_ECC_MODE_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) +#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_MODE_ERR_S 3 +/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 9 +/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 +/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_ERR_S 12 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 14 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(30)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 30 +/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR (BIT(31)) +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000001U +#define EFUSE_RPT4_RESERVED1_ERR_S 31 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFFFF +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ +#define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x00FFFFFFU #define EFUSE_RPT4_RESERVED2_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm -ing key4 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm -ing key3 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm -ing key2 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm -ing key1 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm -ing key0 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the user data is reliable 1: Means that programming - user data failed and the number of error bytes is over 6..*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr -ogramming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: Means that programm -ing user data failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory..*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode..*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/ +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode..*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0..*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW..*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW..*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW..*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW..*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2..*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW..*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine..*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ +#define EFUSE_REPEAT_ERR_CNT 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU +#define EFUSE_REPEAT_ERR_CNT_S 10 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block - number 0-10, respectively..*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/WS/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command..*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/WS/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command..*/ +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ #define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : R/WC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : R/WC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt..*/ +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt..*/ +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt..*/ +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt..*/ +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage..*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage..*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care..*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage..*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse..*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU #define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ..*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ..*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ -/*description: Stores eFuse version..*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index 78d797a3d1..c5f811d94e 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -1,500 +1,2515 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ - +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; - uint32_t pgm_data1; - uint32_t pgm_data2; - uint32_t pgm_data3; - uint32_t pgm_data4; - uint32_t pgm_data5; - uint32_t pgm_data6; - uint32_t pgm_data7; - uint32_t pgm_check_value0; - uint32_t pgm_check_value1; - uint32_t pgm_check_value2; - uint32_t rd_wr_dis; - union { - struct { - uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t reg_rpt4_reserved5 : 1; /*Reserved*/ - uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ - uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ - uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/ - uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/ - uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/ - uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/ - uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/ - uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/ - uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/ - uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/ - uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/ - uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/ - uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ - uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/ - uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/ - uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/ - uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ - uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/ - uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/ - uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/ - uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/ - uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/ - uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/ - uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/ - uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/ - uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/ - uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/ - uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/ - uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_direct_boot : 1; /*Set this bit to disable direct boot..*/ - uint32_t dis_usb_serial_jtag_rom_print : 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download through USB-Serial-JTAG.*/ - uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ - uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ - uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/ - uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/ - uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/ - uint32_t reg_dis_usb_otg_download_mode : 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major : 1; - uint32_t disable_blk_version_major : 1; - uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_sys_0; - union { - struct { - uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version_minor_low: 3; - uint32_t pkg_version: 3; - uint32_t blk_version_minor:3; - uint32_t reg_sys_data_part0_0: 5; - }; - uint32_t val; - } rd_mac_spi_sys_3; - union { - struct { - uint32_t reserved1: 13; - uint32_t k_rtc_ldo: 7; - uint32_t k_dig_ldo: 7; - uint32_t v_rtc_dbias20_low: 5; - }; - uint32_t val; - } rd_mac_spi_sys_4; - union { - struct { - uint32_t v_rtc_dbias20_hi: 3; - uint32_t v_dig_dbias20: 8; - uint32_t dig_dbias_hvt: 5; - uint32_t reserved1: 7; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; - }; - uint32_t val; - } rd_mac_spi_sys_5; - uint32_t rd_sys_part1_data0; - uint32_t rd_sys_part1_data1; - uint32_t rd_sys_part1_data2; - uint32_t rd_sys_part1_data3; - union { - struct { - uint32_t blk_version_major: 2; - uint32_t reserved1: 11; - uint32_t ocode: 8; /*ADC OCode*/ - uint32_t reserved2: 11; - }; - uint32_t val; - } rd_sys_part1_data4; - uint32_t rd_sys_part1_data5; - uint32_t rd_sys_part1_data6; - uint32_t rd_sys_part1_data7; - uint32_t rd_usr_data0; - uint32_t rd_usr_data1; - uint32_t rd_usr_data2; - uint32_t rd_usr_data3; - uint32_t rd_usr_data4; - uint32_t rd_usr_data5; - uint32_t rd_usr_data6; - uint32_t rd_usr_data7; - uint32_t rd_key0_data0; - uint32_t rd_key0_data1; - uint32_t rd_key0_data2; - uint32_t rd_key0_data3; - uint32_t rd_key0_data4; - uint32_t rd_key0_data5; - uint32_t rd_key0_data6; - uint32_t rd_key0_data7; - uint32_t rd_key1_data0; - uint32_t rd_key1_data1; - uint32_t rd_key1_data2; - uint32_t rd_key1_data3; - uint32_t rd_key1_data4; - uint32_t rd_key1_data5; - uint32_t rd_key1_data6; - uint32_t rd_key1_data7; - uint32_t rd_key2_data0; - uint32_t rd_key2_data1; - uint32_t rd_key2_data2; - uint32_t rd_key2_data3; - uint32_t rd_key2_data4; - uint32_t rd_key2_data5; - uint32_t rd_key2_data6; - uint32_t rd_key2_data7; - uint32_t rd_key3_data0; - uint32_t rd_key3_data1; - uint32_t rd_key3_data2; - uint32_t rd_key3_data3; - uint32_t rd_key3_data4; - uint32_t rd_key3_data5; - uint32_t rd_key3_data6; - uint32_t rd_key3_data7; - uint32_t rd_key4_data0; - uint32_t rd_key4_data1; - uint32_t rd_key4_data2; - uint32_t rd_key4_data3; - uint32_t rd_key4_data4; - uint32_t rd_key4_data5; - uint32_t rd_key4_data6; - uint32_t rd_key4_data7; - uint32_t rd_key5_data0; - uint32_t rd_key5_data1; - uint32_t rd_key5_data2; - uint32_t rd_key5_data3; - uint32_t rd_key5_data4; - uint32_t rd_key5_data5; - uint32_t rd_key5_data6; - uint32_t rd_key5_data7; - uint32_t rd_sys_part2_data0; - uint32_t rd_sys_part2_data1; - uint32_t rd_sys_part2_data2; - uint32_t rd_sys_part2_data3; - uint32_t rd_sys_part2_data4; - uint32_t rd_sys_part2_data5; - uint32_t rd_sys_part2_data6; - uint32_t rd_sys_part2_data7; - union { - struct { - uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved5_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_direct_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_rom_print_err:1;/*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/ - uint32_t reg_dis_usb_otg_download_mode_err: 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/ - uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - uint32_t wr_tim_conf0; - union { - struct { - uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_dcache : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + uint32_t dis_dcache:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_icache:1; + /** dis_download_dcache : RO; bitpos: [11]; default: 0; + * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_dcache:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** dis_usb_otg : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + uint32_t dis_usb_otg:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + uint32_t dis_twai:1; + /** dis_app_cpu : RO; bitpos: [15]; default: 0; + * Disable app cpu. + */ + uint32_t dis_app_cpu:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** usb_ext_phy_enable : RO; bitpos: [26]; default: 0; + * Set this bit to enable external PHY. + */ + uint32_t usb_ext_phy_enable:1; + /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; + * Bluetooth GPIO signal output security level control. + */ + uint32_t btlc_gpio_enable:2; + /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + uint32_t vdd_spi_modecurlim:1; + /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + uint32_t vdd_spi_drefh:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + uint32_t vdd_spi_drefm:2; + /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + uint32_t vdd_spi_drefl:2; + /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; + * SPI regulator power up signal. + */ + uint32_t vdd_spi_xpd:1; + /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; + * SPI regulator output is short connected to VDD3P3_RTC_IO. + */ + uint32_t vdd_spi_tieh:1; + /** vdd_spi_force : RO; bitpos: [6]; default: 0; + * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + */ + uint32_t vdd_spi_force:1; + /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + uint32_t vdd_spi_en_init:1; + /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + uint32_t vdd_spi_encurlim:1; + /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ + uint32_t vdd_spi_dcurlim:3; + /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + */ + uint32_t vdd_spi_init:2; + /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + uint32_t vdd_spi_dcap:2; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** rpt4_reserved0 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved0:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** dis_usb_jtag : RO; bitpos: [22]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ + uint32_t dis_usb_jtag:1; + /** dis_usb_serial_jtag : RO; bitpos: [23]; default: 0; + * Set this bit to disable usb device. + */ + uint32_t dis_usb_serial_jtag:1; + /** strap_jtag_sel : RO; bitpos: [24]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ + uint32_t strap_jtag_sel:1; + /** usb_phy_sel : RO; bitpos: [25]; default: 0; + * This bit is used to switch internal PHY and external PHY for USB OTG and USB + * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to + * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to + * USB Device. + */ + uint32_t usb_phy_sel:1; + /** power_glitch_dsense : RO; bitpos: [27:26]; default: 0; + * Sample delay configuration of power glitch. + */ + uint32_t power_glitch_dsense:2; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Selectes the default UART print channel. 0: UART0. 1: UART1. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** flash_ecc_mode : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ + uint32_t flash_ecc_mode:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Set this bit to disable UART download mode through USB. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ + uint32_t flash_ecc_en:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** powerglitch_en : RO; bitpos: [30]; default: 0; + * Set this bit to enable power glitch function. + */ + uint32_t powerglitch_en:1; + /** dis_usb_otg_download_mode : R; bitpos: [31]; default: 0; + * Set this bit to disable download through USB-OTG + */ + uint32_t dis_usb_otg_download_mode:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** pkg_version : R; bitpos: [23:21]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** blk_version_minor : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ + uint32_t blk_version_minor:3; + /** reserved_1_123 : R; bitpos: [31:27]; default: 0; + * reserved + */ + uint32_t reserved_1_123:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ +typedef union { + struct { + /** reserved_1_128 : R; bitpos: [12:0]; default: 0; + * reserved + */ + uint32_t reserved_1_128:13; + /** k_rtc_ldo : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ + uint32_t k_rtc_ldo:7; + /** k_dig_ldo : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ + uint32_t k_dig_ldo:7; + /** v_rtc_dbias20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ +typedef union { + struct { + /** v_rtc_dbias20_1 : R; bitpos: [2:0]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20_1:3; + /** v_dig_dbias20 : R; bitpos: [10:3]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20:8; + /** dig_dbias_hvt : R; bitpos: [15:11]; default: 0; + * BLOCK1 digital dbias when hvt + */ + uint32_t dig_dbias_hvt:5; + /** reserved_1_176 : R; bitpos: [22:16]; default: 0; + * reserved + */ + uint32_t reserved_1_176:7; + /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** wafer_version_major : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** adc2_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; + * ADC2 calibration voltage at atten3 + */ + uint32_t adc2_cal_vol_atten3:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** blk_version_major : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + */ + uint32_t blk_version_major:2; + /** reserved_2_130 : R; bitpos: [3:2]; default: 0; + * reserved + */ + uint32_t reserved_2_130:2; + /** temp_calib : R; bitpos: [12:4]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** ocode : R; bitpos: [20:13]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_init_code_atten0 : R; bitpos: [28:21]; default: 0; + * ADC1 init code at atten0 + */ + uint32_t adc1_init_code_atten0:8; + /** adc1_init_code_atten1 : R; bitpos: [31:29]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_init_code_atten1_1 : R; bitpos: [2:0]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1_1:3; + /** adc1_init_code_atten2 : R; bitpos: [8:3]; default: 0; + * ADC1 init code at atten2 + */ + uint32_t adc1_init_code_atten2:6; + /** adc1_init_code_atten3 : R; bitpos: [14:9]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:6; + /** adc2_init_code_atten0 : R; bitpos: [22:15]; default: 0; + * ADC2 init code at atten0 + */ + uint32_t adc2_init_code_atten0:8; + /** adc2_init_code_atten1 : R; bitpos: [28:23]; default: 0; + * ADC2 init code at atten1 + */ + uint32_t adc2_init_code_atten1:6; + /** adc2_init_code_atten2 : R; bitpos: [31:29]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc2_init_code_atten2_1 : R; bitpos: [2:0]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2_1:3; + /** adc2_init_code_atten3 : R; bitpos: [8:3]; default: 0; + * ADC2 init code at atten3 + */ + uint32_t adc2_init_code_atten3:6; + /** adc1_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:8; + /** adc1_cal_vol_atten1 : R; bitpos: [24:17]; default: 0; + * ADC1 calibration voltage at atten1 + */ + uint32_t adc1_cal_vol_atten1:8; + /** adc1_cal_vol_atten2 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten2_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2_1:1; + /** adc1_cal_vol_atten3 : R; bitpos: [8:1]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:8; + /** adc2_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC2 calibration voltage at atten0 + */ + uint32_t adc2_cal_vol_atten0:8; + /** adc2_cal_vol_atten1 : R; bitpos: [23:17]; default: 0; + * ADC2 calibration voltage at atten1 + */ + uint32_t adc2_cal_vol_atten1:7; + /** adc2_cal_vol_atten2 : R; bitpos: [30:24]; default: 0; + * ADC2 calibration voltage at atten2 + */ + uint32_t adc2_cal_vol_atten2:7; + /** reserved_2_255 : R; bitpos: [31]; default: 0; + * reserved + */ + uint32_t reserved_2_255:1; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_icache_err:1; + /** dis_dcache_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_dcache_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_dcache_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_force_download_err:1; + /** dis_usb_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_can_err:1; + /** dis_app_cpu_err : RO; bitpos: [15]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_app_cpu_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_exchg_pins_err:1; + /** ext_phy_enable_err : RO; bitpos: [26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t ext_phy_enable_err:1; + /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t btlc_gpio_enable_err:2; + /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_modecurlim_err:1; + /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefh_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefm_err:2; + /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefl_err:2; + /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_xpd_err:1; + /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_tieh_err:1; + /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_force_err:1; + /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_en_init_err:1; + /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_encurlim_err:1; + /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcurlim_err:3; + /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_init_err:2; + /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcap_err:2; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_5_err:4; + /** rpt4_reserved0_err : RO; bitpos: [19:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved0_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** dis_usb_jtag_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_usb_device_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_device_err:1; + /** strap_jtag_sel_err : RO; bitpos: [24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t strap_jtag_sel_err:1; + /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_phy_sel_err:1; + /** power_glitch_dsense_err : RO; bitpos: [27:26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t power_glitch_dsense_err:2; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_channel_err:1; + /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_mode_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_en_err:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_version_err:16; + /** powerglitch_en_err : RO; bitpos: [30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t powerglitch_en_err:1; + /** rpt4_reserved1_err : RO; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err:1; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved2_err : RO; bitpos: [23:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved2_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34607760; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + uint32_t reserved_1f0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_EFUSE_STRUCT_H_ */