From eda943b7c54585bb53bd9f95879d707f90b3b1be Mon Sep 17 00:00:00 2001 From: houwenxiang Date: Fri, 1 May 2020 20:40:24 +0800 Subject: [PATCH] driver(uart): fix uart module reset issue (release/v4.1) On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue, while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory before the software reset to solve this problem. --- components/esp32/system_api_esp32.c | 2 +- components/soc/esp32/include/hal/uart_ll.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/components/esp32/system_api_esp32.c b/components/esp32/system_api_esp32.c index a6779b54bc..f59b9ff1ae 100644 --- a/components/esp32/system_api_esp32.c +++ b/components/esp32/system_api_esp32.c @@ -102,7 +102,7 @@ void IRAM_ATTR esp_restart_noos(void) // Reset timer/spi/uart DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST); + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset diff --git a/components/soc/esp32/include/hal/uart_ll.h b/components/soc/esp32/include/hal/uart_ll.h index 091b8db3df..37e1c81859 100644 --- a/components/soc/esp32/include/hal/uart_ll.h +++ b/components/soc/esp32/include/hal/uart_ll.h @@ -215,6 +215,8 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) /** * @brief Reset the UART hw txfifo. * + * Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo. + * * @param hw Beginning address of the peripheral registers. * * @return None