diff --git a/components/hal/esp32c5/include/hal/parlio_ll.h b/components/hal/esp32c5/include/hal/parlio_ll.h
index 5f818acd25..735de524d1 100644
--- a/components/hal/esp32c5/include/hal/parlio_ll.h
+++ b/components/hal/esp32c5/include/hal/parlio_ll.h
@@ -377,6 +377,18 @@ static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
     while (dev->reg_update.rx_reg_update);
 }
 
+/**
+ * @brief Get the RX fifo cycle count
+ *
+ * @param dev Parallel IO register base address
+ * @return
+ *        - RX fifo cycle count
+ */
+static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
+{
+    return dev->rx_st0.rx_cnt;
+}
+
 ///////////////////////////////////TX Unit///////////////////////////////////////
 
 /**
diff --git a/components/hal/esp32h2/include/hal/parlio_ll.h b/components/hal/esp32h2/include/hal/parlio_ll.h
index dd284cb900..59b738cd9d 100644
--- a/components/hal/esp32h2/include/hal/parlio_ll.h
+++ b/components/hal/esp32h2/include/hal/parlio_ll.h
@@ -13,6 +13,8 @@
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/hal_utils.h"
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
 #include "soc/pcr_struct.h"
 #include "soc/parl_io_struct.h"
 #include "hal/parlio_types.h"
@@ -372,6 +374,22 @@ static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
     while (dev->reg_update.rx_reg_update);
 }
 
+/**
+ * @brief Get the RX fifo cycle count
+ *
+ * @param dev Parallel IO register base address
+ * @return
+ *        - RX fifo cycle count
+ */
+static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
+{
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
+        return dev->rx_st0.rx_cnt;
+    }
+    /* For the H2 chip revision that smaller than v1.2, only the highest 4-bit are effective,
+     *  need to right shift 1 bit to get the actual count */
+    return dev->rx_st0.rx_cnt >> 1;
+}
 ///////////////////////////////////TX Unit///////////////////////////////////////
 
 /**
diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h
index 94cb605c99..2ca418cb59 100644
--- a/components/hal/esp32p4/include/hal/parlio_ll.h
+++ b/components/hal/esp32p4/include/hal/parlio_ll.h
@@ -407,6 +407,18 @@ static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
     while (dev->reg_update.rx_reg_update);
 }
 
+/**
+ * @brief Get the RX fifo cycle count
+ *
+ * @param dev Parallel IO register base address
+ * @return
+ *        - RX fifo cycle count
+ */
+static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
+{
+    return dev->rx_st0.rx_cnt;
+}
+
 ///////////////////////////////////TX Unit///////////////////////////////////////
 
 /**
diff --git a/components/soc/esp32h2/register/soc/parl_io_reg.h b/components/soc/esp32h2/register/soc/parl_io_reg.h
index d68f5191cb..05b4ec3fe3 100644
--- a/components/soc/esp32h2/register/soc/parl_io_reg.h
+++ b/components/soc/esp32h2/register/soc/parl_io_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -359,13 +359,16 @@ extern "C" {
  *  Parallel IO RX status register0
  */
 #define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
-/** PARL_IO_RX_CNT : RO; bitpos: [12:9]; default: 0;
+/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
  *  Indicates the cycle number of reading Rx FIFO.
+ *  For the H2 chip revision smaller than v1.2,
+ *  only the highest 4-bit are effective,
+ *  need to right shift 1 bit to get the actual count
  */
-#define PARL_IO_RX_CNT    0x0000000FU
+#define PARL_IO_RX_CNT    0x0000001FU
 #define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
-#define PARL_IO_RX_CNT_V  0x0000000FU
-#define PARL_IO_RX_CNT_S  9
+#define PARL_IO_RX_CNT_V  0x0000001FU
+#define PARL_IO_RX_CNT_S  8
 /** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
  *  Indicates the current written bit number into Rx FIFO.
  */
diff --git a/components/soc/esp32h2/register/soc/parl_io_struct.h b/components/soc/esp32h2/register/soc/parl_io_struct.h
index 6e501e6c57..d74bef0e25 100644
--- a/components/soc/esp32h2/register/soc/parl_io_struct.h
+++ b/components/soc/esp32h2/register/soc/parl_io_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -345,11 +345,14 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:9;
-        /** rx_cnt : RO; bitpos: [12:9]; default: 0;
+        uint32_t reserved_0:8;
+        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
          *  Indicates the cycle number of reading Rx FIFO.
+         *  For the H2 chip revision smaller than v1.2,
+         *  only the highest 4-bit are effective,
+         *  need to right shift 1 bit to get the actual count
          */
-        uint32_t rx_cnt:4;
+        uint32_t rx_cnt:5;
         /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
          *  Indicates the current written bit number into Rx FIFO.
          */