From ab53d300d00b2471e2982e6eb8274d43b6183dc4 Mon Sep 17 00:00:00 2001
From: wanckl <wanlei@espressif.com>
Date: Wed, 7 Aug 2024 19:44:48 +0800
Subject: [PATCH] feat(esp_driver_spi): add config for data io default level

---
 .../esp_driver_spi/include/driver/spi_common.h   |  1 +
 components/esp_driver_spi/src/gpspi/spi_master.c |  1 +
 components/hal/include/hal/spi_hal.h             |  8 ++++++++
 components/hal/spi_hal.c                         | 16 +++++++++++-----
 4 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/components/esp_driver_spi/include/driver/spi_common.h b/components/esp_driver_spi/include/driver/spi_common.h
index d842adc377..364e2d2278 100644
--- a/components/esp_driver_spi/include/driver/spi_common.h
+++ b/components/esp_driver_spi/include/driver/spi_common.h
@@ -116,6 +116,7 @@ typedef struct {
     int data5_io_num;     ///< GPIO pin for spi data5 signal in octal mode, or -1 if not used.
     int data6_io_num;     ///< GPIO pin for spi data6 signal in octal mode, or -1 if not used.
     int data7_io_num;     ///< GPIO pin for spi data7 signal in octal mode, or -1 if not used.
+    bool data_io_default_level; ///< Output data IO default level when no transaction.
     int max_transfer_sz;  ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` if DMA is disabled.
     uint32_t flags;       ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
     esp_intr_cpu_affinity_t  isr_cpu_id;    ///< Select cpu core to register SPI ISR.
diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c
index e565e42d16..bc2ce1967f 100644
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@@ -314,6 +314,7 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id)
         spi_ll_enable_clock(host_id, true);
     }
     spi_hal_init(&host->hal, host_id);
+    spi_hal_config_io_default_level(&host->hal, bus_attr->bus_cfg.data_io_default_level);
 
     if (host_id != SPI1_HOST) {
         //SPI1 attributes are already initialized at start up.
diff --git a/components/hal/include/hal/spi_hal.h b/components/hal/include/hal/spi_hal.h
index 41f32a5f52..0ad890170b 100644
--- a/components/hal/include/hal/spi_hal.h
+++ b/components/hal/include/hal/spi_hal.h
@@ -168,6 +168,14 @@ typedef struct {
  */
 void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id);
 
+/**
+ * Config default output IO level when don't have transaction
+ *
+ * @param hal Context of the HAL layer.
+ * @param level IO level to config
+ */
+void spi_hal_config_io_default_level(spi_hal_context_t *hal, bool level);
+
 /**
  * Deinit the peripheral (and the context if needed).
  *
diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c
index 8d1dca9006..03402357db 100644
--- a/components/hal/spi_hal.c
+++ b/components/hal/spi_hal.c
@@ -26,11 +26,6 @@ void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id)
     memset(hal, 0, sizeof(spi_hal_context_t));
     spi_dev_t *hw = SPI_LL_GET_HW(host_id);
     hal->hw = hw;
-
-#if SPI_LL_MOSI_FREE_LEVEL
-    // Change default data line level to low which same as esp32
-    spi_ll_set_mosi_free_level(hw, 0);
-#endif
     spi_ll_master_init(hw);
 
     //Force a transaction done interrupt. This interrupt won't fire yet because
@@ -43,6 +38,17 @@ void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id)
     spi_ll_apply_config(hw);
 }
 
+void spi_hal_config_io_default_level(spi_hal_context_t *hal, bool level)
+{
+#if SPI_LL_MOSI_FREE_LEVEL
+    // Config default output data line level when don't have transaction
+    spi_ll_set_mosi_free_level(hal->hw, level);
+    spi_ll_apply_config(hal->hw);
+#else
+    HAL_LOGW(SPI_HAL_TAG, "The target don't support this config")
+#endif
+}
+
 void spi_hal_deinit(spi_hal_context_t *hal)
 {
     spi_dev_t *hw = hal->hw;