From acecfe4ba51cce9056d602011505dba0e31e6151 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 10 Mar 2023 10:55:09 +0800 Subject: [PATCH] bugfix: Slow clock power domain management has been maintained in pd_flags --- components/esp_hw_support/sleep_modes.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c83c44c5a4..41aaa3d8e3 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -723,8 +723,7 @@ void IRAM_ATTR esp_deep_sleep_start(void) #if SOC_PMU_SUPPORTED uint32_t force_pd_flags = PMU_SLEEP_PD_TOP | PMU_SLEEP_PD_VDDSDIO | PMU_SLEEP_PD_MODEM | PMU_SLEEP_PD_HP_PERIPH \ - | PMU_SLEEP_PD_CPU | PMU_SLEEP_PD_MEM | PMU_SLEEP_PD_XTAL | PMU_SLEEP_PD_RC_FAST \ - | PMU_SLEEP_PD_XTAL32K |PMU_SLEEP_PD_RC32K; + | PMU_SLEEP_PD_CPU | PMU_SLEEP_PD_MEM | PMU_SLEEP_PD_XTAL; #else uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL; #endif