diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt index 6d3d4fbaba..0c602f92c1 100644 --- a/components/esp_adc/CMakeLists.txt +++ b/components/esp_adc/CMakeLists.txt @@ -4,10 +4,12 @@ set(includes "include" "interface" "${target}/include" "deprecated/include") set(srcs "adc_cali.c" "adc_cali_curve_fitting.c" - "adc_oneshot.c" - "adc_common.c" "deprecated/esp_adc_cal_common_legacy.c") +if(CONFIG_SOC_ADC_SUPPORTED) + list(APPEND srcs "adc_oneshot.c" "adc_common.c") +endif() + if(CONFIG_SOC_ADC_DMA_SUPPORTED) list(APPEND srcs "adc_continuous.c") if(CONFIG_SOC_ADC_MONITOR_SUPPORTED) diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c index 8681c91aae..1d63f66686 100644 --- a/components/esp_hw_support/regi2c_ctrl.c +++ b/components/esp_hw_support/regi2c_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -79,7 +79,7 @@ void IRAM_ATTR regi2c_analog_cali_reg_write(void) regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]); } } - +#endif //#if ADC_CALI_PD_WORKAROUND /** * REGI2C_SARADC reference count @@ -109,6 +109,3 @@ void regi2c_saradc_disable(void) regi2c_exit_critical(); } - - -#endif //#if ADC_CALI_PD_WORKAROUND diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 4162435838..b18b3685e9 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -40,8 +40,6 @@ if(NOT BOOTLOADER_BUILD) "gpio_hal.c" "uart_hal.c" "uart_hal_iram.c" - "adc_hal_common.c" - "adc_oneshot_hal.c" "${target}/clk_tree_hal.c") if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) @@ -110,6 +108,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "parlio_hal.c") endif() + if(CONFIG_SOC_ADC_SUPPORTED) + list(APPEND srcs "adc_hal_common.c" "adc_oneshot_hal.c") + endif() + if(CONFIG_SOC_ADC_DMA_SUPPORTED) list(APPEND srcs "adc_hal.c") endif() diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h index 5e37c7e411..ea733f3566 100644 --- a/components/hal/include/hal/i2c_types.h +++ b/components/hal/include/hal/i2c_types.h @@ -92,11 +92,12 @@ typedef struct { int timeout; /*!< timeout value */ } i2c_hal_timing_config_t; - +#if SOC_I2C_SUPPORTED /** * @brief I2C group clock source */ typedef soc_periph_i2c_clk_src_t i2c_clock_source_t; +#endif #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/regi2c_defs.h b/components/soc/esp32c6/include/soc/regi2c_defs.h index 397a42c2a3..38db4f1595 100644 --- a/components/soc/esp32c6/include/soc/regi2c_defs.h +++ b/components/soc/esp32c6/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,11 +27,3 @@ #define ANA_CONFIG2_M BIT(18) #define ANA_I2C_SAR_FORCE_PU BIT(16) - - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32h2/include/soc/regi2c_defs.h b/components/soc/esp32h2/include/soc/regi2c_defs.h index c7991ec3e0..e9611d885e 100644 --- a/components/soc/esp32h2/include/soc/regi2c_defs.h +++ b/components/soc/esp32h2/include/soc/regi2c_defs.h @@ -26,10 +26,3 @@ #define ANA_CONFIG2_M BIT(18) #define ANA_I2C_SAR_FORCE_PU BIT(16) - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32p4/adc_periph.c b/components/soc/esp32p4/adc_periph.c new file mode 100644 index 0000000000..47081cfc68 --- /dev/null +++ b/components/soc/esp32p4/adc_periph.c @@ -0,0 +1,10 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {}; diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c new file mode 100644 index 0000000000..890525bc2b --- /dev/null +++ b/components/soc/esp32p4/gdma_periph.c @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" + +const gdma_signal_conn_t gdma_periph_signals = {}; diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c index e69de29bb2..c23436882a 100644 --- a/components/soc/esp32p4/gpio_periph.c +++ b/components/soc/esp32p4/gpio_periph.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[] = { + +}; + +// _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); + +const uint32_t GPIO_HOLD_MASK[] = { + +}; + +// _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c new file mode 100644 index 0000000000..b444a1255d --- /dev/null +++ b/components/soc/esp32p4/i2c_periph.c @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { +}; diff --git a/components/soc/esp32p4/i2s_periph.c b/components/soc/esp32p4/i2s_periph.c new file mode 100644 index 0000000000..1e466a3433 --- /dev/null +++ b/components/soc/esp32p4/i2s_periph.c @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2s_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..cf0f176453 --- /dev/null +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,956 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 7 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_CALIBRATION_V1_SUPPORTED + bool + default n + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CACHE_L2_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 2 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default n + +config SOC_INT_CLIC_SUPPORTED + bool + default y + +config SOC_BRANCH_PREDICTOR_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_SIZE + hex + default 0x80000000 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_GDMA_GROUPS + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP + int + default 3 + +config SOC_GDMA_SUPPORT_ETM + bool + default n + +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 64 + +config SOC_GPIO_ETM_EVENTS_PER_GROUP + int + default 8 + +config SOC_GPIO_ETM_TASKS_PER_GROUP + int + default 8 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_GPIO_VALID_GPIO_MASK + hex + default 0xFFFFFFFFFFFFFFFF + +config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK + int + default 0 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000007FFFFF00 + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_I2C_NUM + int + default 1 + +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_CLR_BUS + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_RTC + bool + default y + +config SOC_I2S_NUM + int + default 1 + +config SOC_I2S_HW_VERSION_2 + bool + default y + +config SOC_I2S_SUPPORTS_XTAL + bool + default y + +config SOC_I2S_SUPPORTS_PLL_F160M + bool + default y + +config SOC_I2S_SUPPORTS_PCM + bool + default y + +config SOC_I2S_SUPPORTS_PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_TX + bool + default y + +config SOC_I2S_PDM_MAX_TX_LINES + int + default 2 + +config SOC_I2S_SUPPORTS_TDM + bool + default y + +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_LEDC_TIMER_BIT_WIDTH + int + default 20 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_LEDC_GAMMA_FADE_RANGE_MAX + int + default 16 + +config SOC_MMU_PAGE_SIZE_CONFIGURABLE + bool + default n + +config SOC_MMU_PERIPH_NUM + int + default 2 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 2 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED + bool + default n + +config SOC_MPU_MIN_REGION_SIZE + hex + default 0x20000000 + +config SOC_MPU_REGIONS_MAX_NUM + int + default 8 + +config SOC_MPU_REGION_RO_SUPPORTED + bool + default n + +config SOC_MPU_REGION_WO_SUPPORTED + bool + default n + +config SOC_PCNT_GROUPS + int + default 1 + +config SOC_PCNT_UNITS_PER_GROUP + int + default 4 + +config SOC_PCNT_CHANNELS_PER_UNIT + int + default 2 + +config SOC_PCNT_THRES_POINT_PER_UNIT + int + default 2 + +config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE + bool + default y + +config SOC_RMT_GROUPS + int + default 1 + +config SOC_RMT_TX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_RX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_CHANNELS_PER_GROUP + int + default 4 + +config SOC_RMT_MEM_WORDS_PER_CHANNEL + int + default 48 + +config SOC_RMT_SUPPORT_RX_PINGPONG + bool + default y + +config SOC_RMT_SUPPORT_RX_DEMODULATION + bool + default y + +config SOC_RMT_SUPPORT_TX_ASYNC_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_COUNT + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_SYNCHRO + bool + default y + +config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY + bool + default y + +config SOC_RMT_SUPPORT_XTAL + bool + default y + +config SOC_RMT_SUPPORT_RC_FAST + bool + default y + +config SOC_MCPWM_GROUPS + int + default 1 + +config SOC_MCPWM_TIMERS_PER_GROUP + int + default 3 + +config SOC_MCPWM_OPERATORS_PER_GROUP + int + default 3 + +config SOC_MCPWM_COMPARATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GENERATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_TRIGGERS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GPIO_FAULTS_PER_GROUP + int + default 3 + +config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP + bool + default y + +config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER + int + default 3 + +config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP + int + default 3 + +config SOC_MCPWM_SWSYNC_CAN_PROPAGATE + bool + default y + +config SOC_MCPWM_SUPPORT_ETM + bool + default y + +config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP + bool + default y + +config SOC_PARLIO_GROUPS + int + default 1 + +config SOC_PARLIO_TX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_RX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH + int + default 16 + +config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH + int + default 16 + +config SOC_PARLIO_TX_RX_SHARE_INTERRUPT + bool + default y + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SDMMC_USE_IOMUX + bool + default y + +config SOC_SDMMC_USE_GPIO_MATRIX + bool + default y + +config SOC_SDMMC_NUM_SLOTS + int + default 2 + +config SOC_SDMMC_IOMUX_FUNC + bool + default n + +config SOC_SDMMC_DMA_NEED_CACHE_WB + bool + default y + +config SOC_SDM_GROUPS + int + default 1 + +config SOC_SDM_CHANNELS_PER_GROUP + int + default 4 + +config SOC_SDM_CLK_SUPPORT_PLL_F80M + bool + default y + +config SOC_SDM_CLK_SUPPORT_XTAL + bool + default y + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default n + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_SPI_SUPPORT_CLK_PLL_F80M + bool + default y + +config SOC_SPI_SUPPORT_CLK_RC_FAST + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_SPI_MEM_SUPPORT_WRAP + bool + default y + +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_RC_FAST + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_TIMER_SUPPORT_ETM + bool + default n + +config SOC_TWAI_CONTROLLER_NUM + int + default 2 + +config SOC_TWAI_CLK_SUPPORT_XTAL + bool + default y + +config SOC_TWAI_BRP_MIN + int + default 2 + +config SOC_TWAI_BRP_MAX + int + default 32768 + +config SOC_TWAI_SUPPORTS_RX_STATUS + bool + default y + +config SOC_EFUSE_DIS_DOWNLOAD_ICACHE + bool + default y + +config SOC_EFUSE_DIS_PAD_JTAG + bool + default y + +config SOC_EFUSE_DIS_USB_JTAG + bool + default y + +config SOC_EFUSE_DIS_DIRECT_BOOT + bool + default y + +config SOC_EFUSE_SOFT_DIS_JTAG + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default y + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 32 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_UART_NUM + int + default 2 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_PLL_F80M_CLK + bool + default y + +config SOC_UART_SUPPORT_RTC_CLK + bool + default y + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH + int + default 12 + +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_TOP_PD + bool + default y + +config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY + bool + default y + +config SOC_PM_CPU_RETENTION_BY_SW + bool + default n + +config SOC_PM_PAU_LINK_NUM + int + default 4 + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default n + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL + bool + default y diff --git a/components/soc/esp32p4/include/soc/adc_channel.h b/components/soc/esp32p4/include/soc/adc_channel.h new file mode 100644 index 0000000000..d2aa55b41e --- /dev/null +++ b/components/soc/esp32p4/include/soc/adc_channel.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32p4/include/soc/boot_mode.h b/components/soc/esp32p4/include/soc/boot_mode.h new file mode 100644 index 0000000000..d532dc1bc9 --- /dev/null +++ b/components/soc/esp32p4/include/soc/boot_mode.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32p4/include/soc/clic_reg.h b/components/soc/esp32p4/include/soc/clic_reg.h new file mode 100644 index 0000000000..29853d2b5d --- /dev/null +++ b/components/soc/esp32p4/include/soc/clic_reg.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define NLBITS 3 +#define CLIC_EXT_INTR_NUM_OFFSET 16 +#define DUALCORE_CLIC_CTRL_OFF 0x10000 + +#define DR_REG_CLIC_BASE ( 0x20800000 ) +#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 ) + +#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0) +/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NMBITS 0x00000003 +#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S)) +#define CLIC_INT_CONFIG_NMBITS_V 0x3 +#define CLIC_INT_CONFIG_NMBITS_S 5 +/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NLBITS 0x0000000F +#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S)) +#define CLIC_INT_CONFIG_NLBITS_V 0xF +#define CLIC_INT_CONFIG_NLBITS_S 1 +/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NVBITS (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_M (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_V 0x1 +#define CLIC_INT_CONFIG_NVBITS_S 0 + +#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4) +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_CTLBITS 0x0000000F +#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S)) +#define CLIC_INT_INFO_CTLBITS_V 0xF +#define CLIC_INT_INFO_CTLBITS_S 21 +/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_VERSION 0x000000FF +#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S)) +#define CLIC_INT_INFO_VERSION_V 0xFF +#define CLIC_INT_INFO_VERSION_S 13 +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_NUM_INT 0x00001FFF +#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S)) +#define CLIC_INT_INFO_NUM_INT_V 0x1FFF +#define CLIC_INT_INFO_NUM_INT_S 0 + +#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8) +/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_CPU_INT_THRESH 0x000000FF +#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S)) +#define CLIC_CPU_INT_THRESH_V 0xFF +#define CLIC_CPU_INT_THRESH_S 24 + +#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4) +/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_CTL 0x000000FF +#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S)) +#define CLIC_INT_CTL_V 0xFF +#define CLIC_INT_CTL_S 24 +/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_MODE 0x00000003 +#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S)) +#define CLIC_INT_ATTR_MODE_V 0x3 +#define CLIC_INT_ATTR_MODE_S 22 +/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_TRIG 0x00000003 +#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S)) +#define CLIC_INT_ATTR_TRIG_V 0x3 +#define CLIC_INT_ATTR_TRIG_S 17 +/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_SHV (BIT(16)) +#define CLIC_INT_ATTR_SHV_M (BIT(16)) +#define CLIC_INT_ATTR_SHV_V 0x1 +#define CLIC_INT_ATTR_SHV_S 16 +/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IE (BIT(8)) +#define CLIC_INT_IE_M (BIT(8)) +#define CLIC_INT_IE_V 0x1 +#define CLIC_INT_IE_S 8 +/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IP (BIT(0)) +#define CLIC_INT_IP_M (BIT(0)) +#define CLIC_INT_IP_V 0x1 +#define CLIC_INT_IP_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h new file mode 100644 index 0000000000..e6a690eb8b --- /dev/null +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -0,0 +1,232 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32P4 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ + SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// + +//TODO: IDF-7486 +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + + + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + + + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + + + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +//TODO: IDF-6511 +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ +} soc_periph_uart_clk_src_legacy_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + + + +///////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +//TODO: IDF-7502 +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + + +//////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +//TODO: IDF-6516 +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h new file mode 100644 index 0000000000..d3ba233faa --- /dev/null +++ b/components/soc/esp32p4/include/soc/clkout_channel.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +//Copied from C6, please check. TODO: IDF-7526 +// ESP32P4 CLKOUT signals has no corresponding iomux pins diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h b/components/soc/esp32p4/include/soc/core0_interrupt_reg.h deleted file mode 100644 index a71a12b423..0000000000 --- a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h +++ /dev/null @@ -1,1624 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** CORE0_LP_RTC_INT_MAP_REG register - * NA - */ -#define CORE0_LP_RTC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x0) -/** CORE0_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_RTC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_RTC_INT_MAP_M (CORE0_CORE0_LP_RTC_INT_MAP_V << CORE0_CORE0_LP_RTC_INT_MAP_S) -#define CORE0_CORE0_LP_RTC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_RTC_INT_MAP_S 0 - -/** CORE0_LP_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_LP_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4) -/** CORE0_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_WDT_INT_MAP_M (CORE0_CORE0_LP_WDT_INT_MAP_V << CORE0_CORE0_LP_WDT_INT_MAP_S) -#define CORE0_CORE0_LP_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_WDT_INT_MAP_S 0 - -/** CORE0_LP_TIMER_REG_0_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8) -/** CORE0_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_M (CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S) -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S 0 - -/** CORE0_LP_TIMER_REG_1_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc) -/** CORE0_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_M (CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S) -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S 0 - -/** CORE0_MB_HP_INT_MAP_REG register - * NA - */ -#define CORE0_MB_HP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10) -/** CORE0_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_MB_HP_INT_MAP 0x0000003FU -#define CORE0_CORE0_MB_HP_INT_MAP_M (CORE0_CORE0_MB_HP_INT_MAP_V << CORE0_CORE0_MB_HP_INT_MAP_S) -#define CORE0_CORE0_MB_HP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_MB_HP_INT_MAP_S 0 - -/** CORE0_MB_LP_INT_MAP_REG register - * NA - */ -#define CORE0_MB_LP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14) -/** CORE0_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_MB_LP_INT_MAP 0x0000003FU -#define CORE0_CORE0_MB_LP_INT_MAP_M (CORE0_CORE0_MB_LP_INT_MAP_V << CORE0_CORE0_MB_LP_INT_MAP_S) -#define CORE0_CORE0_MB_LP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_MB_LP_INT_MAP_S 0 - -/** CORE0_PMU_REG_0_INT_MAP_REG register - * NA - */ -#define CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18) -/** CORE0_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMU_REG_0_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMU_REG_0_INT_MAP_M (CORE0_CORE0_PMU_REG_0_INT_MAP_V << CORE0_CORE0_PMU_REG_0_INT_MAP_S) -#define CORE0_CORE0_PMU_REG_0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMU_REG_0_INT_MAP_S 0 - -/** CORE0_PMU_REG_1_INT_MAP_REG register - * NA - */ -#define CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c) -/** CORE0_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMU_REG_1_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMU_REG_1_INT_MAP_M (CORE0_CORE0_PMU_REG_1_INT_MAP_V << CORE0_CORE0_PMU_REG_1_INT_MAP_S) -#define CORE0_CORE0_PMU_REG_1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMU_REG_1_INT_MAP_S 0 - -/** CORE0_LP_ANAPERI_INT_MAP_REG register - * NA - */ -#define CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x20) -/** CORE0_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_ANAPERI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_M (CORE0_CORE0_LP_ANAPERI_INT_MAP_V << CORE0_CORE0_LP_ANAPERI_INT_MAP_S) -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_S 0 - -/** CORE0_LP_ADC_INT_MAP_REG register - * NA - */ -#define CORE0_LP_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x24) -/** CORE0_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_ADC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_ADC_INT_MAP_M (CORE0_CORE0_LP_ADC_INT_MAP_V << CORE0_CORE0_LP_ADC_INT_MAP_S) -#define CORE0_CORE0_LP_ADC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_ADC_INT_MAP_S 0 - -/** CORE0_LP_GPIO_INT_MAP_REG register - * NA - */ -#define CORE0_LP_GPIO_INT_MAP_REG (DR_REG_CORE0_BASE + 0x28) -/** CORE0_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_GPIO_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_GPIO_INT_MAP_M (CORE0_CORE0_LP_GPIO_INT_MAP_V << CORE0_CORE0_LP_GPIO_INT_MAP_S) -#define CORE0_CORE0_LP_GPIO_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_GPIO_INT_MAP_S 0 - -/** CORE0_LP_I2C_INT_MAP_REG register - * NA - */ -#define CORE0_LP_I2C_INT_MAP_REG (DR_REG_CORE0_BASE + 0x2c) -/** CORE0_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_I2C_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_I2C_INT_MAP_M (CORE0_CORE0_LP_I2C_INT_MAP_V << CORE0_CORE0_LP_I2C_INT_MAP_S) -#define CORE0_CORE0_LP_I2C_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_I2C_INT_MAP_S 0 - -/** CORE0_LP_I2S_INT_MAP_REG register - * NA - */ -#define CORE0_LP_I2S_INT_MAP_REG (DR_REG_CORE0_BASE + 0x30) -/** CORE0_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_I2S_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_I2S_INT_MAP_M (CORE0_CORE0_LP_I2S_INT_MAP_V << CORE0_CORE0_LP_I2S_INT_MAP_S) -#define CORE0_CORE0_LP_I2S_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_I2S_INT_MAP_S 0 - -/** CORE0_LP_SPI_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x34) -/** CORE0_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SPI_INT_MAP_M (CORE0_CORE0_LP_SPI_INT_MAP_V << CORE0_CORE0_LP_SPI_INT_MAP_S) -#define CORE0_CORE0_LP_SPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SPI_INT_MAP_S 0 - -/** CORE0_LP_TOUCH_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_CORE0_BASE + 0x38) -/** CORE0_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TOUCH_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TOUCH_INT_MAP_M (CORE0_CORE0_LP_TOUCH_INT_MAP_V << CORE0_CORE0_LP_TOUCH_INT_MAP_S) -#define CORE0_CORE0_LP_TOUCH_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TOUCH_INT_MAP_S 0 - -/** CORE0_LP_TSENS_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TSENS_INT_MAP_REG (DR_REG_CORE0_BASE + 0x3c) -/** CORE0_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TSENS_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TSENS_INT_MAP_M (CORE0_CORE0_LP_TSENS_INT_MAP_V << CORE0_CORE0_LP_TSENS_INT_MAP_S) -#define CORE0_CORE0_LP_TSENS_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TSENS_INT_MAP_S 0 - -/** CORE0_LP_UART_INT_MAP_REG register - * NA - */ -#define CORE0_LP_UART_INT_MAP_REG (DR_REG_CORE0_BASE + 0x40) -/** CORE0_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_UART_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_UART_INT_MAP_M (CORE0_CORE0_LP_UART_INT_MAP_V << CORE0_CORE0_LP_UART_INT_MAP_S) -#define CORE0_CORE0_LP_UART_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_UART_INT_MAP_S 0 - -/** CORE0_LP_EFUSE_INT_MAP_REG register - * NA - */ -#define CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x44) -/** CORE0_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_EFUSE_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_EFUSE_INT_MAP_M (CORE0_CORE0_LP_EFUSE_INT_MAP_V << CORE0_CORE0_LP_EFUSE_INT_MAP_S) -#define CORE0_CORE0_LP_EFUSE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_EFUSE_INT_MAP_S 0 - -/** CORE0_LP_SW_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SW_INT_MAP_REG (DR_REG_CORE0_BASE + 0x48) -/** CORE0_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SW_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SW_INT_MAP_M (CORE0_CORE0_LP_SW_INT_MAP_V << CORE0_CORE0_LP_SW_INT_MAP_S) -#define CORE0_CORE0_LP_SW_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SW_INT_MAP_S 0 - -/** CORE0_LP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4c) -/** CORE0_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SYSREG_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SYSREG_INT_MAP_M (CORE0_CORE0_LP_SYSREG_INT_MAP_V << CORE0_CORE0_LP_SYSREG_INT_MAP_S) -#define CORE0_CORE0_LP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SYSREG_INT_MAP_S 0 - -/** CORE0_LP_HUK_INT_MAP_REG register - * NA - */ -#define CORE0_LP_HUK_INT_MAP_REG (DR_REG_CORE0_BASE + 0x50) -/** CORE0_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_HUK_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_HUK_INT_MAP_M (CORE0_CORE0_LP_HUK_INT_MAP_V << CORE0_CORE0_LP_HUK_INT_MAP_S) -#define CORE0_CORE0_LP_HUK_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_HUK_INT_MAP_S 0 - -/** CORE0_SYS_ICM_INT_MAP_REG register - * NA - */ -#define CORE0_SYS_ICM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x54) -/** CORE0_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYS_ICM_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYS_ICM_INT_MAP_M (CORE0_CORE0_SYS_ICM_INT_MAP_V << CORE0_CORE0_SYS_ICM_INT_MAP_S) -#define CORE0_CORE0_SYS_ICM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYS_ICM_INT_MAP_S 0 - -/** CORE0_USB_DEVICE_INT_MAP_REG register - * NA - */ -#define CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x58) -/** CORE0_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_DEVICE_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_DEVICE_INT_MAP_M (CORE0_CORE0_USB_DEVICE_INT_MAP_V << CORE0_CORE0_USB_DEVICE_INT_MAP_S) -#define CORE0_CORE0_USB_DEVICE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_DEVICE_INT_MAP_S 0 - -/** CORE0_SDIO_HOST_INT_MAP_REG register - * NA - */ -#define CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x5c) -/** CORE0_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SDIO_HOST_INT_MAP 0x0000003FU -#define CORE0_CORE0_SDIO_HOST_INT_MAP_M (CORE0_CORE0_SDIO_HOST_INT_MAP_V << CORE0_CORE0_SDIO_HOST_INT_MAP_S) -#define CORE0_CORE0_SDIO_HOST_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SDIO_HOST_INT_MAP_S 0 - -/** CORE0_GDMA_INT_MAP_REG register - * NA - */ -#define CORE0_GDMA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x60) -/** CORE0_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GDMA_INT_MAP 0x0000003FU -#define CORE0_CORE0_GDMA_INT_MAP_M (CORE0_CORE0_GDMA_INT_MAP_V << CORE0_CORE0_GDMA_INT_MAP_S) -#define CORE0_CORE0_GDMA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GDMA_INT_MAP_S 0 - -/** CORE0_SPI2_INT_MAP_REG register - * NA - */ -#define CORE0_SPI2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x64) -/** CORE0_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SPI2_INT_MAP 0x0000003FU -#define CORE0_CORE0_SPI2_INT_MAP_M (CORE0_CORE0_SPI2_INT_MAP_V << CORE0_CORE0_SPI2_INT_MAP_S) -#define CORE0_CORE0_SPI2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SPI2_INT_MAP_S 0 - -/** CORE0_SPI3_INT_MAP_REG register - * NA - */ -#define CORE0_SPI3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x68) -/** CORE0_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SPI3_INT_MAP 0x0000003FU -#define CORE0_CORE0_SPI3_INT_MAP_M (CORE0_CORE0_SPI3_INT_MAP_V << CORE0_CORE0_SPI3_INT_MAP_S) -#define CORE0_CORE0_SPI3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SPI3_INT_MAP_S 0 - -/** CORE0_I2S0_INT_MAP_REG register - * NA - */ -#define CORE0_I2S0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x6c) -/** CORE0_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S0_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S0_INT_MAP_M (CORE0_CORE0_I2S0_INT_MAP_V << CORE0_CORE0_I2S0_INT_MAP_S) -#define CORE0_CORE0_I2S0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S0_INT_MAP_S 0 - -/** CORE0_I2S1_INT_MAP_REG register - * NA - */ -#define CORE0_I2S1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x70) -/** CORE0_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S1_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S1_INT_MAP_M (CORE0_CORE0_I2S1_INT_MAP_V << CORE0_CORE0_I2S1_INT_MAP_S) -#define CORE0_CORE0_I2S1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S1_INT_MAP_S 0 - -/** CORE0_I2S2_INT_MAP_REG register - * NA - */ -#define CORE0_I2S2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x74) -/** CORE0_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S2_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S2_INT_MAP_M (CORE0_CORE0_I2S2_INT_MAP_V << CORE0_CORE0_I2S2_INT_MAP_S) -#define CORE0_CORE0_I2S2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S2_INT_MAP_S 0 - -/** CORE0_UHCI0_INT_MAP_REG register - * NA - */ -#define CORE0_UHCI0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x78) -/** CORE0_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UHCI0_INT_MAP 0x0000003FU -#define CORE0_CORE0_UHCI0_INT_MAP_M (CORE0_CORE0_UHCI0_INT_MAP_V << CORE0_CORE0_UHCI0_INT_MAP_S) -#define CORE0_CORE0_UHCI0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UHCI0_INT_MAP_S 0 - -/** CORE0_UART0_INT_MAP_REG register - * NA - */ -#define CORE0_UART0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x7c) -/** CORE0_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART0_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART0_INT_MAP_M (CORE0_CORE0_UART0_INT_MAP_V << CORE0_CORE0_UART0_INT_MAP_S) -#define CORE0_CORE0_UART0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART0_INT_MAP_S 0 - -/** CORE0_UART1_INT_MAP_REG register - * NA - */ -#define CORE0_UART1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x80) -/** CORE0_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART1_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART1_INT_MAP_M (CORE0_CORE0_UART1_INT_MAP_V << CORE0_CORE0_UART1_INT_MAP_S) -#define CORE0_CORE0_UART1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART1_INT_MAP_S 0 - -/** CORE0_UART2_INT_MAP_REG register - * NA - */ -#define CORE0_UART2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x84) -/** CORE0_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART2_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART2_INT_MAP_M (CORE0_CORE0_UART2_INT_MAP_V << CORE0_CORE0_UART2_INT_MAP_S) -#define CORE0_CORE0_UART2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART2_INT_MAP_S 0 - -/** CORE0_UART3_INT_MAP_REG register - * NA - */ -#define CORE0_UART3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x88) -/** CORE0_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART3_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART3_INT_MAP_M (CORE0_CORE0_UART3_INT_MAP_V << CORE0_CORE0_UART3_INT_MAP_S) -#define CORE0_CORE0_UART3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART3_INT_MAP_S 0 - -/** CORE0_UART4_INT_MAP_REG register - * NA - */ -#define CORE0_UART4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8c) -/** CORE0_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART4_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART4_INT_MAP_M (CORE0_CORE0_UART4_INT_MAP_V << CORE0_CORE0_UART4_INT_MAP_S) -#define CORE0_CORE0_UART4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART4_INT_MAP_S 0 - -/** CORE0_LCD_CAM_INT_MAP_REG register - * NA - */ -#define CORE0_LCD_CAM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x90) -/** CORE0_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LCD_CAM_INT_MAP 0x0000003FU -#define CORE0_CORE0_LCD_CAM_INT_MAP_M (CORE0_CORE0_LCD_CAM_INT_MAP_V << CORE0_CORE0_LCD_CAM_INT_MAP_S) -#define CORE0_CORE0_LCD_CAM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LCD_CAM_INT_MAP_S 0 - -/** CORE0_ADC_INT_MAP_REG register - * NA - */ -#define CORE0_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x94) -/** CORE0_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ADC_INT_MAP 0x0000003FU -#define CORE0_CORE0_ADC_INT_MAP_M (CORE0_CORE0_ADC_INT_MAP_V << CORE0_CORE0_ADC_INT_MAP_S) -#define CORE0_CORE0_ADC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ADC_INT_MAP_S 0 - -/** CORE0_PWM0_INT_MAP_REG register - * NA - */ -#define CORE0_PWM0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x98) -/** CORE0_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PWM0_INT_MAP 0x0000003FU -#define CORE0_CORE0_PWM0_INT_MAP_M (CORE0_CORE0_PWM0_INT_MAP_V << CORE0_CORE0_PWM0_INT_MAP_S) -#define CORE0_CORE0_PWM0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PWM0_INT_MAP_S 0 - -/** CORE0_PWM1_INT_MAP_REG register - * NA - */ -#define CORE0_PWM1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x9c) -/** CORE0_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PWM1_INT_MAP 0x0000003FU -#define CORE0_CORE0_PWM1_INT_MAP_M (CORE0_CORE0_PWM1_INT_MAP_V << CORE0_CORE0_PWM1_INT_MAP_S) -#define CORE0_CORE0_PWM1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PWM1_INT_MAP_S 0 - -/** CORE0_CAN0_INT_MAP_REG register - * NA - */ -#define CORE0_CAN0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa0) -/** CORE0_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN0_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN0_INT_MAP_M (CORE0_CORE0_CAN0_INT_MAP_V << CORE0_CORE0_CAN0_INT_MAP_S) -#define CORE0_CORE0_CAN0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN0_INT_MAP_S 0 - -/** CORE0_CAN1_INT_MAP_REG register - * NA - */ -#define CORE0_CAN1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa4) -/** CORE0_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN1_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN1_INT_MAP_M (CORE0_CORE0_CAN1_INT_MAP_V << CORE0_CORE0_CAN1_INT_MAP_S) -#define CORE0_CORE0_CAN1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN1_INT_MAP_S 0 - -/** CORE0_CAN2_INT_MAP_REG register - * NA - */ -#define CORE0_CAN2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa8) -/** CORE0_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN2_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN2_INT_MAP_M (CORE0_CORE0_CAN2_INT_MAP_V << CORE0_CORE0_CAN2_INT_MAP_S) -#define CORE0_CORE0_CAN2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN2_INT_MAP_S 0 - -/** CORE0_RMT_INT_MAP_REG register - * NA - */ -#define CORE0_RMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xac) -/** CORE0_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_RMT_INT_MAP 0x0000003FU -#define CORE0_CORE0_RMT_INT_MAP_M (CORE0_CORE0_RMT_INT_MAP_V << CORE0_CORE0_RMT_INT_MAP_S) -#define CORE0_CORE0_RMT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_RMT_INT_MAP_S 0 - -/** CORE0_I2C0_INT_MAP_REG register - * NA - */ -#define CORE0_I2C0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb0) -/** CORE0_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2C0_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2C0_INT_MAP_M (CORE0_CORE0_I2C0_INT_MAP_V << CORE0_CORE0_I2C0_INT_MAP_S) -#define CORE0_CORE0_I2C0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2C0_INT_MAP_S 0 - -/** CORE0_I2C1_INT_MAP_REG register - * NA - */ -#define CORE0_I2C1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb4) -/** CORE0_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2C1_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2C1_INT_MAP_M (CORE0_CORE0_I2C1_INT_MAP_V << CORE0_CORE0_I2C1_INT_MAP_S) -#define CORE0_CORE0_I2C1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2C1_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_T0_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb8) -/** CORE0_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_M (CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_T1_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xbc) -/** CORE0_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_M (CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc0) -/** CORE0_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_M (CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_T0_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc4) -/** CORE0_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_M (CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_T1_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc8) -/** CORE0_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_M (CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xcc) -/** CORE0_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_M (CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S 0 - -/** CORE0_LEDC_INT_MAP_REG register - * NA - */ -#define CORE0_LEDC_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd0) -/** CORE0_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LEDC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LEDC_INT_MAP_M (CORE0_CORE0_LEDC_INT_MAP_V << CORE0_CORE0_LEDC_INT_MAP_S) -#define CORE0_CORE0_LEDC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LEDC_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET0_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd4) -/** CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET1_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd8) -/** CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET2_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xdc) -/** CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe0) -/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe4) -/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe8) -/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xec) -/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf0) -/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf4) -/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf8) -/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xfc) -/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x100) -/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x104) -/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x108) -/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10c) -/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE0_RSA_INT_MAP_REG register - * NA - */ -#define CORE0_RSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x110) -/** CORE0_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_RSA_INT_MAP 0x0000003FU -#define CORE0_CORE0_RSA_INT_MAP_M (CORE0_CORE0_RSA_INT_MAP_V << CORE0_CORE0_RSA_INT_MAP_S) -#define CORE0_CORE0_RSA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_RSA_INT_MAP_S 0 - -/** CORE0_AES_INT_MAP_REG register - * NA - */ -#define CORE0_AES_INT_MAP_REG (DR_REG_CORE0_BASE + 0x114) -/** CORE0_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AES_INT_MAP 0x0000003FU -#define CORE0_CORE0_AES_INT_MAP_M (CORE0_CORE0_AES_INT_MAP_V << CORE0_CORE0_AES_INT_MAP_S) -#define CORE0_CORE0_AES_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AES_INT_MAP_S 0 - -/** CORE0_SHA_INT_MAP_REG register - * NA - */ -#define CORE0_SHA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x118) -/** CORE0_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SHA_INT_MAP 0x0000003FU -#define CORE0_CORE0_SHA_INT_MAP_M (CORE0_CORE0_SHA_INT_MAP_V << CORE0_CORE0_SHA_INT_MAP_S) -#define CORE0_CORE0_SHA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SHA_INT_MAP_S 0 - -/** CORE0_ECC_INT_MAP_REG register - * NA - */ -#define CORE0_ECC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x11c) -/** CORE0_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ECC_INT_MAP 0x0000003FU -#define CORE0_CORE0_ECC_INT_MAP_M (CORE0_CORE0_ECC_INT_MAP_V << CORE0_CORE0_ECC_INT_MAP_S) -#define CORE0_CORE0_ECC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ECC_INT_MAP_S 0 - -/** CORE0_ECDSA_INT_MAP_REG register - * NA - */ -#define CORE0_ECDSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x120) -/** CORE0_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ECDSA_INT_MAP 0x0000003FU -#define CORE0_CORE0_ECDSA_INT_MAP_M (CORE0_CORE0_ECDSA_INT_MAP_V << CORE0_CORE0_ECDSA_INT_MAP_S) -#define CORE0_CORE0_ECDSA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ECDSA_INT_MAP_S 0 - -/** CORE0_KM_INT_MAP_REG register - * NA - */ -#define CORE0_KM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x124) -/** CORE0_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_KM_INT_MAP 0x0000003FU -#define CORE0_CORE0_KM_INT_MAP_M (CORE0_CORE0_KM_INT_MAP_V << CORE0_CORE0_KM_INT_MAP_S) -#define CORE0_CORE0_KM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_KM_INT_MAP_S 0 - -/** CORE0_GPIO_INT0_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT0_MAP_REG (DR_REG_CORE0_BASE + 0x128) -/** CORE0_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT0_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT0_MAP_M (CORE0_CORE0_GPIO_INT0_MAP_V << CORE0_CORE0_GPIO_INT0_MAP_S) -#define CORE0_CORE0_GPIO_INT0_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT0_MAP_S 0 - -/** CORE0_GPIO_INT1_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT1_MAP_REG (DR_REG_CORE0_BASE + 0x12c) -/** CORE0_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT1_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT1_MAP_M (CORE0_CORE0_GPIO_INT1_MAP_V << CORE0_CORE0_GPIO_INT1_MAP_S) -#define CORE0_CORE0_GPIO_INT1_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT1_MAP_S 0 - -/** CORE0_GPIO_INT2_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT2_MAP_REG (DR_REG_CORE0_BASE + 0x130) -/** CORE0_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT2_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT2_MAP_M (CORE0_CORE0_GPIO_INT2_MAP_V << CORE0_CORE0_GPIO_INT2_MAP_S) -#define CORE0_CORE0_GPIO_INT2_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT2_MAP_S 0 - -/** CORE0_GPIO_INT3_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT3_MAP_REG (DR_REG_CORE0_BASE + 0x134) -/** CORE0_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT3_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT3_MAP_M (CORE0_CORE0_GPIO_INT3_MAP_V << CORE0_CORE0_GPIO_INT3_MAP_S) -#define CORE0_CORE0_GPIO_INT3_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT3_MAP_S 0 - -/** CORE0_GPIO_PAD_COMP_INT_MAP_REG register - * NA - */ -#define CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x138) -/** CORE0_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_M (CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S) -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_0_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE0_BASE + 0x13c) -/** CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_1_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE0_BASE + 0x140) -/** CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_2_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE0_BASE + 0x144) -/** CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_3_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE0_BASE + 0x148) -/** CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S 0 - -/** CORE0_CACHE_INT_MAP_REG register - * NA - */ -#define CORE0_CACHE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14c) -/** CORE0_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CACHE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CACHE_INT_MAP_M (CORE0_CORE0_CACHE_INT_MAP_V << CORE0_CORE0_CACHE_INT_MAP_S) -#define CORE0_CORE0_CACHE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CACHE_INT_MAP_S 0 - -/** CORE0_FLASH_MSPI_INT_MAP_REG register - * NA - */ -#define CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x150) -/** CORE0_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_FLASH_MSPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_M (CORE0_CORE0_FLASH_MSPI_INT_MAP_V << CORE0_CORE0_FLASH_MSPI_INT_MAP_S) -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_S 0 - -/** CORE0_CSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x154) -/** CORE0_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_M (CORE0_CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CORE0_CSI_BRIDGE_INT_MAP_S) -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_S 0 - -/** CORE0_DSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x158) -/** CORE0_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_M (CORE0_CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_CORE0_DSI_BRIDGE_INT_MAP_S) -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_S 0 - -/** CORE0_CSI_INT_MAP_REG register - * NA - */ -#define CORE0_CSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x15c) -/** CORE0_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CSI_INT_MAP 0x0000003FU -#define CORE0_CORE0_CSI_INT_MAP_M (CORE0_CORE0_CSI_INT_MAP_V << CORE0_CORE0_CSI_INT_MAP_S) -#define CORE0_CORE0_CSI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CSI_INT_MAP_S 0 - -/** CORE0_DSI_INT_MAP_REG register - * NA - */ -#define CORE0_DSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x160) -/** CORE0_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DSI_INT_MAP 0x0000003FU -#define CORE0_CORE0_DSI_INT_MAP_M (CORE0_CORE0_DSI_INT_MAP_V << CORE0_CORE0_DSI_INT_MAP_S) -#define CORE0_CORE0_DSI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DSI_INT_MAP_S 0 - -/** CORE0_GMII_PHY_INT_MAP_REG register - * NA - */ -#define CORE0_GMII_PHY_INT_MAP_REG (DR_REG_CORE0_BASE + 0x164) -/** CORE0_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GMII_PHY_INT_MAP 0x0000003FU -#define CORE0_CORE0_GMII_PHY_INT_MAP_M (CORE0_CORE0_GMII_PHY_INT_MAP_V << CORE0_CORE0_GMII_PHY_INT_MAP_S) -#define CORE0_CORE0_GMII_PHY_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GMII_PHY_INT_MAP_S 0 - -/** CORE0_LPI_INT_MAP_REG register - * NA - */ -#define CORE0_LPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x168) -/** CORE0_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LPI_INT_MAP_M (CORE0_CORE0_LPI_INT_MAP_V << CORE0_CORE0_LPI_INT_MAP_S) -#define CORE0_CORE0_LPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LPI_INT_MAP_S 0 - -/** CORE0_PMT_INT_MAP_REG register - * NA - */ -#define CORE0_PMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x16c) -/** CORE0_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMT_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMT_INT_MAP_M (CORE0_CORE0_PMT_INT_MAP_V << CORE0_CORE0_PMT_INT_MAP_S) -#define CORE0_CORE0_PMT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMT_INT_MAP_S 0 - -/** CORE0_SBD_INT_MAP_REG register - * NA - */ -#define CORE0_SBD_INT_MAP_REG (DR_REG_CORE0_BASE + 0x170) -/** CORE0_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SBD_INT_MAP 0x0000003FU -#define CORE0_CORE0_SBD_INT_MAP_M (CORE0_CORE0_SBD_INT_MAP_V << CORE0_CORE0_SBD_INT_MAP_S) -#define CORE0_CORE0_SBD_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SBD_INT_MAP_S 0 - -/** CORE0_USB_OTG_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x174) -/** CORE0_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG_INT_MAP_M (CORE0_CORE0_USB_OTG_INT_MAP_V << CORE0_CORE0_USB_OTG_INT_MAP_S) -#define CORE0_CORE0_USB_OTG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG_INT_MAP_S 0 - -/** CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x178) -/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 - -/** CORE0_JPEG_INT_MAP_REG register - * NA - */ -#define CORE0_JPEG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x17c) -/** CORE0_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_JPEG_INT_MAP 0x0000003FU -#define CORE0_CORE0_JPEG_INT_MAP_M (CORE0_CORE0_JPEG_INT_MAP_V << CORE0_CORE0_JPEG_INT_MAP_S) -#define CORE0_CORE0_JPEG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_JPEG_INT_MAP_S 0 - -/** CORE0_PPA_INT_MAP_REG register - * NA - */ -#define CORE0_PPA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x180) -/** CORE0_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PPA_INT_MAP 0x0000003FU -#define CORE0_CORE0_PPA_INT_MAP_M (CORE0_CORE0_PPA_INT_MAP_V << CORE0_CORE0_PPA_INT_MAP_S) -#define CORE0_CORE0_PPA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PPA_INT_MAP_S 0 - -/** CORE0_CORE0_TRACE_INT_MAP_REG register - * NA - */ -#define CORE0_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x184) -/** CORE0_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CORE0_TRACE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_M (CORE0_CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_CORE0_TRACE_INT_MAP_S) -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_S 0 - -/** CORE0_CORE1_TRACE_INT_MAP_REG register - * NA - */ -#define CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x188) -/** CORE0_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CORE1_TRACE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_M (CORE0_CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE0_CORE1_TRACE_INT_MAP_S) -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_S 0 - -/** CORE0_HP_CORE_CTRL_INT_MAP_REG register - * NA - */ -#define CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18c) -/** CORE0_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_M (CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S) -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S 0 - -/** CORE0_ISP_INT_MAP_REG register - * NA - */ -#define CORE0_ISP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x190) -/** CORE0_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ISP_INT_MAP 0x0000003FU -#define CORE0_CORE0_ISP_INT_MAP_M (CORE0_CORE0_ISP_INT_MAP_V << CORE0_CORE0_ISP_INT_MAP_S) -#define CORE0_CORE0_ISP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ISP_INT_MAP_S 0 - -/** CORE0_I3C_MST_INT_MAP_REG register - * NA - */ -#define CORE0_I3C_MST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x194) -/** CORE0_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I3C_MST_INT_MAP 0x0000003FU -#define CORE0_CORE0_I3C_MST_INT_MAP_M (CORE0_CORE0_I3C_MST_INT_MAP_V << CORE0_CORE0_I3C_MST_INT_MAP_S) -#define CORE0_CORE0_I3C_MST_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I3C_MST_INT_MAP_S 0 - -/** CORE0_I3C_SLV_INT_MAP_REG register - * NA - */ -#define CORE0_I3C_SLV_INT_MAP_REG (DR_REG_CORE0_BASE + 0x198) -/** CORE0_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I3C_SLV_INT_MAP 0x0000003FU -#define CORE0_CORE0_I3C_SLV_INT_MAP_M (CORE0_CORE0_I3C_SLV_INT_MAP_V << CORE0_CORE0_I3C_SLV_INT_MAP_S) -#define CORE0_CORE0_I3C_SLV_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I3C_SLV_INT_MAP_S 0 - -/** CORE0_USB_OTG11_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG11_INT_MAP_REG (DR_REG_CORE0_BASE + 0x19c) -/** CORE0_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG11_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG11_INT_MAP_M (CORE0_CORE0_USB_OTG11_INT_MAP_V << CORE0_CORE0_USB_OTG11_INT_MAP_S) -#define CORE0_CORE0_USB_OTG11_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG11_INT_MAP_S 0 - -/** CORE0_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a0) -/** CORE0_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_M (CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE0_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a4) -/** CORE0_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_M (CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a8) -/** CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ac) -/** CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b0) -/** CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE0_PSRAM_MSPI_INT_MAP_REG register - * NA - */ -#define CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b4) -/** CORE0_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_M (CORE0_CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_CORE0_PSRAM_MSPI_INT_MAP_S) -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_S 0 - -/** CORE0_HP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b8) -/** CORE0_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_SYSREG_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_SYSREG_INT_MAP_M (CORE0_CORE0_HP_SYSREG_INT_MAP_V << CORE0_CORE0_HP_SYSREG_INT_MAP_S) -#define CORE0_CORE0_HP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_SYSREG_INT_MAP_S 0 - -/** CORE0_PCNT_INT_MAP_REG register - * NA - */ -#define CORE0_PCNT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1bc) -/** CORE0_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PCNT_INT_MAP 0x0000003FU -#define CORE0_CORE0_PCNT_INT_MAP_M (CORE0_CORE0_PCNT_INT_MAP_V << CORE0_CORE0_PCNT_INT_MAP_S) -#define CORE0_CORE0_PCNT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PCNT_INT_MAP_S 0 - -/** CORE0_HP_PAU_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PAU_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c0) -/** CORE0_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PAU_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PAU_INT_MAP_M (CORE0_CORE0_HP_PAU_INT_MAP_V << CORE0_CORE0_HP_PAU_INT_MAP_S) -#define CORE0_CORE0_HP_PAU_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PAU_INT_MAP_S 0 - -/** CORE0_HP_PARLIO_RX_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c4) -/** CORE0_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_M (CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S) -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S 0 - -/** CORE0_HP_PARLIO_TX_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c8) -/** CORE0_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_M (CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S) -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1cc) -/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d0) -/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d4) -/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d8) -/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1dc) -/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e0) -/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e4) -/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e8) -/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ec) -/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f0) -/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f4) -/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S 0 - -/** CORE0_H264_REG_INT_MAP_REG register - * NA - */ -#define CORE0_H264_REG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f8) -/** CORE0_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_REG_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_REG_INT_MAP_M (CORE0_CORE0_H264_REG_INT_MAP_V << CORE0_CORE0_H264_REG_INT_MAP_S) -#define CORE0_CORE0_H264_REG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_REG_INT_MAP_S 0 - -/** CORE0_ASSIST_DEBUG_INT_MAP_REG register - * NA - */ -#define CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1fc) -/** CORE0_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP 0x0000003FU -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_M (CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S) -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S 0 - -/** CORE0_INTR_STATUS_REG_0_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_0_REG (DR_REG_CORE0_BASE + 0x200) -/** CORE0_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_0 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_0_M (CORE0_CORE0_INTR_STATUS_0_V << CORE0_CORE0_INTR_STATUS_0_S) -#define CORE0_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_0_S 0 - -/** CORE0_INTR_STATUS_REG_1_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_1_REG (DR_REG_CORE0_BASE + 0x204) -/** CORE0_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_1 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_1_M (CORE0_CORE0_INTR_STATUS_1_V << CORE0_CORE0_INTR_STATUS_1_S) -#define CORE0_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_1_S 0 - -/** CORE0_INTR_STATUS_REG_2_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_2_REG (DR_REG_CORE0_BASE + 0x208) -/** CORE0_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_2 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_2_M (CORE0_CORE0_INTR_STATUS_2_V << CORE0_CORE0_INTR_STATUS_2_S) -#define CORE0_CORE0_INTR_STATUS_2_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_2_S 0 - -/** CORE0_INTR_STATUS_REG_3_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_3_REG (DR_REG_CORE0_BASE + 0x20c) -/** CORE0_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_3 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_3_M (CORE0_CORE0_INTR_STATUS_3_V << CORE0_CORE0_INTR_STATUS_3_S) -#define CORE0_CORE0_INTR_STATUS_3_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_3_S 0 - -/** CORE0_CLOCK_GATE_REG register - * NA - */ -#define CORE0_CLOCK_GATE_REG (DR_REG_CORE0_BASE + 0x210) -/** CORE0_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define CORE0_CORE0_REG_CLK_EN (BIT(0)) -#define CORE0_CORE0_REG_CLK_EN_M (CORE0_CORE0_REG_CLK_EN_V << CORE0_CORE0_REG_CLK_EN_S) -#define CORE0_CORE0_REG_CLK_EN_V 0x00000001U -#define CORE0_CORE0_REG_CLK_EN_S 0 - -/** CORE0_INTERRUPT_REG_DATE_REG register - * NA - */ -#define CORE0_INTERRUPT_REG_DATE_REG (DR_REG_CORE0_BASE + 0x3fc) -/** CORE0_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ -#define CORE0_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define CORE0_CORE0_INTERRUPT_REG_DATE_M (CORE0_CORE0_INTERRUPT_REG_DATE_V << CORE0_CORE0_INTERRUPT_REG_DATE_S) -#define CORE0_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define CORE0_CORE0_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h b/components/soc/esp32p4/include/soc/core0_interrupt_struct.h deleted file mode 100644 index 0fc7cf301c..0000000000 --- a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h +++ /dev/null @@ -1,2298 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: CORE0 LP RTC INT MAP REG */ -/** Type of lp_rtc_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_rtc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_rtc_int_map_reg_t; - - -/** Group: CORE0 LP WDT INT MAP REG */ -/** Type of lp_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_wdt_int_map_reg_t; - - -/** Group: CORE0 LP TIMER REG 0 INT MAP REG */ -/** Type of lp_timer_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_timer_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_timer_reg_0_int_map_reg_t; - - -/** Group: CORE0 LP TIMER REG 1 INT MAP REG */ -/** Type of lp_timer_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_timer_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_timer_reg_1_int_map_reg_t; - - -/** Group: CORE0 MB HP INT MAP REG */ -/** Type of mb_hp_int_map register - * NA - */ -typedef union { - struct { - /** core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_mb_hp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_mb_hp_int_map_reg_t; - - -/** Group: CORE0 MB LP INT MAP REG */ -/** Type of mb_lp_int_map register - * NA - */ -typedef union { - struct { - /** core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_mb_lp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_mb_lp_int_map_reg_t; - - -/** Group: CORE0 PMU REG 0 INT MAP REG */ -/** Type of pmu_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmu_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmu_reg_0_int_map_reg_t; - - -/** Group: CORE0 PMU REG 1 INT MAP REG */ -/** Type of pmu_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmu_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmu_reg_1_int_map_reg_t; - - -/** Group: CORE0 LP ANAPERI INT MAP REG */ -/** Type of lp_anaperi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_anaperi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_anaperi_int_map_reg_t; - - -/** Group: CORE0 LP ADC INT MAP REG */ -/** Type of lp_adc_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_adc_int_map_reg_t; - - -/** Group: CORE0 LP GPIO INT MAP REG */ -/** Type of lp_gpio_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_gpio_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_gpio_int_map_reg_t; - - -/** Group: CORE0 LP I2C INT MAP REG */ -/** Type of lp_i2c_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_i2c_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_i2c_int_map_reg_t; - - -/** Group: CORE0 LP I2S INT MAP REG */ -/** Type of lp_i2s_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_i2s_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_i2s_int_map_reg_t; - - -/** Group: CORE0 LP SPI INT MAP REG */ -/** Type of lp_spi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_spi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_spi_int_map_reg_t; - - -/** Group: CORE0 LP TOUCH INT MAP REG */ -/** Type of lp_touch_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_touch_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_touch_int_map_reg_t; - - -/** Group: CORE0 LP TSENS INT MAP REG */ -/** Type of lp_tsens_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_tsens_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_tsens_int_map_reg_t; - - -/** Group: CORE0 LP UART INT MAP REG */ -/** Type of lp_uart_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_uart_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_uart_int_map_reg_t; - - -/** Group: CORE0 LP EFUSE INT MAP REG */ -/** Type of lp_efuse_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_efuse_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_efuse_int_map_reg_t; - - -/** Group: CORE0 LP SW INT MAP REG */ -/** Type of lp_sw_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_sw_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_sw_int_map_reg_t; - - -/** Group: CORE0 LP SYSREG INT MAP REG */ -/** Type of lp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_sysreg_int_map_reg_t; - - -/** Group: CORE0 LP HUK INT MAP REG */ -/** Type of lp_huk_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_huk_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_huk_int_map_reg_t; - - -/** Group: CORE0 SYS ICM INT MAP REG */ -/** Type of sys_icm_int_map register - * NA - */ -typedef union { - struct { - /** core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sys_icm_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sys_icm_int_map_reg_t; - - -/** Group: CORE0 USB DEVICE INT MAP REG */ -/** Type of usb_device_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_device_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_device_int_map_reg_t; - - -/** Group: CORE0 SDIO HOST INT MAP REG */ -/** Type of sdio_host_int_map register - * NA - */ -typedef union { - struct { - /** core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sdio_host_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sdio_host_int_map_reg_t; - - -/** Group: CORE0 GDMA INT MAP REG */ -/** Type of gdma_int_map register - * NA - */ -typedef union { - struct { - /** core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gdma_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gdma_int_map_reg_t; - - -/** Group: CORE0 SPI2 INT MAP REG */ -/** Type of spi2_int_map register - * NA - */ -typedef union { - struct { - /** core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_spi2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_spi2_int_map_reg_t; - - -/** Group: CORE0 SPI3 INT MAP REG */ -/** Type of spi3_int_map register - * NA - */ -typedef union { - struct { - /** core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_spi3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_spi3_int_map_reg_t; - - -/** Group: CORE0 I2S0 INT MAP REG */ -/** Type of i2s0_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s0_int_map_reg_t; - - -/** Group: CORE0 I2S1 INT MAP REG */ -/** Type of i2s1_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s1_int_map_reg_t; - - -/** Group: CORE0 I2S2 INT MAP REG */ -/** Type of i2s2_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s2_int_map_reg_t; - - -/** Group: CORE0 UHCI0 INT MAP REG */ -/** Type of uhci0_int_map register - * NA - */ -typedef union { - struct { - /** core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uhci0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uhci0_int_map_reg_t; - - -/** Group: CORE0 UART0 INT MAP REG */ -/** Type of uart0_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart0_int_map_reg_t; - - -/** Group: CORE0 UART1 INT MAP REG */ -/** Type of uart1_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart1_int_map_reg_t; - - -/** Group: CORE0 UART2 INT MAP REG */ -/** Type of uart2_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart2_int_map_reg_t; - - -/** Group: CORE0 UART3 INT MAP REG */ -/** Type of uart3_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart3_int_map_reg_t; - - -/** Group: CORE0 UART4 INT MAP REG */ -/** Type of uart4_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart4_int_map_reg_t; - - -/** Group: CORE0 LCD CAM INT MAP REG */ -/** Type of lcd_cam_int_map register - * NA - */ -typedef union { - struct { - /** core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lcd_cam_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lcd_cam_int_map_reg_t; - - -/** Group: CORE0 ADC INT MAP REG */ -/** Type of adc_int_map register - * NA - */ -typedef union { - struct { - /** core0_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_adc_int_map_reg_t; - - -/** Group: CORE0 PWM0 INT MAP REG */ -/** Type of pwm0_int_map register - * NA - */ -typedef union { - struct { - /** core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pwm0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pwm0_int_map_reg_t; - - -/** Group: CORE0 PWM1 INT MAP REG */ -/** Type of pwm1_int_map register - * NA - */ -typedef union { - struct { - /** core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pwm1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pwm1_int_map_reg_t; - - -/** Group: CORE0 CAN0 INT MAP REG */ -/** Type of can0_int_map register - * NA - */ -typedef union { - struct { - /** core0_can0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can0_int_map_reg_t; - - -/** Group: CORE0 CAN1 INT MAP REG */ -/** Type of can1_int_map register - * NA - */ -typedef union { - struct { - /** core0_can1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can1_int_map_reg_t; - - -/** Group: CORE0 CAN2 INT MAP REG */ -/** Type of can2_int_map register - * NA - */ -typedef union { - struct { - /** core0_can2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can2_int_map_reg_t; - - -/** Group: CORE0 RMT INT MAP REG */ -/** Type of rmt_int_map register - * NA - */ -typedef union { - struct { - /** core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_rmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_rmt_int_map_reg_t; - - -/** Group: CORE0 I2C0 INT MAP REG */ -/** Type of i2c0_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2c0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2c0_int_map_reg_t; - - -/** Group: CORE0 I2C1 INT MAP REG */ -/** Type of i2c1_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2c1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2c1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 T0 INT MAP REG */ -/** Type of timergrp0_t0_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_t0_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 T1 INT MAP REG */ -/** Type of timergrp0_t1_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_t1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 WDT INT MAP REG */ -/** Type of timergrp0_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_wdt_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 T0 INT MAP REG */ -/** Type of timergrp1_t0_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_t0_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 T1 INT MAP REG */ -/** Type of timergrp1_t1_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_t1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 WDT INT MAP REG */ -/** Type of timergrp1_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_wdt_int_map_reg_t; - - -/** Group: CORE0 LEDC INT MAP REG */ -/** Type of ledc_int_map register - * NA - */ -typedef union { - struct { - /** core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ledc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ledc_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET0 INT MAP REG */ -/** Type of systimer_target0_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target0_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET1 INT MAP REG */ -/** Type of systimer_target1_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target1_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET2 INT MAP REG */ -/** Type of systimer_target2_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target2_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH0 INT MAP REG */ -/** Type of ahb_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH1 INT MAP REG */ -/** Type of ahb_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH2 INT MAP REG */ -/** Type of ahb_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH0 INT MAP REG */ -/** Type of ahb_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH1 INT MAP REG */ -/** Type of ahb_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH2 INT MAP REG */ -/** Type of ahb_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH0 INT MAP REG */ -/** Type of axi_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH1 INT MAP REG */ -/** Type of axi_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH2 INT MAP REG */ -/** Type of axi_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH0 INT MAP REG */ -/** Type of axi_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH1 INT MAP REG */ -/** Type of axi_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH2 INT MAP REG */ -/** Type of axi_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE0 RSA INT MAP REG */ -/** Type of rsa_int_map register - * NA - */ -typedef union { - struct { - /** core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_rsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_rsa_int_map_reg_t; - - -/** Group: CORE0 AES INT MAP REG */ -/** Type of aes_int_map register - * NA - */ -typedef union { - struct { - /** core0_aes_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_aes_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_aes_int_map_reg_t; - - -/** Group: CORE0 SHA INT MAP REG */ -/** Type of sha_int_map register - * NA - */ -typedef union { - struct { - /** core0_sha_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sha_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sha_int_map_reg_t; - - -/** Group: CORE0 ECC INT MAP REG */ -/** Type of ecc_int_map register - * NA - */ -typedef union { - struct { - /** core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ecc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ecc_int_map_reg_t; - - -/** Group: CORE0 ECDSA INT MAP REG */ -/** Type of ecdsa_int_map register - * NA - */ -typedef union { - struct { - /** core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ecdsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ecdsa_int_map_reg_t; - - -/** Group: CORE0 KM INT MAP REG */ -/** Type of km_int_map register - * NA - */ -typedef union { - struct { - /** core0_km_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_km_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_km_int_map_reg_t; - - -/** Group: CORE0 GPIO INT0 MAP REG */ -/** Type of gpio_int0_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int0_map_reg_t; - - -/** Group: CORE0 GPIO INT1 MAP REG */ -/** Type of gpio_int1_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int1_map_reg_t; - - -/** Group: CORE0 GPIO INT2 MAP REG */ -/** Type of gpio_int2_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int2_map_reg_t; - - -/** Group: CORE0 GPIO INT3 MAP REG */ -/** Type of gpio_int3_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int3_map_reg_t; - - -/** Group: CORE0 GPIO PAD COMP INT MAP REG */ -/** Type of gpio_pad_comp_int_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_pad_comp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_pad_comp_int_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 0 MAP REG */ -/** Type of cpu_int_from_cpu_0_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_0_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 1 MAP REG */ -/** Type of cpu_int_from_cpu_1_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_1_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 2 MAP REG */ -/** Type of cpu_int_from_cpu_2_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_2_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 3 MAP REG */ -/** Type of cpu_int_from_cpu_3_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_3_map_reg_t; - - -/** Group: CORE0 CACHE INT MAP REG */ -/** Type of cache_int_map register - * NA - */ -typedef union { - struct { - /** core0_cache_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cache_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cache_int_map_reg_t; - - -/** Group: CORE0 FLASH MSPI INT MAP REG */ -/** Type of flash_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_flash_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_flash_mspi_int_map_reg_t; - - -/** Group: CORE0 CSI BRIDGE INT MAP REG */ -/** Type of csi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_csi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_csi_bridge_int_map_reg_t; - - -/** Group: CORE0 DSI BRIDGE INT MAP REG */ -/** Type of dsi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dsi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dsi_bridge_int_map_reg_t; - - -/** Group: CORE0 CSI INT MAP REG */ -/** Type of csi_int_map register - * NA - */ -typedef union { - struct { - /** core0_csi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_csi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_csi_int_map_reg_t; - - -/** Group: CORE0 DSI INT MAP REG */ -/** Type of dsi_int_map register - * NA - */ -typedef union { - struct { - /** core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dsi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dsi_int_map_reg_t; - - -/** Group: CORE0 GMII PHY INT MAP REG */ -/** Type of gmii_phy_int_map register - * NA - */ -typedef union { - struct { - /** core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gmii_phy_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gmii_phy_int_map_reg_t; - - -/** Group: CORE0 LPI INT MAP REG */ -/** Type of lpi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lpi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lpi_int_map_reg_t; - - -/** Group: CORE0 PMT INT MAP REG */ -/** Type of pmt_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmt_int_map_reg_t; - - -/** Group: CORE0 SBD INT MAP REG */ -/** Type of sbd_int_map register - * NA - */ -typedef union { - struct { - /** core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sbd_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sbd_int_map_reg_t; - - -/** Group: CORE0 USB OTG INT MAP REG */ -/** Type of usb_otg_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg_int_map_reg_t; - - -/** Group: CORE0 USB OTG ENDP MULTI PROC INT MAP REG */ -/** Type of usb_otg_endp_multi_proc_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg_endp_multi_proc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg_endp_multi_proc_int_map_reg_t; - - -/** Group: CORE0 JPEG INT MAP REG */ -/** Type of jpeg_int_map register - * NA - */ -typedef union { - struct { - /** core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_jpeg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_jpeg_int_map_reg_t; - - -/** Group: CORE0 PPA INT MAP REG */ -/** Type of ppa_int_map register - * NA - */ -typedef union { - struct { - /** core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ppa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ppa_int_map_reg_t; - - -/** Group: CORE0 CORE0 TRACE INT MAP REG */ -/** Type of core0_trace_int_map register - * NA - */ -typedef union { - struct { - /** core0_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_core0_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_core0_trace_int_map_reg_t; - - -/** Group: CORE0 CORE1 TRACE INT MAP REG */ -/** Type of core1_trace_int_map register - * NA - */ -typedef union { - struct { - /** core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_core1_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_core1_trace_int_map_reg_t; - - -/** Group: CORE0 HP CORE CTRL INT MAP REG */ -/** Type of hp_core_ctrl_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_core_ctrl_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_core_ctrl_int_map_reg_t; - - -/** Group: CORE0 ISP INT MAP REG */ -/** Type of isp_int_map register - * NA - */ -typedef union { - struct { - /** core0_isp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_isp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_isp_int_map_reg_t; - - -/** Group: CORE0 I3C MST INT MAP REG */ -/** Type of i3c_mst_int_map register - * NA - */ -typedef union { - struct { - /** core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i3c_mst_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i3c_mst_int_map_reg_t; - - -/** Group: CORE0 I3C SLV INT MAP REG */ -/** Type of i3c_slv_int_map register - * NA - */ -typedef union { - struct { - /** core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i3c_slv_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i3c_slv_int_map_reg_t; - - -/** Group: CORE0 USB OTG11 INT MAP REG */ -/** Type of usb_otg11_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg11_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg11_int_map_reg_t; - - -/** Group: CORE0 DMA2D IN CH0 INT MAP REG */ -/** Type of dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE0 DMA2D IN CH1 INT MAP REG */ -/** Type of dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH0 INT MAP REG */ -/** Type of dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH1 INT MAP REG */ -/** Type of dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH2 INT MAP REG */ -/** Type of dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE0 PSRAM MSPI INT MAP REG */ -/** Type of psram_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_psram_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_psram_mspi_int_map_reg_t; - - -/** Group: CORE0 HP SYSREG INT MAP REG */ -/** Type of hp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_sysreg_int_map_reg_t; - - -/** Group: CORE0 PCNT INT MAP REG */ -/** Type of pcnt_int_map register - * NA - */ -typedef union { - struct { - /** core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pcnt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pcnt_int_map_reg_t; - - -/** Group: CORE0 HP PAU INT MAP REG */ -/** Type of hp_pau_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_pau_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_pau_int_map_reg_t; - - -/** Group: CORE0 HP PARLIO RX INT MAP REG */ -/** Type of hp_parlio_rx_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_parlio_rx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_parlio_rx_int_map_reg_t; - - -/** Group: CORE0 HP PARLIO TX INT MAP REG */ -/** Type of hp_parlio_tx_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_parlio_tx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_parlio_tx_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH0 INT MAP REG */ -/** Type of h264_dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH1 INT MAP REG */ -/** Type of h264_dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH2 INT MAP REG */ -/** Type of h264_dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH3 INT MAP REG */ -/** Type of h264_dma2d_out_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch3_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH4 INT MAP REG */ -/** Type of h264_dma2d_out_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch4_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH0 INT MAP REG */ -/** Type of h264_dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH1 INT MAP REG */ -/** Type of h264_dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH2 INT MAP REG */ -/** Type of h264_dma2d_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch2_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH3 INT MAP REG */ -/** Type of h264_dma2d_in_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch3_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH4 INT MAP REG */ -/** Type of h264_dma2d_in_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch4_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH5 INT MAP REG */ -/** Type of h264_dma2d_in_ch5_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch5_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch5_int_map_reg_t; - - -/** Group: CORE0 H264 REG INT MAP REG */ -/** Type of h264_reg_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_reg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_reg_int_map_reg_t; - - -/** Group: CORE0 ASSIST DEBUG INT MAP REG */ -/** Type of assist_debug_int_map register - * NA - */ -typedef union { - struct { - /** core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_assist_debug_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_assist_debug_int_map_reg_t; - - -/** Group: CORE0 INTR STATUS REG 0 REG */ -/** Type of intr_status_reg_0 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_0:32; - }; - uint32_t val; -} core0_intr_status_reg_0_reg_t; - - -/** Group: CORE0 INTR STATUS REG 1 REG */ -/** Type of intr_status_reg_1 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_1:32; - }; - uint32_t val; -} core0_intr_status_reg_1_reg_t; - - -/** Group: CORE0 INTR STATUS REG 2 REG */ -/** Type of intr_status_reg_2 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_2:32; - }; - uint32_t val; -} core0_intr_status_reg_2_reg_t; - - -/** Group: CORE0 INTR STATUS REG 3 REG */ -/** Type of intr_status_reg_3 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_3:32; - }; - uint32_t val; -} core0_intr_status_reg_3_reg_t; - - -/** Group: CORE0 CLOCK GATE REG */ -/** Type of clock_gate register - * NA - */ -typedef union { - struct { - /** core0_reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t core0_reg_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} core0_clock_gate_reg_t; - - -/** Group: CORE0 INTERRUPT REG DATE REG */ -/** Type of interrupt_reg_date register - * NA - */ -typedef union { - struct { - /** core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ - uint32_t core0_interrupt_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} core0_interrupt_reg_date_reg_t; - - -typedef struct { - volatile core0_lp_rtc_int_map_reg_t lp_rtc_int_map; - volatile core0_lp_wdt_int_map_reg_t lp_wdt_int_map; - volatile core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; - volatile core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; - volatile core0_mb_hp_int_map_reg_t mb_hp_int_map; - volatile core0_mb_lp_int_map_reg_t mb_lp_int_map; - volatile core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; - volatile core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; - volatile core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map; - volatile core0_lp_adc_int_map_reg_t lp_adc_int_map; - volatile core0_lp_gpio_int_map_reg_t lp_gpio_int_map; - volatile core0_lp_i2c_int_map_reg_t lp_i2c_int_map; - volatile core0_lp_i2s_int_map_reg_t lp_i2s_int_map; - volatile core0_lp_spi_int_map_reg_t lp_spi_int_map; - volatile core0_lp_touch_int_map_reg_t lp_touch_int_map; - volatile core0_lp_tsens_int_map_reg_t lp_tsens_int_map; - volatile core0_lp_uart_int_map_reg_t lp_uart_int_map; - volatile core0_lp_efuse_int_map_reg_t lp_efuse_int_map; - volatile core0_lp_sw_int_map_reg_t lp_sw_int_map; - volatile core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map; - volatile core0_lp_huk_int_map_reg_t lp_huk_int_map; - volatile core0_sys_icm_int_map_reg_t sys_icm_int_map; - volatile core0_usb_device_int_map_reg_t usb_device_int_map; - volatile core0_sdio_host_int_map_reg_t sdio_host_int_map; - volatile core0_gdma_int_map_reg_t gdma_int_map; - volatile core0_spi2_int_map_reg_t spi2_int_map; - volatile core0_spi3_int_map_reg_t spi3_int_map; - volatile core0_i2s0_int_map_reg_t i2s0_int_map; - volatile core0_i2s1_int_map_reg_t i2s1_int_map; - volatile core0_i2s2_int_map_reg_t i2s2_int_map; - volatile core0_uhci0_int_map_reg_t uhci0_int_map; - volatile core0_uart0_int_map_reg_t uart0_int_map; - volatile core0_uart1_int_map_reg_t uart1_int_map; - volatile core0_uart2_int_map_reg_t uart2_int_map; - volatile core0_uart3_int_map_reg_t uart3_int_map; - volatile core0_uart4_int_map_reg_t uart4_int_map; - volatile core0_lcd_cam_int_map_reg_t lcd_cam_int_map; - volatile core0_adc_int_map_reg_t adc_int_map; - volatile core0_pwm0_int_map_reg_t pwm0_int_map; - volatile core0_pwm1_int_map_reg_t pwm1_int_map; - volatile core0_can0_int_map_reg_t can0_int_map; - volatile core0_can1_int_map_reg_t can1_int_map; - volatile core0_can2_int_map_reg_t can2_int_map; - volatile core0_rmt_int_map_reg_t rmt_int_map; - volatile core0_i2c0_int_map_reg_t i2c0_int_map; - volatile core0_i2c1_int_map_reg_t i2c1_int_map; - volatile core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; - volatile core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; - volatile core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; - volatile core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; - volatile core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; - volatile core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; - volatile core0_ledc_int_map_reg_t ledc_int_map; - volatile core0_systimer_target0_int_map_reg_t systimer_target0_int_map; - volatile core0_systimer_target1_int_map_reg_t systimer_target1_int_map; - volatile core0_systimer_target2_int_map_reg_t systimer_target2_int_map; - volatile core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; - volatile core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; - volatile core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; - volatile core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; - volatile core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; - volatile core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; - volatile core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; - volatile core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; - volatile core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; - volatile core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; - volatile core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; - volatile core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; - volatile core0_rsa_int_map_reg_t rsa_int_map; - volatile core0_aes_int_map_reg_t aes_int_map; - volatile core0_sha_int_map_reg_t sha_int_map; - volatile core0_ecc_int_map_reg_t ecc_int_map; - volatile core0_ecdsa_int_map_reg_t ecdsa_int_map; - volatile core0_km_int_map_reg_t km_int_map; - volatile core0_gpio_int0_map_reg_t gpio_int0_map; - volatile core0_gpio_int1_map_reg_t gpio_int1_map; - volatile core0_gpio_int2_map_reg_t gpio_int2_map; - volatile core0_gpio_int3_map_reg_t gpio_int3_map; - volatile core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; - volatile core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; - volatile core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; - volatile core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; - volatile core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; - volatile core0_cache_int_map_reg_t cache_int_map; - volatile core0_flash_mspi_int_map_reg_t flash_mspi_int_map; - volatile core0_csi_bridge_int_map_reg_t csi_bridge_int_map; - volatile core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map; - volatile core0_csi_int_map_reg_t csi_int_map; - volatile core0_dsi_int_map_reg_t dsi_int_map; - volatile core0_gmii_phy_int_map_reg_t gmii_phy_int_map; - volatile core0_lpi_int_map_reg_t lpi_int_map; - volatile core0_pmt_int_map_reg_t pmt_int_map; - volatile core0_sbd_int_map_reg_t sbd_int_map; - volatile core0_usb_otg_int_map_reg_t usb_otg_int_map; - volatile core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; - volatile core0_jpeg_int_map_reg_t jpeg_int_map; - volatile core0_ppa_int_map_reg_t ppa_int_map; - volatile core0_core0_trace_int_map_reg_t core0_trace_int_map; - volatile core0_core1_trace_int_map_reg_t core1_trace_int_map; - volatile core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; - volatile core0_isp_int_map_reg_t isp_int_map; - volatile core0_i3c_mst_int_map_reg_t i3c_mst_int_map; - volatile core0_i3c_slv_int_map_reg_t i3c_slv_int_map; - volatile core0_usb_otg11_int_map_reg_t usb_otg11_int_map; - volatile core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; - volatile core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; - volatile core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; - volatile core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; - volatile core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; - volatile core0_psram_mspi_int_map_reg_t psram_mspi_int_map; - volatile core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map; - volatile core0_pcnt_int_map_reg_t pcnt_int_map; - volatile core0_hp_pau_int_map_reg_t hp_pau_int_map; - volatile core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; - volatile core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; - volatile core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; - volatile core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; - volatile core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; - volatile core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; - volatile core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; - volatile core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; - volatile core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; - volatile core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; - volatile core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; - volatile core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; - volatile core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; - volatile core0_h264_reg_int_map_reg_t h264_reg_int_map; - volatile core0_assist_debug_int_map_reg_t assist_debug_int_map; - volatile core0_intr_status_reg_0_reg_t intr_status_reg_0; - volatile core0_intr_status_reg_1_reg_t intr_status_reg_1; - volatile core0_intr_status_reg_2_reg_t intr_status_reg_2; - volatile core0_intr_status_reg_3_reg_t intr_status_reg_3; - volatile core0_clock_gate_reg_t clock_gate; - uint32_t reserved_214[122]; - volatile core0_interrupt_reg_date_reg_t interrupt_reg_date; -} core0_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(core0_dev_t) == 0x400, "Invalid size of core0_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h b/components/soc/esp32p4/include/soc/core1_interrupt_reg.h deleted file mode 100644 index f7a6bd5409..0000000000 --- a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h +++ /dev/null @@ -1,1624 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** CORE1_LP_RTC_INT_MAP_REG register - * NA - */ -#define CORE1_LP_RTC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x0) -/** CORE1_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_RTC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_RTC_INT_MAP_M (CORE1_CORE1_LP_RTC_INT_MAP_V << CORE1_CORE1_LP_RTC_INT_MAP_S) -#define CORE1_CORE1_LP_RTC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_RTC_INT_MAP_S 0 - -/** CORE1_LP_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_LP_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4) -/** CORE1_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_WDT_INT_MAP_M (CORE1_CORE1_LP_WDT_INT_MAP_V << CORE1_CORE1_LP_WDT_INT_MAP_S) -#define CORE1_CORE1_LP_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_WDT_INT_MAP_S 0 - -/** CORE1_LP_TIMER_REG_0_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8) -/** CORE1_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S) -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S 0 - -/** CORE1_LP_TIMER_REG_1_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc) -/** CORE1_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S) -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S 0 - -/** CORE1_MB_HP_INT_MAP_REG register - * NA - */ -#define CORE1_MB_HP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10) -/** CORE1_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_MB_HP_INT_MAP 0x0000003FU -#define CORE1_CORE1_MB_HP_INT_MAP_M (CORE1_CORE1_MB_HP_INT_MAP_V << CORE1_CORE1_MB_HP_INT_MAP_S) -#define CORE1_CORE1_MB_HP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_MB_HP_INT_MAP_S 0 - -/** CORE1_MB_LP_INT_MAP_REG register - * NA - */ -#define CORE1_MB_LP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14) -/** CORE1_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_MB_LP_INT_MAP 0x0000003FU -#define CORE1_CORE1_MB_LP_INT_MAP_M (CORE1_CORE1_MB_LP_INT_MAP_V << CORE1_CORE1_MB_LP_INT_MAP_S) -#define CORE1_CORE1_MB_LP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_MB_LP_INT_MAP_S 0 - -/** CORE1_PMU_REG_0_INT_MAP_REG register - * NA - */ -#define CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18) -/** CORE1_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMU_REG_0_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMU_REG_0_INT_MAP_M (CORE1_CORE1_PMU_REG_0_INT_MAP_V << CORE1_CORE1_PMU_REG_0_INT_MAP_S) -#define CORE1_CORE1_PMU_REG_0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMU_REG_0_INT_MAP_S 0 - -/** CORE1_PMU_REG_1_INT_MAP_REG register - * NA - */ -#define CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c) -/** CORE1_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMU_REG_1_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMU_REG_1_INT_MAP_M (CORE1_CORE1_PMU_REG_1_INT_MAP_V << CORE1_CORE1_PMU_REG_1_INT_MAP_S) -#define CORE1_CORE1_PMU_REG_1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMU_REG_1_INT_MAP_S 0 - -/** CORE1_LP_ANAPERI_INT_MAP_REG register - * NA - */ -#define CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x20) -/** CORE1_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_ANAPERI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_M (CORE1_CORE1_LP_ANAPERI_INT_MAP_V << CORE1_CORE1_LP_ANAPERI_INT_MAP_S) -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_S 0 - -/** CORE1_LP_ADC_INT_MAP_REG register - * NA - */ -#define CORE1_LP_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x24) -/** CORE1_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_ADC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_ADC_INT_MAP_M (CORE1_CORE1_LP_ADC_INT_MAP_V << CORE1_CORE1_LP_ADC_INT_MAP_S) -#define CORE1_CORE1_LP_ADC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_ADC_INT_MAP_S 0 - -/** CORE1_LP_GPIO_INT_MAP_REG register - * NA - */ -#define CORE1_LP_GPIO_INT_MAP_REG (DR_REG_CORE1_BASE + 0x28) -/** CORE1_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_GPIO_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_GPIO_INT_MAP_M (CORE1_CORE1_LP_GPIO_INT_MAP_V << CORE1_CORE1_LP_GPIO_INT_MAP_S) -#define CORE1_CORE1_LP_GPIO_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_GPIO_INT_MAP_S 0 - -/** CORE1_LP_I2C_INT_MAP_REG register - * NA - */ -#define CORE1_LP_I2C_INT_MAP_REG (DR_REG_CORE1_BASE + 0x2c) -/** CORE1_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_I2C_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_I2C_INT_MAP_M (CORE1_CORE1_LP_I2C_INT_MAP_V << CORE1_CORE1_LP_I2C_INT_MAP_S) -#define CORE1_CORE1_LP_I2C_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_I2C_INT_MAP_S 0 - -/** CORE1_LP_I2S_INT_MAP_REG register - * NA - */ -#define CORE1_LP_I2S_INT_MAP_REG (DR_REG_CORE1_BASE + 0x30) -/** CORE1_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_I2S_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_I2S_INT_MAP_M (CORE1_CORE1_LP_I2S_INT_MAP_V << CORE1_CORE1_LP_I2S_INT_MAP_S) -#define CORE1_CORE1_LP_I2S_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_I2S_INT_MAP_S 0 - -/** CORE1_LP_SPI_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x34) -/** CORE1_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SPI_INT_MAP_M (CORE1_CORE1_LP_SPI_INT_MAP_V << CORE1_CORE1_LP_SPI_INT_MAP_S) -#define CORE1_CORE1_LP_SPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SPI_INT_MAP_S 0 - -/** CORE1_LP_TOUCH_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_CORE1_BASE + 0x38) -/** CORE1_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TOUCH_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TOUCH_INT_MAP_M (CORE1_CORE1_LP_TOUCH_INT_MAP_V << CORE1_CORE1_LP_TOUCH_INT_MAP_S) -#define CORE1_CORE1_LP_TOUCH_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TOUCH_INT_MAP_S 0 - -/** CORE1_LP_TSENS_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TSENS_INT_MAP_REG (DR_REG_CORE1_BASE + 0x3c) -/** CORE1_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TSENS_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TSENS_INT_MAP_M (CORE1_CORE1_LP_TSENS_INT_MAP_V << CORE1_CORE1_LP_TSENS_INT_MAP_S) -#define CORE1_CORE1_LP_TSENS_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TSENS_INT_MAP_S 0 - -/** CORE1_LP_UART_INT_MAP_REG register - * NA - */ -#define CORE1_LP_UART_INT_MAP_REG (DR_REG_CORE1_BASE + 0x40) -/** CORE1_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_UART_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_UART_INT_MAP_M (CORE1_CORE1_LP_UART_INT_MAP_V << CORE1_CORE1_LP_UART_INT_MAP_S) -#define CORE1_CORE1_LP_UART_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_UART_INT_MAP_S 0 - -/** CORE1_LP_EFUSE_INT_MAP_REG register - * NA - */ -#define CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x44) -/** CORE1_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_EFUSE_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_EFUSE_INT_MAP_M (CORE1_CORE1_LP_EFUSE_INT_MAP_V << CORE1_CORE1_LP_EFUSE_INT_MAP_S) -#define CORE1_CORE1_LP_EFUSE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_EFUSE_INT_MAP_S 0 - -/** CORE1_LP_SW_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SW_INT_MAP_REG (DR_REG_CORE1_BASE + 0x48) -/** CORE1_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SW_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SW_INT_MAP_M (CORE1_CORE1_LP_SW_INT_MAP_V << CORE1_CORE1_LP_SW_INT_MAP_S) -#define CORE1_CORE1_LP_SW_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SW_INT_MAP_S 0 - -/** CORE1_LP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4c) -/** CORE1_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SYSREG_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SYSREG_INT_MAP_M (CORE1_CORE1_LP_SYSREG_INT_MAP_V << CORE1_CORE1_LP_SYSREG_INT_MAP_S) -#define CORE1_CORE1_LP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SYSREG_INT_MAP_S 0 - -/** CORE1_LP_HUK_INT_MAP_REG register - * NA - */ -#define CORE1_LP_HUK_INT_MAP_REG (DR_REG_CORE1_BASE + 0x50) -/** CORE1_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_HUK_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_HUK_INT_MAP_M (CORE1_CORE1_LP_HUK_INT_MAP_V << CORE1_CORE1_LP_HUK_INT_MAP_S) -#define CORE1_CORE1_LP_HUK_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_HUK_INT_MAP_S 0 - -/** CORE1_SYS_ICM_INT_MAP_REG register - * NA - */ -#define CORE1_SYS_ICM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x54) -/** CORE1_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYS_ICM_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYS_ICM_INT_MAP_M (CORE1_CORE1_SYS_ICM_INT_MAP_V << CORE1_CORE1_SYS_ICM_INT_MAP_S) -#define CORE1_CORE1_SYS_ICM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYS_ICM_INT_MAP_S 0 - -/** CORE1_USB_DEVICE_INT_MAP_REG register - * NA - */ -#define CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x58) -/** CORE1_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_DEVICE_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_DEVICE_INT_MAP_M (CORE1_CORE1_USB_DEVICE_INT_MAP_V << CORE1_CORE1_USB_DEVICE_INT_MAP_S) -#define CORE1_CORE1_USB_DEVICE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_DEVICE_INT_MAP_S 0 - -/** CORE1_SDIO_HOST_INT_MAP_REG register - * NA - */ -#define CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x5c) -/** CORE1_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SDIO_HOST_INT_MAP 0x0000003FU -#define CORE1_CORE1_SDIO_HOST_INT_MAP_M (CORE1_CORE1_SDIO_HOST_INT_MAP_V << CORE1_CORE1_SDIO_HOST_INT_MAP_S) -#define CORE1_CORE1_SDIO_HOST_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SDIO_HOST_INT_MAP_S 0 - -/** CORE1_GDMA_INT_MAP_REG register - * NA - */ -#define CORE1_GDMA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x60) -/** CORE1_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GDMA_INT_MAP 0x0000003FU -#define CORE1_CORE1_GDMA_INT_MAP_M (CORE1_CORE1_GDMA_INT_MAP_V << CORE1_CORE1_GDMA_INT_MAP_S) -#define CORE1_CORE1_GDMA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GDMA_INT_MAP_S 0 - -/** CORE1_SPI2_INT_MAP_REG register - * NA - */ -#define CORE1_SPI2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x64) -/** CORE1_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SPI2_INT_MAP 0x0000003FU -#define CORE1_CORE1_SPI2_INT_MAP_M (CORE1_CORE1_SPI2_INT_MAP_V << CORE1_CORE1_SPI2_INT_MAP_S) -#define CORE1_CORE1_SPI2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SPI2_INT_MAP_S 0 - -/** CORE1_SPI3_INT_MAP_REG register - * NA - */ -#define CORE1_SPI3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x68) -/** CORE1_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SPI3_INT_MAP 0x0000003FU -#define CORE1_CORE1_SPI3_INT_MAP_M (CORE1_CORE1_SPI3_INT_MAP_V << CORE1_CORE1_SPI3_INT_MAP_S) -#define CORE1_CORE1_SPI3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SPI3_INT_MAP_S 0 - -/** CORE1_I2S0_INT_MAP_REG register - * NA - */ -#define CORE1_I2S0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x6c) -/** CORE1_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S0_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S0_INT_MAP_M (CORE1_CORE1_I2S0_INT_MAP_V << CORE1_CORE1_I2S0_INT_MAP_S) -#define CORE1_CORE1_I2S0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S0_INT_MAP_S 0 - -/** CORE1_I2S1_INT_MAP_REG register - * NA - */ -#define CORE1_I2S1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x70) -/** CORE1_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S1_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S1_INT_MAP_M (CORE1_CORE1_I2S1_INT_MAP_V << CORE1_CORE1_I2S1_INT_MAP_S) -#define CORE1_CORE1_I2S1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S1_INT_MAP_S 0 - -/** CORE1_I2S2_INT_MAP_REG register - * NA - */ -#define CORE1_I2S2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x74) -/** CORE1_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S2_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S2_INT_MAP_M (CORE1_CORE1_I2S2_INT_MAP_V << CORE1_CORE1_I2S2_INT_MAP_S) -#define CORE1_CORE1_I2S2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S2_INT_MAP_S 0 - -/** CORE1_UHCI0_INT_MAP_REG register - * NA - */ -#define CORE1_UHCI0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x78) -/** CORE1_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UHCI0_INT_MAP 0x0000003FU -#define CORE1_CORE1_UHCI0_INT_MAP_M (CORE1_CORE1_UHCI0_INT_MAP_V << CORE1_CORE1_UHCI0_INT_MAP_S) -#define CORE1_CORE1_UHCI0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UHCI0_INT_MAP_S 0 - -/** CORE1_UART0_INT_MAP_REG register - * NA - */ -#define CORE1_UART0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x7c) -/** CORE1_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART0_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART0_INT_MAP_M (CORE1_CORE1_UART0_INT_MAP_V << CORE1_CORE1_UART0_INT_MAP_S) -#define CORE1_CORE1_UART0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART0_INT_MAP_S 0 - -/** CORE1_UART1_INT_MAP_REG register - * NA - */ -#define CORE1_UART1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x80) -/** CORE1_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART1_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART1_INT_MAP_M (CORE1_CORE1_UART1_INT_MAP_V << CORE1_CORE1_UART1_INT_MAP_S) -#define CORE1_CORE1_UART1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART1_INT_MAP_S 0 - -/** CORE1_UART2_INT_MAP_REG register - * NA - */ -#define CORE1_UART2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x84) -/** CORE1_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART2_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART2_INT_MAP_M (CORE1_CORE1_UART2_INT_MAP_V << CORE1_CORE1_UART2_INT_MAP_S) -#define CORE1_CORE1_UART2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART2_INT_MAP_S 0 - -/** CORE1_UART3_INT_MAP_REG register - * NA - */ -#define CORE1_UART3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x88) -/** CORE1_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART3_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART3_INT_MAP_M (CORE1_CORE1_UART3_INT_MAP_V << CORE1_CORE1_UART3_INT_MAP_S) -#define CORE1_CORE1_UART3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART3_INT_MAP_S 0 - -/** CORE1_UART4_INT_MAP_REG register - * NA - */ -#define CORE1_UART4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8c) -/** CORE1_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART4_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART4_INT_MAP_M (CORE1_CORE1_UART4_INT_MAP_V << CORE1_CORE1_UART4_INT_MAP_S) -#define CORE1_CORE1_UART4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART4_INT_MAP_S 0 - -/** CORE1_LCD_CAM_INT_MAP_REG register - * NA - */ -#define CORE1_LCD_CAM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x90) -/** CORE1_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LCD_CAM_INT_MAP 0x0000003FU -#define CORE1_CORE1_LCD_CAM_INT_MAP_M (CORE1_CORE1_LCD_CAM_INT_MAP_V << CORE1_CORE1_LCD_CAM_INT_MAP_S) -#define CORE1_CORE1_LCD_CAM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LCD_CAM_INT_MAP_S 0 - -/** CORE1_ADC_INT_MAP_REG register - * NA - */ -#define CORE1_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x94) -/** CORE1_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ADC_INT_MAP 0x0000003FU -#define CORE1_CORE1_ADC_INT_MAP_M (CORE1_CORE1_ADC_INT_MAP_V << CORE1_CORE1_ADC_INT_MAP_S) -#define CORE1_CORE1_ADC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ADC_INT_MAP_S 0 - -/** CORE1_PWM0_INT_MAP_REG register - * NA - */ -#define CORE1_PWM0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x98) -/** CORE1_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PWM0_INT_MAP 0x0000003FU -#define CORE1_CORE1_PWM0_INT_MAP_M (CORE1_CORE1_PWM0_INT_MAP_V << CORE1_CORE1_PWM0_INT_MAP_S) -#define CORE1_CORE1_PWM0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PWM0_INT_MAP_S 0 - -/** CORE1_PWM1_INT_MAP_REG register - * NA - */ -#define CORE1_PWM1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x9c) -/** CORE1_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PWM1_INT_MAP 0x0000003FU -#define CORE1_CORE1_PWM1_INT_MAP_M (CORE1_CORE1_PWM1_INT_MAP_V << CORE1_CORE1_PWM1_INT_MAP_S) -#define CORE1_CORE1_PWM1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PWM1_INT_MAP_S 0 - -/** CORE1_CAN0_INT_MAP_REG register - * NA - */ -#define CORE1_CAN0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa0) -/** CORE1_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN0_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN0_INT_MAP_M (CORE1_CORE1_CAN0_INT_MAP_V << CORE1_CORE1_CAN0_INT_MAP_S) -#define CORE1_CORE1_CAN0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN0_INT_MAP_S 0 - -/** CORE1_CAN1_INT_MAP_REG register - * NA - */ -#define CORE1_CAN1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa4) -/** CORE1_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN1_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN1_INT_MAP_M (CORE1_CORE1_CAN1_INT_MAP_V << CORE1_CORE1_CAN1_INT_MAP_S) -#define CORE1_CORE1_CAN1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN1_INT_MAP_S 0 - -/** CORE1_CAN2_INT_MAP_REG register - * NA - */ -#define CORE1_CAN2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa8) -/** CORE1_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN2_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN2_INT_MAP_M (CORE1_CORE1_CAN2_INT_MAP_V << CORE1_CORE1_CAN2_INT_MAP_S) -#define CORE1_CORE1_CAN2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN2_INT_MAP_S 0 - -/** CORE1_RMT_INT_MAP_REG register - * NA - */ -#define CORE1_RMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xac) -/** CORE1_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_RMT_INT_MAP 0x0000003FU -#define CORE1_CORE1_RMT_INT_MAP_M (CORE1_CORE1_RMT_INT_MAP_V << CORE1_CORE1_RMT_INT_MAP_S) -#define CORE1_CORE1_RMT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_RMT_INT_MAP_S 0 - -/** CORE1_I2C0_INT_MAP_REG register - * NA - */ -#define CORE1_I2C0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb0) -/** CORE1_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2C0_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2C0_INT_MAP_M (CORE1_CORE1_I2C0_INT_MAP_V << CORE1_CORE1_I2C0_INT_MAP_S) -#define CORE1_CORE1_I2C0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2C0_INT_MAP_S 0 - -/** CORE1_I2C1_INT_MAP_REG register - * NA - */ -#define CORE1_I2C1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb4) -/** CORE1_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2C1_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2C1_INT_MAP_M (CORE1_CORE1_I2C1_INT_MAP_V << CORE1_CORE1_I2C1_INT_MAP_S) -#define CORE1_CORE1_I2C1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2C1_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_T0_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb8) -/** CORE1_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_T1_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xbc) -/** CORE1_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc0) -/** CORE1_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_T0_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc4) -/** CORE1_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_T1_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc8) -/** CORE1_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xcc) -/** CORE1_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S 0 - -/** CORE1_LEDC_INT_MAP_REG register - * NA - */ -#define CORE1_LEDC_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd0) -/** CORE1_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LEDC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LEDC_INT_MAP_M (CORE1_CORE1_LEDC_INT_MAP_V << CORE1_CORE1_LEDC_INT_MAP_S) -#define CORE1_CORE1_LEDC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LEDC_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET0_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd4) -/** CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET1_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd8) -/** CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET2_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xdc) -/** CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe0) -/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe4) -/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe8) -/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xec) -/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf0) -/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf4) -/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf8) -/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xfc) -/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x100) -/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x104) -/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x108) -/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10c) -/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE1_RSA_INT_MAP_REG register - * NA - */ -#define CORE1_RSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x110) -/** CORE1_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_RSA_INT_MAP 0x0000003FU -#define CORE1_CORE1_RSA_INT_MAP_M (CORE1_CORE1_RSA_INT_MAP_V << CORE1_CORE1_RSA_INT_MAP_S) -#define CORE1_CORE1_RSA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_RSA_INT_MAP_S 0 - -/** CORE1_AES_INT_MAP_REG register - * NA - */ -#define CORE1_AES_INT_MAP_REG (DR_REG_CORE1_BASE + 0x114) -/** CORE1_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AES_INT_MAP 0x0000003FU -#define CORE1_CORE1_AES_INT_MAP_M (CORE1_CORE1_AES_INT_MAP_V << CORE1_CORE1_AES_INT_MAP_S) -#define CORE1_CORE1_AES_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AES_INT_MAP_S 0 - -/** CORE1_SHA_INT_MAP_REG register - * NA - */ -#define CORE1_SHA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x118) -/** CORE1_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SHA_INT_MAP 0x0000003FU -#define CORE1_CORE1_SHA_INT_MAP_M (CORE1_CORE1_SHA_INT_MAP_V << CORE1_CORE1_SHA_INT_MAP_S) -#define CORE1_CORE1_SHA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SHA_INT_MAP_S 0 - -/** CORE1_ECC_INT_MAP_REG register - * NA - */ -#define CORE1_ECC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x11c) -/** CORE1_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ECC_INT_MAP 0x0000003FU -#define CORE1_CORE1_ECC_INT_MAP_M (CORE1_CORE1_ECC_INT_MAP_V << CORE1_CORE1_ECC_INT_MAP_S) -#define CORE1_CORE1_ECC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ECC_INT_MAP_S 0 - -/** CORE1_ECDSA_INT_MAP_REG register - * NA - */ -#define CORE1_ECDSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x120) -/** CORE1_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ECDSA_INT_MAP 0x0000003FU -#define CORE1_CORE1_ECDSA_INT_MAP_M (CORE1_CORE1_ECDSA_INT_MAP_V << CORE1_CORE1_ECDSA_INT_MAP_S) -#define CORE1_CORE1_ECDSA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ECDSA_INT_MAP_S 0 - -/** CORE1_KM_INT_MAP_REG register - * NA - */ -#define CORE1_KM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x124) -/** CORE1_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_KM_INT_MAP 0x0000003FU -#define CORE1_CORE1_KM_INT_MAP_M (CORE1_CORE1_KM_INT_MAP_V << CORE1_CORE1_KM_INT_MAP_S) -#define CORE1_CORE1_KM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_KM_INT_MAP_S 0 - -/** CORE1_GPIO_INT0_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT0_MAP_REG (DR_REG_CORE1_BASE + 0x128) -/** CORE1_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT0_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT0_MAP_M (CORE1_CORE1_GPIO_INT0_MAP_V << CORE1_CORE1_GPIO_INT0_MAP_S) -#define CORE1_CORE1_GPIO_INT0_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT0_MAP_S 0 - -/** CORE1_GPIO_INT1_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT1_MAP_REG (DR_REG_CORE1_BASE + 0x12c) -/** CORE1_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT1_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT1_MAP_M (CORE1_CORE1_GPIO_INT1_MAP_V << CORE1_CORE1_GPIO_INT1_MAP_S) -#define CORE1_CORE1_GPIO_INT1_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT1_MAP_S 0 - -/** CORE1_GPIO_INT2_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT2_MAP_REG (DR_REG_CORE1_BASE + 0x130) -/** CORE1_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT2_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT2_MAP_M (CORE1_CORE1_GPIO_INT2_MAP_V << CORE1_CORE1_GPIO_INT2_MAP_S) -#define CORE1_CORE1_GPIO_INT2_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT2_MAP_S 0 - -/** CORE1_GPIO_INT3_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT3_MAP_REG (DR_REG_CORE1_BASE + 0x134) -/** CORE1_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT3_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT3_MAP_M (CORE1_CORE1_GPIO_INT3_MAP_V << CORE1_CORE1_GPIO_INT3_MAP_S) -#define CORE1_CORE1_GPIO_INT3_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT3_MAP_S 0 - -/** CORE1_GPIO_PAD_COMP_INT_MAP_REG register - * NA - */ -#define CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x138) -/** CORE1_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_M (CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V << CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S) -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_0_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE1_BASE + 0x13c) -/** CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_1_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE1_BASE + 0x140) -/** CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_2_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE1_BASE + 0x144) -/** CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_3_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE1_BASE + 0x148) -/** CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S 0 - -/** CORE1_CACHE_INT_MAP_REG register - * NA - */ -#define CORE1_CACHE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14c) -/** CORE1_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CACHE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CACHE_INT_MAP_M (CORE1_CORE1_CACHE_INT_MAP_V << CORE1_CORE1_CACHE_INT_MAP_S) -#define CORE1_CORE1_CACHE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CACHE_INT_MAP_S 0 - -/** CORE1_FLASH_MSPI_INT_MAP_REG register - * NA - */ -#define CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x150) -/** CORE1_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_FLASH_MSPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_M (CORE1_CORE1_FLASH_MSPI_INT_MAP_V << CORE1_CORE1_FLASH_MSPI_INT_MAP_S) -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_S 0 - -/** CORE1_CSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x154) -/** CORE1_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_M (CORE1_CORE1_CSI_BRIDGE_INT_MAP_V << CORE1_CORE1_CSI_BRIDGE_INT_MAP_S) -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_S 0 - -/** CORE1_DSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x158) -/** CORE1_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_M (CORE1_CORE1_DSI_BRIDGE_INT_MAP_V << CORE1_CORE1_DSI_BRIDGE_INT_MAP_S) -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_S 0 - -/** CORE1_CSI_INT_MAP_REG register - * NA - */ -#define CORE1_CSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x15c) -/** CORE1_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CSI_INT_MAP 0x0000003FU -#define CORE1_CORE1_CSI_INT_MAP_M (CORE1_CORE1_CSI_INT_MAP_V << CORE1_CORE1_CSI_INT_MAP_S) -#define CORE1_CORE1_CSI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CSI_INT_MAP_S 0 - -/** CORE1_DSI_INT_MAP_REG register - * NA - */ -#define CORE1_DSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x160) -/** CORE1_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DSI_INT_MAP 0x0000003FU -#define CORE1_CORE1_DSI_INT_MAP_M (CORE1_CORE1_DSI_INT_MAP_V << CORE1_CORE1_DSI_INT_MAP_S) -#define CORE1_CORE1_DSI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DSI_INT_MAP_S 0 - -/** CORE1_GMII_PHY_INT_MAP_REG register - * NA - */ -#define CORE1_GMII_PHY_INT_MAP_REG (DR_REG_CORE1_BASE + 0x164) -/** CORE1_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GMII_PHY_INT_MAP 0x0000003FU -#define CORE1_CORE1_GMII_PHY_INT_MAP_M (CORE1_CORE1_GMII_PHY_INT_MAP_V << CORE1_CORE1_GMII_PHY_INT_MAP_S) -#define CORE1_CORE1_GMII_PHY_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GMII_PHY_INT_MAP_S 0 - -/** CORE1_LPI_INT_MAP_REG register - * NA - */ -#define CORE1_LPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x168) -/** CORE1_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LPI_INT_MAP_M (CORE1_CORE1_LPI_INT_MAP_V << CORE1_CORE1_LPI_INT_MAP_S) -#define CORE1_CORE1_LPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LPI_INT_MAP_S 0 - -/** CORE1_PMT_INT_MAP_REG register - * NA - */ -#define CORE1_PMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x16c) -/** CORE1_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMT_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMT_INT_MAP_M (CORE1_CORE1_PMT_INT_MAP_V << CORE1_CORE1_PMT_INT_MAP_S) -#define CORE1_CORE1_PMT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMT_INT_MAP_S 0 - -/** CORE1_SBD_INT_MAP_REG register - * NA - */ -#define CORE1_SBD_INT_MAP_REG (DR_REG_CORE1_BASE + 0x170) -/** CORE1_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SBD_INT_MAP 0x0000003FU -#define CORE1_CORE1_SBD_INT_MAP_M (CORE1_CORE1_SBD_INT_MAP_V << CORE1_CORE1_SBD_INT_MAP_S) -#define CORE1_CORE1_SBD_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SBD_INT_MAP_S 0 - -/** CORE1_USB_OTG_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x174) -/** CORE1_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG_INT_MAP_M (CORE1_CORE1_USB_OTG_INT_MAP_V << CORE1_CORE1_USB_OTG_INT_MAP_S) -#define CORE1_CORE1_USB_OTG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG_INT_MAP_S 0 - -/** CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x178) -/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 - -/** CORE1_JPEG_INT_MAP_REG register - * NA - */ -#define CORE1_JPEG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x17c) -/** CORE1_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_JPEG_INT_MAP 0x0000003FU -#define CORE1_CORE1_JPEG_INT_MAP_M (CORE1_CORE1_JPEG_INT_MAP_V << CORE1_CORE1_JPEG_INT_MAP_S) -#define CORE1_CORE1_JPEG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_JPEG_INT_MAP_S 0 - -/** CORE1_PPA_INT_MAP_REG register - * NA - */ -#define CORE1_PPA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x180) -/** CORE1_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PPA_INT_MAP 0x0000003FU -#define CORE1_CORE1_PPA_INT_MAP_M (CORE1_CORE1_PPA_INT_MAP_V << CORE1_CORE1_PPA_INT_MAP_S) -#define CORE1_CORE1_PPA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PPA_INT_MAP_S 0 - -/** CORE1_CORE0_TRACE_INT_MAP_REG register - * NA - */ -#define CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x184) -/** CORE1_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CORE0_TRACE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_M (CORE1_CORE1_CORE0_TRACE_INT_MAP_V << CORE1_CORE1_CORE0_TRACE_INT_MAP_S) -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_S 0 - -/** CORE1_CORE1_TRACE_INT_MAP_REG register - * NA - */ -#define CORE1_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x188) -/** CORE1_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CORE1_TRACE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_M (CORE1_CORE1_CORE1_TRACE_INT_MAP_V << CORE1_CORE1_CORE1_TRACE_INT_MAP_S) -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_S 0 - -/** CORE1_HP_CORE_CTRL_INT_MAP_REG register - * NA - */ -#define CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18c) -/** CORE1_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_M (CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V << CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S) -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S 0 - -/** CORE1_ISP_INT_MAP_REG register - * NA - */ -#define CORE1_ISP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x190) -/** CORE1_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ISP_INT_MAP 0x0000003FU -#define CORE1_CORE1_ISP_INT_MAP_M (CORE1_CORE1_ISP_INT_MAP_V << CORE1_CORE1_ISP_INT_MAP_S) -#define CORE1_CORE1_ISP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ISP_INT_MAP_S 0 - -/** CORE1_I3C_MST_INT_MAP_REG register - * NA - */ -#define CORE1_I3C_MST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x194) -/** CORE1_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I3C_MST_INT_MAP 0x0000003FU -#define CORE1_CORE1_I3C_MST_INT_MAP_M (CORE1_CORE1_I3C_MST_INT_MAP_V << CORE1_CORE1_I3C_MST_INT_MAP_S) -#define CORE1_CORE1_I3C_MST_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I3C_MST_INT_MAP_S 0 - -/** CORE1_I3C_SLV_INT_MAP_REG register - * NA - */ -#define CORE1_I3C_SLV_INT_MAP_REG (DR_REG_CORE1_BASE + 0x198) -/** CORE1_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I3C_SLV_INT_MAP 0x0000003FU -#define CORE1_CORE1_I3C_SLV_INT_MAP_M (CORE1_CORE1_I3C_SLV_INT_MAP_V << CORE1_CORE1_I3C_SLV_INT_MAP_S) -#define CORE1_CORE1_I3C_SLV_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I3C_SLV_INT_MAP_S 0 - -/** CORE1_USB_OTG11_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG11_INT_MAP_REG (DR_REG_CORE1_BASE + 0x19c) -/** CORE1_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG11_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG11_INT_MAP_M (CORE1_CORE1_USB_OTG11_INT_MAP_V << CORE1_CORE1_USB_OTG11_INT_MAP_S) -#define CORE1_CORE1_USB_OTG11_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG11_INT_MAP_S 0 - -/** CORE1_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a0) -/** CORE1_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE1_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a4) -/** CORE1_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a8) -/** CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ac) -/** CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b0) -/** CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE1_PSRAM_MSPI_INT_MAP_REG register - * NA - */ -#define CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b4) -/** CORE1_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_M (CORE1_CORE1_PSRAM_MSPI_INT_MAP_V << CORE1_CORE1_PSRAM_MSPI_INT_MAP_S) -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_S 0 - -/** CORE1_HP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b8) -/** CORE1_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_SYSREG_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_SYSREG_INT_MAP_M (CORE1_CORE1_HP_SYSREG_INT_MAP_V << CORE1_CORE1_HP_SYSREG_INT_MAP_S) -#define CORE1_CORE1_HP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_SYSREG_INT_MAP_S 0 - -/** CORE1_PCNT_INT_MAP_REG register - * NA - */ -#define CORE1_PCNT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1bc) -/** CORE1_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PCNT_INT_MAP 0x0000003FU -#define CORE1_CORE1_PCNT_INT_MAP_M (CORE1_CORE1_PCNT_INT_MAP_V << CORE1_CORE1_PCNT_INT_MAP_S) -#define CORE1_CORE1_PCNT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PCNT_INT_MAP_S 0 - -/** CORE1_HP_PAU_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PAU_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c0) -/** CORE1_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PAU_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PAU_INT_MAP_M (CORE1_CORE1_HP_PAU_INT_MAP_V << CORE1_CORE1_HP_PAU_INT_MAP_S) -#define CORE1_CORE1_HP_PAU_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PAU_INT_MAP_S 0 - -/** CORE1_HP_PARLIO_RX_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c4) -/** CORE1_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S) -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S 0 - -/** CORE1_HP_PARLIO_TX_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c8) -/** CORE1_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S) -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1cc) -/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d0) -/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d4) -/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d8) -/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1dc) -/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e0) -/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e4) -/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e8) -/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ec) -/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f0) -/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f4) -/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S 0 - -/** CORE1_H264_REG_INT_MAP_REG register - * NA - */ -#define CORE1_H264_REG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f8) -/** CORE1_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_REG_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_REG_INT_MAP_M (CORE1_CORE1_H264_REG_INT_MAP_V << CORE1_CORE1_H264_REG_INT_MAP_S) -#define CORE1_CORE1_H264_REG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_REG_INT_MAP_S 0 - -/** CORE1_ASSIST_DEBUG_INT_MAP_REG register - * NA - */ -#define CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1fc) -/** CORE1_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003FU -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_M (CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V << CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S) -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S 0 - -/** CORE1_INTR_STATUS_REG_0_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_0_REG (DR_REG_CORE1_BASE + 0x200) -/** CORE1_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_0 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_0_M (CORE1_CORE1_INTR_STATUS_0_V << CORE1_CORE1_INTR_STATUS_0_S) -#define CORE1_CORE1_INTR_STATUS_0_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_0_S 0 - -/** CORE1_INTR_STATUS_REG_1_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_1_REG (DR_REG_CORE1_BASE + 0x204) -/** CORE1_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_1 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_1_M (CORE1_CORE1_INTR_STATUS_1_V << CORE1_CORE1_INTR_STATUS_1_S) -#define CORE1_CORE1_INTR_STATUS_1_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_1_S 0 - -/** CORE1_INTR_STATUS_REG_2_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_2_REG (DR_REG_CORE1_BASE + 0x208) -/** CORE1_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_2 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_2_M (CORE1_CORE1_INTR_STATUS_2_V << CORE1_CORE1_INTR_STATUS_2_S) -#define CORE1_CORE1_INTR_STATUS_2_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_2_S 0 - -/** CORE1_INTR_STATUS_REG_3_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_3_REG (DR_REG_CORE1_BASE + 0x20c) -/** CORE1_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_3 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_3_M (CORE1_CORE1_INTR_STATUS_3_V << CORE1_CORE1_INTR_STATUS_3_S) -#define CORE1_CORE1_INTR_STATUS_3_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_3_S 0 - -/** CORE1_CLOCK_GATE_REG register - * NA - */ -#define CORE1_CLOCK_GATE_REG (DR_REG_CORE1_BASE + 0x210) -/** CORE1_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define CORE1_CORE1_REG_CLK_EN (BIT(0)) -#define CORE1_CORE1_REG_CLK_EN_M (CORE1_CORE1_REG_CLK_EN_V << CORE1_CORE1_REG_CLK_EN_S) -#define CORE1_CORE1_REG_CLK_EN_V 0x00000001U -#define CORE1_CORE1_REG_CLK_EN_S 0 - -/** CORE1_INTERRUPT_REG_DATE_REG register - * NA - */ -#define CORE1_INTERRUPT_REG_DATE_REG (DR_REG_CORE1_BASE + 0x3fc) -/** CORE1_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ -#define CORE1_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define CORE1_CORE1_INTERRUPT_REG_DATE_M (CORE1_CORE1_INTERRUPT_REG_DATE_V << CORE1_CORE1_INTERRUPT_REG_DATE_S) -#define CORE1_CORE1_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define CORE1_CORE1_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h b/components/soc/esp32p4/include/soc/core1_interrupt_struct.h deleted file mode 100644 index 38dbda26b3..0000000000 --- a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h +++ /dev/null @@ -1,2298 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: CORE1 LP RTC INT MAP REG */ -/** Type of lp_rtc_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_rtc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_rtc_int_map_reg_t; - - -/** Group: CORE1 LP WDT INT MAP REG */ -/** Type of lp_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_wdt_int_map_reg_t; - - -/** Group: CORE1 LP TIMER REG 0 INT MAP REG */ -/** Type of lp_timer_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_timer_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_timer_reg_0_int_map_reg_t; - - -/** Group: CORE1 LP TIMER REG 1 INT MAP REG */ -/** Type of lp_timer_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_timer_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_timer_reg_1_int_map_reg_t; - - -/** Group: CORE1 MB HP INT MAP REG */ -/** Type of mb_hp_int_map register - * NA - */ -typedef union { - struct { - /** core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_mb_hp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_mb_hp_int_map_reg_t; - - -/** Group: CORE1 MB LP INT MAP REG */ -/** Type of mb_lp_int_map register - * NA - */ -typedef union { - struct { - /** core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_mb_lp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_mb_lp_int_map_reg_t; - - -/** Group: CORE1 PMU REG 0 INT MAP REG */ -/** Type of pmu_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmu_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmu_reg_0_int_map_reg_t; - - -/** Group: CORE1 PMU REG 1 INT MAP REG */ -/** Type of pmu_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmu_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmu_reg_1_int_map_reg_t; - - -/** Group: CORE1 LP ANAPERI INT MAP REG */ -/** Type of lp_anaperi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_anaperi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_anaperi_int_map_reg_t; - - -/** Group: CORE1 LP ADC INT MAP REG */ -/** Type of lp_adc_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_adc_int_map_reg_t; - - -/** Group: CORE1 LP GPIO INT MAP REG */ -/** Type of lp_gpio_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_gpio_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_gpio_int_map_reg_t; - - -/** Group: CORE1 LP I2C INT MAP REG */ -/** Type of lp_i2c_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_i2c_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_i2c_int_map_reg_t; - - -/** Group: CORE1 LP I2S INT MAP REG */ -/** Type of lp_i2s_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_i2s_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_i2s_int_map_reg_t; - - -/** Group: CORE1 LP SPI INT MAP REG */ -/** Type of lp_spi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_spi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_spi_int_map_reg_t; - - -/** Group: CORE1 LP TOUCH INT MAP REG */ -/** Type of lp_touch_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_touch_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_touch_int_map_reg_t; - - -/** Group: CORE1 LP TSENS INT MAP REG */ -/** Type of lp_tsens_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_tsens_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_tsens_int_map_reg_t; - - -/** Group: CORE1 LP UART INT MAP REG */ -/** Type of lp_uart_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_uart_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_uart_int_map_reg_t; - - -/** Group: CORE1 LP EFUSE INT MAP REG */ -/** Type of lp_efuse_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_efuse_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_efuse_int_map_reg_t; - - -/** Group: CORE1 LP SW INT MAP REG */ -/** Type of lp_sw_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_sw_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_sw_int_map_reg_t; - - -/** Group: CORE1 LP SYSREG INT MAP REG */ -/** Type of lp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_sysreg_int_map_reg_t; - - -/** Group: CORE1 LP HUK INT MAP REG */ -/** Type of lp_huk_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_huk_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_huk_int_map_reg_t; - - -/** Group: CORE1 SYS ICM INT MAP REG */ -/** Type of sys_icm_int_map register - * NA - */ -typedef union { - struct { - /** core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sys_icm_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sys_icm_int_map_reg_t; - - -/** Group: CORE1 USB DEVICE INT MAP REG */ -/** Type of usb_device_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_device_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_device_int_map_reg_t; - - -/** Group: CORE1 SDIO HOST INT MAP REG */ -/** Type of sdio_host_int_map register - * NA - */ -typedef union { - struct { - /** core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sdio_host_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sdio_host_int_map_reg_t; - - -/** Group: CORE1 GDMA INT MAP REG */ -/** Type of gdma_int_map register - * NA - */ -typedef union { - struct { - /** core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gdma_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gdma_int_map_reg_t; - - -/** Group: CORE1 SPI2 INT MAP REG */ -/** Type of spi2_int_map register - * NA - */ -typedef union { - struct { - /** core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_spi2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_spi2_int_map_reg_t; - - -/** Group: CORE1 SPI3 INT MAP REG */ -/** Type of spi3_int_map register - * NA - */ -typedef union { - struct { - /** core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_spi3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_spi3_int_map_reg_t; - - -/** Group: CORE1 I2S0 INT MAP REG */ -/** Type of i2s0_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s0_int_map_reg_t; - - -/** Group: CORE1 I2S1 INT MAP REG */ -/** Type of i2s1_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s1_int_map_reg_t; - - -/** Group: CORE1 I2S2 INT MAP REG */ -/** Type of i2s2_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s2_int_map_reg_t; - - -/** Group: CORE1 UHCI0 INT MAP REG */ -/** Type of uhci0_int_map register - * NA - */ -typedef union { - struct { - /** core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uhci0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uhci0_int_map_reg_t; - - -/** Group: CORE1 UART0 INT MAP REG */ -/** Type of uart0_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart0_int_map_reg_t; - - -/** Group: CORE1 UART1 INT MAP REG */ -/** Type of uart1_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart1_int_map_reg_t; - - -/** Group: CORE1 UART2 INT MAP REG */ -/** Type of uart2_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart2_int_map_reg_t; - - -/** Group: CORE1 UART3 INT MAP REG */ -/** Type of uart3_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart3_int_map_reg_t; - - -/** Group: CORE1 UART4 INT MAP REG */ -/** Type of uart4_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart4_int_map_reg_t; - - -/** Group: CORE1 LCD CAM INT MAP REG */ -/** Type of lcd_cam_int_map register - * NA - */ -typedef union { - struct { - /** core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lcd_cam_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lcd_cam_int_map_reg_t; - - -/** Group: CORE1 ADC INT MAP REG */ -/** Type of adc_int_map register - * NA - */ -typedef union { - struct { - /** core1_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_adc_int_map_reg_t; - - -/** Group: CORE1 PWM0 INT MAP REG */ -/** Type of pwm0_int_map register - * NA - */ -typedef union { - struct { - /** core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pwm0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pwm0_int_map_reg_t; - - -/** Group: CORE1 PWM1 INT MAP REG */ -/** Type of pwm1_int_map register - * NA - */ -typedef union { - struct { - /** core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pwm1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pwm1_int_map_reg_t; - - -/** Group: CORE1 CAN0 INT MAP REG */ -/** Type of can0_int_map register - * NA - */ -typedef union { - struct { - /** core1_can0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can0_int_map_reg_t; - - -/** Group: CORE1 CAN1 INT MAP REG */ -/** Type of can1_int_map register - * NA - */ -typedef union { - struct { - /** core1_can1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can1_int_map_reg_t; - - -/** Group: CORE1 CAN2 INT MAP REG */ -/** Type of can2_int_map register - * NA - */ -typedef union { - struct { - /** core1_can2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can2_int_map_reg_t; - - -/** Group: CORE1 RMT INT MAP REG */ -/** Type of rmt_int_map register - * NA - */ -typedef union { - struct { - /** core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_rmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_rmt_int_map_reg_t; - - -/** Group: CORE1 I2C0 INT MAP REG */ -/** Type of i2c0_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2c0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2c0_int_map_reg_t; - - -/** Group: CORE1 I2C1 INT MAP REG */ -/** Type of i2c1_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2c1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2c1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 T0 INT MAP REG */ -/** Type of timergrp0_t0_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_t0_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 T1 INT MAP REG */ -/** Type of timergrp0_t1_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_t1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 WDT INT MAP REG */ -/** Type of timergrp0_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_wdt_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 T0 INT MAP REG */ -/** Type of timergrp1_t0_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_t0_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 T1 INT MAP REG */ -/** Type of timergrp1_t1_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_t1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 WDT INT MAP REG */ -/** Type of timergrp1_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_wdt_int_map_reg_t; - - -/** Group: CORE1 LEDC INT MAP REG */ -/** Type of ledc_int_map register - * NA - */ -typedef union { - struct { - /** core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ledc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ledc_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET0 INT MAP REG */ -/** Type of systimer_target0_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target0_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET1 INT MAP REG */ -/** Type of systimer_target1_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target1_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET2 INT MAP REG */ -/** Type of systimer_target2_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target2_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH0 INT MAP REG */ -/** Type of ahb_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH1 INT MAP REG */ -/** Type of ahb_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH2 INT MAP REG */ -/** Type of ahb_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH0 INT MAP REG */ -/** Type of ahb_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH1 INT MAP REG */ -/** Type of ahb_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH2 INT MAP REG */ -/** Type of ahb_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH0 INT MAP REG */ -/** Type of axi_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH1 INT MAP REG */ -/** Type of axi_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH2 INT MAP REG */ -/** Type of axi_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH0 INT MAP REG */ -/** Type of axi_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH1 INT MAP REG */ -/** Type of axi_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH2 INT MAP REG */ -/** Type of axi_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE1 RSA INT MAP REG */ -/** Type of rsa_int_map register - * NA - */ -typedef union { - struct { - /** core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_rsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_rsa_int_map_reg_t; - - -/** Group: CORE1 AES INT MAP REG */ -/** Type of aes_int_map register - * NA - */ -typedef union { - struct { - /** core1_aes_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_aes_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_aes_int_map_reg_t; - - -/** Group: CORE1 SHA INT MAP REG */ -/** Type of sha_int_map register - * NA - */ -typedef union { - struct { - /** core1_sha_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sha_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sha_int_map_reg_t; - - -/** Group: CORE1 ECC INT MAP REG */ -/** Type of ecc_int_map register - * NA - */ -typedef union { - struct { - /** core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ecc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ecc_int_map_reg_t; - - -/** Group: CORE1 ECDSA INT MAP REG */ -/** Type of ecdsa_int_map register - * NA - */ -typedef union { - struct { - /** core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ecdsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ecdsa_int_map_reg_t; - - -/** Group: CORE1 KM INT MAP REG */ -/** Type of km_int_map register - * NA - */ -typedef union { - struct { - /** core1_km_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_km_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_km_int_map_reg_t; - - -/** Group: CORE1 GPIO INT0 MAP REG */ -/** Type of gpio_int0_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int0_map_reg_t; - - -/** Group: CORE1 GPIO INT1 MAP REG */ -/** Type of gpio_int1_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int1_map_reg_t; - - -/** Group: CORE1 GPIO INT2 MAP REG */ -/** Type of gpio_int2_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int2_map_reg_t; - - -/** Group: CORE1 GPIO INT3 MAP REG */ -/** Type of gpio_int3_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int3_map_reg_t; - - -/** Group: CORE1 GPIO PAD COMP INT MAP REG */ -/** Type of gpio_pad_comp_int_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_pad_comp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_pad_comp_int_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 0 MAP REG */ -/** Type of cpu_int_from_cpu_0_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_0_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 1 MAP REG */ -/** Type of cpu_int_from_cpu_1_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_1_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 2 MAP REG */ -/** Type of cpu_int_from_cpu_2_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_2_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 3 MAP REG */ -/** Type of cpu_int_from_cpu_3_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_3_map_reg_t; - - -/** Group: CORE1 CACHE INT MAP REG */ -/** Type of cache_int_map register - * NA - */ -typedef union { - struct { - /** core1_cache_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cache_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cache_int_map_reg_t; - - -/** Group: CORE1 FLASH MSPI INT MAP REG */ -/** Type of flash_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_flash_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_flash_mspi_int_map_reg_t; - - -/** Group: CORE1 CSI BRIDGE INT MAP REG */ -/** Type of csi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_csi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_csi_bridge_int_map_reg_t; - - -/** Group: CORE1 DSI BRIDGE INT MAP REG */ -/** Type of dsi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dsi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dsi_bridge_int_map_reg_t; - - -/** Group: CORE1 CSI INT MAP REG */ -/** Type of csi_int_map register - * NA - */ -typedef union { - struct { - /** core1_csi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_csi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_csi_int_map_reg_t; - - -/** Group: CORE1 DSI INT MAP REG */ -/** Type of dsi_int_map register - * NA - */ -typedef union { - struct { - /** core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dsi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dsi_int_map_reg_t; - - -/** Group: CORE1 GMII PHY INT MAP REG */ -/** Type of gmii_phy_int_map register - * NA - */ -typedef union { - struct { - /** core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gmii_phy_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gmii_phy_int_map_reg_t; - - -/** Group: CORE1 LPI INT MAP REG */ -/** Type of lpi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lpi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lpi_int_map_reg_t; - - -/** Group: CORE1 PMT INT MAP REG */ -/** Type of pmt_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmt_int_map_reg_t; - - -/** Group: CORE1 SBD INT MAP REG */ -/** Type of sbd_int_map register - * NA - */ -typedef union { - struct { - /** core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sbd_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sbd_int_map_reg_t; - - -/** Group: CORE1 USB OTG INT MAP REG */ -/** Type of usb_otg_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg_int_map_reg_t; - - -/** Group: CORE1 USB OTG ENDP MULTI PROC INT MAP REG */ -/** Type of usb_otg_endp_multi_proc_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg_endp_multi_proc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg_endp_multi_proc_int_map_reg_t; - - -/** Group: CORE1 JPEG INT MAP REG */ -/** Type of jpeg_int_map register - * NA - */ -typedef union { - struct { - /** core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_jpeg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_jpeg_int_map_reg_t; - - -/** Group: CORE1 PPA INT MAP REG */ -/** Type of ppa_int_map register - * NA - */ -typedef union { - struct { - /** core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ppa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ppa_int_map_reg_t; - - -/** Group: CORE1 CORE0 TRACE INT MAP REG */ -/** Type of core0_trace_int_map register - * NA - */ -typedef union { - struct { - /** core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_core0_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_core0_trace_int_map_reg_t; - - -/** Group: CORE1 CORE1 TRACE INT MAP REG */ -/** Type of core1_trace_int_map register - * NA - */ -typedef union { - struct { - /** core1_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_core1_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_core1_trace_int_map_reg_t; - - -/** Group: CORE1 HP CORE CTRL INT MAP REG */ -/** Type of hp_core_ctrl_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_core_ctrl_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_core_ctrl_int_map_reg_t; - - -/** Group: CORE1 ISP INT MAP REG */ -/** Type of isp_int_map register - * NA - */ -typedef union { - struct { - /** core1_isp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_isp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_isp_int_map_reg_t; - - -/** Group: CORE1 I3C MST INT MAP REG */ -/** Type of i3c_mst_int_map register - * NA - */ -typedef union { - struct { - /** core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i3c_mst_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i3c_mst_int_map_reg_t; - - -/** Group: CORE1 I3C SLV INT MAP REG */ -/** Type of i3c_slv_int_map register - * NA - */ -typedef union { - struct { - /** core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i3c_slv_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i3c_slv_int_map_reg_t; - - -/** Group: CORE1 USB OTG11 INT MAP REG */ -/** Type of usb_otg11_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg11_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg11_int_map_reg_t; - - -/** Group: CORE1 DMA2D IN CH0 INT MAP REG */ -/** Type of dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE1 DMA2D IN CH1 INT MAP REG */ -/** Type of dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH0 INT MAP REG */ -/** Type of dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH1 INT MAP REG */ -/** Type of dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH2 INT MAP REG */ -/** Type of dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE1 PSRAM MSPI INT MAP REG */ -/** Type of psram_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_psram_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_psram_mspi_int_map_reg_t; - - -/** Group: CORE1 HP SYSREG INT MAP REG */ -/** Type of hp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_sysreg_int_map_reg_t; - - -/** Group: CORE1 PCNT INT MAP REG */ -/** Type of pcnt_int_map register - * NA - */ -typedef union { - struct { - /** core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pcnt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pcnt_int_map_reg_t; - - -/** Group: CORE1 HP PAU INT MAP REG */ -/** Type of hp_pau_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_pau_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_pau_int_map_reg_t; - - -/** Group: CORE1 HP PARLIO RX INT MAP REG */ -/** Type of hp_parlio_rx_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_parlio_rx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_parlio_rx_int_map_reg_t; - - -/** Group: CORE1 HP PARLIO TX INT MAP REG */ -/** Type of hp_parlio_tx_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_parlio_tx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_parlio_tx_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH0 INT MAP REG */ -/** Type of h264_dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH1 INT MAP REG */ -/** Type of h264_dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH2 INT MAP REG */ -/** Type of h264_dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH3 INT MAP REG */ -/** Type of h264_dma2d_out_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch3_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH4 INT MAP REG */ -/** Type of h264_dma2d_out_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch4_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH0 INT MAP REG */ -/** Type of h264_dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH1 INT MAP REG */ -/** Type of h264_dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH2 INT MAP REG */ -/** Type of h264_dma2d_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch2_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH3 INT MAP REG */ -/** Type of h264_dma2d_in_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch3_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH4 INT MAP REG */ -/** Type of h264_dma2d_in_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch4_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH5 INT MAP REG */ -/** Type of h264_dma2d_in_ch5_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch5_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch5_int_map_reg_t; - - -/** Group: CORE1 H264 REG INT MAP REG */ -/** Type of h264_reg_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_reg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_reg_int_map_reg_t; - - -/** Group: CORE1 ASSIST DEBUG INT MAP REG */ -/** Type of assist_debug_int_map register - * NA - */ -typedef union { - struct { - /** core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_assist_debug_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_assist_debug_int_map_reg_t; - - -/** Group: CORE1 INTR STATUS REG 0 REG */ -/** Type of intr_status_reg_0 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_0:32; - }; - uint32_t val; -} core1_intr_status_reg_0_reg_t; - - -/** Group: CORE1 INTR STATUS REG 1 REG */ -/** Type of intr_status_reg_1 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_1:32; - }; - uint32_t val; -} core1_intr_status_reg_1_reg_t; - - -/** Group: CORE1 INTR STATUS REG 2 REG */ -/** Type of intr_status_reg_2 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_2:32; - }; - uint32_t val; -} core1_intr_status_reg_2_reg_t; - - -/** Group: CORE1 INTR STATUS REG 3 REG */ -/** Type of intr_status_reg_3 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_3:32; - }; - uint32_t val; -} core1_intr_status_reg_3_reg_t; - - -/** Group: CORE1 CLOCK GATE REG */ -/** Type of clock_gate register - * NA - */ -typedef union { - struct { - /** core1_reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t core1_reg_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} core1_clock_gate_reg_t; - - -/** Group: CORE1 INTERRUPT REG DATE REG */ -/** Type of interrupt_reg_date register - * NA - */ -typedef union { - struct { - /** core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ - uint32_t core1_interrupt_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} core1_interrupt_reg_date_reg_t; - - -typedef struct { - volatile core1_lp_rtc_int_map_reg_t lp_rtc_int_map; - volatile core1_lp_wdt_int_map_reg_t lp_wdt_int_map; - volatile core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; - volatile core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; - volatile core1_mb_hp_int_map_reg_t mb_hp_int_map; - volatile core1_mb_lp_int_map_reg_t mb_lp_int_map; - volatile core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; - volatile core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; - volatile core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map; - volatile core1_lp_adc_int_map_reg_t lp_adc_int_map; - volatile core1_lp_gpio_int_map_reg_t lp_gpio_int_map; - volatile core1_lp_i2c_int_map_reg_t lp_i2c_int_map; - volatile core1_lp_i2s_int_map_reg_t lp_i2s_int_map; - volatile core1_lp_spi_int_map_reg_t lp_spi_int_map; - volatile core1_lp_touch_int_map_reg_t lp_touch_int_map; - volatile core1_lp_tsens_int_map_reg_t lp_tsens_int_map; - volatile core1_lp_uart_int_map_reg_t lp_uart_int_map; - volatile core1_lp_efuse_int_map_reg_t lp_efuse_int_map; - volatile core1_lp_sw_int_map_reg_t lp_sw_int_map; - volatile core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map; - volatile core1_lp_huk_int_map_reg_t lp_huk_int_map; - volatile core1_sys_icm_int_map_reg_t sys_icm_int_map; - volatile core1_usb_device_int_map_reg_t usb_device_int_map; - volatile core1_sdio_host_int_map_reg_t sdio_host_int_map; - volatile core1_gdma_int_map_reg_t gdma_int_map; - volatile core1_spi2_int_map_reg_t spi2_int_map; - volatile core1_spi3_int_map_reg_t spi3_int_map; - volatile core1_i2s0_int_map_reg_t i2s0_int_map; - volatile core1_i2s1_int_map_reg_t i2s1_int_map; - volatile core1_i2s2_int_map_reg_t i2s2_int_map; - volatile core1_uhci0_int_map_reg_t uhci0_int_map; - volatile core1_uart0_int_map_reg_t uart0_int_map; - volatile core1_uart1_int_map_reg_t uart1_int_map; - volatile core1_uart2_int_map_reg_t uart2_int_map; - volatile core1_uart3_int_map_reg_t uart3_int_map; - volatile core1_uart4_int_map_reg_t uart4_int_map; - volatile core1_lcd_cam_int_map_reg_t lcd_cam_int_map; - volatile core1_adc_int_map_reg_t adc_int_map; - volatile core1_pwm0_int_map_reg_t pwm0_int_map; - volatile core1_pwm1_int_map_reg_t pwm1_int_map; - volatile core1_can0_int_map_reg_t can0_int_map; - volatile core1_can1_int_map_reg_t can1_int_map; - volatile core1_can2_int_map_reg_t can2_int_map; - volatile core1_rmt_int_map_reg_t rmt_int_map; - volatile core1_i2c0_int_map_reg_t i2c0_int_map; - volatile core1_i2c1_int_map_reg_t i2c1_int_map; - volatile core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; - volatile core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; - volatile core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; - volatile core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; - volatile core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; - volatile core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; - volatile core1_ledc_int_map_reg_t ledc_int_map; - volatile core1_systimer_target0_int_map_reg_t systimer_target0_int_map; - volatile core1_systimer_target1_int_map_reg_t systimer_target1_int_map; - volatile core1_systimer_target2_int_map_reg_t systimer_target2_int_map; - volatile core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; - volatile core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; - volatile core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; - volatile core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; - volatile core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; - volatile core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; - volatile core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; - volatile core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; - volatile core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; - volatile core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; - volatile core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; - volatile core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; - volatile core1_rsa_int_map_reg_t rsa_int_map; - volatile core1_aes_int_map_reg_t aes_int_map; - volatile core1_sha_int_map_reg_t sha_int_map; - volatile core1_ecc_int_map_reg_t ecc_int_map; - volatile core1_ecdsa_int_map_reg_t ecdsa_int_map; - volatile core1_km_int_map_reg_t km_int_map; - volatile core1_gpio_int0_map_reg_t gpio_int0_map; - volatile core1_gpio_int1_map_reg_t gpio_int1_map; - volatile core1_gpio_int2_map_reg_t gpio_int2_map; - volatile core1_gpio_int3_map_reg_t gpio_int3_map; - volatile core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; - volatile core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; - volatile core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; - volatile core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; - volatile core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; - volatile core1_cache_int_map_reg_t cache_int_map; - volatile core1_flash_mspi_int_map_reg_t flash_mspi_int_map; - volatile core1_csi_bridge_int_map_reg_t csi_bridge_int_map; - volatile core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map; - volatile core1_csi_int_map_reg_t csi_int_map; - volatile core1_dsi_int_map_reg_t dsi_int_map; - volatile core1_gmii_phy_int_map_reg_t gmii_phy_int_map; - volatile core1_lpi_int_map_reg_t lpi_int_map; - volatile core1_pmt_int_map_reg_t pmt_int_map; - volatile core1_sbd_int_map_reg_t sbd_int_map; - volatile core1_usb_otg_int_map_reg_t usb_otg_int_map; - volatile core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; - volatile core1_jpeg_int_map_reg_t jpeg_int_map; - volatile core1_ppa_int_map_reg_t ppa_int_map; - volatile core1_core0_trace_int_map_reg_t core0_trace_int_map; - volatile core1_core1_trace_int_map_reg_t core1_trace_int_map; - volatile core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; - volatile core1_isp_int_map_reg_t isp_int_map; - volatile core1_i3c_mst_int_map_reg_t i3c_mst_int_map; - volatile core1_i3c_slv_int_map_reg_t i3c_slv_int_map; - volatile core1_usb_otg11_int_map_reg_t usb_otg11_int_map; - volatile core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; - volatile core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; - volatile core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; - volatile core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; - volatile core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; - volatile core1_psram_mspi_int_map_reg_t psram_mspi_int_map; - volatile core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map; - volatile core1_pcnt_int_map_reg_t pcnt_int_map; - volatile core1_hp_pau_int_map_reg_t hp_pau_int_map; - volatile core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; - volatile core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; - volatile core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; - volatile core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; - volatile core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; - volatile core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; - volatile core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; - volatile core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; - volatile core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; - volatile core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; - volatile core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; - volatile core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; - volatile core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; - volatile core1_h264_reg_int_map_reg_t h264_reg_int_map; - volatile core1_assist_debug_int_map_reg_t assist_debug_int_map; - volatile core1_intr_status_reg_0_reg_t intr_status_reg_0; - volatile core1_intr_status_reg_1_reg_t intr_status_reg_1; - volatile core1_intr_status_reg_2_reg_t intr_status_reg_2; - volatile core1_intr_status_reg_3_reg_t intr_status_reg_3; - volatile core1_clock_gate_reg_t clock_gate; - uint32_t reserved_214[122]; - volatile core1_interrupt_reg_date_reg_t interrupt_reg_date; -} core1_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(core1_dev_t) == 0x400, "Invalid size of core1_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/dport_access.h b/components/soc/esp32p4/include/soc/dport_access.h new file mode 100644 index 0000000000..3747073d22 --- /dev/null +++ b/components/soc/esp32p4/include/soc/dport_access.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _DPORT_ACCESS_H_ +#define _DPORT_ACCESS_H_ + +#include +#include "soc.h" +#include "uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif + +#endif /* _DPORT_ACCESS_H_ */ diff --git a/components/soc/esp32p4/include/soc/efuse_mem_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h similarity index 99% rename from components/soc/esp32p4/include/soc/efuse_mem_reg.h rename to components/soc/esp32p4/include/soc/efuse_reg.h index e982d77684..f095267388 100644 --- a/components/soc/esp32p4/include/soc/efuse_mem_reg.h +++ b/components/soc/esp32p4/include/soc/efuse_reg.h @@ -11,6 +11,9 @@ extern "C" { #endif +#define EFUSE_READ_OP_CODE 0x5aa5 +#define EFUSE_WRITE_OP_CODE 0x5a5a + /** EFUSE_PGM_DATA0_REG register * Register 0 that stores data to be programmed. */ diff --git a/components/soc/esp32p4/include/soc/efuse_mem_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/efuse_mem_struct.h rename to components/soc/esp32p4/include/soc/efuse_struct.h index 5db3b2ace5..1ed1b20ab8 100644 --- a/components/soc/esp32p4/include/soc/efuse_mem_struct.h +++ b/components/soc/esp32p4/include/soc/efuse_struct.h @@ -4439,6 +4439,7 @@ typedef struct { volatile efuse_apb2otp_en_reg_t apb2otp_en; } efuse_dev_t; +extern efuse_dev_t EFUSE; #ifndef __cplusplus _Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/ext_mem_defs.h b/components/soc/esp32p4/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..6e8f3373ab --- /dev/null +++ b/components/soc/esp32p4/include/soc/ext_mem_defs.h @@ -0,0 +1,152 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + + +#define IRAM0_CACHE_ADDRESS_LOW 0x40000000 +#define IRAM0_CACHE_ADDRESS_HIGH 0x50000000 + +#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range +#define DRAM0_CACHE_OPERATION_HIGH 0x44000000 + +#define SINGLE_BANK_CACHE_ADDRESS_LOW 0x40000000 +#define SINGLE_BANK_CACHE_ADDRESS_HIGH 0x44000000 +#define DUAL_BANK_CACHE_ADDRESS_LOW 0x48000000 +#define DUAL_BANK_CACHE_ADDRESS_HIGH 0x4C000000 + +#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) +#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) +#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) +#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) + +#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) +#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) + +//TODO, remove these cache function dependencies +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE (0x400 * 4) +#define DCACHE_MMU_SIZE (0x400 * 4) + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) (0x400 * 4) + +#define MMU_MSPI_ACCESS_FLASH 0 +#define MMU_MSPI_ACCESS_SPIRAM BIT(10) +#define MMU_MSPI_VALID BIT(12) +#define MMU_MSPI_INVALID 0 +#define MMU_MSPI_SENSITIVE BIT(13) + +#define MMU_PSRAM_ACCESS_SPIRAM BIT(10) +#define MMU_PSRAM_VALID BIT(11) +#define MMU_PSRAM_SENSITIVE BIT(12) + +#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH +#define MMU_ACCESS_SPIRAM MMU_MSPI_ACCESS_SPIRAM +#define MMU_VALID MMU_MSPI_VALID +#define MMU_SENSITIVE MMU_MSPI_SENSITIVE +#define DMMU_SENSITIVE MMU_PSRAM_SENSITIVE + +#define MMU_INVALID_MASK MMU_MSPI_VALID +#define MMU_INVALID MMU_MSPI_INVALID + +#define DMMU_INVALID_MASK MMU_PSRAM_VALID +#define DMMU_INVALID 0 + +#define CACHE_MAX_SYNC_NUM 0x400000 +#define CACHE_MAX_LOCK_NUM 0x8000 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define MMU_VALID_VAL_MASK 0x3ff +/** + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define MMU_MAX_PADDR_PAGE_NUM 1024 +//MMU entry num +#define MMU_ENTRY_NUM 1024 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & MMU_VADDR_MASK + */ +#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1) + +#define SOC_MMU_FLASH_VADDR_BASE 0x40000000 +#define SOC_MMU_PSRAM_VADDR_BASE 0x48000000 + +#define SOC_MMU_FLASH_VADDR_START 0x40000000 +#define SOC_MMU_FLASH_VADDR_END 0x44000000 +#define SOC_MMU_PSRAM_VADDR_START 0x48000000 +#define SOC_MMU_PSRAM_VADDR_END 0x4C000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 1024 MMU entries, needs 0x3F to hold it. + * + * Therefore, 0x3F,FFFF + */ +#define SOC_MMU_MEM_PHYSICAL_LINEAR_CAP (SOC_MMU_FLASH_VADDR_BASE ^ SOC_MMU_PSRAM_VADDR_BASE) +#define SOC_MMU_LINEAR_FLASH_ADDR_MASK (0xBFFFFFF) +#define SOC_MMU_LINEAR_PARSM_ADDR_MASK (0xBFFFFFF | SOC_MMU_MEM_PHYSICAL_LINEAR_CAP) + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (SOC_MMU_FLASH_VADDR_START & SOC_MMU_LINEAR_FLASH_ADDR_MASK) +#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_FLASH_ADDR_MASK + 1) +#define SOC_MMU_FLASH_LINEAR_ADDRESS_SIZE (SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH - SOC_MMU_FLASH_LINEAR_ADDRESS_LOW) + +#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (SOC_MMU_PSRAM_VADDR_START & SOC_MMU_LINEAR_PARSM_ADDR_MASK) +#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_PARSM_ADDR_MASK + 1) +#define SOC_MMU_PSRAM_LINEAR_ADDRESS_SIZE (SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH - SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW) + +/** + * I/D share the MMU linear address range + */ +_Static_assert((SOC_MMU_FLASH_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP) == (SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP), \ + "IRAM0 and DRAM0 raw linear address should be same"); + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/gdma_channel.h b/components/soc/esp32p4/include/soc/gdma_channel.h new file mode 100644 index 0000000000..d2aa55b41e --- /dev/null +++ b/components/soc/esp32p4/include/soc/gdma_channel.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/include/soc/gpio_ext_reg.h index f994cd233e..157a4c9e0a 100644 --- a/components/soc/esp32p4/include/soc/gpio_ext_reg.h +++ b/components/soc/esp32p4/include/soc/gpio_ext_reg.h @@ -23,7 +23,7 @@ extern "C" { /** GPIOSD_SIGMADELTA0_REG register * Duty Cycle Configure Register of SDM0 */ -#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0) +#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -42,7 +42,7 @@ extern "C" { /** GPIOSD_SIGMADELTA1_REG register * Duty Cycle Configure Register of SDM1 */ -#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4) +#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -61,7 +61,7 @@ extern "C" { /** GPIOSD_SIGMADELTA2_REG register * Duty Cycle Configure Register of SDM2 */ -#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8) +#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -80,7 +80,7 @@ extern "C" { /** GPIOSD_SIGMADELTA3_REG register * Duty Cycle Configure Register of SDM3 */ -#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc) +#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -99,7 +99,7 @@ extern "C" { /** GPIOSD_SIGMADELTA4_REG register * Duty Cycle Configure Register of SDM4 */ -#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10) +#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x10) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -118,7 +118,7 @@ extern "C" { /** GPIOSD_SIGMADELTA5_REG register * Duty Cycle Configure Register of SDM5 */ -#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14) +#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x14) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -137,7 +137,7 @@ extern "C" { /** GPIOSD_SIGMADELTA6_REG register * Duty Cycle Configure Register of SDM6 */ -#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18) +#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x18) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -156,7 +156,7 @@ extern "C" { /** GPIOSD_SIGMADELTA7_REG register * Duty Cycle Configure Register of SDM7 */ -#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c) +#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x1c) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -175,7 +175,7 @@ extern "C" { /** GPIOSD_SIGMADELTA_MISC_REG register * MISC Register */ -#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24) +#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) /** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; * Clock enable bit of sigma delta modulation. */ @@ -194,7 +194,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH0_REG register * Glitch Filter Configure Register of Channel0 */ -#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30) +#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -227,7 +227,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH1_REG register * Glitch Filter Configure Register of Channel1 */ -#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34) +#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -260,7 +260,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH2_REG register * Glitch Filter Configure Register of Channel2 */ -#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38) +#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -293,7 +293,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH3_REG register * Glitch Filter Configure Register of Channel3 */ -#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c) +#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -326,7 +326,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH4_REG register * Glitch Filter Configure Register of Channel4 */ -#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40) +#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -359,7 +359,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH5_REG register * Glitch Filter Configure Register of Channel5 */ -#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44) +#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -392,7 +392,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH6_REG register * Glitch Filter Configure Register of Channel6 */ -#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48) +#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -425,7 +425,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH7_REG register * Glitch Filter Configure Register of Channel7 */ -#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c) +#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -458,7 +458,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH0_CFG_REG register * Etm Config register of Channel0 */ -#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60) +#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -477,7 +477,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH1_CFG_REG register * Etm Config register of Channel1 */ -#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64) +#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -496,7 +496,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH2_CFG_REG register * Etm Config register of Channel2 */ -#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68) +#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -515,7 +515,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH3_CFG_REG register * Etm Config register of Channel3 */ -#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c) +#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -534,7 +534,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH4_CFG_REG register * Etm Config register of Channel4 */ -#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70) +#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -553,7 +553,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH5_CFG_REG register * Etm Config register of Channel5 */ -#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74) +#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -572,7 +572,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH6_CFG_REG register * Etm Config register of Channel6 */ -#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78) +#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -591,7 +591,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH7_CFG_REG register * Etm Config register of Channel7 */ -#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c) +#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -610,7 +610,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P0_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0) +#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) /** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -671,7 +671,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P1_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4) +#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) /** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -732,7 +732,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P2_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8) +#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) /** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -793,7 +793,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P3_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac) +#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) /** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -854,7 +854,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P4_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0) +#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) /** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -915,7 +915,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P5_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4) +#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) /** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -976,7 +976,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P6_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8) +#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) /** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1037,7 +1037,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P7_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc) +#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc) /** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1098,7 +1098,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P8_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0) +#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc0) /** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1159,7 +1159,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P9_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4) +#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc4) /** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1220,7 +1220,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P10_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8) +#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc8) /** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1281,7 +1281,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P11_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc) +#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xcc) /** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1342,7 +1342,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P12_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0) +#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd0) /** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1403,7 +1403,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P13_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4) +#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd4) /** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1450,7 +1450,7 @@ extern "C" { /** GPIOSD_VERSION_REG register * Version Control Register */ -#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc) +#define GPIOSD_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) /** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952; * Version control register. */ diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h new file mode 100644 index 0000000000..6238eeffbb --- /dev/null +++ b/components/soc/esp32p4/include/soc/gpio_pins.h @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..cdb82686cc --- /dev/null +++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h @@ -0,0 +1,487 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define SD_CARD_CCLK_2_PAD_OUT_IDX 0 +#define SD_CARD_CCMD_2_PAD_IN_IDX 1 +#define SD_CARD_CCMD_2_PAD_OUT_IDX 1 +#define SD_CARD_CDATA0_2_PAD_IN_IDX 2 +#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2 +#define SD_CARD_CDATA1_2_PAD_IN_IDX 3 +#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3 +#define SD_CARD_CDATA2_2_PAD_IN_IDX 4 +#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4 +#define SD_CARD_CDATA3_2_PAD_IN_IDX 5 +#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5 +#define SD_CARD_CDATA4_2_PAD_IN_IDX 6 +#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6 +#define SD_CARD_CDATA5_2_PAD_IN_IDX 7 +#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7 +#define SD_CARD_CDATA6_2_PAD_IN_IDX 8 +#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8 +#define SD_CARD_CDATA7_2_PAD_IN_IDX 9 +#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9 +#define UART0_RXD_PAD_IN_IDX 10 +#define UART0_TXD_PAD_OUT_IDX 10 +#define UART0_CTS_PAD_IN_IDX 11 +#define UART0_RTS_PAD_OUT_IDX 11 +#define UART0_DSR_PAD_IN_IDX 12 +#define UART0_DTR_PAD_OUT_IDX 12 +#define UART1_RXD_PAD_IN_IDX 13 +#define UART1_TXD_PAD_OUT_IDX 13 +#define UART1_CTS_PAD_IN_IDX 14 +#define UART1_RTS_PAD_OUT_IDX 14 +#define UART1_DSR_PAD_IN_IDX 15 +#define UART1_DTR_PAD_OUT_IDX 15 +#define UART2_RXD_PAD_IN_IDX 16 +#define UART2_TXD_PAD_OUT_IDX 16 +#define UART2_CTS_PAD_IN_IDX 17 +#define UART2_RTS_PAD_OUT_IDX 17 +#define UART2_DSR_PAD_IN_IDX 18 +#define UART2_DTR_PAD_OUT_IDX 18 +#define UART3_RXD_PAD_IN_IDX 19 +#define UART3_TXD_PAD_OUT_IDX 19 +#define UART3_CTS_PAD_IN_IDX 20 +#define UART3_RTS_PAD_OUT_IDX 20 +#define UART3_DSR_PAD_IN_IDX 21 +#define UART3_DTR_PAD_OUT_IDX 21 +#define UART4_RXD_PAD_IN_IDX 22 +#define UART4_TXD_PAD_OUT_IDX 22 +#define UART4_CTS_PAD_IN_IDX 23 +#define UART4_RTS_PAD_OUT_IDX 23 +#define UART4_DSR_PAD_IN_IDX 24 +#define UART4_DTR_PAD_OUT_IDX 24 +#define I2S0_O_BCK_PAD_IN_IDX 25 +#define I2S0_O_BCK_PAD_OUT_IDX 25 +#define I2S0_MCLK_PAD_IN_IDX 26 +#define I2S0_MCLK_PAD_OUT_IDX 26 +#define I2S0_O_WS_PAD_IN_IDX 27 +#define I2S0_O_WS_PAD_OUT_IDX 27 +#define I2S0_I_SD_PAD_IN_IDX 28 +#define I2S0_O_SD_PAD_OUT_IDX 28 +#define I2S0_I_BCK_PAD_IN_IDX 29 +#define I2S0_I_BCK_PAD_OUT_IDX 29 +#define I2S0_I_WS_PAD_IN_IDX 30 +#define I2S0_I_WS_PAD_OUT_IDX 30 +#define I2S1_O_BCK_PAD_IN_IDX 31 +#define I2S1_O_BCK_PAD_OUT_IDX 31 +#define I2S1_MCLK_PAD_IN_IDX 32 +#define I2S1_MCLK_PAD_OUT_IDX 32 +#define I2S1_O_WS_PAD_IN_IDX 33 +#define I2S1_O_WS_PAD_OUT_IDX 33 +#define I2S1_I_SD_PAD_IN_IDX 34 +#define I2S1_O_SD_PAD_OUT_IDX 34 +#define I2S1_I_BCK_PAD_IN_IDX 35 +#define I2S1_I_BCK_PAD_OUT_IDX 35 +#define I2S1_I_WS_PAD_IN_IDX 36 +#define I2S1_I_WS_PAD_OUT_IDX 36 +#define I2S2_O_BCK_PAD_IN_IDX 37 +#define I2S2_O_BCK_PAD_OUT_IDX 37 +#define I2S2_MCLK_PAD_IN_IDX 38 +#define I2S2_MCLK_PAD_OUT_IDX 38 +#define I2S2_O_WS_PAD_IN_IDX 39 +#define I2S2_O_WS_PAD_OUT_IDX 39 +#define I2S2_I_SD_PAD_IN_IDX 40 +#define I2S2_O_SD_PAD_OUT_IDX 40 +#define I2S2_I_BCK_PAD_IN_IDX 41 +#define I2S2_I_BCK_PAD_OUT_IDX 41 +#define I2S2_I_WS_PAD_IN_IDX 42 +#define I2S2_I_WS_PAD_OUT_IDX 42 +#define I2S0_I_SD1_PAD_IN_IDX 43 +#define I2S0_O_SD1_PAD_OUT_IDX 43 +#define I2S0_I_SD2_PAD_IN_IDX 44 +#define SPI2_DQS_PAD_OUT_IDX 44 +#define I2S0_I_SD3_PAD_IN_IDX 45 +#define SPI3_CS2_PAD_OUT_IDX 45 +#define SPI3_CS1_PAD_OUT_IDX 46 +#define SPI3_CK_PAD_IN_IDX 47 +#define SPI3_CK_PAD_OUT_IDX 47 +#define SPI3_Q_PAD_IN_IDX 48 +#define SPI3_QO_PAD_OUT_IDX 48 +#define SPI3_D_PAD_IN_IDX 49 +#define SPI3_D_PAD_OUT_IDX 49 +#define SPI3_HOLD_PAD_IN_IDX 50 +#define SPI3_HOLD_PAD_OUT_IDX 50 +#define SPI3_WP_PAD_IN_IDX 51 +#define SPI3_WP_PAD_OUT_IDX 51 +#define SPI3_CS_PAD_IN_IDX 52 +#define SPI3_CS_PAD_OUT_IDX 52 +#define SPI2_CK_PAD_IN_IDX 53 +#define SPI2_CK_PAD_OUT_IDX 53 +#define SPI2_Q_PAD_IN_IDX 54 +#define SPI2_Q_PAD_OUT_IDX 54 +#define SPI2_D_PAD_IN_IDX 55 +#define SPI2_D_PAD_OUT_IDX 55 +#define SPI2_HOLD_PAD_IN_IDX 56 +#define SPI2_HOLD_PAD_OUT_IDX 56 +#define SPI2_WP_PAD_IN_IDX 57 +#define SPI2_WP_PAD_OUT_IDX 57 +#define SPI2_IO4_PAD_IN_IDX 58 +#define SPI2_IO4_PAD_OUT_IDX 58 +#define SPI2_IO5_PAD_IN_IDX 59 +#define SPI2_IO5_PAD_OUT_IDX 59 +#define SPI2_IO6_PAD_IN_IDX 60 +#define SPI2_IO6_PAD_OUT_IDX 60 +#define SPI2_IO7_PAD_IN_IDX 61 +#define SPI2_IO7_PAD_OUT_IDX 61 +#define SPI2_CS_PAD_IN_IDX 62 +#define SPI2_CS_PAD_OUT_IDX 62 +#define PCNT_RST_PAD_IN0_IDX 63 +#define SPI2_CS1_PAD_OUT_IDX 63 +#define PCNT_RST_PAD_IN1_IDX 64 +#define SPI2_CS2_PAD_OUT_IDX 64 +#define PCNT_RST_PAD_IN2_IDX 65 +#define SPI2_CS3_PAD_OUT_IDX 65 +#define PCNT_RST_PAD_IN3_IDX 66 +#define SPI2_CS4_PAD_OUT_IDX 66 +#define SPI2_CS5_PAD_OUT_IDX 67 +#define I2C0_SCL_PAD_IN_IDX 68 +#define I2C0_SCL_PAD_OUT_IDX 68 +#define I2C0_SDA_PAD_IN_IDX 69 +#define I2C0_SDA_PAD_OUT_IDX 69 +#define I2C1_SCL_PAD_IN_IDX 70 +#define I2C1_SCL_PAD_OUT_IDX 70 +#define I2C1_SDA_PAD_IN_IDX 71 +#define I2C1_SDA_PAD_OUT_IDX 71 +#define GPIO_SD0_OUT_IDX 72 +#define GPIO_SD1_OUT_IDX 73 +#define UART0_SLP_CLK_PAD_IN_IDX 74 +#define GPIO_SD2_OUT_IDX 74 +#define UART1_SLP_CLK_PAD_IN_IDX 75 +#define GPIO_SD3_OUT_IDX 75 +#define UART2_SLP_CLK_PAD_IN_IDX 76 +#define GPIO_SD4_OUT_IDX 76 +#define UART3_SLP_CLK_PAD_IN_IDX 77 +#define GPIO_SD5_OUT_IDX 77 +#define UART4_SLP_CLK_PAD_IN_IDX 78 +#define GPIO_SD6_OUT_IDX 78 +#define GPIO_SD7_OUT_IDX 79 +#define CAN0_RX_PAD_IN_IDX 80 +#define CAN0_TX_PAD_OUT_IDX 80 +#define CAN0_BUS_OFF_ON_PAD_OUT_IDX 81 +#define CAN0_CLKOUT_PAD_OUT_IDX 82 +#define CAN1_RX_PAD_IN_IDX 83 +#define CAN1_TX_PAD_OUT_IDX 83 +#define CAN1_BUS_OFF_ON_PAD_OUT_IDX 84 +#define CAN1_CLKOUT_PAD_OUT_IDX 85 +#define CAN2_RX_PAD_IN_IDX 86 +#define CAN2_TX_PAD_OUT_IDX 86 +#define CAN2_BUS_OFF_ON_PAD_OUT_IDX 87 +#define CAN2_CLKOUT_PAD_OUT_IDX 88 +#define PWM0_SYNC0_PAD_IN_IDX 89 +#define PWM0_CH0_A_PAD_OUT_IDX 89 +#define PWM0_SYNC1_PAD_IN_IDX 90 +#define PWM0_CH0_B_PAD_OUT_IDX 90 +#define PWM0_SYNC2_PAD_IN_IDX 91 +#define PWM0_CH1_A_PAD_OUT_IDX 91 +#define PWM0_F0_PAD_IN_IDX 92 +#define PWM0_CH1_B_PAD_OUT_IDX 92 +#define PWM0_F1_PAD_IN_IDX 93 +#define PWM0_CH2_A_PAD_OUT_IDX 93 +#define PWM0_F2_PAD_IN_IDX 94 +#define PWM0_CH2_B_PAD_OUT_IDX 94 +#define PWM0_CAP0_PAD_IN_IDX 95 +#define PWM1_CH0_A_PAD_OUT_IDX 95 +#define PWM0_CAP1_PAD_IN_IDX 96 +#define PWM1_CH0_B_PAD_OUT_IDX 96 +#define PWM0_CAP2_PAD_IN_IDX 97 +#define PWM1_CH1_A_PAD_OUT_IDX 97 +#define PWM1_SYNC0_PAD_IN_IDX 98 +#define PWM1_CH1_B_PAD_OUT_IDX 98 +#define PWM1_SYNC1_PAD_IN_IDX 99 +#define PWM1_CH2_A_PAD_OUT_IDX 99 +#define PWM1_SYNC2_PAD_IN_IDX 100 +#define PWM1_CH2_B_PAD_OUT_IDX 100 +#define PWM1_F0_PAD_IN_IDX 101 +#define ADP_CHRG_PAD_OUT_IDX 101 +#define PWM1_F1_PAD_IN_IDX 102 +#define ADP_DISCHRG_PAD_OUT_IDX 102 +#define PWM1_F2_PAD_IN_IDX 103 +#define ADP_PRB_EN_PAD_OUT_IDX 103 +#define PWM1_CAP0_PAD_IN_IDX 104 +#define ADP_SNS_EN_PAD_OUT_IDX 104 +#define PWM1_CAP1_PAD_IN_IDX 105 +#define TWAI0_STANDBY_PAD_OUT_IDX 105 +#define PWM1_CAP2_PAD_IN_IDX 106 +#define TWAI1_STANDBY_PAD_OUT_IDX 106 +#define GMII_MDI_PAD_IN_IDX 107 +#define TWAI2_STANDBY_PAD_OUT_IDX 107 +#define GMAC_PHY_COL_PAD_IN_IDX 108 +#define GMII_MDC_PAD_OUT_IDX 108 +#define GMAC_PHY_CRS_PAD_IN_IDX 109 +#define GMII_MDO_PAD_OUT_IDX 109 +#define USB_OTG11_IDDIG_PAD_IN_IDX 110 +#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110 +#define USB_OTG11_AVALID_PAD_IN_IDX 111 +#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111 +#define USB_SRP_BVALID_PAD_IN_IDX 112 +#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112 +#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113 +#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113 +#define USB_SRP_SESSEND_PAD_IN_IDX 114 +#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114 +#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115 +#define OTG_DRVVBUS_PAD_OUT_IDX 116 +#define ULPI_CLK_PAD_IN_IDX 117 +#define RNG_CHAIN_CLK_PAD_OUT_IDX 117 +#define USB_HSPHY_REFCLK_IN_IDX 118 +#define HP_PROBE_TOP_OUT0_IDX 118 +#define HP_PROBE_TOP_OUT1_IDX 119 +#define HP_PROBE_TOP_OUT2_IDX 120 +#define HP_PROBE_TOP_OUT3_IDX 121 +#define HP_PROBE_TOP_OUT4_IDX 122 +#define HP_PROBE_TOP_OUT5_IDX 123 +#define HP_PROBE_TOP_OUT6_IDX 124 +#define HP_PROBE_TOP_OUT7_IDX 125 +#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126 +#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126 +#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127 +#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127 +#define SD_CARD_INT_N_1_PAD_IN_IDX 128 +#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128 +#define SD_CARD_INT_N_2_PAD_IN_IDX 129 +#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129 +#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130 +#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130 +#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131 +#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131 +#define SD_DATA_STROBE_1_PAD_IN_IDX 132 +#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132 +#define SD_DATA_STROBE_2_PAD_IN_IDX 133 +#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133 +#define I3C_MST_SCL_PAD_IN_IDX 134 +#define I3C_MST_SCL_PAD_OUT_IDX 134 +#define I3C_MST_SDA_PAD_IN_IDX 135 +#define I3C_MST_SDA_PAD_OUT_IDX 135 +#define I3C_SLV_SCL_PAD_IN_IDX 136 +#define I3C_SLV_SCL_PAD_OUT_IDX 136 +#define I3C_SLV_SDA_PAD_IN_IDX 137 +#define I3C_SLV_SDA_PAD_OUT_IDX 137 +#define ADP_PRB_PAD_IN_IDX 138 +#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138 +#define ADP_SNS_PAD_IN_IDX 139 +#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139 +#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140 +#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140 +#define PCNT_SIG_CH0_PAD_IN0_IDX 141 +#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141 +#define PCNT_SIG_CH0_PAD_IN1_IDX 142 +#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142 +#define PCNT_SIG_CH0_PAD_IN2_IDX 143 +#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143 +#define PCNT_SIG_CH0_PAD_IN3_IDX 144 +#define LCD_CS_PAD_OUT_IDX 144 +#define PCNT_SIG_CH1_PAD_IN0_IDX 145 +#define LCD_DC_PAD_OUT_IDX 145 +#define PCNT_SIG_CH1_PAD_IN1_IDX 146 +#define SD_RST_N_1_PAD_OUT_IDX 146 +#define PCNT_SIG_CH1_PAD_IN2_IDX 147 +#define SD_RST_N_2_PAD_OUT_IDX 147 +#define PCNT_SIG_CH1_PAD_IN3_IDX 148 +#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148 +#define PCNT_CTRL_CH0_PAD_IN0_IDX 149 +#define LCD_PCLK_PAD_OUT_IDX 149 +#define PCNT_CTRL_CH0_PAD_IN1_IDX 150 +#define CAM_CLK_PAD_OUT_IDX 150 +#define PCNT_CTRL_CH0_PAD_IN2_IDX 151 +#define LCD_H_ENABLE_PAD_OUT_IDX 151 +#define PCNT_CTRL_CH0_PAD_IN3_IDX 152 +#define LCD_H_SYNC_PAD_OUT_IDX 152 +#define PCNT_CTRL_CH1_PAD_IN0_IDX 153 +#define LCD_V_SYNC_PAD_OUT_IDX 153 +#define PCNT_CTRL_CH1_PAD_IN1_IDX 154 +#define LCD_DATA_OUT_PAD_OUT0_IDX 154 +#define PCNT_CTRL_CH1_PAD_IN2_IDX 155 +#define LCD_DATA_OUT_PAD_OUT1_IDX 155 +#define PCNT_CTRL_CH1_PAD_IN3_IDX 156 +#define LCD_DATA_OUT_PAD_OUT2_IDX 156 +#define LCD_DATA_OUT_PAD_OUT3_IDX 157 +#define CAM_PCLK_PAD_IN_IDX 158 +#define LCD_DATA_OUT_PAD_OUT4_IDX 158 +#define CAM_H_ENABLE_PAD_IN_IDX 159 +#define LCD_DATA_OUT_PAD_OUT5_IDX 159 +#define CAM_H_SYNC_PAD_IN_IDX 160 +#define LCD_DATA_OUT_PAD_OUT6_IDX 160 +#define CAM_V_SYNC_PAD_IN_IDX 161 +#define LCD_DATA_OUT_PAD_OUT7_IDX 161 +#define CAM_DATA_IN_PAD_IN0_IDX 162 +#define LCD_DATA_OUT_PAD_OUT8_IDX 162 +#define CAM_DATA_IN_PAD_IN1_IDX 163 +#define LCD_DATA_OUT_PAD_OUT9_IDX 163 +#define CAM_DATA_IN_PAD_IN2_IDX 164 +#define LCD_DATA_OUT_PAD_OUT10_IDX 164 +#define CAM_DATA_IN_PAD_IN3_IDX 165 +#define LCD_DATA_OUT_PAD_OUT11_IDX 165 +#define CAM_DATA_IN_PAD_IN4_IDX 166 +#define LCD_DATA_OUT_PAD_OUT12_IDX 166 +#define CAM_DATA_IN_PAD_IN5_IDX 167 +#define LCD_DATA_OUT_PAD_OUT13_IDX 167 +#define CAM_DATA_IN_PAD_IN6_IDX 168 +#define LCD_DATA_OUT_PAD_OUT14_IDX 168 +#define CAM_DATA_IN_PAD_IN7_IDX 169 +#define LCD_DATA_OUT_PAD_OUT15_IDX 169 +#define CAM_DATA_IN_PAD_IN8_IDX 170 +#define LCD_DATA_OUT_PAD_OUT16_IDX 170 +#define CAM_DATA_IN_PAD_IN9_IDX 171 +#define LCD_DATA_OUT_PAD_OUT17_IDX 171 +#define CAM_DATA_IN_PAD_IN10_IDX 172 +#define LCD_DATA_OUT_PAD_OUT18_IDX 172 +#define CAM_DATA_IN_PAD_IN11_IDX 173 +#define LCD_DATA_OUT_PAD_OUT19_IDX 173 +#define CAM_DATA_IN_PAD_IN12_IDX 174 +#define LCD_DATA_OUT_PAD_OUT20_IDX 174 +#define CAM_DATA_IN_PAD_IN13_IDX 175 +#define LCD_DATA_OUT_PAD_OUT21_IDX 175 +#define CAM_DATA_IN_PAD_IN14_IDX 176 +#define LCD_DATA_OUT_PAD_OUT22_IDX 176 +#define CAM_DATA_IN_PAD_IN15_IDX 177 +#define LCD_DATA_OUT_PAD_OUT23_IDX 177 +#define GMAC_PHY_RXDV_PAD_IN_IDX 178 +#define GMAC_PHY_TXEN_PAD_OUT_IDX 178 +#define GMAC_PHY_RXD0_PAD_IN_IDX 179 +#define GMAC_PHY_TXD0_PAD_OUT_IDX 179 +#define GMAC_PHY_RXD1_PAD_IN_IDX 180 +#define GMAC_PHY_TXD1_PAD_OUT_IDX 180 +#define GMAC_PHY_RXD2_PAD_IN_IDX 181 +#define GMAC_PHY_TXD2_PAD_OUT_IDX 181 +#define GMAC_PHY_RXD3_PAD_IN_IDX 182 +#define GMAC_PHY_TXD3_PAD_OUT_IDX 182 +#define GMAC_PHY_RXER_PAD_IN_IDX 183 +#define GMAC_PHY_TXER_PAD_OUT_IDX 183 +#define GMAC_RX_CLK_PAD_IN_IDX 184 +#define DBG_CH0_CLK_IDX 184 +#define GMAC_TX_CLK_PAD_IN_IDX 185 +#define DBG_CH1_CLK_IDX 185 +#define PARLIO_RX_CLK_PAD_IN_IDX 186 +#define PARLIO_RX_CLK_PAD_OUT_IDX 186 +#define PARLIO_TX_CLK_PAD_IN_IDX 187 +#define PARLIO_TX_CLK_PAD_OUT_IDX 187 +#define PARLIO_RX_DATA0_PAD_IN_IDX 188 +#define PARLIO_TX_DATA0_PAD_OUT_IDX 188 +#define PARLIO_RX_DATA1_PAD_IN_IDX 189 +#define PARLIO_TX_DATA1_PAD_OUT_IDX 189 +#define PARLIO_RX_DATA2_PAD_IN_IDX 190 +#define PARLIO_TX_DATA2_PAD_OUT_IDX 190 +#define PARLIO_RX_DATA3_PAD_IN_IDX 191 +#define PARLIO_TX_DATA3_PAD_OUT_IDX 191 +#define PARLIO_RX_DATA4_PAD_IN_IDX 192 +#define PARLIO_TX_DATA4_PAD_OUT_IDX 192 +#define PARLIO_RX_DATA5_PAD_IN_IDX 193 +#define PARLIO_TX_DATA5_PAD_OUT_IDX 193 +#define PARLIO_RX_DATA6_PAD_IN_IDX 194 +#define PARLIO_TX_DATA6_PAD_OUT_IDX 194 +#define PARLIO_RX_DATA7_PAD_IN_IDX 195 +#define PARLIO_TX_DATA7_PAD_OUT_IDX 195 +#define PARLIO_RX_DATA8_PAD_IN_IDX 196 +#define PARLIO_TX_DATA8_PAD_OUT_IDX 196 +#define PARLIO_RX_DATA9_PAD_IN_IDX 197 +#define PARLIO_TX_DATA9_PAD_OUT_IDX 197 +#define PARLIO_RX_DATA10_PAD_IN_IDX 198 +#define PARLIO_TX_DATA10_PAD_OUT_IDX 198 +#define PARLIO_RX_DATA11_PAD_IN_IDX 199 +#define PARLIO_TX_DATA11_PAD_OUT_IDX 199 +#define PARLIO_RX_DATA12_PAD_IN_IDX 200 +#define PARLIO_TX_DATA12_PAD_OUT_IDX 200 +#define PARLIO_RX_DATA13_PAD_IN_IDX 201 +#define PARLIO_TX_DATA13_PAD_OUT_IDX 201 +#define PARLIO_RX_DATA14_PAD_IN_IDX 202 +#define PARLIO_TX_DATA14_PAD_OUT_IDX 202 +#define PARLIO_RX_DATA15_PAD_IN_IDX 203 +#define PARLIO_TX_DATA15_PAD_OUT_IDX 203 +#define HP_PROBE_TOP_OUT8_IDX 204 +#define HP_PROBE_TOP_OUT9_IDX 205 +#define HP_PROBE_TOP_OUT10_IDX 206 +#define HP_PROBE_TOP_OUT11_IDX 207 +#define HP_PROBE_TOP_OUT12_IDX 208 +#define HP_PROBE_TOP_OUT13_IDX 209 +#define HP_PROBE_TOP_OUT14_IDX 210 +#define HP_PROBE_TOP_OUT15_IDX 211 +#define CONSTANT0_PAD_OUT_IDX 212 +#define CONSTANT1_PAD_OUT_IDX 213 +#define CORE_GPIO_IN_PAD_IN0_IDX 214 +#define CORE_GPIO_OUT_PAD_OUT0_IDX 214 +#define CORE_GPIO_IN_PAD_IN1_IDX 215 +#define CORE_GPIO_OUT_PAD_OUT1_IDX 215 +#define CORE_GPIO_IN_PAD_IN2_IDX 216 +#define CORE_GPIO_OUT_PAD_OUT2_IDX 216 +#define CORE_GPIO_IN_PAD_IN3_IDX 217 +#define CORE_GPIO_OUT_PAD_OUT3_IDX 217 +#define CORE_GPIO_IN_PAD_IN4_IDX 218 +#define CORE_GPIO_OUT_PAD_OUT4_IDX 218 +#define CORE_GPIO_IN_PAD_IN5_IDX 219 +#define CORE_GPIO_OUT_PAD_OUT5_IDX 219 +#define CORE_GPIO_IN_PAD_IN6_IDX 220 +#define CORE_GPIO_OUT_PAD_OUT6_IDX 220 +#define CORE_GPIO_IN_PAD_IN7_IDX 221 +#define CORE_GPIO_OUT_PAD_OUT7_IDX 221 +#define CORE_GPIO_IN_PAD_IN8_IDX 222 +#define CORE_GPIO_OUT_PAD_OUT8_IDX 222 +#define CORE_GPIO_IN_PAD_IN9_IDX 223 +#define CORE_GPIO_OUT_PAD_OUT9_IDX 223 +#define CORE_GPIO_IN_PAD_IN10_IDX 224 +#define CORE_GPIO_OUT_PAD_OUT10_IDX 224 +#define CORE_GPIO_IN_PAD_IN11_IDX 225 +#define CORE_GPIO_OUT_PAD_OUT11_IDX 225 +#define CORE_GPIO_IN_PAD_IN12_IDX 226 +#define CORE_GPIO_OUT_PAD_OUT12_IDX 226 +#define CORE_GPIO_IN_PAD_IN13_IDX 227 +#define CORE_GPIO_OUT_PAD_OUT13_IDX 227 +#define CORE_GPIO_IN_PAD_IN14_IDX 228 +#define CORE_GPIO_OUT_PAD_OUT14_IDX 228 +#define CORE_GPIO_IN_PAD_IN15_IDX 229 +#define CORE_GPIO_OUT_PAD_OUT15_IDX 229 +#define CORE_GPIO_IN_PAD_IN16_IDX 230 +#define CORE_GPIO_OUT_PAD_OUT16_IDX 230 +#define CORE_GPIO_IN_PAD_IN17_IDX 231 +#define CORE_GPIO_OUT_PAD_OUT17_IDX 231 +#define CORE_GPIO_IN_PAD_IN18_IDX 232 +#define CORE_GPIO_OUT_PAD_OUT18_IDX 232 +#define CORE_GPIO_IN_PAD_IN19_IDX 233 +#define CORE_GPIO_OUT_PAD_OUT19_IDX 233 +#define CORE_GPIO_IN_PAD_IN20_IDX 234 +#define CORE_GPIO_OUT_PAD_OUT20_IDX 234 +#define CORE_GPIO_IN_PAD_IN21_IDX 235 +#define CORE_GPIO_OUT_PAD_OUT21_IDX 235 +#define CORE_GPIO_IN_PAD_IN22_IDX 236 +#define CORE_GPIO_OUT_PAD_OUT22_IDX 236 +#define CORE_GPIO_IN_PAD_IN23_IDX 237 +#define CORE_GPIO_OUT_PAD_OUT23_IDX 237 +#define CORE_GPIO_IN_PAD_IN24_IDX 238 +#define CORE_GPIO_OUT_PAD_OUT24_IDX 238 +#define CORE_GPIO_IN_PAD_IN25_IDX 239 +#define CORE_GPIO_OUT_PAD_OUT25_IDX 239 +#define CORE_GPIO_IN_PAD_IN26_IDX 240 +#define CORE_GPIO_OUT_PAD_OUT26_IDX 240 +#define CORE_GPIO_IN_PAD_IN27_IDX 241 +#define CORE_GPIO_OUT_PAD_OUT27_IDX 241 +#define CORE_GPIO_IN_PAD_IN28_IDX 242 +#define CORE_GPIO_OUT_PAD_OUT28_IDX 242 +#define CORE_GPIO_IN_PAD_IN29_IDX 243 +#define CORE_GPIO_OUT_PAD_OUT29_IDX 243 +#define CORE_GPIO_IN_PAD_IN30_IDX 244 +#define CORE_GPIO_OUT_PAD_OUT30_IDX 244 +#define CORE_GPIO_IN_PAD_IN31_IDX 245 +#define CORE_GPIO_OUT_PAD_OUT31_IDX 245 +#define RMT_SIG_PAD_IN0_IDX 246 +#define RMT_SIG_PAD_OUT0_IDX 246 +#define RMT_SIG_PAD_IN1_IDX 247 +#define RMT_SIG_PAD_OUT1_IDX 247 +#define RMT_SIG_PAD_IN2_IDX 248 +#define RMT_SIG_PAD_OUT2_IDX 248 +#define RMT_SIG_PAD_IN3_IDX 249 +#define RMT_SIG_PAD_OUT3_IDX 249 +#define SIG_IN_FUNC250_IDX 250 +#define SIG_IN_FUNC250_IDX 250 +#define SIG_IN_FUNC251_IDX 251 +#define SIG_IN_FUNC251_IDX 251 +#define SIG_IN_FUNC252_IDX 252 +#define SIG_IN_FUNC252_IDX 252 +#define SIG_IN_FUNC253_IDX 253 +#define SIG_IN_FUNC253_IDX 253 +#define SIG_IN_FUNC254_IDX 254 +#define SIG_IN_FUNC254_IDX 254 +#define SIG_IN_FUNC255_IDX 255 +#define SIG_IN_FUNC255_IDX 255 diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h new file mode 100644 index 0000000000..ac0b5a9ad3 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h @@ -0,0 +1,1624 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE0_LP_RTC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_RTC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M (CORE0_LP_RTC_INT_MAP_V << CORE0_LP_RTC_INT_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M (CORE0_LP_WDT_INT_MAP_V << CORE0_LP_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M (CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_LP_TIMER_REG_0_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M (CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_LP_TIMER_REG_1_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_MB_HP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_MB_HP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_MB_HP_INT_MAP_M (CORE0_MB_HP_INT_MAP_V << CORE0_MB_HP_INT_MAP_S) +#define INTERRUPT_CORE0_MB_HP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MB_HP_INT_MAP_S 0 + +/** INTERRUPT_CORE0_MB_LP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_MB_LP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_MB_LP_INT_MAP_M (CORE0_MB_LP_INT_MAP_V << CORE0_MB_LP_INT_MAP_S) +#define INTERRUPT_CORE0_MB_LP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MB_LP_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M (CORE0_PMU_REG_0_INT_MAP_V << CORE0_PMU_REG_0_INT_MAP_S) +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M (CORE0_PMU_REG_1_INT_MAP_V << CORE0_PMU_REG_1_INT_MAP_S) +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M (CORE0_LP_ANAPERI_INT_MAP_V << CORE0_LP_ANAPERI_INT_MAP_S) +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M (CORE0_LP_ADC_INT_MAP_V << CORE0_LP_ADC_INT_MAP_S) +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M (CORE0_LP_GPIO_INT_MAP_V << CORE0_LP_GPIO_INT_MAP_S) +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_I2C_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_I2C_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M (CORE0_LP_I2C_INT_MAP_V << CORE0_LP_I2C_INT_MAP_S) +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_I2S_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_I2S_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M (CORE0_LP_I2S_INT_MAP_V << CORE0_LP_I2S_INT_MAP_S) +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_SPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M (CORE0_LP_SPI_INT_MAP_V << CORE0_LP_SPI_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M (CORE0_LP_TOUCH_INT_MAP_V << CORE0_LP_TOUCH_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M (CORE0_LP_TSENS_INT_MAP_V << CORE0_LP_TSENS_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_UART_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_UART_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INT_MAP_M (CORE0_LP_UART_INT_MAP_V << CORE0_LP_UART_INT_MAP_S) +#define INTERRUPT_CORE0_LP_UART_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M (CORE0_LP_EFUSE_INT_MAP_V << CORE0_LP_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_SW_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SW_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SW_INT_MAP_M (CORE0_LP_SW_INT_MAP_V << CORE0_LP_SW_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SW_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_SW_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M (CORE0_LP_SYSREG_INT_MAP_V << CORE0_LP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LP_HUK_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_HUK_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M (CORE0_LP_HUK_INT_MAP_V << CORE0_LP_HUK_INT_MAP_S) +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M (CORE0_SYS_ICM_INT_MAP_V << CORE0_SYS_ICM_INT_MAP_S) +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_S 0 + +/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M (CORE0_USB_DEVICE_INT_MAP_V << CORE0_USB_DEVICE_INT_MAP_S) +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M (CORE0_SDIO_HOST_INT_MAP_V << CORE0_SDIO_HOST_INT_MAP_S) +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S 0 + +/** INTERRUPT_CORE0_GDMA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GDMA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GDMA_INT_MAP_M (CORE0_GDMA_INT_MAP_V << CORE0_GDMA_INT_MAP_S) +#define INTERRUPT_CORE0_GDMA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GDMA_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SPI2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SPI2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SPI2_INT_MAP_M (CORE0_SPI2_INT_MAP_V << CORE0_SPI2_INT_MAP_S) +#define INTERRUPT_CORE0_SPI2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SPI2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SPI3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SPI3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SPI3_INT_MAP_M (CORE0_SPI3_INT_MAP_V << CORE0_SPI3_INT_MAP_S) +#define INTERRUPT_CORE0_SPI3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SPI3_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I2S0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S0_INT_MAP_M (CORE0_I2S0_INT_MAP_V << CORE0_I2S0_INT_MAP_S) +#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I2S1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INT_MAP_M (CORE0_I2S1_INT_MAP_V << CORE0_I2S1_INT_MAP_S) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I2S2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S2_INT_MAP_M (CORE0_I2S2_INT_MAP_V << CORE0_I2S2_INT_MAP_S) +#define INTERRUPT_CORE0_I2S2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UHCI0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UHCI0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INT_MAP_M (CORE0_UHCI0_INT_MAP_V << CORE0_UHCI0_INT_MAP_S) +#define INTERRUPT_CORE0_UHCI0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UART0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INT_MAP_M (CORE0_UART0_INT_MAP_V << CORE0_UART0_INT_MAP_S) +#define INTERRUPT_CORE0_UART0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UART1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INT_MAP_M (CORE0_UART1_INT_MAP_V << CORE0_UART1_INT_MAP_S) +#define INTERRUPT_CORE0_UART1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UART2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART2_INT_MAP_M (CORE0_UART2_INT_MAP_V << CORE0_UART2_INT_MAP_S) +#define INTERRUPT_CORE0_UART2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UART3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART3_INT_MAP_M (CORE0_UART3_INT_MAP_V << CORE0_UART3_INT_MAP_S) +#define INTERRUPT_CORE0_UART3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART3_INT_MAP_S 0 + +/** INTERRUPT_CORE0_UART4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART4_INT_MAP_M (CORE0_UART4_INT_MAP_V << CORE0_UART4_INT_MAP_S) +#define INTERRUPT_CORE0_UART4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART4_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M (CORE0_LCD_CAM_INT_MAP_V << CORE0_LCD_CAM_INT_MAP_S) +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0 + +/** INTERRUPT_CORE0_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ADC_INT_MAP_M (CORE0_ADC_INT_MAP_V << CORE0_ADC_INT_MAP_S) +#define INTERRUPT_CORE0_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ADC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PWM0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PWM0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM0_INT_MAP_M (CORE0_PWM0_INT_MAP_V << CORE0_PWM0_INT_MAP_S) +#define INTERRUPT_CORE0_PWM0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PWM1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PWM1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM1_INT_MAP_M (CORE0_PWM1_INT_MAP_V << CORE0_PWM1_INT_MAP_S) +#define INTERRUPT_CORE0_PWM1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CAN0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INT_MAP_M (CORE0_CAN0_INT_MAP_V << CORE0_CAN0_INT_MAP_S) +#define INTERRUPT_CORE0_CAN0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CAN1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INT_MAP_M (CORE0_CAN1_INT_MAP_V << CORE0_CAN1_INT_MAP_S) +#define INTERRUPT_CORE0_CAN1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CAN2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN2_INT_MAP_M (CORE0_CAN2_INT_MAP_V << CORE0_CAN2_INT_MAP_S) +#define INTERRUPT_CORE0_CAN2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_RMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_RMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_RMT_INT_MAP_M (CORE0_RMT_INT_MAP_V << CORE0_RMT_INT_MAP_S) +#define INTERRUPT_CORE0_RMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RMT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I2C0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2C0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C0_INT_MAP_M (CORE0_I2C0_INT_MAP_V << CORE0_I2C0_INT_MAP_S) +#define INTERRUPT_CORE0_I2C0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I2C1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2C1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C1_INT_MAP_M (CORE0_I2C1_INT_MAP_V << CORE0_I2C1_INT_MAP_S) +#define INTERRUPT_CORE0_I2C1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M (CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_TIMERGRP0_T0_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M (CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_TIMERGRP0_T1_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M (CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_TIMERGRP0_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M (CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_TIMERGRP1_T0_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M (CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_TIMERGRP1_T1_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M (CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_TIMERGRP1_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INT_MAP_M (CORE0_LEDC_INT_MAP_V << CORE0_LEDC_INT_MAP_S) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M (CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M (CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M (CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M (CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_AHB_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M (CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_AHB_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M (CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_AHB_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M (CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_AXI_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M (CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_AXI_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M (CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_AXI_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_RSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/** INTERRUPT_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_RSA_INT_MAP_M (CORE0_RSA_INT_MAP_V << CORE0_RSA_INT_MAP_S) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 + +/** INTERRUPT_CORE0_AES_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AES_INT_MAP_M (CORE0_AES_INT_MAP_V << CORE0_AES_INT_MAP_S) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AES_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SHA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INT_MAP_M (CORE0_SHA_INT_MAP_V << CORE0_SHA_INT_MAP_S) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 + +/** INTERRUPT_CORE0_ECC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INT_MAP_M (CORE0_ECC_INT_MAP_V << CORE0_ECC_INT_MAP_S) +#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_ECDSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/** INTERRUPT_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ECDSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INT_MAP_M (CORE0_ECDSA_INT_MAP_V << CORE0_ECDSA_INT_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INT_MAP_S 0 + +/** INTERRUPT_CORE0_KM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/** INTERRUPT_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_KM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_KM_INT_MAP_M (CORE0_KM_INT_MAP_V << CORE0_KM_INT_MAP_S) +#define INTERRUPT_CORE0_KM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_KM_INT_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INT0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/** INTERRUPT_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT0_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT0_MAP_M (CORE0_GPIO_INT0_MAP_V << CORE0_GPIO_INT0_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT0_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INT1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +/** INTERRUPT_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT1_MAP_M (CORE0_GPIO_INT1_MAP_V << CORE0_GPIO_INT1_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT1_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INT2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/** INTERRUPT_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT2_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT2_MAP_M (CORE0_GPIO_INT2_MAP_V << CORE0_GPIO_INT2_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT2_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INT3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/** INTERRUPT_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT3_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT3_MAP_M (CORE0_GPIO_INT3_MAP_V << CORE0_GPIO_INT3_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT3_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M (CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_GPIO_PAD_COMP_INT_MAP_S) +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M (CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CPU_INT_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M (CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CPU_INT_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M (CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CPU_INT_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M (CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CPU_INT_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S 0 + +/** INTERRUPT_CORE0_CACHE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +/** INTERRUPT_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CACHE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INT_MAP_M (CORE0_CACHE_INT_MAP_V << CORE0_CACHE_INT_MAP_S) +#define INTERRUPT_CORE0_CACHE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M (CORE0_FLASH_MSPI_INT_MAP_V << CORE0_FLASH_MSPI_INT_MAP_S) +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M (CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M (CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_DSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CSI_INT_MAP_M (CORE0_CSI_INT_MAP_V << CORE0_CSI_INT_MAP_S) +#define INTERRUPT_CORE0_CSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CSI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DSI_INT_MAP_M (CORE0_DSI_INT_MAP_V << CORE0_DSI_INT_MAP_S) +#define INTERRUPT_CORE0_DSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DSI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/** INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M (CORE0_GMII_PHY_INT_MAP_V << CORE0_GMII_PHY_INT_MAP_S) +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_S 0 + +/** INTERRUPT_CORE0_LPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/** INTERRUPT_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LPI_INT_MAP_M (CORE0_LPI_INT_MAP_V << CORE0_LPI_INT_MAP_S) +#define INTERRUPT_CORE0_LPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LPI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) +/** INTERRUPT_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMT_INT_MAP_M (CORE0_PMT_INT_MAP_V << CORE0_PMT_INT_MAP_S) +#define INTERRUPT_CORE0_PMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_SBD_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/** INTERRUPT_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SBD_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SBD_INT_MAP_M (CORE0_SBD_INT_MAP_V << CORE0_SBD_INT_MAP_S) +#define INTERRUPT_CORE0_SBD_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SBD_INT_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/** INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M (CORE0_USB_OTG_INT_MAP_V << CORE0_USB_OTG_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 + +/** INTERRUPT_CORE0_JPEG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c) +/** INTERRUPT_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_JPEG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_JPEG_INT_MAP_M (CORE0_JPEG_INT_MAP_V << CORE0_JPEG_INT_MAP_S) +#define INTERRUPT_CORE0_JPEG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_JPEG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PPA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/** INTERRUPT_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PPA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PPA_INT_MAP_M (CORE0_PPA_INT_MAP_V << CORE0_PPA_INT_MAP_S) +#define INTERRUPT_CORE0_PPA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PPA_INT_MAP_S 0 + +/** INTERRUPT_CORE0_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/** INTERRUPT_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_M (CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_TRACE_INT_MAP_S) +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M (CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE1_TRACE_INT_MAP_S) +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S 0 + +/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c) +/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M (CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_HP_CORE_CTRL_INT_MAP_S) +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S 0 + +/** INTERRUPT_CORE0_ISP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +/** INTERRUPT_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ISP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ISP_INT_MAP_M (CORE0_ISP_INT_MAP_V << CORE0_ISP_INT_MAP_S) +#define INTERRUPT_CORE0_ISP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ISP_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I3C_MST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +/** INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I3C_MST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M (CORE0_I3C_MST_INT_MAP_V << CORE0_I3C_MST_INT_MAP_S) +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_S 0 + +/** INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +/** INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M (CORE0_I3C_SLV_INT_MAP_V << CORE0_I3C_SLV_INT_MAP_S) +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) +/** INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M (CORE0_USB_OTG11_INT_MAP_V << CORE0_USB_OTG11_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0) +/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M (CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4) +/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M (CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8) +/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M (CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac) +/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M (CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0) +/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M (CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4) +/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M (CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_PSRAM_MSPI_INT_MAP_S) +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S 0 + +/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8) +/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M (CORE0_HP_SYSREG_INT_MAP_V << CORE0_HP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_PCNT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc) +/** INTERRUPT_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PCNT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INT_MAP_M (CORE0_PCNT_INT_MAP_V << CORE0_PCNT_INT_MAP_S) +#define INTERRUPT_CORE0_PCNT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INT_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PAU_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0) +/** INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PAU_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M (CORE0_HP_PAU_INT_MAP_V << CORE0_HP_PAU_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4) +/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M (CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_HP_PARLIO_RX_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8) +/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M (CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_HP_PARLIO_TX_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M (CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_H264_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M (CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_H264_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M (CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_H264_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M (CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_H264_DMA2D_IN_CH3_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M (CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_H264_DMA2D_IN_CH4_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M (CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_H264_DMA2D_IN_CH5_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S 0 + +/** INTERRUPT_CORE0_H264_REG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8) +/** INTERRUPT_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_REG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_REG_INT_MAP_M (CORE0_H264_REG_INT_MAP_V << CORE0_H264_REG_INT_MAP_S) +#define INTERRUPT_CORE0_H264_REG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_H264_REG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M (CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_ASSIST_DEBUG_INT_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S 0 + +/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200) +/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_0_M (CORE0_INTR_STATUS_0_V << CORE0_INTR_STATUS_0_S) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 + +/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204) +/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_1_M (CORE0_INTR_STATUS_1_V << CORE0_INTR_STATUS_1_S) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 + +/** INTERRUPT_CORE0_INTR_STATUS_REG_2_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208) +/** INTERRUPT_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_2_M (CORE0_INTR_STATUS_2_V << CORE0_INTR_STATUS_2_S) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 + +/** INTERRUPT_CORE0_INTR_STATUS_REG_3_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c) +/** INTERRUPT_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_3_M (CORE0_INTR_STATUS_3_V << CORE0_INTR_STATUS_3_S) +#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_3_S 0 + +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * NA + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (CORE0_REG_CLK_EN_V << CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register + * NA + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3fc) +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M (CORE0_INTERRUPT_REG_DATE_V << CORE0_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_struct.h b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h new file mode 100644 index 0000000000..2b5ba97fb8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h @@ -0,0 +1,2298 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: INTERRUPT_CORE0_LP RTC INT MAP REG */ +/** Type of lp_rtc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_rtc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_rtc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP WDT INT MAP REG */ +/** Type of lp_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TIMER REG 0 INT MAP REG */ +/** Type of lp_timer_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_timer_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TIMER REG 1 INT MAP REG */ +/** Type of lp_timer_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_timer_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_MB HP INT MAP REG */ +/** Type of mb_hp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_mb_hp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mb_hp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_MB LP INT MAP REG */ +/** Type of mb_lp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_mb_lp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mb_lp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMU REG 0 INT MAP REG */ +/** Type of pmu_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmu_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMU REG 1 INT MAP REG */ +/** Type of pmu_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmu_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP ANAPERI INT MAP REG */ +/** Type of lp_anaperi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_anaperi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_anaperi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP ADC INT MAP REG */ +/** Type of lp_adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_adc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP GPIO INT MAP REG */ +/** Type of lp_gpio_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_gpio_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_gpio_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP I2C INT MAP REG */ +/** Type of lp_i2c_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_i2c_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2c_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP I2S INT MAP REG */ +/** Type of lp_i2s_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_i2s_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2s_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SPI INT MAP REG */ +/** Type of lp_spi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_spi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_spi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TOUCH INT MAP REG */ +/** Type of lp_touch_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_touch_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_touch_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TSENS INT MAP REG */ +/** Type of lp_tsens_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_tsens_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_tsens_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP UART INT MAP REG */ +/** Type of lp_uart_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_uart_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_uart_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP EFUSE INT MAP REG */ +/** Type of lp_efuse_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_efuse_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_efuse_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SW INT MAP REG */ +/** Type of lp_sw_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_sw_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_sw_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SYSREG INT MAP REG */ +/** Type of lp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP HUK INT MAP REG */ +/** Type of lp_huk_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_huk_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_huk_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYS ICM INT MAP REG */ +/** Type of sys_icm_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sys_icm_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sys_icm_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB DEVICE INT MAP REG */ +/** Type of usb_device_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_device_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_device_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SDIO HOST INT MAP REG */ +/** Type of sdio_host_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sdio_host_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sdio_host_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GDMA INT MAP REG */ +/** Type of gdma_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gdma_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gdma_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SPI2 INT MAP REG */ +/** Type of spi2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_spi2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_spi2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SPI3 INT MAP REG */ +/** Type of spi3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_spi3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_spi3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S0 INT MAP REG */ +/** Type of i2s0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S1 INT MAP REG */ +/** Type of i2s1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S2 INT MAP REG */ +/** Type of i2s2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UHCI0 INT MAP REG */ +/** Type of uhci0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uhci0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uhci0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART0 INT MAP REG */ +/** Type of uart0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART1 INT MAP REG */ +/** Type of uart1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART2 INT MAP REG */ +/** Type of uart2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART3 INT MAP REG */ +/** Type of uart3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART4 INT MAP REG */ +/** Type of uart4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LCD CAM INT MAP REG */ +/** Type of lcd_cam_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lcd_cam_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lcd_cam_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ADC INT MAP REG */ +/** Type of adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_adc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PWM0 INT MAP REG */ +/** Type of pwm0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pwm0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PWM1 INT MAP REG */ +/** Type of pwm1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pwm1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN0 INT MAP REG */ +/** Type of can0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN1 INT MAP REG */ +/** Type of can1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN2 INT MAP REG */ +/** Type of can2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_RMT INT MAP REG */ +/** Type of rmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_rmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rmt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2C0 INT MAP REG */ +/** Type of i2c0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2c0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2C1 INT MAP REG */ +/** Type of i2c1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2c1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 T0 INT MAP REG */ +/** Type of timergrp0_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_t0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 T1 INT MAP REG */ +/** Type of timergrp0_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_t1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 WDT INT MAP REG */ +/** Type of timergrp0_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 T0 INT MAP REG */ +/** Type of timergrp1_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_t0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 T1 INT MAP REG */ +/** Type of timergrp1_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_t1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 WDT INT MAP REG */ +/** Type of timergrp1_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LEDC INT MAP REG */ +/** Type of ledc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ledc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ledc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET0 INT MAP REG */ +/** Type of systimer_target0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET1 INT MAP REG */ +/** Type of systimer_target1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET2 INT MAP REG */ +/** Type of systimer_target2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH0 INT MAP REG */ +/** Type of ahb_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH1 INT MAP REG */ +/** Type of ahb_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH2 INT MAP REG */ +/** Type of ahb_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH0 INT MAP REG */ +/** Type of ahb_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH1 INT MAP REG */ +/** Type of ahb_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH2 INT MAP REG */ +/** Type of ahb_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH0 INT MAP REG */ +/** Type of axi_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH1 INT MAP REG */ +/** Type of axi_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH2 INT MAP REG */ +/** Type of axi_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH0 INT MAP REG */ +/** Type of axi_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH1 INT MAP REG */ +/** Type of axi_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH2 INT MAP REG */ +/** Type of axi_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_RSA INT MAP REG */ +/** Type of rsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_rsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rsa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AES INT MAP REG */ +/** Type of aes_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_aes_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_aes_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_aes_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SHA INT MAP REG */ +/** Type of sha_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sha_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sha_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sha_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ECC INT MAP REG */ +/** Type of ecc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ecc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ECDSA INT MAP REG */ +/** Type of ecdsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ecdsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecdsa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_KM INT MAP REG */ +/** Type of km_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_km_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_km_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_km_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT0 MAP REG */ +/** Type of gpio_int0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int0_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT1 MAP REG */ +/** Type of gpio_int1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int1_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT2 MAP REG */ +/** Type of gpio_int2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int2_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT3 MAP REG */ +/** Type of gpio_int3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int3_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO PAD COMP INT MAP REG */ +/** Type of gpio_pad_comp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_pad_comp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_pad_comp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 0 MAP REG */ +/** Type of cpu_int_from_cpu_0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_0_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 1 MAP REG */ +/** Type of cpu_int_from_cpu_1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_1_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 2 MAP REG */ +/** Type of cpu_int_from_cpu_2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_2_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 3 MAP REG */ +/** Type of cpu_int_from_cpu_3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_3_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CACHE INT MAP REG */ +/** Type of cache_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cache_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cache_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cache_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_FLASH MSPI INT MAP REG */ +/** Type of flash_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_flash_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_flash_mspi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CSI BRIDGE INT MAP REG */ +/** Type of csi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_csi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_csi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DSI BRIDGE INT MAP REG */ +/** Type of dsi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dsi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dsi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CSI INT MAP REG */ +/** Type of csi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_csi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_csi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_csi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DSI INT MAP REG */ +/** Type of dsi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dsi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dsi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GMII PHY INT MAP REG */ +/** Type of gmii_phy_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gmii_phy_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gmii_phy_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LPI INT MAP REG */ +/** Type of lpi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lpi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lpi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMT INT MAP REG */ +/** Type of pmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SBD INT MAP REG */ +/** Type of sbd_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sbd_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sbd_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG INT MAP REG */ +/** Type of usb_otg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG ENDP MULTI PROC INT MAP REG */ +/** Type of usb_otg_endp_multi_proc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg_endp_multi_proc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_JPEG INT MAP REG */ +/** Type of jpeg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_jpeg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_jpeg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PPA INT MAP REG */ +/** Type of ppa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ppa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ppa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_INTERRUPT_CORE0_TRACE INT MAP REG */ +/** Type of interrupt_core0_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_trace_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CORE1 TRACE INT MAP REG */ +/** Type of core1_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_core1_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_core1_trace_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP CORE CTRL INT MAP REG */ +/** Type of hp_core_ctrl_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_core_ctrl_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_core_ctrl_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ISP INT MAP REG */ +/** Type of isp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_isp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_isp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_isp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I3C MST INT MAP REG */ +/** Type of i3c_mst_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i3c_mst_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i3c_mst_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I3C SLV INT MAP REG */ +/** Type of i3c_slv_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i3c_slv_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i3c_slv_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG11 INT MAP REG */ +/** Type of usb_otg11_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg11_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg11_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D IN CH0 INT MAP REG */ +/** Type of dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D IN CH1 INT MAP REG */ +/** Type of dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH0 INT MAP REG */ +/** Type of dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH1 INT MAP REG */ +/** Type of dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH2 INT MAP REG */ +/** Type of dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PSRAM MSPI INT MAP REG */ +/** Type of psram_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_psram_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_psram_mspi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP SYSREG INT MAP REG */ +/** Type of hp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PCNT INT MAP REG */ +/** Type of pcnt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pcnt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pcnt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PAU INT MAP REG */ +/** Type of hp_pau_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_pau_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_pau_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PARLIO RX INT MAP REG */ +/** Type of hp_parlio_rx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_parlio_rx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_parlio_rx_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PARLIO TX INT MAP REG */ +/** Type of hp_parlio_tx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_parlio_tx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_parlio_tx_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH0 INT MAP REG */ +/** Type of h264_dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH1 INT MAP REG */ +/** Type of h264_dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH2 INT MAP REG */ +/** Type of h264_dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH3 INT MAP REG */ +/** Type of h264_dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH4 INT MAP REG */ +/** Type of h264_dma2d_out_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH0 INT MAP REG */ +/** Type of h264_dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH1 INT MAP REG */ +/** Type of h264_dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH2 INT MAP REG */ +/** Type of h264_dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH3 INT MAP REG */ +/** Type of h264_dma2d_in_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH4 INT MAP REG */ +/** Type of h264_dma2d_in_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH5 INT MAP REG */ +/** Type of h264_dma2d_in_ch5_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch5_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 REG INT MAP REG */ +/** Type of h264_reg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_reg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_reg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ASSIST DEBUG INT MAP REG */ +/** Type of assist_debug_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_assist_debug_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_assist_debug_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 0 REG */ +/** Type of intr_status_reg_0 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_0:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_0_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 1 REG */ +/** Type of intr_status_reg_1 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_1:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_1_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 2 REG */ +/** Type of intr_status_reg_2 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_2:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_2_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 3 REG */ +/** Type of intr_status_reg_3 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_3:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_3_reg_t; + + +/** Group: INTERRUPT_CORE0_CLOCK GATE REG */ +/** Type of clock_gate register + * NA + */ +typedef union { + struct { + /** interrupt_core0_reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t interrupt_core0_reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: INTERRUPT_CORE0_INTERRUPT REG DATE REG */ +/** Type of interrupt_reg_date register + * NA + */ +typedef union { + struct { + /** interrupt_core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ + uint32_t interrupt_core0_interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core0_interrupt_reg_date_reg_t; + + +typedef struct { + volatile interrupt_core0_lp_rtc_int_map_reg_t lp_rtc_int_map; + volatile interrupt_core0_lp_wdt_int_map_reg_t lp_wdt_int_map; + volatile interrupt_core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; + volatile interrupt_core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; + volatile interrupt_core0_mb_hp_int_map_reg_t mb_hp_int_map; + volatile interrupt_core0_mb_lp_int_map_reg_t mb_lp_int_map; + volatile interrupt_core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; + volatile interrupt_core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; + volatile interrupt_core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map; + volatile interrupt_core0_lp_adc_int_map_reg_t lp_adc_int_map; + volatile interrupt_core0_lp_gpio_int_map_reg_t lp_gpio_int_map; + volatile interrupt_core0_lp_i2c_int_map_reg_t lp_i2c_int_map; + volatile interrupt_core0_lp_i2s_int_map_reg_t lp_i2s_int_map; + volatile interrupt_core0_lp_spi_int_map_reg_t lp_spi_int_map; + volatile interrupt_core0_lp_touch_int_map_reg_t lp_touch_int_map; + volatile interrupt_core0_lp_tsens_int_map_reg_t lp_tsens_int_map; + volatile interrupt_core0_lp_uart_int_map_reg_t lp_uart_int_map; + volatile interrupt_core0_lp_efuse_int_map_reg_t lp_efuse_int_map; + volatile interrupt_core0_lp_sw_int_map_reg_t lp_sw_int_map; + volatile interrupt_core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map; + volatile interrupt_core0_lp_huk_int_map_reg_t lp_huk_int_map; + volatile interrupt_core0_sys_icm_int_map_reg_t sys_icm_int_map; + volatile interrupt_core0_usb_device_int_map_reg_t usb_device_int_map; + volatile interrupt_core0_sdio_host_int_map_reg_t sdio_host_int_map; + volatile interrupt_core0_gdma_int_map_reg_t gdma_int_map; + volatile interrupt_core0_spi2_int_map_reg_t spi2_int_map; + volatile interrupt_core0_spi3_int_map_reg_t spi3_int_map; + volatile interrupt_core0_i2s0_int_map_reg_t i2s0_int_map; + volatile interrupt_core0_i2s1_int_map_reg_t i2s1_int_map; + volatile interrupt_core0_i2s2_int_map_reg_t i2s2_int_map; + volatile interrupt_core0_uhci0_int_map_reg_t uhci0_int_map; + volatile interrupt_core0_uart0_int_map_reg_t uart0_int_map; + volatile interrupt_core0_uart1_int_map_reg_t uart1_int_map; + volatile interrupt_core0_uart2_int_map_reg_t uart2_int_map; + volatile interrupt_core0_uart3_int_map_reg_t uart3_int_map; + volatile interrupt_core0_uart4_int_map_reg_t uart4_int_map; + volatile interrupt_core0_lcd_cam_int_map_reg_t lcd_cam_int_map; + volatile interrupt_core0_adc_int_map_reg_t adc_int_map; + volatile interrupt_core0_pwm0_int_map_reg_t pwm0_int_map; + volatile interrupt_core0_pwm1_int_map_reg_t pwm1_int_map; + volatile interrupt_core0_can0_int_map_reg_t can0_int_map; + volatile interrupt_core0_can1_int_map_reg_t can1_int_map; + volatile interrupt_core0_can2_int_map_reg_t can2_int_map; + volatile interrupt_core0_rmt_int_map_reg_t rmt_int_map; + volatile interrupt_core0_i2c0_int_map_reg_t i2c0_int_map; + volatile interrupt_core0_i2c1_int_map_reg_t i2c1_int_map; + volatile interrupt_core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; + volatile interrupt_core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; + volatile interrupt_core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; + volatile interrupt_core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; + volatile interrupt_core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; + volatile interrupt_core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; + volatile interrupt_core0_ledc_int_map_reg_t ledc_int_map; + volatile interrupt_core0_systimer_target0_int_map_reg_t systimer_target0_int_map; + volatile interrupt_core0_systimer_target1_int_map_reg_t systimer_target1_int_map; + volatile interrupt_core0_systimer_target2_int_map_reg_t systimer_target2_int_map; + volatile interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; + volatile interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; + volatile interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; + volatile interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; + volatile interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; + volatile interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; + volatile interrupt_core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; + volatile interrupt_core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; + volatile interrupt_core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; + volatile interrupt_core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; + volatile interrupt_core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; + volatile interrupt_core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; + volatile interrupt_core0_rsa_int_map_reg_t rsa_int_map; + volatile interrupt_core0_aes_int_map_reg_t aes_int_map; + volatile interrupt_core0_sha_int_map_reg_t sha_int_map; + volatile interrupt_core0_ecc_int_map_reg_t ecc_int_map; + volatile interrupt_core0_ecdsa_int_map_reg_t ecdsa_int_map; + volatile interrupt_core0_km_int_map_reg_t km_int_map; + volatile interrupt_core0_gpio_int0_map_reg_t gpio_int0_map; + volatile interrupt_core0_gpio_int1_map_reg_t gpio_int1_map; + volatile interrupt_core0_gpio_int2_map_reg_t gpio_int2_map; + volatile interrupt_core0_gpio_int3_map_reg_t gpio_int3_map; + volatile interrupt_core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; + volatile interrupt_core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; + volatile interrupt_core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; + volatile interrupt_core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; + volatile interrupt_core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; + volatile interrupt_core0_cache_int_map_reg_t cache_int_map; + volatile interrupt_core0_flash_mspi_int_map_reg_t flash_mspi_int_map; + volatile interrupt_core0_csi_bridge_int_map_reg_t csi_bridge_int_map; + volatile interrupt_core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map; + volatile interrupt_core0_csi_int_map_reg_t csi_int_map; + volatile interrupt_core0_dsi_int_map_reg_t dsi_int_map; + volatile interrupt_core0_gmii_phy_int_map_reg_t gmii_phy_int_map; + volatile interrupt_core0_lpi_int_map_reg_t lpi_int_map; + volatile interrupt_core0_pmt_int_map_reg_t pmt_int_map; + volatile interrupt_core0_sbd_int_map_reg_t sbd_int_map; + volatile interrupt_core0_usb_otg_int_map_reg_t usb_otg_int_map; + volatile interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; + volatile interrupt_core0_jpeg_int_map_reg_t jpeg_int_map; + volatile interrupt_core0_ppa_int_map_reg_t ppa_int_map; + volatile interrupt_core0_trace_int_map_reg_t interrupt_core0_trace_int_map; + volatile interrupt_core0_core1_trace_int_map_reg_t core1_trace_int_map; + volatile interrupt_core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; + volatile interrupt_core0_isp_int_map_reg_t isp_int_map; + volatile interrupt_core0_i3c_mst_int_map_reg_t i3c_mst_int_map; + volatile interrupt_core0_i3c_slv_int_map_reg_t i3c_slv_int_map; + volatile interrupt_core0_usb_otg11_int_map_reg_t usb_otg11_int_map; + volatile interrupt_core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; + volatile interrupt_core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; + volatile interrupt_core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; + volatile interrupt_core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; + volatile interrupt_core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; + volatile interrupt_core0_psram_mspi_int_map_reg_t psram_mspi_int_map; + volatile interrupt_core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map; + volatile interrupt_core0_pcnt_int_map_reg_t pcnt_int_map; + volatile interrupt_core0_hp_pau_int_map_reg_t hp_pau_int_map; + volatile interrupt_core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; + volatile interrupt_core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; + volatile interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; + volatile interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; + volatile interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; + volatile interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; + volatile interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; + volatile interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; + volatile interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; + volatile interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; + volatile interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; + volatile interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; + volatile interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; + volatile interrupt_core0_h264_reg_int_map_reg_t h264_reg_int_map; + volatile interrupt_core0_assist_debug_int_map_reg_t assist_debug_int_map; + volatile interrupt_core0_intr_status_reg_0_reg_t intr_status_reg_0; + volatile interrupt_core0_intr_status_reg_1_reg_t intr_status_reg_1; + volatile interrupt_core0_intr_status_reg_2_reg_t intr_status_reg_2; + volatile interrupt_core0_intr_status_reg_3_reg_t intr_status_reg_3; + volatile interrupt_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_214[122]; + volatile interrupt_core0_interrupt_reg_date_reg_t interrupt_reg_date; +} interrupt_core0_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core0_dev_t) == 0x400, "Invalid size of interrupt_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h new file mode 100644 index 0000000000..d4afbcfbe1 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h @@ -0,0 +1,1624 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE1_LP_RTC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0) +/** INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_RTC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M (INTERRUPT_CORE1_LP_RTC_INT_MAP_V << INTERRUPT_CORE1_LP_RTC_INT_MAP_S) +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4) +/** INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M (INTERRUPT_CORE1_LP_WDT_INT_MAP_V << INTERRUPT_CORE1_LP_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8) +/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M (INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc) +/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M (INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_MB_HP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10) +/** INTERRUPT_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_MB_HP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_MB_HP_INT_MAP_M (INTERRUPT_CORE1_MB_HP_INT_MAP_V << INTERRUPT_CORE1_MB_HP_INT_MAP_S) +#define INTERRUPT_CORE1_MB_HP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_MB_HP_INT_MAP_S 0 + +/** INTERRUPT_CORE1_MB_LP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14) +/** INTERRUPT_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_MB_LP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_MB_LP_INT_MAP_M (INTERRUPT_CORE1_MB_LP_INT_MAP_V << INTERRUPT_CORE1_MB_LP_INT_MAP_S) +#define INTERRUPT_CORE1_MB_LP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_MB_LP_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18) +/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M (INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c) +/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M (INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20) +/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M (INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V << INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S) +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24) +/** INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M (INTERRUPT_CORE1_LP_ADC_INT_MAP_V << INTERRUPT_CORE1_LP_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28) +/** INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M (INTERRUPT_CORE1_LP_GPIO_INT_MAP_V << INTERRUPT_CORE1_LP_GPIO_INT_MAP_S) +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_I2C_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c) +/** INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_I2C_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M (INTERRUPT_CORE1_LP_I2C_INT_MAP_V << INTERRUPT_CORE1_LP_I2C_INT_MAP_S) +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_I2S_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30) +/** INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_I2S_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M (INTERRUPT_CORE1_LP_I2S_INT_MAP_V << INTERRUPT_CORE1_LP_I2S_INT_MAP_S) +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_SPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34) +/** INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M (INTERRUPT_CORE1_LP_SPI_INT_MAP_V << INTERRUPT_CORE1_LP_SPI_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38) +/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M (INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V << INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c) +/** INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M (INTERRUPT_CORE1_LP_TSENS_INT_MAP_V << INTERRUPT_CORE1_LP_TSENS_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_UART_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40) +/** INTERRUPT_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_UART_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_UART_INT_MAP_M (INTERRUPT_CORE1_LP_UART_INT_MAP_V << INTERRUPT_CORE1_LP_UART_INT_MAP_S) +#define INTERRUPT_CORE1_LP_UART_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_UART_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44) +/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M (INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V << INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_SW_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48) +/** INTERRUPT_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SW_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SW_INT_MAP_M (INTERRUPT_CORE1_LP_SW_INT_MAP_V << INTERRUPT_CORE1_LP_SW_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SW_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_SW_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c) +/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M (INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LP_HUK_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50) +/** INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_HUK_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M (INTERRUPT_CORE1_LP_HUK_INT_MAP_V << INTERRUPT_CORE1_LP_HUK_INT_MAP_S) +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54) +/** INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M (INTERRUPT_CORE1_SYS_ICM_INT_MAP_V << INTERRUPT_CORE1_SYS_ICM_INT_MAP_S) +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_S 0 + +/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58) +/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M (INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V << INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S) +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c) +/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M (INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V << INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S) +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S 0 + +/** INTERRUPT_CORE1_GDMA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60) +/** INTERRUPT_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GDMA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GDMA_INT_MAP_M (INTERRUPT_CORE1_GDMA_INT_MAP_V << INTERRUPT_CORE1_GDMA_INT_MAP_S) +#define INTERRUPT_CORE1_GDMA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GDMA_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SPI2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64) +/** INTERRUPT_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SPI2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SPI2_INT_MAP_M (INTERRUPT_CORE1_SPI2_INT_MAP_V << INTERRUPT_CORE1_SPI2_INT_MAP_S) +#define INTERRUPT_CORE1_SPI2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SPI2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SPI3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68) +/** INTERRUPT_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SPI3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SPI3_INT_MAP_M (INTERRUPT_CORE1_SPI3_INT_MAP_V << INTERRUPT_CORE1_SPI3_INT_MAP_S) +#define INTERRUPT_CORE1_SPI3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SPI3_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I2S0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c) +/** INTERRUPT_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S0_INT_MAP_M (INTERRUPT_CORE1_I2S0_INT_MAP_V << INTERRUPT_CORE1_I2S0_INT_MAP_S) +#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I2S1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70) +/** INTERRUPT_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S1_INT_MAP_M (INTERRUPT_CORE1_I2S1_INT_MAP_V << INTERRUPT_CORE1_I2S1_INT_MAP_S) +#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I2S2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74) +/** INTERRUPT_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S2_INT_MAP_M (INTERRUPT_CORE1_I2S2_INT_MAP_V << INTERRUPT_CORE1_I2S2_INT_MAP_S) +#define INTERRUPT_CORE1_I2S2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I2S2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UHCI0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78) +/** INTERRUPT_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UHCI0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UHCI0_INT_MAP_M (INTERRUPT_CORE1_UHCI0_INT_MAP_V << INTERRUPT_CORE1_UHCI0_INT_MAP_S) +#define INTERRUPT_CORE1_UHCI0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UHCI0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UART0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c) +/** INTERRUPT_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART0_INT_MAP_M (INTERRUPT_CORE1_UART0_INT_MAP_V << INTERRUPT_CORE1_UART0_INT_MAP_S) +#define INTERRUPT_CORE1_UART0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UART0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UART1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80) +/** INTERRUPT_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART1_INT_MAP_M (INTERRUPT_CORE1_UART1_INT_MAP_V << INTERRUPT_CORE1_UART1_INT_MAP_S) +#define INTERRUPT_CORE1_UART1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UART1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UART2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84) +/** INTERRUPT_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART2_INT_MAP_M (INTERRUPT_CORE1_UART2_INT_MAP_V << INTERRUPT_CORE1_UART2_INT_MAP_S) +#define INTERRUPT_CORE1_UART2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UART2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UART3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88) +/** INTERRUPT_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART3_INT_MAP_M (INTERRUPT_CORE1_UART3_INT_MAP_V << INTERRUPT_CORE1_UART3_INT_MAP_S) +#define INTERRUPT_CORE1_UART3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UART3_INT_MAP_S 0 + +/** INTERRUPT_CORE1_UART4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c) +/** INTERRUPT_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART4_INT_MAP_M (INTERRUPT_CORE1_UART4_INT_MAP_V << INTERRUPT_CORE1_UART4_INT_MAP_S) +#define INTERRUPT_CORE1_UART4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_UART4_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90) +/** INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M (INTERRUPT_CORE1_LCD_CAM_INT_MAP_V << INTERRUPT_CORE1_LCD_CAM_INT_MAP_S) +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0 + +/** INTERRUPT_CORE1_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94) +/** INTERRUPT_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ADC_INT_MAP_M (INTERRUPT_CORE1_ADC_INT_MAP_V << INTERRUPT_CORE1_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_ADC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PWM0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98) +/** INTERRUPT_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PWM0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PWM0_INT_MAP_M (INTERRUPT_CORE1_PWM0_INT_MAP_V << INTERRUPT_CORE1_PWM0_INT_MAP_S) +#define INTERRUPT_CORE1_PWM0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PWM0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PWM1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c) +/** INTERRUPT_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PWM1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PWM1_INT_MAP_M (INTERRUPT_CORE1_PWM1_INT_MAP_V << INTERRUPT_CORE1_PWM1_INT_MAP_S) +#define INTERRUPT_CORE1_PWM1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PWM1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CAN0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0) +/** INTERRUPT_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN0_INT_MAP_M (INTERRUPT_CORE1_CAN0_INT_MAP_V << INTERRUPT_CORE1_CAN0_INT_MAP_S) +#define INTERRUPT_CORE1_CAN0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CAN0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CAN1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4) +/** INTERRUPT_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN1_INT_MAP_M (INTERRUPT_CORE1_CAN1_INT_MAP_V << INTERRUPT_CORE1_CAN1_INT_MAP_S) +#define INTERRUPT_CORE1_CAN1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CAN1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CAN2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8) +/** INTERRUPT_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN2_INT_MAP_M (INTERRUPT_CORE1_CAN2_INT_MAP_V << INTERRUPT_CORE1_CAN2_INT_MAP_S) +#define INTERRUPT_CORE1_CAN2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CAN2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_RMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac) +/** INTERRUPT_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_RMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_RMT_INT_MAP_M (INTERRUPT_CORE1_RMT_INT_MAP_V << INTERRUPT_CORE1_RMT_INT_MAP_S) +#define INTERRUPT_CORE1_RMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_RMT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I2C0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0) +/** INTERRUPT_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2C0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2C0_INT_MAP_M (INTERRUPT_CORE1_I2C0_INT_MAP_V << INTERRUPT_CORE1_I2C0_INT_MAP_S) +#define INTERRUPT_CORE1_I2C0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I2C0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I2C1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4) +/** INTERRUPT_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2C1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2C1_INT_MAP_M (INTERRUPT_CORE1_I2C1_INT_MAP_V << INTERRUPT_CORE1_I2C1_INT_MAP_S) +#define INTERRUPT_CORE1_I2C1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I2C1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8) +/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc) +/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0) +/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4) +/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8) +/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc) +/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LEDC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0) +/** INTERRUPT_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LEDC_INT_MAP_M (INTERRUPT_CORE1_LEDC_INT_MAP_V << INTERRUPT_CORE1_LEDC_INT_MAP_S) +#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4) +/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8) +/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc) +/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_RSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110) +/** INTERRUPT_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_RSA_INT_MAP_M (INTERRUPT_CORE1_RSA_INT_MAP_V << INTERRUPT_CORE1_RSA_INT_MAP_S) +#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_RSA_INT_MAP_S 0 + +/** INTERRUPT_CORE1_AES_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114) +/** INTERRUPT_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AES_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AES_INT_MAP_M (INTERRUPT_CORE1_AES_INT_MAP_V << INTERRUPT_CORE1_AES_INT_MAP_S) +#define INTERRUPT_CORE1_AES_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_AES_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SHA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118) +/** INTERRUPT_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SHA_INT_MAP_M (INTERRUPT_CORE1_SHA_INT_MAP_V << INTERRUPT_CORE1_SHA_INT_MAP_S) +#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SHA_INT_MAP_S 0 + +/** INTERRUPT_CORE1_ECC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c) +/** INTERRUPT_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ECC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ECC_INT_MAP_M (INTERRUPT_CORE1_ECC_INT_MAP_V << INTERRUPT_CORE1_ECC_INT_MAP_S) +#define INTERRUPT_CORE1_ECC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_ECC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_ECDSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120) +/** INTERRUPT_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ECDSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ECDSA_INT_MAP_M (INTERRUPT_CORE1_ECDSA_INT_MAP_V << INTERRUPT_CORE1_ECDSA_INT_MAP_S) +#define INTERRUPT_CORE1_ECDSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_ECDSA_INT_MAP_S 0 + +/** INTERRUPT_CORE1_KM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124) +/** INTERRUPT_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_KM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_KM_INT_MAP_M (INTERRUPT_CORE1_KM_INT_MAP_V << INTERRUPT_CORE1_KM_INT_MAP_S) +#define INTERRUPT_CORE1_KM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_KM_INT_MAP_S 0 + +/** INTERRUPT_CORE1_GPIO_INT0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128) +/** INTERRUPT_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT0_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT0_MAP_M (INTERRUPT_CORE1_GPIO_INT0_MAP_V << INTERRUPT_CORE1_GPIO_INT0_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT0_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT0_MAP_S 0 + +/** INTERRUPT_CORE1_GPIO_INT1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c) +/** INTERRUPT_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT1_MAP_M (INTERRUPT_CORE1_GPIO_INT1_MAP_V << INTERRUPT_CORE1_GPIO_INT1_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT1_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT1_MAP_S 0 + +/** INTERRUPT_CORE1_GPIO_INT2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130) +/** INTERRUPT_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT2_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT2_MAP_M (INTERRUPT_CORE1_GPIO_INT2_MAP_V << INTERRUPT_CORE1_GPIO_INT2_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT2_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT2_MAP_S 0 + +/** INTERRUPT_CORE1_GPIO_INT3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134) +/** INTERRUPT_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT3_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT3_MAP_M (INTERRUPT_CORE1_GPIO_INT3_MAP_V << INTERRUPT_CORE1_GPIO_INT3_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT3_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT3_MAP_S 0 + +/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138) +/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M (INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V << INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S) +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S 0 + +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S 0 + +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S 0 + +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S 0 + +/** INTERRUPT_CORE1_CACHE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c) +/** INTERRUPT_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CACHE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CACHE_INT_MAP_M (INTERRUPT_CORE1_CACHE_INT_MAP_V << INTERRUPT_CORE1_CACHE_INT_MAP_S) +#define INTERRUPT_CORE1_CACHE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CACHE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150) +/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M (INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V << INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154) +/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M (INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158) +/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M (INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c) +/** INTERRUPT_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CSI_INT_MAP_M (INTERRUPT_CORE1_CSI_INT_MAP_V << INTERRUPT_CORE1_CSI_INT_MAP_S) +#define INTERRUPT_CORE1_CSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CSI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160) +/** INTERRUPT_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DSI_INT_MAP_M (INTERRUPT_CORE1_DSI_INT_MAP_V << INTERRUPT_CORE1_DSI_INT_MAP_S) +#define INTERRUPT_CORE1_DSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DSI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164) +/** INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M (INTERRUPT_CORE1_GMII_PHY_INT_MAP_V << INTERRUPT_CORE1_GMII_PHY_INT_MAP_S) +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_S 0 + +/** INTERRUPT_CORE1_LPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168) +/** INTERRUPT_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LPI_INT_MAP_M (INTERRUPT_CORE1_LPI_INT_MAP_V << INTERRUPT_CORE1_LPI_INT_MAP_S) +#define INTERRUPT_CORE1_LPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_LPI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c) +/** INTERRUPT_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMT_INT_MAP_M (INTERRUPT_CORE1_PMT_INT_MAP_V << INTERRUPT_CORE1_PMT_INT_MAP_S) +#define INTERRUPT_CORE1_PMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PMT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_SBD_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170) +/** INTERRUPT_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SBD_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SBD_INT_MAP_M (INTERRUPT_CORE1_SBD_INT_MAP_V << INTERRUPT_CORE1_SBD_INT_MAP_S) +#define INTERRUPT_CORE1_SBD_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_SBD_INT_MAP_S 0 + +/** INTERRUPT_CORE1_USB_OTG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174) +/** INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M (INTERRUPT_CORE1_USB_OTG_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178) +/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 + +/** INTERRUPT_CORE1_JPEG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c) +/** INTERRUPT_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_JPEG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_JPEG_INT_MAP_M (INTERRUPT_CORE1_JPEG_INT_MAP_V << INTERRUPT_CORE1_JPEG_INT_MAP_S) +#define INTERRUPT_CORE1_JPEG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_JPEG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PPA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180) +/** INTERRUPT_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PPA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PPA_INT_MAP_M (INTERRUPT_CORE1_PPA_INT_MAP_V << INTERRUPT_CORE1_PPA_INT_MAP_S) +#define INTERRUPT_CORE1_PPA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PPA_INT_MAP_S 0 + +/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184) +/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M (INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188) +/** INTERRUPT_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_M (INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S 0 + +/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c) +/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M (INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V << INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S) +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S 0 + +/** INTERRUPT_CORE1_ISP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190) +/** INTERRUPT_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ISP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ISP_INT_MAP_M (INTERRUPT_CORE1_ISP_INT_MAP_V << INTERRUPT_CORE1_ISP_INT_MAP_S) +#define INTERRUPT_CORE1_ISP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_ISP_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I3C_MST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194) +/** INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I3C_MST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M (INTERRUPT_CORE1_I3C_MST_INT_MAP_V << INTERRUPT_CORE1_I3C_MST_INT_MAP_S) +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_S 0 + +/** INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198) +/** INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M (INTERRUPT_CORE1_I3C_SLV_INT_MAP_V << INTERRUPT_CORE1_I3C_SLV_INT_MAP_S) +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_S 0 + +/** INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c) +/** INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M (INTERRUPT_CORE1_USB_OTG11_INT_MAP_V << INTERRUPT_CORE1_USB_OTG11_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0) +/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4) +/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8) +/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac) +/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0) +/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4) +/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M (INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V << INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S 0 + +/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8) +/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M (INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_PCNT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc) +/** INTERRUPT_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PCNT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PCNT_INT_MAP_M (INTERRUPT_CORE1_PCNT_INT_MAP_V << INTERRUPT_CORE1_PCNT_INT_MAP_S) +#define INTERRUPT_CORE1_PCNT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_PCNT_INT_MAP_S 0 + +/** INTERRUPT_CORE1_HP_PAU_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0) +/** INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PAU_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M (INTERRUPT_CORE1_HP_PAU_INT_MAP_V << INTERRUPT_CORE1_HP_PAU_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_S 0 + +/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4) +/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M (INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S 0 + +/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8) +/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M (INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S 0 + +/** INTERRUPT_CORE1_H264_REG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8) +/** INTERRUPT_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_REG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_REG_INT_MAP_M (INTERRUPT_CORE1_H264_REG_INT_MAP_V << INTERRUPT_CORE1_H264_REG_INT_MAP_S) +#define INTERRUPT_CORE1_H264_REG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_H264_REG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc) +/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M (INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V << INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S) +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S 0 + +/** INTERRUPT_CORE1_INTR_STATUS_REG_0_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200) +/** INTERRUPT_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_0_M (INTERRUPT_CORE1_INTR_STATUS_0_V << INTERRUPT_CORE1_INTR_STATUS_0_S) +#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_0_S 0 + +/** INTERRUPT_CORE1_INTR_STATUS_REG_1_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204) +/** INTERRUPT_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_1_M (INTERRUPT_CORE1_INTR_STATUS_1_V << INTERRUPT_CORE1_INTR_STATUS_1_S) +#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_1_S 0 + +/** INTERRUPT_CORE1_INTR_STATUS_REG_2_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208) +/** INTERRUPT_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_2_M (INTERRUPT_CORE1_INTR_STATUS_2_V << INTERRUPT_CORE1_INTR_STATUS_2_S) +#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_2_S 0 + +/** INTERRUPT_CORE1_INTR_STATUS_REG_3_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c) +/** INTERRUPT_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_3_M (INTERRUPT_CORE1_INTR_STATUS_3_V << INTERRUPT_CORE1_INTR_STATUS_3_S) +#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_3_S 0 + +/** INTERRUPT_CORE1_CLOCK_GATE_REG register + * NA + */ +#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210) +/** INTERRUPT_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ +#define INTERRUPT_CORE1_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE1_REG_CLK_EN_M (INTERRUPT_CORE1_REG_CLK_EN_V << INTERRUPT_CORE1_REG_CLK_EN_S) +#define INTERRUPT_CORE1_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE1_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG register + * NA + */ +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3fc) +/** INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M (INTERRUPT_CORE1_INTERRUPT_REG_DATE_V << INTERRUPT_CORE1_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_struct.h b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h new file mode 100644 index 0000000000..8ded5f7582 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h @@ -0,0 +1,2298 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: INTERRUPT CORE1LP RTC INT MAP REG */ +/** Type of lp_rtc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_rtc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_rtc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP WDT INT MAP REG */ +/** Type of lp_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TIMER REG 0 INT MAP REG */ +/** Type of lp_timer_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_timer_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_timer_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TIMER REG 1 INT MAP REG */ +/** Type of lp_timer_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_timer_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_timer_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1MB HP INT MAP REG */ +/** Type of mb_hp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_mb_hp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_mb_hp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1MB LP INT MAP REG */ +/** Type of mb_lp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_mb_lp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_mb_lp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMU REG 0 INT MAP REG */ +/** Type of pmu_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmu_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmu_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMU REG 1 INT MAP REG */ +/** Type of pmu_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmu_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmu_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP ANAPERI INT MAP REG */ +/** Type of lp_anaperi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_anaperi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_anaperi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP ADC INT MAP REG */ +/** Type of lp_adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_adc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP GPIO INT MAP REG */ +/** Type of lp_gpio_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_gpio_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_gpio_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP I2C INT MAP REG */ +/** Type of lp_i2c_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_i2c_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_i2c_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP I2S INT MAP REG */ +/** Type of lp_i2s_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_i2s_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_i2s_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SPI INT MAP REG */ +/** Type of lp_spi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_spi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_spi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TOUCH INT MAP REG */ +/** Type of lp_touch_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_touch_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_touch_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TSENS INT MAP REG */ +/** Type of lp_tsens_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_tsens_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_tsens_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP UART INT MAP REG */ +/** Type of lp_uart_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_uart_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_uart_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP EFUSE INT MAP REG */ +/** Type of lp_efuse_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_efuse_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_efuse_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SW INT MAP REG */ +/** Type of lp_sw_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_sw_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_sw_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SYSREG INT MAP REG */ +/** Type of lp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP HUK INT MAP REG */ +/** Type of lp_huk_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_huk_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_huk_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYS ICM INT MAP REG */ +/** Type of sys_icm_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sys_icm_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sys_icm_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB DEVICE INT MAP REG */ +/** Type of usb_device_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_device_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_device_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SDIO HOST INT MAP REG */ +/** Type of sdio_host_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sdio_host_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sdio_host_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GDMA INT MAP REG */ +/** Type of gdma_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gdma_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gdma_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SPI2 INT MAP REG */ +/** Type of spi2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_spi2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_spi2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SPI3 INT MAP REG */ +/** Type of spi3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_spi3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_spi3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S0 INT MAP REG */ +/** Type of i2s0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S1 INT MAP REG */ +/** Type of i2s1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S2 INT MAP REG */ +/** Type of i2s2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UHCI0 INT MAP REG */ +/** Type of uhci0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uhci0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uhci0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART0 INT MAP REG */ +/** Type of uart0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART1 INT MAP REG */ +/** Type of uart1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART2 INT MAP REG */ +/** Type of uart2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART3 INT MAP REG */ +/** Type of uart3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART4 INT MAP REG */ +/** Type of uart4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LCD CAM INT MAP REG */ +/** Type of lcd_cam_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lcd_cam_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lcd_cam_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ADC INT MAP REG */ +/** Type of adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_adc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PWM0 INT MAP REG */ +/** Type of pwm0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pwm0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pwm0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PWM1 INT MAP REG */ +/** Type of pwm1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pwm1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pwm1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN0 INT MAP REG */ +/** Type of can0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN1 INT MAP REG */ +/** Type of can1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN2 INT MAP REG */ +/** Type of can2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1RMT INT MAP REG */ +/** Type of rmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_rmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_rmt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2C0 INT MAP REG */ +/** Type of i2c0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2c0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2c0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2C1 INT MAP REG */ +/** Type of i2c1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2c1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2c1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 T0 INT MAP REG */ +/** Type of timergrp0_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_t0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 T1 INT MAP REG */ +/** Type of timergrp0_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_t1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 WDT INT MAP REG */ +/** Type of timergrp0_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 T0 INT MAP REG */ +/** Type of timergrp1_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_t0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 T1 INT MAP REG */ +/** Type of timergrp1_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_t1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 WDT INT MAP REG */ +/** Type of timergrp1_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LEDC INT MAP REG */ +/** Type of ledc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ledc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ledc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET0 INT MAP REG */ +/** Type of systimer_target0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET1 INT MAP REG */ +/** Type of systimer_target1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET2 INT MAP REG */ +/** Type of systimer_target2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH0 INT MAP REG */ +/** Type of ahb_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH1 INT MAP REG */ +/** Type of ahb_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH2 INT MAP REG */ +/** Type of ahb_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH0 INT MAP REG */ +/** Type of ahb_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH1 INT MAP REG */ +/** Type of ahb_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH2 INT MAP REG */ +/** Type of ahb_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH0 INT MAP REG */ +/** Type of axi_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH1 INT MAP REG */ +/** Type of axi_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH2 INT MAP REG */ +/** Type of axi_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH0 INT MAP REG */ +/** Type of axi_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH1 INT MAP REG */ +/** Type of axi_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH2 INT MAP REG */ +/** Type of axi_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1RSA INT MAP REG */ +/** Type of rsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_rsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_rsa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AES INT MAP REG */ +/** Type of aes_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_aes_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_aes_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_aes_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SHA INT MAP REG */ +/** Type of sha_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sha_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sha_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sha_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ECC INT MAP REG */ +/** Type of ecc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ecc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ecc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ECDSA INT MAP REG */ +/** Type of ecdsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ecdsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ecdsa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1KM INT MAP REG */ +/** Type of km_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_km_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_km_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_km_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT0 MAP REG */ +/** Type of gpio_int0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int0_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT1 MAP REG */ +/** Type of gpio_int1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int1_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT2 MAP REG */ +/** Type of gpio_int2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int2_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT3 MAP REG */ +/** Type of gpio_int3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int3_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO PAD COMP INT MAP REG */ +/** Type of gpio_pad_comp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_pad_comp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_pad_comp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 0 MAP REG */ +/** Type of cpu_int_from_cpu_0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_0_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 1 MAP REG */ +/** Type of cpu_int_from_cpu_1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_1_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 2 MAP REG */ +/** Type of cpu_int_from_cpu_2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_2_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 3 MAP REG */ +/** Type of cpu_int_from_cpu_3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_3_map_reg_t; + + +/** Group: INTERRUPT CORE1CACHE INT MAP REG */ +/** Type of cache_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cache_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cache_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cache_int_map_reg_t; + + +/** Group: INTERRUPT CORE1FLASH MSPI INT MAP REG */ +/** Type of flash_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_flash_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_flash_mspi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CSI BRIDGE INT MAP REG */ +/** Type of csi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_csi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_csi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DSI BRIDGE INT MAP REG */ +/** Type of dsi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dsi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dsi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CSI INT MAP REG */ +/** Type of csi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_csi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_csi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_csi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DSI INT MAP REG */ +/** Type of dsi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dsi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dsi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GMII PHY INT MAP REG */ +/** Type of gmii_phy_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gmii_phy_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gmii_phy_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LPI INT MAP REG */ +/** Type of lpi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lpi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lpi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMT INT MAP REG */ +/** Type of pmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SBD INT MAP REG */ +/** Type of sbd_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sbd_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sbd_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG INT MAP REG */ +/** Type of usb_otg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG ENDP MULTI PROC INT MAP REG */ +/** Type of usb_otg_endp_multi_proc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg_endp_multi_proc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1JPEG INT MAP REG */ +/** Type of jpeg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_jpeg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_jpeg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PPA INT MAP REG */ +/** Type of ppa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ppa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ppa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CORE0 TRACE INT MAP REG */ +/** Type of core0_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_core0_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_core0_trace_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TRACE INT MAP REG */ +/** Type of interrupt_core1_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_trace_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP CORE CTRL INT MAP REG */ +/** Type of hp_core_ctrl_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_core_ctrl_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_core_ctrl_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ISP INT MAP REG */ +/** Type of isp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_isp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_isp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_isp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I3C MST INT MAP REG */ +/** Type of i3c_mst_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i3c_mst_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i3c_mst_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I3C SLV INT MAP REG */ +/** Type of i3c_slv_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i3c_slv_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i3c_slv_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG11 INT MAP REG */ +/** Type of usb_otg11_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg11_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg11_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D IN CH0 INT MAP REG */ +/** Type of dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D IN CH1 INT MAP REG */ +/** Type of dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH0 INT MAP REG */ +/** Type of dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH1 INT MAP REG */ +/** Type of dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH2 INT MAP REG */ +/** Type of dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PSRAM MSPI INT MAP REG */ +/** Type of psram_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_psram_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_psram_mspi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP SYSREG INT MAP REG */ +/** Type of hp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PCNT INT MAP REG */ +/** Type of pcnt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pcnt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pcnt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PAU INT MAP REG */ +/** Type of hp_pau_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_pau_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_pau_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PARLIO RX INT MAP REG */ +/** Type of hp_parlio_rx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_parlio_rx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_parlio_rx_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PARLIO TX INT MAP REG */ +/** Type of hp_parlio_tx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_parlio_tx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_parlio_tx_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH0 INT MAP REG */ +/** Type of h264_dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH1 INT MAP REG */ +/** Type of h264_dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH2 INT MAP REG */ +/** Type of h264_dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH3 INT MAP REG */ +/** Type of h264_dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH4 INT MAP REG */ +/** Type of h264_dma2d_out_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH0 INT MAP REG */ +/** Type of h264_dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH1 INT MAP REG */ +/** Type of h264_dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH2 INT MAP REG */ +/** Type of h264_dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH3 INT MAP REG */ +/** Type of h264_dma2d_in_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH4 INT MAP REG */ +/** Type of h264_dma2d_in_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH5 INT MAP REG */ +/** Type of h264_dma2d_in_ch5_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch5_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 REG INT MAP REG */ +/** Type of h264_reg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_reg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_reg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ASSIST DEBUG INT MAP REG */ +/** Type of assist_debug_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_assist_debug_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_assist_debug_int_map_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 0 REG */ +/** Type of intr_status_reg_0 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_0:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_0_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 1 REG */ +/** Type of intr_status_reg_1 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_1:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_1_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 2 REG */ +/** Type of intr_status_reg_2 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_2:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_2_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 3 REG */ +/** Type of intr_status_reg_3 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_3:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_3_reg_t; + + +/** Group: INTERRUPT CORE1CLOCK GATE REG */ +/** Type of clock_gate register + * NA + */ +typedef union { + struct { + /** interrupt_core1_reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t interrupt_core1_reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core1_clock_gate_reg_t; + + +/** Group: INTERRUPT CORE1INTERRUPT REG DATE REG */ +/** Type of interrupt_reg_date register + * NA + */ +typedef union { + struct { + /** interrupt_core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ + uint32_t interrupt_core1_interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core1_interrupt_reg_date_reg_t; + + +typedef struct { + volatile interrupt_core1_lp_rtc_int_map_reg_t lp_rtc_int_map; + volatile interrupt_core1_lp_wdt_int_map_reg_t lp_wdt_int_map; + volatile interrupt_core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; + volatile interrupt_core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; + volatile interrupt_core1_mb_hp_int_map_reg_t mb_hp_int_map; + volatile interrupt_core1_mb_lp_int_map_reg_t mb_lp_int_map; + volatile interrupt_core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; + volatile interrupt_core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; + volatile interrupt_core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map; + volatile interrupt_core1_lp_adc_int_map_reg_t lp_adc_int_map; + volatile interrupt_core1_lp_gpio_int_map_reg_t lp_gpio_int_map; + volatile interrupt_core1_lp_i2c_int_map_reg_t lp_i2c_int_map; + volatile interrupt_core1_lp_i2s_int_map_reg_t lp_i2s_int_map; + volatile interrupt_core1_lp_spi_int_map_reg_t lp_spi_int_map; + volatile interrupt_core1_lp_touch_int_map_reg_t lp_touch_int_map; + volatile interrupt_core1_lp_tsens_int_map_reg_t lp_tsens_int_map; + volatile interrupt_core1_lp_uart_int_map_reg_t lp_uart_int_map; + volatile interrupt_core1_lp_efuse_int_map_reg_t lp_efuse_int_map; + volatile interrupt_core1_lp_sw_int_map_reg_t lp_sw_int_map; + volatile interrupt_core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map; + volatile interrupt_core1_lp_huk_int_map_reg_t lp_huk_int_map; + volatile interrupt_core1_sys_icm_int_map_reg_t sys_icm_int_map; + volatile interrupt_core1_usb_device_int_map_reg_t usb_device_int_map; + volatile interrupt_core1_sdio_host_int_map_reg_t sdio_host_int_map; + volatile interrupt_core1_gdma_int_map_reg_t gdma_int_map; + volatile interrupt_core1_spi2_int_map_reg_t spi2_int_map; + volatile interrupt_core1_spi3_int_map_reg_t spi3_int_map; + volatile interrupt_core1_i2s0_int_map_reg_t i2s0_int_map; + volatile interrupt_core1_i2s1_int_map_reg_t i2s1_int_map; + volatile interrupt_core1_i2s2_int_map_reg_t i2s2_int_map; + volatile interrupt_core1_uhci0_int_map_reg_t uhci0_int_map; + volatile interrupt_core1_uart0_int_map_reg_t uart0_int_map; + volatile interrupt_core1_uart1_int_map_reg_t uart1_int_map; + volatile interrupt_core1_uart2_int_map_reg_t uart2_int_map; + volatile interrupt_core1_uart3_int_map_reg_t uart3_int_map; + volatile interrupt_core1_uart4_int_map_reg_t uart4_int_map; + volatile interrupt_core1_lcd_cam_int_map_reg_t lcd_cam_int_map; + volatile interrupt_core1_adc_int_map_reg_t adc_int_map; + volatile interrupt_core1_pwm0_int_map_reg_t pwm0_int_map; + volatile interrupt_core1_pwm1_int_map_reg_t pwm1_int_map; + volatile interrupt_core1_can0_int_map_reg_t can0_int_map; + volatile interrupt_core1_can1_int_map_reg_t can1_int_map; + volatile interrupt_core1_can2_int_map_reg_t can2_int_map; + volatile interrupt_core1_rmt_int_map_reg_t rmt_int_map; + volatile interrupt_core1_i2c0_int_map_reg_t i2c0_int_map; + volatile interrupt_core1_i2c1_int_map_reg_t i2c1_int_map; + volatile interrupt_core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; + volatile interrupt_core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; + volatile interrupt_core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; + volatile interrupt_core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; + volatile interrupt_core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; + volatile interrupt_core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; + volatile interrupt_core1_ledc_int_map_reg_t ledc_int_map; + volatile interrupt_core1_systimer_target0_int_map_reg_t systimer_target0_int_map; + volatile interrupt_core1_systimer_target1_int_map_reg_t systimer_target1_int_map; + volatile interrupt_core1_systimer_target2_int_map_reg_t systimer_target2_int_map; + volatile interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; + volatile interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; + volatile interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; + volatile interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; + volatile interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; + volatile interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; + volatile interrupt_core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; + volatile interrupt_core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; + volatile interrupt_core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; + volatile interrupt_core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; + volatile interrupt_core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; + volatile interrupt_core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; + volatile interrupt_core1_rsa_int_map_reg_t rsa_int_map; + volatile interrupt_core1_aes_int_map_reg_t aes_int_map; + volatile interrupt_core1_sha_int_map_reg_t sha_int_map; + volatile interrupt_core1_ecc_int_map_reg_t ecc_int_map; + volatile interrupt_core1_ecdsa_int_map_reg_t ecdsa_int_map; + volatile interrupt_core1_km_int_map_reg_t km_int_map; + volatile interrupt_core1_gpio_int0_map_reg_t gpio_int0_map; + volatile interrupt_core1_gpio_int1_map_reg_t gpio_int1_map; + volatile interrupt_core1_gpio_int2_map_reg_t gpio_int2_map; + volatile interrupt_core1_gpio_int3_map_reg_t gpio_int3_map; + volatile interrupt_core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; + volatile interrupt_core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; + volatile interrupt_core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; + volatile interrupt_core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; + volatile interrupt_core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; + volatile interrupt_core1_cache_int_map_reg_t cache_int_map; + volatile interrupt_core1_flash_mspi_int_map_reg_t flash_mspi_int_map; + volatile interrupt_core1_csi_bridge_int_map_reg_t csi_bridge_int_map; + volatile interrupt_core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map; + volatile interrupt_core1_csi_int_map_reg_t csi_int_map; + volatile interrupt_core1_dsi_int_map_reg_t dsi_int_map; + volatile interrupt_core1_gmii_phy_int_map_reg_t gmii_phy_int_map; + volatile interrupt_core1_lpi_int_map_reg_t lpi_int_map; + volatile interrupt_core1_pmt_int_map_reg_t pmt_int_map; + volatile interrupt_core1_sbd_int_map_reg_t sbd_int_map; + volatile interrupt_core1_usb_otg_int_map_reg_t usb_otg_int_map; + volatile interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; + volatile interrupt_core1_jpeg_int_map_reg_t jpeg_int_map; + volatile interrupt_core1_ppa_int_map_reg_t ppa_int_map; + volatile interrupt_core1_core0_trace_int_map_reg_t core0_trace_int_map; + volatile interrupt_core1_trace_int_map_reg_t interrupt_core1_trace_int_map; + volatile interrupt_core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; + volatile interrupt_core1_isp_int_map_reg_t isp_int_map; + volatile interrupt_core1_i3c_mst_int_map_reg_t i3c_mst_int_map; + volatile interrupt_core1_i3c_slv_int_map_reg_t i3c_slv_int_map; + volatile interrupt_core1_usb_otg11_int_map_reg_t usb_otg11_int_map; + volatile interrupt_core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; + volatile interrupt_core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; + volatile interrupt_core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; + volatile interrupt_core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; + volatile interrupt_core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; + volatile interrupt_core1_psram_mspi_int_map_reg_t psram_mspi_int_map; + volatile interrupt_core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map; + volatile interrupt_core1_pcnt_int_map_reg_t pcnt_int_map; + volatile interrupt_core1_hp_pau_int_map_reg_t hp_pau_int_map; + volatile interrupt_core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; + volatile interrupt_core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; + volatile interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; + volatile interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; + volatile interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; + volatile interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; + volatile interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; + volatile interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; + volatile interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; + volatile interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; + volatile interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; + volatile interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; + volatile interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; + volatile interrupt_core1_h264_reg_int_map_reg_t h264_reg_int_map; + volatile interrupt_core1_assist_debug_int_map_reg_t assist_debug_int_map; + volatile interrupt_core1_intr_status_reg_0_reg_t intr_status_reg_0; + volatile interrupt_core1_intr_status_reg_1_reg_t intr_status_reg_1; + volatile interrupt_core1_intr_status_reg_2_reg_t intr_status_reg_2; + volatile interrupt_core1_intr_status_reg_3_reg_t intr_status_reg_3; + volatile interrupt_core1_clock_gate_reg_t clock_gate; + uint32_t reserved_214[122]; + volatile interrupt_core1_interrupt_reg_date_reg_t interrupt_reg_date; +} interrupt_core1_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core1_dev_t) == 0x400, "Invalid size of interrupt_core1_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_reg.h b/components/soc/esp32p4/include/soc/interrupt_reg.h new file mode 100644 index 0000000000..b799b19144 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/clic_reg.h" +#include "soc/soc_caps.h" + +// ESP32P4 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y) +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG +#define INTERRUPT_CORE1_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/include/soc/io_mux_reg.h index 488097ee6d..475aa25bd1 100644 --- a/components/soc/esp32p4/include/soc/io_mux_reg.h +++ b/components/soc/esp32p4/include/soc/io_mux_reg.h @@ -64,6 +64,17 @@ #define MCU_SEL_V 0x7 #define MCU_SEL_S 12 +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + #define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) #define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) #define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); @@ -138,6 +149,55 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) +#define SPI_CS1_GPIO_NUM 26 +#define SPI_HD_GPIO_NUM 27 +#define SPI_WP_GPIO_NUM 28 +#define SPI_CS0_GPIO_NUM 29 +#define SPI_CLK_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 31 +#define SPI_D_GPIO_NUM 32 +#define SPI_D4_GPIO_NUM 33 +#define SPI_D5_GPIO_NUM 34 +#define SPI_D6_GPIO_NUM 35 +#define SPI_D7_GPIO_NUM 36 +#define SPI_DQS_GPIO_NUM 37 + +#define PIN_FUNC_SPI_DEBUG 4 +#define FLASH_CS_DEBUG_GPIO_NUM 49 +#define FLASH_Q_DEBUG_GPIO_NUM 50 +#define FLASH_WP_DEBUG_GPIO_NUM 51 +#define FLASH_HD_DEBUG_GPIO_NUM 52 +#define FLASH_CLK_DEBUG_GPIO_NUM 53 +#define FLASH_D_DEBUG_GPIO_NUM 54 + +#define PSRAM_D_DEBUG_GPIO_NUM 28 +#define PSRAM_Q_DEBUG_GPIO_NUM 29 +#define PSRAM_WP_DEBUG_GPIO_NUM 30 +#define PSRAM_HOLD_DEBUG_GPIO_NUM 31 +#define PSRAM_DP4_DEBUG_GPIO_NUM 32 +#define PSRAM_DP5_DEBUG_GPIO_NUM 33 +#define PSRAM_DP6_DEBUG_GPIO_NUM 34 +#define PSRAM_DP7_DEBUG_GPIO_NUM 35 +#define PSRAM_DQS0_DEBUG_GPIO_NUM 36 +#define PSRAM_CLK_DEBUG_GPIO_NUM 22 +#define PSRAM_CS_DEBUG_GPIO_NUM 23 +#define PSRAM_DP8_DEBUG_GPIO_NUM 39 +#define PSRAM_DP9_DEBUG_GPIO_NUM 40 +#define PSRAM_DP10_DEBUG_GPIO_NUM 41 +#define PSRAM_DP11_DEBUG_GPIO_NUM 42 +#define PSRAM_DP12_DEBUG_GPIO_NUM 43 +#define PSRAM_DP13_DEBUG_GPIO_NUM 44 +#define PSRAM_DP14_DEBUG_GPIO_NUM 45 +#define PSRAM_DP15_DEBUG_GPIO_NUM 46 +#define PSRAM_DQS1_DEBUG_GPIO_NUM 47 + +#define SD_CLK_GPIO_NUM 12 +#define SD_CMD_GPIO_NUM 11 +#define SD_DATA0_GPIO_NUM 13 +#define SD_DATA1_GPIO_NUM 14 +#define SD_DATA2_GPIO_NUM 9 +#define SD_DATA3_GPIO_NUM 10 + #define MAX_RTC_GPIO_NUM 15 #define MAX_PAD_GPIO_NUM 56 #define MAX_GPIO_NUM 56 diff --git a/components/soc/esp32p4/include/soc/lcdcam_reg.h b/components/soc/esp32p4/include/soc/lcd_cam_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/lcdcam_reg.h rename to components/soc/esp32p4/include/soc/lcd_cam_reg.h diff --git a/components/soc/esp32p4/include/soc/lcdcam_struct.h b/components/soc/esp32p4/include/soc/lcd_cam_struct.h similarity index 99% rename from components/soc/esp32p4/include/soc/lcdcam_struct.h rename to components/soc/esp32p4/include/soc/lcd_cam_struct.h index 52187ae4c2..2ce7658d43 100644 --- a/components/soc/esp32p4/include/soc/lcdcam_struct.h +++ b/components/soc/esp32p4/include/soc/lcd_cam_struct.h @@ -820,7 +820,7 @@ typedef union { } lcdcam_lc_reg_date_reg_t; -typedef struct { +typedef struct lcdcam_dev_t { volatile lcdcam_lcd_clock_reg_t lcd_clock; volatile lcdcam_cam_ctrl_reg_t cam_ctrl; volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h b/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h deleted file mode 100644 index 901915903a..0000000000 --- a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h +++ /dev/null @@ -1,1036 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_AONCLKRST_LP_CLK_CONF_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_CONF_REG (DR_REG_LP_AONCLKRST_BASE + 0x0) -/** LP_AONCLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * need_des - */ -#define LP_AONCLKRST_SLOW_CLK_SEL 0x00000003U -#define LP_AONCLKRST_SLOW_CLK_SEL_M (LP_AONCLKRST_SLOW_CLK_SEL_V << LP_AONCLKRST_SLOW_CLK_SEL_S) -#define LP_AONCLKRST_SLOW_CLK_SEL_V 0x00000003U -#define LP_AONCLKRST_SLOW_CLK_SEL_S 0 -/** LP_AONCLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; - * need_des - */ -#define LP_AONCLKRST_FAST_CLK_SEL 0x00000003U -#define LP_AONCLKRST_FAST_CLK_SEL_M (LP_AONCLKRST_FAST_CLK_SEL_V << LP_AONCLKRST_FAST_CLK_SEL_S) -#define LP_AONCLKRST_FAST_CLK_SEL_V 0x00000003U -#define LP_AONCLKRST_FAST_CLK_SEL_S 2 -/** LP_AONCLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LP_PERI_DIV_NUM 0x0000003FU -#define LP_AONCLKRST_LP_PERI_DIV_NUM_M (LP_AONCLKRST_LP_PERI_DIV_NUM_V << LP_AONCLKRST_LP_PERI_DIV_NUM_S) -#define LP_AONCLKRST_LP_PERI_DIV_NUM_V 0x0000003FU -#define LP_AONCLKRST_LP_PERI_DIV_NUM_S 4 -/** LP_AONCLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M (BIT(10)) -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_M (LP_AONCLKRST_ANA_SEL_REF_PLL8M_V << LP_AONCLKRST_ANA_SEL_REF_PLL8M_S) -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_S 10 - -/** LP_AONCLKRST_LP_CLK_PO_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x4) -/** LP_AONCLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_M (LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V << LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S) -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S 0 -/** LP_AONCLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_LP_BUS_OEN (BIT(1)) -#define LP_AONCLKRST_CLK_LP_BUS_OEN_M (LP_AONCLKRST_CLK_LP_BUS_OEN_V << LP_AONCLKRST_CLK_LP_BUS_OEN_S) -#define LP_AONCLKRST_CLK_LP_BUS_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_LP_BUS_OEN_S 1 -/** LP_AONCLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_AON_SLOW_OEN (BIT(2)) -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_M (LP_AONCLKRST_CLK_AON_SLOW_OEN_V << LP_AONCLKRST_CLK_AON_SLOW_OEN_S) -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_S 2 -/** LP_AONCLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_AON_FAST_OEN (BIT(3)) -#define LP_AONCLKRST_CLK_AON_FAST_OEN_M (LP_AONCLKRST_CLK_AON_FAST_OEN_V << LP_AONCLKRST_CLK_AON_FAST_OEN_S) -#define LP_AONCLKRST_CLK_AON_FAST_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_AON_FAST_OEN_S 3 -/** LP_AONCLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_SLOW_OEN (BIT(4)) -#define LP_AONCLKRST_CLK_SLOW_OEN_M (LP_AONCLKRST_CLK_SLOW_OEN_V << LP_AONCLKRST_CLK_SLOW_OEN_S) -#define LP_AONCLKRST_CLK_SLOW_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SLOW_OEN_S 4 -/** LP_AONCLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_FAST_OEN (BIT(5)) -#define LP_AONCLKRST_CLK_FAST_OEN_M (LP_AONCLKRST_CLK_FAST_OEN_V << LP_AONCLKRST_CLK_FAST_OEN_S) -#define LP_AONCLKRST_CLK_FAST_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_FAST_OEN_S 5 -/** LP_AONCLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_FOSC_OEN (BIT(6)) -#define LP_AONCLKRST_CLK_FOSC_OEN_M (LP_AONCLKRST_CLK_FOSC_OEN_V << LP_AONCLKRST_CLK_FOSC_OEN_S) -#define LP_AONCLKRST_CLK_FOSC_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_FOSC_OEN_S 6 -/** LP_AONCLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_RC32K_OEN (BIT(7)) -#define LP_AONCLKRST_CLK_RC32K_OEN_M (LP_AONCLKRST_CLK_RC32K_OEN_V << LP_AONCLKRST_CLK_RC32K_OEN_S) -#define LP_AONCLKRST_CLK_RC32K_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_RC32K_OEN_S 7 -/** LP_AONCLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_SXTAL_OEN (BIT(8)) -#define LP_AONCLKRST_CLK_SXTAL_OEN_M (LP_AONCLKRST_CLK_SXTAL_OEN_V << LP_AONCLKRST_CLK_SXTAL_OEN_S) -#define LP_AONCLKRST_CLK_SXTAL_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SXTAL_OEN_S 8 -/** LP_AONCLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; - * 1'b1: probe sosc clk on - * 1'b0: probe sosc clk off - */ -#define LP_AONCLKRST_CLK_SOSC_OEN (BIT(9)) -#define LP_AONCLKRST_CLK_SOSC_OEN_M (LP_AONCLKRST_CLK_SOSC_OEN_V << LP_AONCLKRST_CLK_SOSC_OEN_S) -#define LP_AONCLKRST_CLK_SOSC_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SOSC_OEN_S 9 - -/** LP_AONCLKRST_LP_CLK_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x8) -/** LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S) -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S 26 -/** LP_AONCLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; - * need_des - */ -#define LP_AONCLKRST_CK_EN_LP_RAM (BIT(27)) -#define LP_AONCLKRST_CK_EN_LP_RAM_M (LP_AONCLKRST_CK_EN_LP_RAM_V << LP_AONCLKRST_CK_EN_LP_RAM_S) -#define LP_AONCLKRST_CK_EN_LP_RAM_V 0x00000001U -#define LP_AONCLKRST_CK_EN_LP_RAM_S 27 -/** LP_AONCLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_ETM_EVENT_TICK_EN (BIT(28)) -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_M (LP_AONCLKRST_ETM_EVENT_TICK_EN_V << LP_AONCLKRST_ETM_EVENT_TICK_EN_S) -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_V 0x00000001U -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_S 28 -/** LP_AONCLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_M (LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V << LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S) -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S 29 -/** LP_AONCLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON (BIT(30)) -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_M (LP_AONCLKRST_XTAL_CLK_FORCE_ON_V << LP_AONCLKRST_XTAL_CLK_FORCE_ON_S) -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_S 30 -/** LP_AONCLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON (BIT(31)) -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_M (LP_AONCLKRST_FOSC_CLK_FORCE_ON_V << LP_AONCLKRST_FOSC_CLK_FORCE_ON_S) -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_S 31 - -/** LP_AONCLKRST_LP_RST_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_RST_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0xc) -/** LP_AONCLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_HUK (BIT(24)) -#define LP_AONCLKRST_RST_EN_LP_HUK_M (LP_AONCLKRST_RST_EN_LP_HUK_V << LP_AONCLKRST_RST_EN_LP_HUK_S) -#define LP_AONCLKRST_RST_EN_LP_HUK_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_HUK_S 24 -/** LP_AONCLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_ANAPERI (BIT(25)) -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_M (LP_AONCLKRST_RST_EN_LP_ANAPERI_V << LP_AONCLKRST_RST_EN_LP_ANAPERI_S) -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_S 25 -/** LP_AONCLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_WDT (BIT(26)) -#define LP_AONCLKRST_RST_EN_LP_WDT_M (LP_AONCLKRST_RST_EN_LP_WDT_V << LP_AONCLKRST_RST_EN_LP_WDT_S) -#define LP_AONCLKRST_RST_EN_LP_WDT_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_WDT_S 26 -/** LP_AONCLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_TIMER (BIT(27)) -#define LP_AONCLKRST_RST_EN_LP_TIMER_M (LP_AONCLKRST_RST_EN_LP_TIMER_V << LP_AONCLKRST_RST_EN_LP_TIMER_S) -#define LP_AONCLKRST_RST_EN_LP_TIMER_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_TIMER_S 27 -/** LP_AONCLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_RTC (BIT(28)) -#define LP_AONCLKRST_RST_EN_LP_RTC_M (LP_AONCLKRST_RST_EN_LP_RTC_V << LP_AONCLKRST_RST_EN_LP_RTC_S) -#define LP_AONCLKRST_RST_EN_LP_RTC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_RTC_S 28 -/** LP_AONCLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_MAILBOX (BIT(29)) -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_M (LP_AONCLKRST_RST_EN_LP_MAILBOX_V << LP_AONCLKRST_RST_EN_LP_MAILBOX_S) -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_S 29 -/** LP_AONCLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_M (LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V << LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S) -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S 30 -/** LP_AONCLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_RAM (BIT(31)) -#define LP_AONCLKRST_RST_EN_LP_RAM_M (LP_AONCLKRST_RST_EN_LP_RAM_V << LP_AONCLKRST_RST_EN_LP_RAM_S) -#define LP_AONCLKRST_RST_EN_LP_RAM_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_RAM_S 31 - -/** LP_AONCLKRST_RESET_CAUSE_REG register - * need_des - */ -#define LP_AONCLKRST_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x10) -/** LP_AONCLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; - * 6'h1: POR reset - * 6'h9: PMU LP PERI power down reset - * 6'ha: PMU LP CPU reset - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: software reset - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_S 0 -/** LP_AONCLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_FLAG (BIT(6)) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_M (LP_AONCLKRST_LPCORE_RESET_FLAG_V << LP_AONCLKRST_LPCORE_RESET_FLAG_S) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_FLAG_S 6 -/** LP_AONCLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_M (LP_AONCLKRST_HPCORE0_RESET_CAUSE_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_S) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_S 7 -/** LP_AONCLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_FLAG (BIT(13)) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_M (LP_AONCLKRST_HPCORE0_RESET_FLAG_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_S) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_S 13 -/** LP_AONCLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_M (LP_AONCLKRST_HPCORE1_RESET_CAUSE_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_S) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_S 14 -/** LP_AONCLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_FLAG (BIT(20)) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_M (LP_AONCLKRST_HPCORE1_RESET_FLAG_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_S) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_S 20 -/** LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; - * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore - * pmu_lp_cpu_reset reset_cause - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 -/** LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S 26 -/** LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_M (LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V << LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S 27 -/** LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 -/** LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S 29 -/** LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 -/** LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S 31 - -/** LP_AONCLKRST_HPCPU_RESET_CTRL0_REG register - * need_des - */ -#define LP_AONCLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x14) -/** LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; - * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup - * reset feature - */ -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S) -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 -/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; - * need_des - */ -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 -/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; - * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset - * hpcore0 feature - */ -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 -/** LP_AONCLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_STALL_WAIT 0x0000007FU -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_M (LP_AONCLKRST_HPCORE0_STALL_WAIT_V << LP_AONCLKRST_HPCORE0_STALL_WAIT_S) -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_S 5 -/** LP_AONCLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_STALL_EN (BIT(12)) -#define LP_AONCLKRST_HPCORE0_STALL_EN_M (LP_AONCLKRST_HPCORE0_STALL_EN_V << LP_AONCLKRST_HPCORE0_STALL_EN_S) -#define LP_AONCLKRST_HPCORE0_STALL_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_STALL_EN_S 12 -/** LP_AONCLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_SW_RESET (BIT(13)) -#define LP_AONCLKRST_HPCORE0_SW_RESET_M (LP_AONCLKRST_HPCORE0_SW_RESET_V << LP_AONCLKRST_HPCORE0_SW_RESET_S) -#define LP_AONCLKRST_HPCORE0_SW_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_SW_RESET_S 13 -/** LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S) -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 -/** LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S) -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 -/** LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; - * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup - * reset feature - */ -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S) -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 -/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; - * need_des - */ -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 -/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; - * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset - * hpcore1 feature - */ -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 -/** LP_AONCLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_STALL_WAIT 0x0000007FU -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_M (LP_AONCLKRST_HPCORE1_STALL_WAIT_V << LP_AONCLKRST_HPCORE1_STALL_WAIT_S) -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_S 21 -/** LP_AONCLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_STALL_EN (BIT(28)) -#define LP_AONCLKRST_HPCORE1_STALL_EN_M (LP_AONCLKRST_HPCORE1_STALL_EN_V << LP_AONCLKRST_HPCORE1_STALL_EN_S) -#define LP_AONCLKRST_HPCORE1_STALL_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_STALL_EN_S 28 -/** LP_AONCLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_SW_RESET (BIT(29)) -#define LP_AONCLKRST_HPCORE1_SW_RESET_M (LP_AONCLKRST_HPCORE1_SW_RESET_V << LP_AONCLKRST_HPCORE1_SW_RESET_S) -#define LP_AONCLKRST_HPCORE1_SW_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_SW_RESET_S 29 -/** LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S) -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 -/** LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S) -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 - -/** LP_AONCLKRST_HPCPU_RESET_CTRL1_REG register - * need_des - */ -#define LP_AONCLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x18) -/** LP_AONCLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; - * HP core0 software stall when set to 8'h86 - */ -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_M (LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S) -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S 16 -/** LP_AONCLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; - * HP core1 software stall when set to 8'h86 - */ -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_M (LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S) -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S 24 - -/** LP_AONCLKRST_FOSC_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_FOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x1c) -/** LP_AONCLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; - * need_des - */ -#define LP_AONCLKRST_FOSC_DFREQ 0x000003FFU -#define LP_AONCLKRST_FOSC_DFREQ_M (LP_AONCLKRST_FOSC_DFREQ_V << LP_AONCLKRST_FOSC_DFREQ_S) -#define LP_AONCLKRST_FOSC_DFREQ_V 0x000003FFU -#define LP_AONCLKRST_FOSC_DFREQ_S 22 - -/** LP_AONCLKRST_RC32K_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_RC32K_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x20) -/** LP_AONCLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; - * need_des - */ -#define LP_AONCLKRST_RC32K_DFREQ 0xFFFFFFFFU -#define LP_AONCLKRST_RC32K_DFREQ_M (LP_AONCLKRST_RC32K_DFREQ_V << LP_AONCLKRST_RC32K_DFREQ_S) -#define LP_AONCLKRST_RC32K_DFREQ_V 0xFFFFFFFFU -#define LP_AONCLKRST_RC32K_DFREQ_S 0 - -/** LP_AONCLKRST_SOSC_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_SOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x24) -/** LP_AONCLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; - * need_des - */ -#define LP_AONCLKRST_SOSC_DFREQ 0x000003FFU -#define LP_AONCLKRST_SOSC_DFREQ_M (LP_AONCLKRST_SOSC_DFREQ_V << LP_AONCLKRST_SOSC_DFREQ_S) -#define LP_AONCLKRST_SOSC_DFREQ_V 0x000003FFU -#define LP_AONCLKRST_SOSC_DFREQ_S 22 - -/** LP_AONCLKRST_CLK_TO_HP_REG register - * need_des - */ -#define LP_AONCLKRST_CLK_TO_HP_REG (DR_REG_LP_AONCLKRST_BASE + 0x28) -/** LP_AONCLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_XTAL32K (BIT(28)) -#define LP_AONCLKRST_ICG_HP_XTAL32K_M (LP_AONCLKRST_ICG_HP_XTAL32K_V << LP_AONCLKRST_ICG_HP_XTAL32K_S) -#define LP_AONCLKRST_ICG_HP_XTAL32K_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_XTAL32K_S 28 -/** LP_AONCLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_SOSC (BIT(29)) -#define LP_AONCLKRST_ICG_HP_SOSC_M (LP_AONCLKRST_ICG_HP_SOSC_V << LP_AONCLKRST_ICG_HP_SOSC_S) -#define LP_AONCLKRST_ICG_HP_SOSC_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_SOSC_S 29 -/** LP_AONCLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_OSC32K (BIT(30)) -#define LP_AONCLKRST_ICG_HP_OSC32K_M (LP_AONCLKRST_ICG_HP_OSC32K_V << LP_AONCLKRST_ICG_HP_OSC32K_S) -#define LP_AONCLKRST_ICG_HP_OSC32K_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_OSC32K_S 30 -/** LP_AONCLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_FOSC (BIT(31)) -#define LP_AONCLKRST_ICG_HP_FOSC_M (LP_AONCLKRST_ICG_HP_FOSC_V << LP_AONCLKRST_ICG_HP_FOSC_S) -#define LP_AONCLKRST_ICG_HP_FOSC_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_FOSC_S 31 - -/** LP_AONCLKRST_LPMEM_FORCE_REG register - * need_des - */ -#define LP_AONCLKRST_LPMEM_FORCE_REG (DR_REG_LP_AONCLKRST_BASE + 0x2c) -/** LP_AONCLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; - * reserved - */ -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_M (LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V << LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S) -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S 31 - -/** LP_AONCLKRST_XTAL32K_REG register - * need_des - */ -#define LP_AONCLKRST_XTAL32K_REG (DR_REG_LP_AONCLKRST_BASE + 0x30) -/** LP_AONCLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DRES_XTAL32K 0x00000007U -#define LP_AONCLKRST_DRES_XTAL32K_M (LP_AONCLKRST_DRES_XTAL32K_V << LP_AONCLKRST_DRES_XTAL32K_S) -#define LP_AONCLKRST_DRES_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DRES_XTAL32K_S 22 -/** LP_AONCLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DGM_XTAL32K 0x00000007U -#define LP_AONCLKRST_DGM_XTAL32K_M (LP_AONCLKRST_DGM_XTAL32K_V << LP_AONCLKRST_DGM_XTAL32K_S) -#define LP_AONCLKRST_DGM_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DGM_XTAL32K_S 25 -/** LP_AONCLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_DBUF_XTAL32K (BIT(28)) -#define LP_AONCLKRST_DBUF_XTAL32K_M (LP_AONCLKRST_DBUF_XTAL32K_V << LP_AONCLKRST_DBUF_XTAL32K_S) -#define LP_AONCLKRST_DBUF_XTAL32K_V 0x00000001U -#define LP_AONCLKRST_DBUF_XTAL32K_S 28 -/** LP_AONCLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DAC_XTAL32K 0x00000007U -#define LP_AONCLKRST_DAC_XTAL32K_M (LP_AONCLKRST_DAC_XTAL32K_V << LP_AONCLKRST_DAC_XTAL32K_S) -#define LP_AONCLKRST_DAC_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DAC_XTAL32K_S 29 - -/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x34) -/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S) -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x38) -/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_M (LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S) -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x3c) -/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_M (LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S) -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HP_CLK_CTRL_REG register - * HP Clock Control Register. - */ -#define LP_AONCLKRST_HP_CLK_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x40) -/** LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; - * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. - */ -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S) -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S 0 -/** LP_AONCLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; - * HP SoC Root Clock Enable. - */ -#define LP_AONCLKRST_HP_ROOT_CLK_EN (BIT(2)) -#define LP_AONCLKRST_HP_ROOT_CLK_EN_M (LP_AONCLKRST_HP_ROOT_CLK_EN_V << LP_AONCLKRST_HP_ROOT_CLK_EN_S) -#define LP_AONCLKRST_HP_ROOT_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_ROOT_CLK_EN_S 2 -/** LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; - * PARLIO TX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 -/** LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; - * PARLIO RX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 -/** LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; - * UART4 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 -/** LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; - * UART3 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 -/** LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; - * UART2 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 -/** LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; - * UART1 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 -/** LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; - * UART0 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 -/** LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; - * I2S2 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S 10 -/** LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; - * I2S1 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S 11 -/** LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; - * I2S0 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S 12 -/** LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; - * EMAC RX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 -/** LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; - * EMAC TX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 -/** LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; - * EMAC TXRX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 -/** LP_AONCLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; - * XTAL 32K Clock Enable. - */ -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_M (LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V << LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S) -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S 16 -/** LP_AONCLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; - * RC 32K Clock Enable. - */ -#define LP_AONCLKRST_HP_RC_32K_CLK_EN (BIT(17)) -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_M (LP_AONCLKRST_HP_RC_32K_CLK_EN_V << LP_AONCLKRST_HP_RC_32K_CLK_EN_S) -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_S 17 -/** LP_AONCLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; - * SOSC 150K Clock Enable. - */ -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_M (LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V << LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S) -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S 18 -/** LP_AONCLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; - * PLL 8M Clock Enable. - */ -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN (BIT(19)) -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_M (LP_AONCLKRST_HP_PLL_8M_CLK_EN_V << LP_AONCLKRST_HP_PLL_8M_CLK_EN_S) -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_S 19 -/** LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; - * AUDIO PLL Clock Enable. - */ -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S) -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S 20 -/** LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; - * SDIO PLL2 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S 21 -/** LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; - * SDIO PLL1 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S 22 -/** LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; - * SDIO PLL0 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S 23 -/** LP_AONCLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; - * FOSC 20M Clock Enable. - */ -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_M (LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V << LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S) -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S 24 -/** LP_AONCLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; - * XTAL 40M Clock Enalbe. - */ -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_M (LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V << LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S) -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S 25 -/** LP_AONCLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; - * CPLL 400M Clock Enable. - */ -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_M (LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V << LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S) -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S 26 -/** LP_AONCLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; - * SPLL 480M Clock Enable. - */ -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_M (LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V << LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S) -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S 27 -/** LP_AONCLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; - * MPLL 500M Clock Enable. - */ -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_M (LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V << LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S) -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S 28 - -/** LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG register - * HP USB Clock Reset Control Register. - */ -#define LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x44) -/** LP_AONCLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; - * unused. - */ -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_M (LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S) -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S 0 -/** LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; - * unused. - */ -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 -/** LP_AONCLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; - * unused. - */ -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_M (LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S) -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S 2 -/** LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; - * unused. - */ -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 -/** LP_AONCLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * usb otg11 fs phy clock enable. - */ -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_M (LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V << LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S 4 -/** LP_AONCLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * usb device fs phy clock enable. - */ -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_M (LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V << LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S) -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S 5 -/** LP_AONCLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; - * usb 480m to 25m divide number. - */ -#define LP_AONCLKRST_USB_48M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_48M_DIV_NUM_M (LP_AONCLKRST_USB_48M_DIV_NUM_V << LP_AONCLKRST_USB_48M_DIV_NUM_S) -#define LP_AONCLKRST_USB_48M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_48M_DIV_NUM_S 6 -/** LP_AONCLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; - * usb 500m to 25m divide number. - */ -#define LP_AONCLKRST_USB_25M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_25M_DIV_NUM_M (LP_AONCLKRST_USB_25M_DIV_NUM_V << LP_AONCLKRST_USB_25M_DIV_NUM_S) -#define LP_AONCLKRST_USB_25M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_25M_DIV_NUM_S 14 -/** LP_AONCLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; - * usb 480m to 12m divide number. - */ -#define LP_AONCLKRST_USB_12M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_12M_DIV_NUM_M (LP_AONCLKRST_USB_12M_DIV_NUM_V << LP_AONCLKRST_USB_12M_DIV_NUM_S) -#define LP_AONCLKRST_USB_12M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_12M_DIV_NUM_S 22 - -/** LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG register - * HP USB Clock Reset Control Register. - */ -#define LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x48) -/** LP_AONCLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; - * usb otg20 adp reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_M (LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V << LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S 0 -/** LP_AONCLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; - * usb otg20 phy reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_M (LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V << LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S 1 -/** LP_AONCLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; - * usb otg20 reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20 (BIT(2)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_M (LP_AONCLKRST_RST_EN_USB_OTG20_V << LP_AONCLKRST_RST_EN_USB_OTG20_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_S 2 -/** LP_AONCLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; - * usb org11 reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG11 (BIT(3)) -#define LP_AONCLKRST_RST_EN_USB_OTG11_M (LP_AONCLKRST_RST_EN_USB_OTG11_V << LP_AONCLKRST_RST_EN_USB_OTG11_S) -#define LP_AONCLKRST_RST_EN_USB_OTG11_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG11_S 3 -/** LP_AONCLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; - * usb device reset en - */ -#define LP_AONCLKRST_RST_EN_USB_DEVICE (BIT(4)) -#define LP_AONCLKRST_RST_EN_USB_DEVICE_M (LP_AONCLKRST_RST_EN_USB_DEVICE_V << LP_AONCLKRST_RST_EN_USB_DEVICE_S) -#define LP_AONCLKRST_RST_EN_USB_DEVICE_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_DEVICE_S 4 -/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; - * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. - */ -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 -/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; - * usb otg20 hs phy refclk enable. - */ -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 -/** LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; - * usb otg20 ulpi clock enable. - */ -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S 31 - -/** LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register - * need_des - */ -#define LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x4c) -/** LP_AONCLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; - * hp sdmmc reset en - */ -#define LP_AONCLKRST_RST_EN_SDMMC (BIT(28)) -#define LP_AONCLKRST_RST_EN_SDMMC_M (LP_AONCLKRST_RST_EN_SDMMC_V << LP_AONCLKRST_RST_EN_SDMMC_S) -#define LP_AONCLKRST_RST_EN_SDMMC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_SDMMC_S 28 -/** LP_AONCLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; - * hp sdmmc force norst - */ -#define LP_AONCLKRST_FORCE_NORST_SDMMC (BIT(29)) -#define LP_AONCLKRST_FORCE_NORST_SDMMC_M (LP_AONCLKRST_FORCE_NORST_SDMMC_V << LP_AONCLKRST_FORCE_NORST_SDMMC_S) -#define LP_AONCLKRST_FORCE_NORST_SDMMC_V 0x00000001U -#define LP_AONCLKRST_FORCE_NORST_SDMMC_S 29 -/** LP_AONCLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; - * hp emac reset en - */ -#define LP_AONCLKRST_RST_EN_EMAC (BIT(30)) -#define LP_AONCLKRST_RST_EN_EMAC_M (LP_AONCLKRST_RST_EN_EMAC_V << LP_AONCLKRST_RST_EN_EMAC_S) -#define LP_AONCLKRST_RST_EN_EMAC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_EMAC_S 30 -/** LP_AONCLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; - * hp emac force norst - */ -#define LP_AONCLKRST_FORCE_NORST_EMAC (BIT(31)) -#define LP_AONCLKRST_FORCE_NORST_EMAC_M (LP_AONCLKRST_FORCE_NORST_EMAC_V << LP_AONCLKRST_FORCE_NORST_EMAC_S) -#define LP_AONCLKRST_FORCE_NORST_EMAC_V 0x00000001U -#define LP_AONCLKRST_FORCE_NORST_EMAC_S 31 - -/** LP_AONCLKRST_DATE_REG register - * need_des - */ -#define LP_AONCLKRST_DATE_REG (DR_REG_LP_AONCLKRST_BASE + 0x3fc) -/** LP_AONCLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_EN (BIT(31)) -#define LP_AONCLKRST_CLK_EN_M (LP_AONCLKRST_CLK_EN_V << LP_AONCLKRST_CLK_EN_S) -#define LP_AONCLKRST_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..de3f17820c --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h @@ -0,0 +1,1036 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 +/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_SEL_REF_PLL8M (BIT(10)) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_M (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U +#define LP_CLKRST_ANA_SEL_REF_PLL8M_S 10 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S 0 +/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_LP_BUS_OEN (BIT(1)) +#define LP_CLKRST_CLK_LP_BUS_OEN_M (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S) +#define LP_CLKRST_CLK_LP_BUS_OEN_V 0x00000001U +#define LP_CLKRST_CLK_LP_BUS_OEN_S 1 +/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_SLOW_OEN (BIT(2)) +#define LP_CLKRST_CLK_AON_SLOW_OEN_M (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S) +#define LP_CLKRST_CLK_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_SLOW_OEN_S 2 +/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_FAST_OEN (BIT(3)) +#define LP_CLKRST_CLK_AON_FAST_OEN_M (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S) +#define LP_CLKRST_CLK_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_FAST_OEN_S 3 +/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SLOW_OEN (BIT(4)) +#define LP_CLKRST_CLK_SLOW_OEN_M (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S) +#define LP_CLKRST_CLK_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SLOW_OEN_S 4 +/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FAST_OEN (BIT(5)) +#define LP_CLKRST_CLK_FAST_OEN_M (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S) +#define LP_CLKRST_CLK_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FAST_OEN_S 5 +/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FOSC_OEN (BIT(6)) +#define LP_CLKRST_CLK_FOSC_OEN_M (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S) +#define LP_CLKRST_CLK_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FOSC_OEN_S 6 +/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_RC32K_OEN (BIT(7)) +#define LP_CLKRST_CLK_RC32K_OEN_M (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S) +#define LP_CLKRST_CLK_RC32K_OEN_V 0x00000001U +#define LP_CLKRST_CLK_RC32K_OEN_S 7 +/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SXTAL_OEN (BIT(8)) +#define LP_CLKRST_CLK_SXTAL_OEN_M (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S) +#define LP_CLKRST_CLK_SXTAL_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SXTAL_OEN_S 8 +/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off + */ +#define LP_CLKRST_CLK_SOSC_OEN (BIT(9)) +#define LP_CLKRST_CLK_SOSC_OEN_M (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S) +#define LP_CLKRST_CLK_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SOSC_OEN_S 9 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S 26 +/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LP_CLKRST_CK_EN_LP_RAM (BIT(27)) +#define LP_CLKRST_CK_EN_LP_RAM_M (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S) +#define LP_CLKRST_CK_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_CK_EN_LP_RAM_S 27 +/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_ETM_EVENT_TICK_EN (BIT(28)) +#define LP_CLKRST_ETM_EVENT_TICK_EN_M (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S) +#define LP_CLKRST_ETM_EVENT_TICK_EN_V 0x00000001U +#define LP_CLKRST_ETM_EVENT_TICK_EN_S 28 +/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S 29 +/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_XTAL_CLK_FORCE_ON (BIT(30)) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_M (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_XTAL_CLK_FORCE_ON_S 30 +/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FOSC_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_M (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_FOSC_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_HUK (BIT(24)) +#define LP_CLKRST_RST_EN_LP_HUK_M (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S) +#define LP_CLKRST_RST_EN_LP_HUK_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_HUK_S 24 +/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_ANAPERI (BIT(25)) +#define LP_CLKRST_RST_EN_LP_ANAPERI_M (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S) +#define LP_CLKRST_RST_EN_LP_ANAPERI_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_ANAPERI_S 25 +/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_WDT (BIT(26)) +#define LP_CLKRST_RST_EN_LP_WDT_M (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S) +#define LP_CLKRST_RST_EN_LP_WDT_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_WDT_S 26 +/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_TIMER (BIT(27)) +#define LP_CLKRST_RST_EN_LP_TIMER_M (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S) +#define LP_CLKRST_RST_EN_LP_TIMER_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_TIMER_S 27 +/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RTC (BIT(28)) +#define LP_CLKRST_RST_EN_LP_RTC_M (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S) +#define LP_CLKRST_RST_EN_LP_RTC_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RTC_S 28 +/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_MAILBOX (BIT(29)) +#define LP_CLKRST_RST_EN_LP_MAILBOX_M (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S) +#define LP_CLKRST_RST_EN_LP_MAILBOX_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_MAILBOX_S 29 +/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S 30 +/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RAM (BIT(31)) +#define LP_CLKRST_RST_EN_LP_RAM_M (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S) +#define LP_CLKRST_RST_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RAM_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_M (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_S 0 +/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG (BIT(6)) +#define LP_CLKRST_LPCORE_RESET_FLAG_M (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_S 6 +/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_M (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_S 7 +/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG (BIT(13)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_M (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_S 13 +/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_M (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_S 14 +/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG (BIT(20)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_M (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_S 20 +/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 +/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S 26 +/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S 27 +/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 +/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S 29 +/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 +/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 +/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_M (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S) +#define LP_CLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_S 5 +/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_EN (BIT(12)) +#define LP_CLKRST_HPCORE0_STALL_EN_M (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S) +#define LP_CLKRST_HPCORE0_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_STALL_EN_S 12 +/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_SW_RESET (BIT(13)) +#define LP_CLKRST_HPCORE0_SW_RESET_M (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S) +#define LP_CLKRST_HPCORE0_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_SW_RESET_S 13 +/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 +/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 +/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 +/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_M (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S) +#define LP_CLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_S 21 +/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_EN (BIT(28)) +#define LP_CLKRST_HPCORE1_STALL_EN_M (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S) +#define LP_CLKRST_HPCORE1_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_STALL_EN_S 28 +/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_SW_RESET (BIT(29)) +#define LP_CLKRST_HPCORE1_SW_RESET_M (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S) +#define LP_CLKRST_HPCORE1_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_SW_RESET_S 29 +/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 +/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S 16 +/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S 24 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_S 0 + +/** LP_CLKRST_SOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_SOSC_DFREQ 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_M (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S) +#define LP_CLKRST_SOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34) +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S) +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38) +/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c) +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S 0 + +/** LP_CLKRST_HP_CLK_CTRL_REG register + * HP Clock Control Register. + */ +#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40) +/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S) +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S 0 +/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ +#define LP_CLKRST_HP_ROOT_CLK_EN (BIT(2)) +#define LP_CLKRST_HP_ROOT_CLK_EN_M (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S) +#define LP_CLKRST_HP_ROOT_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_ROOT_CLK_EN_S 2 +/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 +/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 +/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 +/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 +/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 +/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 +/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 +/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S 10 +/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S 11 +/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S 12 +/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; + * EMAC RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 +/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; + * EMAC TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 +/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; + * EMAC TXRX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 +/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S 16 +/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ +#define LP_CLKRST_HP_RC_32K_CLK_EN (BIT(17)) +#define LP_CLKRST_HP_RC_32K_CLK_EN_M (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S) +#define LP_CLKRST_HP_RC_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_RC_32K_CLK_EN_S 17 +/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ +#define LP_CLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S 18 +/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ +#define LP_CLKRST_HP_PLL_8M_CLK_EN (BIT(19)) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_M (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PLL_8M_CLK_EN_S 19 +/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S 20 +/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S 21 +/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S 22 +/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S 23 +/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ +#define LP_CLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S 24 +/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enalbe. + */ +#define LP_CLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S 25 +/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ +#define LP_CLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S 26 +/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ +#define LP_CLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S 27 +/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ +#define LP_CLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S 28 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44) +/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S 0 +/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 +/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S 2 +/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 +/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ +#define LP_CLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S 4 +/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S 5 +/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ +#define LP_CLKRST_USB_48M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_M (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S) +#define LP_CLKRST_USB_48M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_S 6 +/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ +#define LP_CLKRST_USB_25M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_M (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S) +#define LP_CLKRST_USB_25M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_S 14 +/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ +#define LP_CLKRST_USB_12M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_M (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S) +#define LP_CLKRST_USB_12M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_S 22 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48) +/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S 0 +/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S 1 +/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20 (BIT(2)) +#define LP_CLKRST_RST_EN_USB_OTG20_M (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S) +#define LP_CLKRST_RST_EN_USB_OTG20_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_S 2 +/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG11 (BIT(3)) +#define LP_CLKRST_RST_EN_USB_OTG11_M (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S) +#define LP_CLKRST_RST_EN_USB_OTG11_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG11_S 3 +/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ +#define LP_CLKRST_RST_EN_USB_DEVICE (BIT(4)) +#define LP_CLKRST_RST_EN_USB_DEVICE_M (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S) +#define LP_CLKRST_RST_EN_USB_DEVICE_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_DEVICE_S 4 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 +/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S 31 + +/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register + * need_des + */ +#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c) +/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ +#define LP_CLKRST_RST_EN_SDMMC (BIT(28)) +#define LP_CLKRST_RST_EN_SDMMC_M (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S) +#define LP_CLKRST_RST_EN_SDMMC_V 0x00000001U +#define LP_CLKRST_RST_EN_SDMMC_S 28 +/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ +#define LP_CLKRST_FORCE_NORST_SDMMC (BIT(29)) +#define LP_CLKRST_FORCE_NORST_SDMMC_M (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S) +#define LP_CLKRST_FORCE_NORST_SDMMC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_SDMMC_S 29 +/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; + * hp emac reset en + */ +#define LP_CLKRST_RST_EN_EMAC (BIT(30)) +#define LP_CLKRST_RST_EN_EMAC_M (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S) +#define LP_CLKRST_RST_EN_EMAC_V 0x00000001U +#define LP_CLKRST_RST_EN_EMAC_S 30 +/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; + * hp emac force norst + */ +#define LP_CLKRST_FORCE_NORST_EMAC (BIT(31)) +#define LP_CLKRST_FORCE_NORST_EMAC_M (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S) +#define LP_CLKRST_FORCE_NORST_EMAC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_EMAC_S 31 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h similarity index 91% rename from components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h rename to components/soc/esp32p4/include/soc/lp_clkrst_struct.h index 6012eb38d7..2ade245136 100644 --- a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h +++ b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h @@ -35,7 +35,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} lp_aonclkrst_lp_clk_conf_reg_t; +} lp_clkrst_lp_clk_conf_reg_t; /** Type of lp_clk_po_en register * need_des @@ -86,7 +86,7 @@ typedef union { uint32_t reserved_10:22; }; uint32_t val; -} lp_aonclkrst_lp_clk_po_en_reg_t; +} lp_clkrst_lp_clk_po_en_reg_t; /** Type of lp_clk_en register * need_des @@ -120,7 +120,7 @@ typedef union { uint32_t fosc_clk_force_on:1; }; uint32_t val; -} lp_aonclkrst_lp_clk_en_reg_t; +} lp_clkrst_lp_clk_en_reg_t; /** Type of lp_rst_en register * need_des @@ -162,7 +162,7 @@ typedef union { uint32_t rst_en_lp_ram:1; }; uint32_t val; -} lp_aonclkrst_lp_rst_en_reg_t; +} lp_clkrst_lp_rst_en_reg_t; /** Type of reset_cause register * need_des @@ -264,7 +264,7 @@ typedef union { uint32_t hpcore1_reset_flag_clr:1; }; uint32_t val; -} lp_aonclkrst_reset_cause_reg_t; +} lp_clkrst_reset_cause_reg_t; /** Type of hpcpu_reset_ctrl0 register * need_des @@ -343,7 +343,7 @@ typedef union { uint32_t hpcore1_stat_vector_sel:1; }; uint32_t val; -} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t; +} lp_clkrst_hpcpu_reset_ctrl0_reg_t; /** Type of hpcpu_reset_ctrl1 register * need_des @@ -361,7 +361,7 @@ typedef union { uint32_t hpcore1_sw_stall_code:8; }; uint32_t val; -} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t; +} lp_clkrst_hpcpu_reset_ctrl1_reg_t; /** Type of fosc_cntl register * need_des @@ -375,7 +375,7 @@ typedef union { uint32_t fosc_dfreq:10; }; uint32_t val; -} lp_aonclkrst_fosc_cntl_reg_t; +} lp_clkrst_fosc_cntl_reg_t; /** Type of rc32k_cntl register * need_des @@ -388,7 +388,7 @@ typedef union { uint32_t rc32k_dfreq:32; }; uint32_t val; -} lp_aonclkrst_rc32k_cntl_reg_t; +} lp_clkrst_rc32k_cntl_reg_t; /** Type of sosc_cntl register * need_des @@ -402,7 +402,7 @@ typedef union { uint32_t sosc_dfreq:10; }; uint32_t val; -} lp_aonclkrst_sosc_cntl_reg_t; +} lp_clkrst_sosc_cntl_reg_t; /** Type of clk_to_hp register * need_des @@ -428,7 +428,7 @@ typedef union { uint32_t icg_hp_fosc:1; }; uint32_t val; -} lp_aonclkrst_clk_to_hp_reg_t; +} lp_clkrst_clk_to_hp_reg_t; /** Type of lpmem_force register * need_des @@ -442,7 +442,7 @@ typedef union { uint32_t lpmem_clk_force_on:1; }; uint32_t val; -} lp_aonclkrst_lpmem_force_reg_t; +} lp_clkrst_lpmem_force_reg_t; /** Type of xtal32k register * need_des @@ -468,7 +468,7 @@ typedef union { uint32_t dac_xtal32k:3; }; uint32_t val; -} lp_aonclkrst_xtal32k_reg_t; +} lp_clkrst_xtal32k_reg_t; /** Type of mux_hpsys_reset_bypass register * need_des @@ -481,7 +481,7 @@ typedef union { uint32_t mux_hpsys_reset_bypass:32; }; uint32_t val; -} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t; +} lp_clkrst_mux_hpsys_reset_bypass_reg_t; /** Type of hpsys_0_reset_bypass register * need_des @@ -494,7 +494,7 @@ typedef union { uint32_t hpsys_0_reset_bypass:32; }; uint32_t val; -} lp_aonclkrst_hpsys_0_reset_bypass_reg_t; +} lp_clkrst_hpsys_0_reset_bypass_reg_t; /** Type of hpsys_apm_reset_bypass register * need_des @@ -507,7 +507,7 @@ typedef union { uint32_t hpsys_apm_reset_bypass:32; }; uint32_t val; -} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t; +} lp_clkrst_hpsys_apm_reset_bypass_reg_t; /** Type of hp_clk_ctrl register * HP Clock Control Register. @@ -629,7 +629,7 @@ typedef union { uint32_t reserved_29:3; }; uint32_t val; -} lp_aonclkrst_hp_clk_ctrl_reg_t; +} lp_clkrst_hp_clk_ctrl_reg_t; /** Type of hp_usb_clkrst_ctrl0 register * HP USB Clock Reset Control Register. @@ -675,7 +675,7 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t; +} lp_clkrst_hp_usb_clkrst_ctrl0_reg_t; /** Type of hp_usb_clkrst_ctrl1 register * HP USB Clock Reset Control Register. @@ -717,7 +717,7 @@ typedef union { uint32_t usb_otg20_ulpi_clk_en:1; }; uint32_t val; -} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t; +} lp_clkrst_hp_usb_clkrst_ctrl1_reg_t; /** Type of hp_sdmmc_emac_rst_ctrl register * need_des @@ -743,7 +743,7 @@ typedef union { uint32_t force_norst_emac:1; }; uint32_t val; -} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t; +} lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t; /** Type of date register * need_des @@ -757,37 +757,37 @@ typedef union { uint32_t clk_en:1; }; uint32_t val; -} lp_aonclkrst_date_reg_t; +} lp_clkrst_date_reg_t; typedef struct { - volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf; - volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en; - volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en; - volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en; - volatile lp_aonclkrst_reset_cause_reg_t reset_cause; - volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0; - volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1; - volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl; - volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl; - volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl; - volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp; - volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force; - volatile lp_aonclkrst_xtal32k_reg_t xtal32k; - volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass; - volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass; - volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass; - volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl; - volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0; - volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1; - volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl; + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0; + volatile lp_clkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + volatile lp_clkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass; + volatile lp_clkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass; + volatile lp_clkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass; + volatile lp_clkrst_hp_clk_ctrl_reg_t hp_clk_ctrl; + volatile lp_clkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0; + volatile lp_clkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1; + volatile lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl; uint32_t reserved_050[235]; - volatile lp_aonclkrst_date_reg_t date; -} lp_aonclkrst_dev_t; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; #ifndef __cplusplus -_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure"); +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h new file mode 100644 index 0000000000..5bfb2830d2 --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_LP_GPIO_SIG_MAP_H_ +#define _SOC_LP_GPIO_SIG_MAP_H_ + +#define LP_I2C_SCL_PAD_IN_IDX 0 +#define LP_I2C_SCL_PAD_OUT_IDX 0 +#define LP_I2C_SDA_PAD_IN_IDX 1 +#define LP_I2C_SDA_PAD_OUT_IDX 1 +#define LP_UART_RXD_PAD_IN_IDX 2 +#define LP_UART_TXD_PAD_OUT_IDX 2 +#define LP_UART_CTSN_PAD_IN_IDX 3 +#define LP_UART_RTSN_PAD_OUT_IDX 3 +#define LP_UART_DSRN_PAD_IN_IDX 4 +#define LP_UART_DTRN_PAD_OUT_IDX 4 +#define LP_SPI_CK_PAD_IN_IDX 5 +#define LP_SPI_CK_PAD_OUT_IDX 5 +#define LP_SPI_CS_PAD_IN_IDX 6 +#define LP_SPI_CS_PAD_OUT_IDX 6 +#define LP_SPI_D_PAD_IN_IDX 7 +#define LP_SPI_D_PAD_OUT_IDX 7 +#define LP_SPI_Q_PAD_IN_IDX 8 +#define LP_SPI_Q_PAD_OUT_IDX 8 +#define LP_I2S_I_BCK_PAD_IN_IDX 9 +#define LP_I2S_I_BCK_PAD_OUT_IDX 9 +#define LP_I2S_I_SD_PAD_IN_IDX 10 +#define LP_I2S_O_SD_PAD_OUT_IDX 10 +#define LP_I2S_I_WS_PAD_IN_IDX 11 +#define LP_I2S_I_WS_PAD_OUT_IDX 11 +#define LP_I2S_O_BCK_PAD_IN_IDX 12 +#define LP_I2S_O_BCK_PAD_OUT_IDX 12 +#define LP_I2S_O_WS_PAD_IN_IDX 13 +#define LP_I2S_O_WS_PAD_OUT_IDX 13 +#define LP_PROBE_TOP_OUT0_IDX 14 +#define LP_PROBE_TOP_OUT1_IDX 15 +#define LP_PROBE_TOP_OUT2_IDX 16 +#define LP_PROBE_TOP_OUT3_IDX 17 +#define LP_PROBE_TOP_OUT4_IDX 18 +#define LP_PROBE_TOP_OUT5_IDX 19 +#define LP_PROBE_TOP_OUT6_IDX 20 +#define LP_PROBE_TOP_OUT7_IDX 21 +#define LP_PROBE_TOP_OUT8_IDX 22 +#define LP_PROBE_TOP_OUT9_IDX 23 +#define LP_PROBE_TOP_OUT10_IDX 24 +#define LP_PROBE_TOP_OUT11_IDX 25 +#define LP_PROBE_TOP_OUT12_IDX 26 +#define LP_PROBE_TOP_OUT13_IDX 27 +#define LP_PROBE_TOP_OUT14_IDX 28 +#define LP_PROBE_TOP_OUT15_IDX 29 +#define PROBE_CHAIN_CLK_PAD_OUT_IDX 30 +#define GPIO_MAP_DATE_IDX 0x230323 +#endif /* _SOC_LP_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32p4/include/soc/lp_gpio_struct.h b/components/soc/esp32p4/include/soc/lp_gpio_struct.h index 78bcfcaff9..507cf47a8f 100644 --- a/components/soc/esp32p4/include/soc/lp_gpio_struct.h +++ b/components/soc/esp32p4/include/soc/lp_gpio_struct.h @@ -1449,7 +1449,7 @@ typedef union { } lp_gpio_func15_out_sel_cfg_reg_t; -typedef struct { +typedef struct lp_gpio_dev_t { volatile lp_gpio_clk_en_reg_t clk_en; volatile lp_gpio_ver_date_reg_t ver_date; volatile lp_gpio_out_reg_t out; @@ -1512,6 +1512,8 @@ typedef struct { volatile lp_gpio_func15_out_sel_cfg_reg_t func15_out_sel_cfg; } lp_gpio_dev_t; +extern lp_gpio_dev_t LP_GPIO; + #ifndef __cplusplus _Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h new file mode 100644 index 0000000000..ed40ee7b05 --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h @@ -0,0 +1,135 @@ +/** + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_ANA_MST_I2C0_CTRL_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) +/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) +#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) +#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C0_CONF_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) +/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) +#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_S 0 +/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7; + * reserved + */ +#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) +#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C0_DATA_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) +/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S) +#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_S 0 +/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S) +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8 +/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11)) +#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S) +#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11 + +/** LP_I2C_ANA_MST_ANA_CONF1_REG register + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) +/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) +#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_S 0 + +/** LP_I2C_ANA_MST_NOUSE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) +/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** LP_I2C_ANA_MST_DEVICE_EN_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) +/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S) +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0 + +/** LP_I2C_ANA_MST_DATE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc) +/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S) +#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0 +/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28)) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h new file mode 100644 index 0000000000..46aedaf634 --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h @@ -0,0 +1,150 @@ +/** + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of i2c0_ctrl register + * need_des + */ +typedef union { + struct { + /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0; + * need_des + */ + uint32_t i2c0_ctrl:25; + /** i2c0_busy : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t i2c0_busy:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_ctrl_reg_t; + +/** Type of i2c0_conf register + * need_des + */ +typedef union { + struct { + /** i2c0_conf : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t i2c0_conf:24; + /** i2c0_status : RO; bitpos: [31:24]; default: 7; + * reserved + */ + uint32_t i2c0_status:8; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_conf_reg_t; + +/** Type of i2c0_data register + * need_des + */ +typedef union { + struct { + /** i2c0_rdata : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t i2c0_rdata:8; + /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1; + * need_des + */ + uint32_t i2c0_clk_sel:3; + /** i2c_mst_sel : R/W; bitpos: [11]; default: 1; + * need des + */ + uint32_t i2c_mst_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_data_reg_t; + +/** Type of ana_conf1 register + * need_des + */ +typedef union { + struct { + /** ana_conf1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t ana_conf1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_i2c_ana_mst_ana_conf1_reg_t; + +/** Type of nouse register + * need_des + */ +typedef union { + struct { + /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t i2c_mst_nouse:32; + }; + uint32_t val; +} lp_i2c_ana_mst_nouse_reg_t; + +/** Type of device_en register + * need_des + */ +typedef union { + struct { + /** i2c_device_en : R/W; bitpos: [11:0]; default: 0; + * need_des + */ + uint32_t i2c_device_en:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_device_en_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ + uint32_t i2c_mat_date:28; + /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t i2c_mat_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_i2c_ana_mst_date_reg_t; + + +typedef struct lp_i2c_ana_mst_dev_t { + volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data; + volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile lp_i2c_ana_mst_nouse_reg_t nouse; + volatile lp_i2c_ana_mst_device_en_reg_t device_en; + uint32_t reserved_018[249]; + volatile lp_i2c_ana_mst_date_reg_t date; +} lp_i2c_ana_mst_dev_t; + +extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/include/soc/lp_iomux_struct.h index 5d19cd4a0e..c389b7e4fa 100644 --- a/components/soc/esp32p4/include/soc/lp_iomux_struct.h +++ b/components/soc/esp32p4/include/soc/lp_iomux_struct.h @@ -926,7 +926,7 @@ typedef union { } lp_iomux_lp_pad_hys_reg_t; -typedef struct { +typedef struct lp_iomux_dev_t { volatile lp_iomux_clk_en_reg_t clk_en; volatile lp_iomux_ver_date_reg_t ver_date; volatile lp_iomux_pad0_reg_t pad0; diff --git a/components/soc/esp32p4/include/soc/lp_timer_reg.h b/components/soc/esp32p4/include/soc/lp_timer_reg.h new file mode 100644 index 0000000000..7628cbf7e0 --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_timer_reg.h @@ -0,0 +1,342 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/rtc_timer_struct.h b/components/soc/esp32p4/include/soc/lp_timer_struct.h similarity index 81% rename from components/soc/esp32p4/include/soc/rtc_timer_struct.h rename to components/soc/esp32p4/include/soc/lp_timer_struct.h index b20d4e0eb6..11c0aad66e 100644 --- a/components/soc/esp32p4/include/soc/rtc_timer_struct.h +++ b/components/soc/esp32p4/include/soc/lp_timer_struct.h @@ -22,7 +22,7 @@ typedef union { uint32_t main_timer_tar_low0:32; }; uint32_t val; -} rtc_timer_tar0_low_reg_t; +} lp_timer_tar0_low_reg_t; /** Type of tar0_high register * need_des @@ -40,7 +40,7 @@ typedef union { uint32_t main_timer_tar_en0:1; }; uint32_t val; -} rtc_timer_tar0_high_reg_t; +} lp_timer_tar0_high_reg_t; /** Type of tar1_low register * need_des @@ -53,7 +53,7 @@ typedef union { uint32_t main_timer_tar_low1:32; }; uint32_t val; -} rtc_timer_tar1_low_reg_t; +} lp_timer_tar1_low_reg_t; /** Type of tar1_high register * need_des @@ -71,7 +71,7 @@ typedef union { uint32_t main_timer_tar_en1:1; }; uint32_t val; -} rtc_timer_tar1_high_reg_t; +} lp_timer_tar1_high_reg_t; /** Type of update register * need_des @@ -97,7 +97,7 @@ typedef union { uint32_t main_timer_sys_rst:1; }; uint32_t val; -} rtc_timer_update_reg_t; +} lp_timer_update_reg_t; /** Type of main_buf0_low register * need_des @@ -110,7 +110,7 @@ typedef union { uint32_t main_timer_buf0_low:32; }; uint32_t val; -} rtc_timer_main_buf0_low_reg_t; +} lp_timer_main_buf0_low_reg_t; /** Type of main_buf0_high register * need_des @@ -124,7 +124,7 @@ typedef union { uint32_t reserved_16:16; }; uint32_t val; -} rtc_timer_main_buf0_high_reg_t; +} lp_timer_main_buf0_high_reg_t; /** Type of main_buf1_low register * need_des @@ -137,7 +137,7 @@ typedef union { uint32_t main_timer_buf1_low:32; }; uint32_t val; -} rtc_timer_main_buf1_low_reg_t; +} lp_timer_main_buf1_low_reg_t; /** Type of main_buf1_high register * need_des @@ -151,7 +151,7 @@ typedef union { uint32_t reserved_16:16; }; uint32_t val; -} rtc_timer_main_buf1_high_reg_t; +} lp_timer_main_buf1_high_reg_t; /** Type of main_overflow register * need_des @@ -165,7 +165,7 @@ typedef union { uint32_t main_timer_alarm_load:1; }; uint32_t val; -} rtc_timer_main_overflow_reg_t; +} lp_timer_main_overflow_reg_t; /** Type of int_raw register * need_des @@ -183,7 +183,7 @@ typedef union { uint32_t soc_wakeup_int_raw:1; }; uint32_t val; -} rtc_timer_int_raw_reg_t; +} lp_timer_int_raw_reg_t; /** Type of int_st register * need_des @@ -201,7 +201,7 @@ typedef union { uint32_t soc_wakeup_int_st:1; }; uint32_t val; -} rtc_timer_int_st_reg_t; +} lp_timer_int_st_reg_t; /** Type of int_ena register * need_des @@ -219,7 +219,7 @@ typedef union { uint32_t soc_wakeup_int_ena:1; }; uint32_t val; -} rtc_timer_int_ena_reg_t; +} lp_timer_int_ena_reg_t; /** Type of int_clr register * need_des @@ -237,7 +237,7 @@ typedef union { uint32_t soc_wakeup_int_clr:1; }; uint32_t val; -} rtc_timer_int_clr_reg_t; +} lp_timer_int_clr_reg_t; /** Type of lp_int_raw register * need_des @@ -255,7 +255,7 @@ typedef union { uint32_t main_timer_lp_int_raw:1; }; uint32_t val; -} rtc_timer_lp_int_raw_reg_t; +} lp_timer_lp_int_raw_reg_t; /** Type of lp_int_st register * need_des @@ -273,7 +273,7 @@ typedef union { uint32_t main_timer_lp_int_st:1; }; uint32_t val; -} rtc_timer_lp_int_st_reg_t; +} lp_timer_lp_int_st_reg_t; /** Type of lp_int_ena register * need_des @@ -291,7 +291,7 @@ typedef union { uint32_t main_timer_lp_int_ena:1; }; uint32_t val; -} rtc_timer_lp_int_ena_reg_t; +} lp_timer_lp_int_ena_reg_t; /** Type of lp_int_clr register * need_des @@ -309,7 +309,7 @@ typedef union { uint32_t main_timer_lp_int_clr:1; }; uint32_t val; -} rtc_timer_lp_int_clr_reg_t; +} lp_timer_lp_int_clr_reg_t; /** Type of date register * need_des @@ -326,35 +326,35 @@ typedef union { uint32_t clk_en:1; }; uint32_t val; -} rtc_timer_date_reg_t; +} lp_timer_date_reg_t; typedef struct { - volatile rtc_timer_tar0_low_reg_t tar0_low; - volatile rtc_timer_tar0_high_reg_t tar0_high; - volatile rtc_timer_tar1_low_reg_t tar1_low; - volatile rtc_timer_tar1_high_reg_t tar1_high; - volatile rtc_timer_update_reg_t update; - volatile rtc_timer_main_buf0_low_reg_t main_buf0_low; - volatile rtc_timer_main_buf0_high_reg_t main_buf0_high; - volatile rtc_timer_main_buf1_low_reg_t main_buf1_low; - volatile rtc_timer_main_buf1_high_reg_t main_buf1_high; - volatile rtc_timer_main_overflow_reg_t main_overflow; - volatile rtc_timer_int_raw_reg_t int_raw; - volatile rtc_timer_int_st_reg_t int_st; - volatile rtc_timer_int_ena_reg_t int_ena; - volatile rtc_timer_int_clr_reg_t int_clr; - volatile rtc_timer_lp_int_raw_reg_t lp_int_raw; - volatile rtc_timer_lp_int_st_reg_t lp_int_st; - volatile rtc_timer_lp_int_ena_reg_t lp_int_ena; - volatile rtc_timer_lp_int_clr_reg_t lp_int_clr; + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + volatile lp_timer_tar1_low_reg_t tar1_low; + volatile lp_timer_tar1_high_reg_t tar1_high; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; uint32_t reserved_048[237]; - volatile rtc_timer_date_reg_t date; -} rtc_timer_dev_t; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; #ifndef __cplusplus -_Static_assert(sizeof(rtc_timer_dev_t) == 0x400, "Invalid size of rtc_timer_dev_t structure"); +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/lp_wdt_reg.h b/components/soc/esp32p4/include/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..c2fcd17511 --- /dev/null +++ b/components/soc/esp32p4/include/soc/lp_wdt_reg.h @@ -0,0 +1,324 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_FEED (BIT(31)) +#define LP_WDT_FEED_M (LP_WDT_FEED_V << LP_WDT_FEED_S) +#define LP_WDT_FEED_V 0x00000001U +#define LP_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/rtc_wdt_struct.h b/components/soc/esp32p4/include/soc/lp_wdt_struct.h similarity index 85% rename from components/soc/esp32p4/include/soc/rtc_wdt_struct.h rename to components/soc/esp32p4/include/soc/lp_wdt_struct.h index 2c96355399..2e8976accd 100644 --- a/components/soc/esp32p4/include/soc/rtc_wdt_struct.h +++ b/components/soc/esp32p4/include/soc/lp_wdt_struct.h @@ -63,7 +63,7 @@ typedef union { uint32_t wdt_en:1; }; uint32_t val; -} rtc_wdt_config0_reg_t; +} lp_wdt_config0_reg_t; /** Type of config1 register * need_des @@ -76,7 +76,7 @@ typedef union { uint32_t wdt_stg0_hold:32; }; uint32_t val; -} rtc_wdt_config1_reg_t; +} lp_wdt_config1_reg_t; /** Type of config2 register * need_des @@ -89,7 +89,7 @@ typedef union { uint32_t wdt_stg1_hold:32; }; uint32_t val; -} rtc_wdt_config2_reg_t; +} lp_wdt_config2_reg_t; /** Type of config3 register * need_des @@ -102,7 +102,7 @@ typedef union { uint32_t wdt_stg2_hold:32; }; uint32_t val; -} rtc_wdt_config3_reg_t; +} lp_wdt_config3_reg_t; /** Type of config4 register * need_des @@ -115,7 +115,7 @@ typedef union { uint32_t wdt_stg3_hold:32; }; uint32_t val; -} rtc_wdt_config4_reg_t; +} lp_wdt_config4_reg_t; /** Type of feed register * need_des @@ -129,7 +129,7 @@ typedef union { uint32_t feed:1; }; uint32_t val; -} rtc_wdt_feed_reg_t; +} lp_wdt_feed_reg_t; /** Type of wprotect register * need_des @@ -142,7 +142,7 @@ typedef union { uint32_t wdt_wkey:32; }; uint32_t val; -} rtc_wdt_wprotect_reg_t; +} lp_wdt_wprotect_reg_t; /** Type of swd_config register * need_des @@ -176,7 +176,7 @@ typedef union { uint32_t swd_feed:1; }; uint32_t val; -} rtc_wdt_swd_config_reg_t; +} lp_wdt_swd_config_reg_t; /** Type of swd_wprotect register * need_des @@ -189,7 +189,7 @@ typedef union { uint32_t swd_wkey:32; }; uint32_t val; -} rtc_wdt_swd_wprotect_reg_t; +} lp_wdt_swd_wprotect_reg_t; /** Type of int_raw register * need_des @@ -207,7 +207,7 @@ typedef union { uint32_t lp_wdt_int_raw:1; }; uint32_t val; -} rtc_wdt_int_raw_reg_t; +} lp_wdt_int_raw_reg_t; /** Type of int_st register * need_des @@ -225,7 +225,7 @@ typedef union { uint32_t lp_wdt_int_st:1; }; uint32_t val; -} rtc_wdt_int_st_reg_t; +} lp_wdt_int_st_reg_t; /** Type of int_ena register * need_des @@ -243,7 +243,7 @@ typedef union { uint32_t lp_wdt_int_ena:1; }; uint32_t val; -} rtc_wdt_int_ena_reg_t; +} lp_wdt_int_ena_reg_t; /** Type of int_clr register * need_des @@ -261,7 +261,7 @@ typedef union { uint32_t lp_wdt_int_clr:1; }; uint32_t val; -} rtc_wdt_int_clr_reg_t; +} lp_wdt_int_clr_reg_t; /** Type of date register * need_des @@ -278,30 +278,31 @@ typedef union { uint32_t clk_en:1; }; uint32_t val; -} rtc_wdt_date_reg_t; +} lp_wdt_date_reg_t; typedef struct { - volatile rtc_wdt_config0_reg_t config0; - volatile rtc_wdt_config1_reg_t config1; - volatile rtc_wdt_config2_reg_t config2; - volatile rtc_wdt_config3_reg_t config3; - volatile rtc_wdt_config4_reg_t config4; - volatile rtc_wdt_feed_reg_t feed; - volatile rtc_wdt_wprotect_reg_t wprotect; - volatile rtc_wdt_swd_config_reg_t swd_config; - volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect; - volatile rtc_wdt_int_raw_reg_t int_raw; - volatile rtc_wdt_int_st_reg_t int_st; - volatile rtc_wdt_int_ena_reg_t int_ena; - volatile rtc_wdt_int_clr_reg_t int_clr; + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; uint32_t reserved_034[242]; - volatile rtc_wdt_date_reg_t date; -} rtc_wdt_dev_t; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; +extern lp_wdt_dev_t LP_WDT; #ifndef __cplusplus -_Static_assert(sizeof(rtc_wdt_dev_t) == 0x400, "Invalid size of rtc_wdt_dev_t structure"); +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/memprot_defs.h b/components/soc/esp32p4/include/soc/memprot_defs.h new file mode 100644 index 0000000000..9723f61eb5 --- /dev/null +++ b/components/soc/esp32p4/include/soc/memprot_defs.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc.h" +#include "esp32p4/rom/cache.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t cat0 : 2; + uint32_t cat1 : 2; + uint32_t cat2 : 2; + uint32_t res0 : 8; + uint32_t splitaddr : 8; + uint32_t res1 : 10; + }; + uint32_t val; +} constrain_reg_fields_t; + +#ifndef I_D_SRAM_SEGMENT_SIZE +#define I_D_SRAM_SEGMENT_SIZE 0x20000 +#endif + +#define I_D_SPLIT_LINE_SHIFT 0x9 +#define I_D_FAULT_ADDR_SHIFT 0x2 + +#define DRAM_SRAM_START 0x3FC7C000 + +//IRAM0 + +//16kB (ICACHE) +#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 +#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF + +//128kB (LEVEL 1) +#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 +#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF + +//128kB (LEVEL 2) +#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 +#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF + +//128kB (LEVEL 3) +#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 +#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF + +//permission bits +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 + +//DRAM0 + +//16kB ICACHE not available from DRAM0 + +//128kB (LEVEL 1) +#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 +#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF + +//128kB (LEVEL 2) +#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 +#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF + +//128kB (LEVEL 3) +#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 +#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 + +//RTC FAST + +//permission bits +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 + +#define AREA_LOW 0 +#define AREA_HIGH 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/mmu.h b/components/soc/esp32p4/include/soc/mmu.h new file mode 100644 index 0000000000..94937c2117 --- /dev/null +++ b/components/soc/esp32p4/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/ext_mem_defs.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//To delete this file +//TODO: IDF-7686 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/parl_io_struct.h b/components/soc/esp32p4/include/soc/parl_io_struct.h index 97c911c737..7c1693b9bc 100644 --- a/components/soc/esp32p4/include/soc/parl_io_struct.h +++ b/components/soc/esp32p4/include/soc/parl_io_struct.h @@ -472,7 +472,7 @@ typedef union { } parl_io_version_reg_t; -typedef struct { +typedef struct parl_io_dev_t { volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; diff --git a/components/soc/esp32p4/include/soc/periph_defs.h b/components/soc/esp32p4/include/soc/periph_defs.h new file mode 100644 index 0000000000..2d6c1eaf8c --- /dev/null +++ b/components/soc/esp32p4/include/soc/periph_defs.h @@ -0,0 +1,223 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_MSPI_MODULE = 0, + PERIPH_DUALMSPI_MODULE, + PERIPH_EMAC_MODULE, + PERIPH_MIPI_DSI_MODULE, + PERIPH_MIPI_CSI_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_I2S2_MODULE, + + PERIPH_LCD_MODULE = 10, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_UART2_MODULE, + PERIPH_UART3_MODULE, + PERIPH_UART4_MODULE, + PERIPH_TWAI0_MODULE, + PERIPH_TWAI1_MODULE, + PERIPH_TWAI2_MODULE, + PERIPH_GPSPI_MODULE, + + PERIPH_GPSPI2_MODULE = 20, + PERIPH_GPSPI3_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_I3C_MODULE, + PERIPH_CAM_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_MCPWM1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_SYSTIMER_MODULE, + + PERIPH_LEDC_MODULE = 30, + PERIPH_RMT_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_PVT_MODULE, + PERIPH_AES_MODULE, + PERIPH_DS_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_RSA_MODULE, + PERIPH_SEC_MODULE, + + PERIPH_SHA_MODULE = 40, + PERIPH_ECDSA_MODULE, + PERIPH_ISP_MODULE, + PERIPH_SDMMC_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_GMAC_MODULE, + PERIPH_JPEG_MODULE, + PERIPH_DMA2D_MODULE, + PERIPH_PPA_MODULE, + PERIPH_AHB_PDMA_MODULE, + PERIPH_AXI_PDMA_MODULE, + PERIPH_UHCI_MODULE, + PERIPH_PCNT_MODULE, + + PERIPH_MODULE_MAX +} periph_module_t; + +typedef enum { + LP_PERIPH_I2C0_MODULE = 0, + LP_PERIPH_UART0_MODULE, + LP_PERIPH_MODULE_MAX, +} lp_periph_module_t; + +typedef enum { + ETS_LP_RTC_INTR_SOURCE = 0, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_TIMER_REG0_INTR_SOURCE, + ETS_LP_TIMER_REG1_INTR_SOURCE, + ETS_MB_HP_INTR_SOURCE, + ETS_MB_LP_INTR_SOURCE, + ETS_PMU_0_INTR_SOURCE, + ETS_PMU_1_INTR_SOURCE, + ETS_LP_ANAPERI_INTR_SOURCE, + ETS_LP_ADC_INTR_SOURCE, + ETS_LP_GPIO_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_I2S_INTR_SOURCE, + ETS_LP_SPI_INTR_SOURCE, + ETS_LP_TOUCH_INTR_SOURCE, + ETS_LP_TSENS_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_EFUSE_INTR_SOURCE, + ETS_LP_SW_INTR_SOURCE, + ETS_LP_SYSREG_INTR_SOURCE, + ETS_LP_HUK_INTR_SOURCE, + ETS_SYS_ICM_INTR_SOURCE, + ETS_USB_DEVICE_INTR_SOURCE, + ETS_SDIO_HOST_INTR_SOURCE, + ETS_GDMA_INTR_SOURCE, + ETS_SPI2_INTR_SOURCE, + ETS_SPI3_INTR_SOURCE, + ETS_I2S0_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, + ETS_I2S2_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_UART2_INTR_SOURCE, + ETS_UART3_INTR_SOURCE, + ETS_UART4_INTR_SOURCE, + ETS_LCD_CAM_INTR_SOURCE, + ETS_ADC_INTR_SOURCE, + ETS_PWM0_INTR_SOURCE, + ETS_PWM1_INTR_SOURCE, + ETS_CAN0_INTR_SOURCE, + ETS_CAN1_INTR_SOURCE, + ETS_CAN2_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C0_INTR_SOURCE, + ETS_I2C1_INTR_SOURCE, + ETS_TIMERGROUP0_T0_INTR_SOURCE, + ETS_TIMERGROUP0_T1_INTR_SOURCE, + ETS_TIMERGROUP0_WDT_INTR_SOURCE, + ETS_TIMERGROUP1_T0_INTR_SOURCE, + ETS_TIMERGROUP1_T1_INTR_SOURCE, + ETS_TIMERGROUP1_WDT_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH0_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH1_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH2_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH0_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH1_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH2_INTR_SOURCE, + ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE, + ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE, + + ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE, + ETS_RSA_INTA_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_KM_INTR_SOURCE, + ETS_GPIO_INTR0_SOURCE, + + ETS_GPIO_INTR1_SOURCE, + ETS_GPIO_INTR2_SOURCE, + ETS_GPIO_INTR3_SOURCE, + ETS_GPIO_PAD_COMP_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU0_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU1_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU2_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU3_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_CSI_BRIDGE_INTR_SOURCE, + + ETS_DSI_BRIDGE_INTR_SOURCE, + ETS_CSI_INTR_SOURCE, + ETS_DSI_INTR_SOURCE, + ETS_GMII_PHY_INTR_SOURCE, + ETS_LPI_INTR_SOURCE, + ETS_PMT_INTR_SOURCE, + ETS_SBD_INTR_SOURCE, + ETS_USB_OTG_INTR_SOURCE, + ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE, + + ETS_JPEG_INTR_SOURCE, + ETS_PPA_INTR_SOURCE, + ETS_CORE0_TRACE_INTR_SOURCE, + ETS_CORE1_TRACE_INTR_SOURCE, + ETS_HP_CORE_CTRL_INTR_SOURCE, + ETS_ISP_INTR_SOURCE, + ETS_I3C_MST_INTR_SOURCE, + ETS_I3C_SLV_INTR_SOURCE, + ETS_USB_OTG11_CH0_INTR_SOURCE, + ETS_DMA2D_IN_CH0_INTR_SOURCE, + + ETS_DMA2D_IN_CH1_INTR_SOURCE, + ETS_DMA2D_OUT_CH0_INTR_SOURCE, + ETS_DMA2D_OUT_CH1_INTR_SOURCE, + ETS_DMA2D_OUT_CH2_INTR_SOURCE, + ETS_PSRAM_MSPI_INTR_SOURCE, + ETS_HP_SYSREG_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + + ETS_HP_PAU_INTR_SOURCE, + ETS_HP_PARLIO_RX_INTR_SOURCE, + ETS_HP_PARLIO_TX_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH0_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH1_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH2_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH3_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH4_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH0_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH1_INTR_SOURCE, + + ETS_H264_DMA2D_IN_CH2_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH3_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH4_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH5_INTR_SOURCE, + ETS_H264_REG_INTR_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, + + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ +} periph_interrput_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..a4fa889f1f --- /dev/null +++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define PMU_ICG_FUNC_CORE0_CPU_CLK_EN 0 +#define PMU_ICG_FUNC_CORE1_CPU_CLK_EN 1 +#define PMU_ICG_FUNC_CORE0_CLIC_CLK_EN 2 +#define PMU_ICG_FUNC_CORE1_CLIC_CLK_EN 3 +#define PMU_ICG_FUNC_MISC_CPU_CLK_EN 4 +#define PMU_ICG_FUNC_MISC_SYS_CLK_EN 5 +#define PMU_ICG_FUNC_ICM_SYS_CLK_EN 6 +#define PMU_ICG_FUNC_ICM_CPU_CLK_EN 7 +#define PMU_ICG_FUNC_ICM_MEM_CLK_EN 8 +#define PMU_ICG_FUNC_ICM_APB_CLK_EN 9 +#define PMU_ICG_FUNC_TCM_CPU_CLK_EN 10 +#define PMU_ICG_FUNC_L2MEM_MEM_CLK_EN 11 +#define PMU_ICG_FUNC_L2MEM_SYS_CLK_EN 12 +#define PMU_ICG_FUNC_L1CACHE_CPU_CLK_EN 13 +#define PMU_ICG_FUNC_LICACHE_D_CPU_CLK_EN 14 +#define PMU_ICG_FUNC_L1CACHE_I0_CPU_CLK_EN 15 +#define PMU_ICG_FUNC_L1CACHE_I1_CPU_CLK_EN 16 +#define PMU_ICG_FUNC_L1CACHE_MEM_CLK_EN 17 +#define PMU_ICG_FUNC_L1CACHE_D_MEM_CLK_EN 18 +#define PMU_ICG_FUNC_L1CACHE_I0_MEM_CLK_EN 19 +#define PMU_ICG_FUNC_L1CACHE_I1_MEM_CLK_EN 20 +#define PMU_ICG_FUNC_L2CACHE_MEM_CLK_EN 21 +#define PMU_ICG_FUNC_L2CACHE_SYS_CLK_EN 22 +#define PMU_ICG_FUNC_REGDMA_SYS_CLK_EN 23 +#define PMU_ICG_FUNC_HP_CLKRST_APB_CLK_EN 24 +#define PMU_ICG_FUNC_SYSREG_APB_CLK_EN 25 +#define PMU_ICG_FUNC_INTRMTX_APB_CLK_EN 26 diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h new file mode 100644 index 0000000000..5fb009f8cb --- /dev/null +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -0,0 +1,204 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Basic address */ +#define DR_REG_HPCPUTCP_BASE 0x3FF00000 +#define DR_REG_HPPERIPH0_BASE 0x50000000 +#define DR_REG_HPPERIPH1_BASE 0x500C0000 +#define DR_REG_LPAON_BASE 0x50110000 +#define DR_REG_LPPERIPH_BASE 0x50120000 + +/* This is raw module base from digital team + * some of them may not be used in rom + * just keep them for a reference + */ +/* + * @module: CPU-PERIPHERAL + * + * @base: 0x3FF00000 + * + * @size: 128KB + */ +#define DR_REG_TRACE0_BASE (DR_REG_HPCPUTCP_BASE + 0x4000) +#define DR_REG_TRACE1_BASE (DR_REG_HPCPUTCP_BASE + 0x5000) +#define DR_REG_CPU_BUS_MON_BASE (DR_REG_HPCPUTCP_BASE + 0x6000) +#define DR_REG_L2MEM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xE000) +#define DR_REG_TCM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xF000) +#define DR_REG_CACHE_BASE (DR_REG_HPCPUTCP_BASE + 0x10000) + +/* + * @module: PERIPHERAL0 + * + * @base: 0x50000000 + * + * @size: 768KB + */ +#define DR_REG_USB2_BASE (DR_REG_HPPERIPH0_BASE + 0x0) +#define DR_REG_USB11_BASE (DR_REG_HPPERIPH0_BASE + 0x40000) +#define DR_REG_USB_WRAP_BASE (DR_REG_HPPERIPH0_BASE + 0x80000) +#define DR_REG_GDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x81000) +#define DR_REG_REGDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x82000) +#define DR_REG_SDMMC_BASE (DR_REG_HPPERIPH0_BASE + 0x83000) +#define DR_REG_H264_CORE_BASE (DR_REG_HPPERIPH0_BASE + 0x84000) +#define DR_REG_AHB_PDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x85000) +#define DR_REG_JPEG_BASE (DR_REG_HPPERIPH0_BASE + 0x86000) +#define DR_REG_PPA_BASE (DR_REG_HPPERIPH0_BASE + 0x87000) +#define DR_REG_DMA2D_BASE (DR_REG_HPPERIPH0_BASE + 0x88000) +#define DR_REG_KEY_MANAGER_BASE (DR_REG_HPPERIPH0_BASE + 0x89000) +#define DR_REG_AXI_DMA_BASE (DR_REG_HPPERIPH0_BASE + 0x8A000) +#define DR_REG_FLASH_SPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8C000) +#define DR_REG_FLASH_SPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8D000) +#define DR_REG_PSRAM_MSPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8E000) +#define DR_REG_PSRAM_MSPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8F000) +#define DR_REG_CRYPTO_BASE (DR_REG_HPPERIPH0_BASE + 0x90000) +#define DR_REG_GMAC_BASE (DR_REG_HPPERIPH0_BASE + 0x98000) +#define DR_REG_USBPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9C000) +#define DR_REG_DDRPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9D000) +#define DR_REG_PVT_BASE (DR_REG_HPPERIPH0_BASE + 0x9E000) +#define DR_REG_CSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0x9F000) +#define DR_REG_DSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0xA0000) +#define DR_REG_ISP_BASE (DR_REG_HPPERIPH0_BASE + 0xA1000) +#define DR_REG_RMT_BASE (DR_REG_HPPERIPH0_BASE + 0xA2000) +#define DR_REG_BITSCRAM_BASE (DR_REG_HPPERIPH0_BASE + 0xA3000) +#define DR_REG_AXI_ICM_BASE (DR_REG_HPPERIPH0_BASE + 0xA4000) +#define DR_REG_HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5000) +#define DR_REG_LP2HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5800) +#define DR_REG_DMA_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA6000) +#define DR_REG_H264_DMA_2D_BASE (DR_REG_HPPERIPH0_BASE + 0xA7000) +/* + * @module: PERIPHERAL1 + * + * @base: 0x500C0000 + * + * @size: 256KB + */ +#define DR_REG_MCPWM0_BASE (DR_REG_HPPERIPH1_BASE + 0x0) +#define DR_REG_MCPWM1_BASE (DR_REG_HPPERIPH1_BASE + 0x1000) +#define DR_REG_TIMG0_BASE (DR_REG_HPPERIPH1_BASE + 0x2000) +#define DR_REG_TIMG1_BASE (DR_REG_HPPERIPH1_BASE + 0x3000) +#define DR_REG_I2C0_BASE (DR_REG_HPPERIPH1_BASE + 0x4000) +#define DR_REG_I2C1_BASE (DR_REG_HPPERIPH1_BASE + 0x5000) +#define DR_REG_I2S0_BASE (DR_REG_HPPERIPH1_BASE + 0x6000) +#define DR_REG_I2S1_BASE (DR_REG_HPPERIPH1_BASE + 0x7000) +#define DR_REG_I2S2_BASE (DR_REG_HPPERIPH1_BASE + 0x8000) +#define DR_REG_PCNT_BASE (DR_REG_HPPERIPH1_BASE + 0x9000) +#define DR_REG_UART0_BASE (DR_REG_HPPERIPH1_BASE + 0xA000) +#define DR_REG_UART1_BASE (DR_REG_HPPERIPH1_BASE + 0xB000) +#define DR_REG_UART2_BASE (DR_REG_HPPERIPH1_BASE + 0xC000) +#define DR_REG_UART3_BASE (DR_REG_HPPERIPH1_BASE + 0xD000) +#define DR_REG_UART4_BASE (DR_REG_HPPERIPH1_BASE + 0xE000) +#define DR_REG_PARIO_BASE (DR_REG_HPPERIPH1_BASE + 0xF000) +#define DR_REG_SPI2_BASE (DR_REG_HPPERIPH1_BASE + 0x10000) +#define DR_REG_SPI3_BASE (DR_REG_HPPERIPH1_BASE + 0x11000) +#define DR_REG_USB2JTAG_BASE (DR_REG_HPPERIPH1_BASE + 0x12000) +#define DR_REG_LEDC_BASE (DR_REG_HPPERIPH1_BASE + 0x13000) +#define DR_REG_ETM_BASE (DR_REG_HPPERIPH1_BASE + 0x15000) +#define DR_REG_INTR_BASE (DR_REG_HPPERIPH1_BASE + 0x16000) +#define DR_REG_TWAI0_BASE (DR_REG_HPPERIPH1_BASE + 0x17000) +#define DR_REG_TWAI1_BASE (DR_REG_HPPERIPH1_BASE + 0x18000) +#define DR_REG_TWAI2_BASE (DR_REG_HPPERIPH1_BASE + 0x19000) +#define DR_REG_I3C_MST_BASE (DR_REG_HPPERIPH1_BASE + 0x1A000) +#define DR_REG_I3C_SLV_BASE (DR_REG_HPPERIPH1_BASE + 0x1B000) +#define DR_REG_LCDCAM_BASE (DR_REG_HPPERIPH1_BASE + 0x1C000) +#define DR_REG_ADC_BASE (DR_REG_HPPERIPH1_BASE + 0x1E000) +#define DR_REG_UHCI_BASE (DR_REG_HPPERIPH1_BASE + 0x1F000) +#define DR_REG_GPIO_BASE (DR_REG_HPPERIPH1_BASE + 0x20000) +#define DR_REG_GPIO_EXT_BASE (DR_REG_HPPERIPH1_BASE + 0x20F00) +#define DR_REG_IO_MUX_BASE (DR_REG_HPPERIPH1_BASE + 0x21000) +#define DR_REG_SYSTIMER_BASE (DR_REG_HPPERIPH1_BASE + 0x22000) +#define DR_REG_MEM_MON_BASE (DR_REG_HPPERIPH1_BASE + 0x23000) +#define DR_REG_AUDIO_ADDC_BASE (DR_REG_HPPERIPH1_BASE + 0x24000) +#define DR_REG_HP_SYS_BASE (DR_REG_HPPERIPH1_BASE + 0x25000) +#define DR_REG_HP_SYS_CLKRST_BASE (DR_REG_HPPERIPH1_BASE + 0x26000) + +/* + * @module: LP AON + * + * @base: 0x50110000 + * + * @size: 64KB + */ +#define DR_REG_LP_SYS_BASE (DR_REG_LPAON_BASE + 0x0) +#define DR_REG_LP_CLKRST_BASE (DR_REG_LPAON_BASE + 0x1000) +#define DR_REG_LP_TIMER_BASE (DR_REG_LPAON_BASE + 0x2000) +#define DR_REG_LP_ANAPERI_BASE (DR_REG_LPAON_BASE + 0x3000) +#define DR_REG_LP_HUK_BASE (DR_REG_LPAON_BASE + 0x4000) +#define DR_REG_PMU_BASE (DR_REG_LPAON_BASE + 0x5000) +#define DR_REG_LP_WDT_BASE (DR_REG_LPAON_BASE + 0x6000) +#define DR_REG_LP_MB_BASE (DR_REG_LPAON_BASE + 0x8000) +#define DR_REG_RTC_BASE (DR_REG_LPAON_BASE + 0x9000) + +/* + * @module: LP PERI + * + * @base: 0x50120000 + * + * @size: 64KB + */ +#define DR_REG_LP_PERI_CLKRST_BASE (DR_REG_LPPERIPH_BASE + 0x0) +#define DR_REG_LP_PERI_BASE (DR_REG_LPPERIPH_BASE + 0x0) +#define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000) +#define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000) +#define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000) +#define DR_REG_LP_I2C_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) +#define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000) +#define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) +#define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000) +#define DR_REG_LP_GPIO_BASE (DR_REG_LPPERIPH_BASE + 0xA000) +#define DR_REG_LP_IOMUX_BASE (DR_REG_LPPERIPH_BASE + 0xB000) +#define DR_REG_LP_INTR_BASE (DR_REG_LPPERIPH_BASE + 0xC000) +#define DR_REG_EFUSE_BASE (DR_REG_LPPERIPH_BASE + 0xD000) +#define DR_REG_LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE000) +#define DR_REG_HP2LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE800) +#define DR_REG_LP_TSENSOR_BASE (DR_REG_LPPERIPH_BASE + 0xF000) + +/** + * This are module helper MACROs for quick module reference + * including some module(renamed) address + */ +#define DR_REG_UART_BASE DR_REG_UART0_BASE +#define DR_REG_UHCI0_BASE DR_REG_UHCI_BASE +#define DR_REG_TIMERGROUP0_BASE DR_REG_TIMG0_BASE +#define DR_REG_TIMERGROUP1_BASE DR_REG_TIMG1_BASE +#define DR_REG_I2S_BASE DR_REG_I2S0_BASE +#define DR_REG_USB_SERIAL_JTAG_BASE DR_REG_USB2JTAG_BASE +#define DR_REG_INTERRUPT_MATRIX_BASE DR_REG_INTR_BASE +#define DR_REG_SOC_ETM_BASE DR_REG_ETM_BASE +#define DR_REG_MCPWM_BASE DR_REG_MCPWM0_BASE +#define DR_REG_PARL_IO_BASE DR_REG_PARIO_BASE +#define DR_REG_PVT_MONITOR_BASE DR_REG_PVT_BASE +#define DR_REG_AES_BASE (DR_REG_CRYPTO_BASE + 0x0) +#define DR_REG_SHA_BASE (DR_REG_CRYPTO_BASE + 0x1000) +#define DR_REG_RSA_BASE (DR_REG_CRYPTO_BASE + 0x2000) +#define DR_REG_ECC_MULT_BASE (DR_REG_CRYPTO_BASE + 0x3000) +#define DR_REG_DS_BASE (DR_REG_CRYPTO_BASE + 0x4000) +#define DR_REG_DIGITAL_SIGNATURE_BASE DR_REG_DS_BASE +#define DR_REG_HMAC_BASE (DR_REG_CRYPTO_BASE + 0x5000) +#define DR_REG_ECDSA_BASE (DR_REG_CRYPTO_BASE + 0x6000) +#define DR_REG_MEM_MONITOR_BASE DR_REG_L2MEM_MON_BASE +#define DR_REG_HP_CLKRST_BASE DR_REG_HP_SYS_CLKRST_BASE +#define DR_REG_DSPI_MEM_BASE DR_REG_PSRAM_MSPI0_BASE +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTR_BASE +#define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR_BASE + 0x800) +#define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE +#define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE + +//TODO: IDF-7542 +// #define DR_REG_TEE_BASE 0x60098000 +// #define DR_REG_HP_APM_BASE 0x60099000 +// #define DR_REG_LP_APM0_BASE 0x60099800 +// #define DR_REG_LP_TEE_BASE 0x600B3400 +// #define DR_REG_LP_APM_BASE 0x600B3800 + +//TODO: IDF-7531 +// #define DR_REG_PAU_BASE 0x60093000 +// #define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 +// #define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 +// #define DR_REG_LP_AON_BASE 0x600B1000 + +//TODO: IDF-7688 +// #define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x3FF06000 diff --git a/components/soc/esp32p4/include/soc/regi2c_bbpll.h b/components/soc/esp32p4/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..235bca28dd --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_bbpll.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ diff --git a/components/soc/esp32p4/include/soc/regi2c_bias.h b/components/soc/esp32p4/include/soc/regi2c_bias.h new file mode 100644 index 0000000000..c3abe087e8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_bias.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32c6.c. + */ diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h new file mode 100644 index 0000000000..24377f9356 --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_brownout.h + * @brief Register definitions for brownout detector + * + * This file lists register fields of the brownout detector, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h. + */ diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..38db4f1595 --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x600AF818 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + + +#define ANA_CONFIG_REG 0x600AF81C +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x600AF820 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32p4/include/soc/regi2c_dig_reg.h b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h new file mode 100644 index 0000000000..8b277dfcd6 --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_dig_reg.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_dig_reg.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_RTC_DREG 4 +#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_RTC_DREG 5 +#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_DIG_DREG 6 +#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_DIG_DREG 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_OR_EN_CONT_CAL 9 +#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 +#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h new file mode 100644 index 0000000000..2388cd02fd --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ diff --git a/components/soc/esp32p4/include/soc/regi2c_saradc.h b/components/soc/esp32p4/include/soc/regi2c_saradc.h new file mode 100644 index 0000000000..7511dfa4e2 --- /dev/null +++ b/components/soc/esp32p4/include/soc/regi2c_saradc.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h new file mode 100644 index 0000000000..b7e3b101a2 --- /dev/null +++ b/components/soc/esp32p4/include/soc/reset_reasons.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// TODO: IDF-7791 +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/rtc.h b/components/soc/esp32p4/include/soc/rtc.h new file mode 100644 index 0000000000..a27bacea55 --- /dev/null +++ b/components/soc/esp32p4/include/soc/rtc.h @@ -0,0 +1,529 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) +#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +// TODO: IDF-7528, TODO: IDF-7529 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + */ +#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 +#define SOC_DELAY_RC32K_ENABLE 300 + +/* Core voltage: // TODO: IDF-7528, TODO: IDF-7529 + * Currently, ESP32C6 never adjust its wake voltage in runtime + * Only sets dig/rtc voltage dbias at startup time + */ +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 128 +#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) +#define RTC_CNTL_MIN_SLP_VAL_MIN (2) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + * + * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL + * However, this is not true on ESP32C6. The conversion to register field values is explicitly done in + * rtc_clk_cal_internal + */ +typedef enum { + RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK + RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator + RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock + RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock + RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock + RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) + uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = CONFIG_XTAL_FREQ, \ + .cpu_freq_mhz = 80, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ + .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 32 kHz internal rc oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_rc32k_enable(bool enable); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * @param clk_8m_en true to enable 8MHz generator + */ +void rtc_clk_8m_enable(bool clk_8m_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + * + * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be + * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Get the current APB frequency. + * @return The calculated APB frequency value, in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +/** + * @brief Clock calibration function used by rtc_clk_cal + * + * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * RTC_SLOW_CLK cycles. + * + * Slow clock calibration feature has two modes of operation: one-off and cycling. + * In cycling mode (which is enabled by default on SoC reset), counting of XTAL + * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled + * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed + * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is + * enabled using TIMG_RTC_CALI_START bit. + * + * @param cal_clk which clock to calibrate + * @param slowclk_cycles number of slow clock cycles to count + * @return number of XTAL clock cycles within the given number of slow clock cycles + */ +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. +/** + * @brief CPU clock source + */ +typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; +#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL +#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M) +#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; +#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator +#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; +#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 +#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator + +/* Alias of frequency related macros */ +#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX + +/* Alias of deprecated function names */ +#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) +#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() +#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) +#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/rtc_timer_reg.h b/components/soc/esp32p4/include/soc/rtc_timer_reg.h deleted file mode 100644 index 16fe3acfba..0000000000 --- a/components/soc/esp32p4/include/soc/rtc_timer_reg.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** RTC_TIMER_TAR0_LOW_REG register - * need_des - */ -#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0 - -/** RTC_TIMER_TAR0_HIGH_REG register - * need_des - */ -#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31 - -/** RTC_TIMER_TAR1_LOW_REG register - * need_des - */ -#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0 - -/** RTC_TIMER_TAR1_HIGH_REG register - * need_des - */ -#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31 - -/** RTC_TIMER_UPDATE_REG register - * need_des - */ -#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10) -/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28)) -#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S) -#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28 -/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29 -/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30 -/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31 - -/** RTC_TIMER_MAIN_BUF0_LOW_REG register - * need_des - */ -#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14) -/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0 - -/** RTC_TIMER_MAIN_BUF0_HIGH_REG register - * need_des - */ -#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18) -/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 - -/** RTC_TIMER_MAIN_BUF1_LOW_REG register - * need_des - */ -#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c) -/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0 - -/** RTC_TIMER_MAIN_BUF1_HIGH_REG register - * need_des - */ -#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20) -/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 - -/** RTC_TIMER_MAIN_OVERFLOW_REG register - * need_des - */ -#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24) -/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 - -/** RTC_TIMER_INT_RAW_REG register - * need_des - */ -#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28) -/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_OVERFLOW_RAW (BIT(30)) -#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S) -#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U -#define RTC_TIMER_OVERFLOW_RAW_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31 - -/** RTC_TIMER_INT_ST_REG register - * need_des - */ -#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c) -/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_OVERFLOW_ST (BIT(30)) -#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S) -#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ST_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31 - -/** RTC_TIMER_INT_ENA_REG register - * need_des - */ -#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30) -/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_OVERFLOW_ENA (BIT(30)) -#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S) -#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ENA_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31 - -/** RTC_TIMER_INT_CLR_REG register - * need_des - */ -#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34) -/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_OVERFLOW_CLR (BIT(30)) -#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S) -#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U -#define RTC_TIMER_OVERFLOW_CLR_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31 - -/** RTC_TIMER_LP_INT_RAW_REG register - * need_des - */ -#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 - -/** RTC_TIMER_LP_INT_ST_REG register - * need_des - */ -#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31 - -/** RTC_TIMER_LP_INT_ENA_REG register - * need_des - */ -#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 - -/** RTC_TIMER_LP_INT_CLR_REG register - * need_des - */ -#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 - -/** RTC_TIMER_DATE_REG register - * need_des - */ -#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc) -/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; - * need_des - */ -#define RTC_TIMER_DATE 0x7FFFFFFFU -#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S) -#define RTC_TIMER_DATE_V 0x7FFFFFFFU -#define RTC_TIMER_DATE_S 0 -/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_TIMER_CLK_EN (BIT(31)) -#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S) -#define RTC_TIMER_CLK_EN_V 0x00000001U -#define RTC_TIMER_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/rtc_wdt_reg.h b/components/soc/esp32p4/include/soc/rtc_wdt_reg.h deleted file mode 100644 index 8d502d3f56..0000000000 --- a/components/soc/esp32p4/include/soc/rtc_wdt_reg.h +++ /dev/null @@ -1,324 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** RTC_WDT_CONFIG0_REG register - * need_des - */ -#define RTC_WDT_CONFIG0_REG (DR_REG_RTC_WDT_BASE + 0x0) -/** RTC_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define RTC_WDT_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_WDT_WDT_PAUSE_IN_SLP_M (RTC_WDT_WDT_PAUSE_IN_SLP_V << RTC_WDT_WDT_PAUSE_IN_SLP_S) -#define RTC_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U -#define RTC_WDT_WDT_PAUSE_IN_SLP_S 9 -/** RTC_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_WDT_WDT_APPCPU_RESET_EN_M (RTC_WDT_WDT_APPCPU_RESET_EN_V << RTC_WDT_WDT_APPCPU_RESET_EN_S) -#define RTC_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U -#define RTC_WDT_WDT_APPCPU_RESET_EN_S 10 -/** RTC_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_WDT_WDT_PROCPU_RESET_EN_M (RTC_WDT_WDT_PROCPU_RESET_EN_V << RTC_WDT_WDT_PROCPU_RESET_EN_S) -#define RTC_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U -#define RTC_WDT_WDT_PROCPU_RESET_EN_S 11 -/** RTC_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; - * need_des - */ -#define RTC_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_M (RTC_WDT_WDT_FLASHBOOT_MOD_EN_V << RTC_WDT_WDT_FLASHBOOT_MOD_EN_S) -#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U -#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_S 12 -/** RTC_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; - * need_des - */ -#define RTC_WDT_WDT_SYS_RESET_LENGTH 0x00000007U -#define RTC_WDT_WDT_SYS_RESET_LENGTH_M (RTC_WDT_WDT_SYS_RESET_LENGTH_V << RTC_WDT_WDT_SYS_RESET_LENGTH_S) -#define RTC_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U -#define RTC_WDT_WDT_SYS_RESET_LENGTH_S 13 -/** RTC_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; - * need_des - */ -#define RTC_WDT_WDT_CPU_RESET_LENGTH 0x00000007U -#define RTC_WDT_WDT_CPU_RESET_LENGTH_M (RTC_WDT_WDT_CPU_RESET_LENGTH_V << RTC_WDT_WDT_CPU_RESET_LENGTH_S) -#define RTC_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U -#define RTC_WDT_WDT_CPU_RESET_LENGTH_S 16 -/** RTC_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_STG3 0x00000007U -#define RTC_WDT_WDT_STG3_M (RTC_WDT_WDT_STG3_V << RTC_WDT_WDT_STG3_S) -#define RTC_WDT_WDT_STG3_V 0x00000007U -#define RTC_WDT_WDT_STG3_S 19 -/** RTC_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_STG2 0x00000007U -#define RTC_WDT_WDT_STG2_M (RTC_WDT_WDT_STG2_V << RTC_WDT_WDT_STG2_S) -#define RTC_WDT_WDT_STG2_V 0x00000007U -#define RTC_WDT_WDT_STG2_S 22 -/** RTC_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_STG1 0x00000007U -#define RTC_WDT_WDT_STG1_M (RTC_WDT_WDT_STG1_V << RTC_WDT_WDT_STG1_S) -#define RTC_WDT_WDT_STG1_V 0x00000007U -#define RTC_WDT_WDT_STG1_S 25 -/** RTC_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_STG0 0x00000007U -#define RTC_WDT_WDT_STG0_M (RTC_WDT_WDT_STG0_V << RTC_WDT_WDT_STG0_S) -#define RTC_WDT_WDT_STG0_V 0x00000007U -#define RTC_WDT_WDT_STG0_S 28 -/** RTC_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_EN (BIT(31)) -#define RTC_WDT_WDT_EN_M (RTC_WDT_WDT_EN_V << RTC_WDT_WDT_EN_S) -#define RTC_WDT_WDT_EN_V 0x00000001U -#define RTC_WDT_WDT_EN_S 31 - -/** RTC_WDT_CONFIG1_REG register - * need_des - */ -#define RTC_WDT_CONFIG1_REG (DR_REG_RTC_WDT_BASE + 0x4) -/** RTC_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; - * need_des - */ -#define RTC_WDT_WDT_STG0_HOLD 0xFFFFFFFFU -#define RTC_WDT_WDT_STG0_HOLD_M (RTC_WDT_WDT_STG0_HOLD_V << RTC_WDT_WDT_STG0_HOLD_S) -#define RTC_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU -#define RTC_WDT_WDT_STG0_HOLD_S 0 - -/** RTC_WDT_CONFIG2_REG register - * need_des - */ -#define RTC_WDT_CONFIG2_REG (DR_REG_RTC_WDT_BASE + 0x8) -/** RTC_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; - * need_des - */ -#define RTC_WDT_WDT_STG1_HOLD 0xFFFFFFFFU -#define RTC_WDT_WDT_STG1_HOLD_M (RTC_WDT_WDT_STG1_HOLD_V << RTC_WDT_WDT_STG1_HOLD_S) -#define RTC_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU -#define RTC_WDT_WDT_STG1_HOLD_S 0 - -/** RTC_WDT_CONFIG3_REG register - * need_des - */ -#define RTC_WDT_CONFIG3_REG (DR_REG_RTC_WDT_BASE + 0xc) -/** RTC_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; - * need_des - */ -#define RTC_WDT_WDT_STG2_HOLD 0xFFFFFFFFU -#define RTC_WDT_WDT_STG2_HOLD_M (RTC_WDT_WDT_STG2_HOLD_V << RTC_WDT_WDT_STG2_HOLD_S) -#define RTC_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU -#define RTC_WDT_WDT_STG2_HOLD_S 0 - -/** RTC_WDT_CONFIG4_REG register - * need_des - */ -#define RTC_WDT_CONFIG4_REG (DR_REG_RTC_WDT_BASE + 0x10) -/** RTC_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; - * need_des - */ -#define RTC_WDT_WDT_STG3_HOLD 0xFFFFFFFFU -#define RTC_WDT_WDT_STG3_HOLD_M (RTC_WDT_WDT_STG3_HOLD_V << RTC_WDT_WDT_STG3_HOLD_S) -#define RTC_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU -#define RTC_WDT_WDT_STG3_HOLD_S 0 - -/** RTC_WDT_FEED_REG register - * need_des - */ -#define RTC_WDT_FEED_REG (DR_REG_RTC_WDT_BASE + 0x14) -/** RTC_WDT_FEED : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_FEED (BIT(31)) -#define RTC_WDT_FEED_M (RTC_WDT_FEED_V << RTC_WDT_FEED_S) -#define RTC_WDT_FEED_V 0x00000001U -#define RTC_WDT_FEED_S 31 - -/** RTC_WDT_WPROTECT_REG register - * need_des - */ -#define RTC_WDT_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x18) -/** RTC_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_WDT_WDT_WKEY 0xFFFFFFFFU -#define RTC_WDT_WDT_WKEY_M (RTC_WDT_WDT_WKEY_V << RTC_WDT_WDT_WKEY_S) -#define RTC_WDT_WDT_WKEY_V 0xFFFFFFFFU -#define RTC_WDT_WDT_WKEY_S 0 - -/** RTC_WDT_SWD_CONFIG_REG register - * need_des - */ -#define RTC_WDT_SWD_CONFIG_REG (DR_REG_RTC_WDT_BASE + 0x1c) -/** RTC_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_RESET_FLAG (BIT(0)) -#define RTC_WDT_SWD_RESET_FLAG_M (RTC_WDT_SWD_RESET_FLAG_V << RTC_WDT_SWD_RESET_FLAG_S) -#define RTC_WDT_SWD_RESET_FLAG_V 0x00000001U -#define RTC_WDT_SWD_RESET_FLAG_S 0 -/** RTC_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_AUTO_FEED_EN (BIT(18)) -#define RTC_WDT_SWD_AUTO_FEED_EN_M (RTC_WDT_SWD_AUTO_FEED_EN_V << RTC_WDT_SWD_AUTO_FEED_EN_S) -#define RTC_WDT_SWD_AUTO_FEED_EN_V 0x00000001U -#define RTC_WDT_SWD_AUTO_FEED_EN_S 18 -/** RTC_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_RST_FLAG_CLR (BIT(19)) -#define RTC_WDT_SWD_RST_FLAG_CLR_M (RTC_WDT_SWD_RST_FLAG_CLR_V << RTC_WDT_SWD_RST_FLAG_CLR_S) -#define RTC_WDT_SWD_RST_FLAG_CLR_V 0x00000001U -#define RTC_WDT_SWD_RST_FLAG_CLR_S 19 -/** RTC_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; - * need_des - */ -#define RTC_WDT_SWD_SIGNAL_WIDTH 0x000003FFU -#define RTC_WDT_SWD_SIGNAL_WIDTH_M (RTC_WDT_SWD_SIGNAL_WIDTH_V << RTC_WDT_SWD_SIGNAL_WIDTH_S) -#define RTC_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU -#define RTC_WDT_SWD_SIGNAL_WIDTH_S 20 -/** RTC_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_DISABLE (BIT(30)) -#define RTC_WDT_SWD_DISABLE_M (RTC_WDT_SWD_DISABLE_V << RTC_WDT_SWD_DISABLE_S) -#define RTC_WDT_SWD_DISABLE_V 0x00000001U -#define RTC_WDT_SWD_DISABLE_S 30 -/** RTC_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_FEED (BIT(31)) -#define RTC_WDT_SWD_FEED_M (RTC_WDT_SWD_FEED_V << RTC_WDT_SWD_FEED_S) -#define RTC_WDT_SWD_FEED_V 0x00000001U -#define RTC_WDT_SWD_FEED_S 31 - -/** RTC_WDT_SWD_WPROTECT_REG register - * need_des - */ -#define RTC_WDT_SWD_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x20) -/** RTC_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define RTC_WDT_SWD_WKEY 0xFFFFFFFFU -#define RTC_WDT_SWD_WKEY_M (RTC_WDT_SWD_WKEY_V << RTC_WDT_SWD_WKEY_S) -#define RTC_WDT_SWD_WKEY_V 0xFFFFFFFFU -#define RTC_WDT_SWD_WKEY_S 0 - -/** RTC_WDT_INT_RAW_REG register - * need_des - */ -#define RTC_WDT_INT_RAW_REG (DR_REG_RTC_WDT_BASE + 0x24) -/** RTC_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_WDT_SUPER_WDT_INT_RAW (BIT(30)) -#define RTC_WDT_SUPER_WDT_INT_RAW_M (RTC_WDT_SUPER_WDT_INT_RAW_V << RTC_WDT_SUPER_WDT_INT_RAW_S) -#define RTC_WDT_SUPER_WDT_INT_RAW_V 0x00000001U -#define RTC_WDT_SUPER_WDT_INT_RAW_S 30 -/** RTC_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_LP_WDT_INT_RAW (BIT(31)) -#define RTC_WDT_LP_WDT_INT_RAW_M (RTC_WDT_LP_WDT_INT_RAW_V << RTC_WDT_LP_WDT_INT_RAW_S) -#define RTC_WDT_LP_WDT_INT_RAW_V 0x00000001U -#define RTC_WDT_LP_WDT_INT_RAW_S 31 - -/** RTC_WDT_INT_ST_REG register - * need_des - */ -#define RTC_WDT_INT_ST_REG (DR_REG_RTC_WDT_BASE + 0x28) -/** RTC_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_WDT_SUPER_WDT_INT_ST (BIT(30)) -#define RTC_WDT_SUPER_WDT_INT_ST_M (RTC_WDT_SUPER_WDT_INT_ST_V << RTC_WDT_SUPER_WDT_INT_ST_S) -#define RTC_WDT_SUPER_WDT_INT_ST_V 0x00000001U -#define RTC_WDT_SUPER_WDT_INT_ST_S 30 -/** RTC_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_LP_WDT_INT_ST (BIT(31)) -#define RTC_WDT_LP_WDT_INT_ST_M (RTC_WDT_LP_WDT_INT_ST_V << RTC_WDT_LP_WDT_INT_ST_S) -#define RTC_WDT_LP_WDT_INT_ST_V 0x00000001U -#define RTC_WDT_LP_WDT_INT_ST_S 31 - -/** RTC_WDT_INT_ENA_REG register - * need_des - */ -#define RTC_WDT_INT_ENA_REG (DR_REG_RTC_WDT_BASE + 0x2c) -/** RTC_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_WDT_SUPER_WDT_INT_ENA (BIT(30)) -#define RTC_WDT_SUPER_WDT_INT_ENA_M (RTC_WDT_SUPER_WDT_INT_ENA_V << RTC_WDT_SUPER_WDT_INT_ENA_S) -#define RTC_WDT_SUPER_WDT_INT_ENA_V 0x00000001U -#define RTC_WDT_SUPER_WDT_INT_ENA_S 30 -/** RTC_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_LP_WDT_INT_ENA (BIT(31)) -#define RTC_WDT_LP_WDT_INT_ENA_M (RTC_WDT_LP_WDT_INT_ENA_V << RTC_WDT_LP_WDT_INT_ENA_S) -#define RTC_WDT_LP_WDT_INT_ENA_V 0x00000001U -#define RTC_WDT_LP_WDT_INT_ENA_S 31 - -/** RTC_WDT_INT_CLR_REG register - * need_des - */ -#define RTC_WDT_INT_CLR_REG (DR_REG_RTC_WDT_BASE + 0x30) -/** RTC_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define RTC_WDT_SUPER_WDT_INT_CLR (BIT(30)) -#define RTC_WDT_SUPER_WDT_INT_CLR_M (RTC_WDT_SUPER_WDT_INT_CLR_V << RTC_WDT_SUPER_WDT_INT_CLR_S) -#define RTC_WDT_SUPER_WDT_INT_CLR_V 0x00000001U -#define RTC_WDT_SUPER_WDT_INT_CLR_S 30 -/** RTC_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_LP_WDT_INT_CLR (BIT(31)) -#define RTC_WDT_LP_WDT_INT_CLR_M (RTC_WDT_LP_WDT_INT_CLR_V << RTC_WDT_LP_WDT_INT_CLR_S) -#define RTC_WDT_LP_WDT_INT_CLR_V 0x00000001U -#define RTC_WDT_LP_WDT_INT_CLR_S 31 - -/** RTC_WDT_DATE_REG register - * need_des - */ -#define RTC_WDT_DATE_REG (DR_REG_RTC_WDT_BASE + 0x3fc) -/** RTC_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; - * need_des - */ -#define RTC_WDT_LP_WDT_DATE 0x7FFFFFFFU -#define RTC_WDT_LP_WDT_DATE_M (RTC_WDT_LP_WDT_DATE_V << RTC_WDT_LP_WDT_DATE_S) -#define RTC_WDT_LP_WDT_DATE_V 0x7FFFFFFFU -#define RTC_WDT_LP_WDT_DATE_S 0 -/** RTC_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define RTC_WDT_CLK_EN (BIT(31)) -#define RTC_WDT_CLK_EN_M (RTC_WDT_CLK_EN_V << RTC_WDT_CLK_EN_S) -#define RTC_WDT_CLK_EN_V 0x00000001U -#define RTC_WDT_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/sdmmc_pins.h b/components/soc/esp32p4/include/soc/sdmmc_pins.h new file mode 100644 index 0000000000..2a5810ff32 --- /dev/null +++ b/components/soc/esp32p4/include/soc/sdmmc_pins.h @@ -0,0 +1,7 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h new file mode 100644 index 0000000000..ba04102638 --- /dev/null +++ b/components/soc/esp32p4/include/soc/soc.h @@ -0,0 +1,261 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6 +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 +#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) // only one I2S on C6 +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i) * 0x1000) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) +#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000) +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//TODO: IDF-7526 +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ ( 40*1000000 ) +#define MODEM_APB_CLK_FREQ ( 80*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +#define XTAL_CLK_FREQ (40*1000000) +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x40000000 +#define SOC_IROM_HIGH 0x44000000 +#define SOC_DROM_LOW 0x40000000 +#define SOC_DROM_HIGH 0x44000000 + +#define SOC_SINGLE_BANK_LOW 0x40000000 +#define SOC_SINGLE_BANK_HIGH 0x44000000 +#define SOC_DUAL_BANK_LOW 0x48000000 +#define SOC_DUAL_BANK_HIGH 0x4c000000 +#define SOC_EXT_DBRAM_DATA_LOW 0x4a000000 +#define SOC_EXT_DBRAM_DATA_HIGH 0x4c000000 + +#define SOC_IROM_MASK_LOW 0x4fc00000 +#define SOC_IROM_MASK_HIGH 0x4fc20000 +#define SOC_DROM_MASK_LOW 0x4fc00000 +#define SOC_DROM_MASK_HIGH 0x4fc20000 +#define SOC_TCM_LOW 0x30100000 +#define SOC_TCM_HIGH 0x30102000 +#define SOC_IRAM_LOW 0x4ff00000 +#define SOC_IRAM_HIGH 0x4ffc0000 +#define SOC_DRAM_LOW 0x4ff00000 +#define SOC_DRAM_HIGH 0x4ffc0000 +#define SOC_RTC_IRAM_LOW 0x50108000 // ESP32-P4 only has 32k LP memory +#define SOC_RTC_IRAM_HIGH 0x50110000 +#define SOC_RTC_DRAM_LOW 0x50108000 +#define SOC_RTC_DRAM_HIGH 0x50110000 +#define SOC_RTC_DATA_LOW 0x50108000 +#define SOC_RTC_DATA_HIGH 0x50110000 + +#define SOC_LP_ROM_LOW 0x50100000 +#define SOC_LP_ROM_HIGH 0x50104000 + +#define SOC_LP_RAM_LOW 0x50108000 +#define SOC_LP_RAM_HIGH 0x50110000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x4ff00000 +#define SOC_DIRAM_IRAM_HIGH 0x4ffc0000 +#define SOC_DIRAM_DRAM_LOW 0x4ff00000 +#define SOC_DIRAM_DRAM_HIGH 0x4ffc0000 +#define SOC_DIRAM_ROM_RESERVE_HIGH 0x4ff40000 + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x4ff00000 +#define SOC_DMA_HIGH 0x4ffc0000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x4ff00000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x4ffc0000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x4ff00000 +#define SOC_MEM_INTERNAL_HIGH 0x4ffc0000 +#define SOC_MEM_INTERNAL_LOW1 0x4ff00000 +#define SOC_MEM_INTERNAL_HIGH1 0x4ffc0000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_DUAL_BANK_HIGH - SOC_DUAL_BANK_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +#define CPU_PERIPH_LOW 0x3ff00000 +#define CPU_PERIPH_HIGH 0x3ff20000 + +// Region of address space that holds peripherals, HP APB peripherals +#define SOC_PERIPHERAL_LOW 0x50000000 +#define SOC_PERIPHERAL_HIGH 0x50100000 + +#define SOC_LP_PERIPH_LOW 0x50110000 +#define SOC_LP_PERIPH_HIGH 0x50130000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4ff5abd0 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt number reserved in riscv/vector.S, not touch this. +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h new file mode 100644 index 0000000000..21a3346f60 --- /dev/null +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -0,0 +1,479 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32p4/include/soc/'` + * + * For more information see `tools/gen_soc_caps_kconfig/README.md` + * +*/ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496 +// #define SOC_ANA_CMPR_SUPPORTED 1 //TODO: IDF-7479 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552 +#define SOC_UART_SUPPORTED 1 +// #define SOC_GDMA_SUPPORTED 1 //TODO: IDF-6504 +// #define SOC_GPTIMER_SUPPORTED 1 //TODO: IDF-6515 +// #define SOC_PCNT_SUPPORTED 1 //TODO: IDF-7475 +// #define SOC_MCPWM_SUPPORTED 1 //TODO: IDF-7493 +// #define SOC_TWAI_SUPPORTED 1 //TODO: IDF-7470 +// #define SOC_ETM_SUPPORTED 1 //TODO: IDF-7478 +// #define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471, TODO: IDF-7472 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// disable usb serial jtag for esp32p4, current image does not support +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: IDF-7496 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: IDF-7482 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_RISCV_COPROC_SUPPORTED 1 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 //TODO: IDF-6508 +// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476 +// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551 +// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503 +// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510 +// #define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491 +#define SOC_SYSTIMER_SUPPORTED 1 +// #define SOC_AES_SUPPORTED 1 //TODO: IDF-6519 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 //TODO: IDF-7541 +// #define SOC_HMAC_SUPPORTED 1 //TODO: IDF-7543 +// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: IDF-6518 +// #define SOC_ECC_SUPPORTED 1 //TODO: IDF-7549 +#define SOC_FLASH_ENC_SUPPORTED 1 +// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: IDF-7544 +// #define SOC_BOD_SUPPORTED 1 //TODO: IDF-7519 +// #define SOC_APM_SUPPORTED 1 //TODO: IDF-7542 +// #define SOC_PMU_SUPPORTED 1 //TODO: IDF-7531 +// #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531 +// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: IDF-7532 +// #define SOC_SPIRAM_SUPPORTED 1 //TODO: IDF-7495 +// #define SOC_ULP_SUPPORTED 1 //TODO: IDF-7534 +// #define SOC_SDMMC_HOST_SUPPORTED 1 //TODO: IDF-6502 +// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: IDF-7526 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_40M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 //TODO: IDF-6496, TODO: IDF-6497 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +#define SOC_ADC_MAX_CHANNEL_NUM (7) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +#define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/ + +// ESP32P4-TODO: Copy from esp32c6, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 +#define SOC_CACHE_L2_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (2U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller +#define SOC_INT_CLIC_SUPPORTED 1 +#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +// TODO: IDF-5360 (Copy from esp32c3, need check) +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups +#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group +#define SOC_GDMA_SUPPORT_ETM (0) // Support ETM submodule + +/*-------------------------- ETM CAPS --------------------------------------*/ +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-P4 has 1 GPIO peripheral +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 64 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 +#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +#define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32P4 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFFFFF) +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK +#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) + +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +// #define SOC_RTCIO_PIN_COUNT 8 //TODO: IDF-7480 +// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 //TODO: IDF-7480 +// #define SOC_RTCIO_HOLD_SUPPORTED 1 //TODO: IDF-7480 +// #define SOC_RTCIO_WAKE_SUPPORTED 1 //TODO: IDF-7480 + +/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ +#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ +#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ +#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ + +/*-------------------------- I2C CAPS ----------------------------------------*/ +// ESP32-P4 has 1 I2C +#define SOC_I2C_NUM (1U) + +#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +#define SOC_I2C_SUPPORT_SLAVE (1) + +// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined. +#define SOC_I2C_SUPPORT_HW_CLR_BUS (1) + +#define SOC_I2C_SUPPORT_XTAL (1) +#define SOC_I2C_SUPPORT_RTC (1) + +/*-------------------------- I2S CAPS ----------------------------------------*/ +#define SOC_I2S_NUM (1U) +#define SOC_I2S_HW_VERSION_2 (1) +#define SOC_I2S_SUPPORTS_XTAL (1) +#define SOC_I2S_SUPPORTS_PLL_F160M (1) +#define SOC_I2S_SUPPORTS_PCM (1) +#define SOC_I2S_SUPPORTS_PDM (1) +#define SOC_I2S_SUPPORTS_PDM_TX (1) +#define SOC_I2S_PDM_MAX_TX_LINES (2) +#define SOC_I2S_SUPPORTS_TDM (1) + +/*-------------------------- LEDC CAPS ---------------------------------------*/ +#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +#define SOC_LEDC_CHANNEL_NUM (6) +#define SOC_LEDC_TIMER_BIT_WIDTH (20) +#define SOC_LEDC_SUPPORT_FADE_STOP (1) +#define SOC_LEDC_GAMMA_FADE_RANGE_MAX (16) + +/*-------------------------- MMU CAPS ----------------------------------------*/ +#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (0) +#define SOC_MMU_PERIPH_NUM (2U) +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (2U) +#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */ + +/*-------------------------- MPU CAPS ----------------------------------------*/ +#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +#define SOC_MPU_MIN_REGION_SIZE 0x20000000U +#define SOC_MPU_REGIONS_MAX_NUM 8 +#define SOC_MPU_REGION_RO_SUPPORTED 0 +#define SOC_MPU_REGION_WO_SUPPORTED 0 + +/*-------------------------- PCNT CAPS ---------------------------------------*/ +#define SOC_PCNT_GROUPS 1U +#define SOC_PCNT_UNITS_PER_GROUP 4 +#define SOC_PCNT_CHANNELS_PER_UNIT 2 +#define SOC_PCNT_THRES_POINT_PER_UNIT 2 +#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 + +/*--------------------------- RMT CAPS ---------------------------------------*/ +#define SOC_RMT_GROUPS 1U /*!< One RMT group */ +#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */ +#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */ +#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */ +#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ +#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ +#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ +#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ +#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ +#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ +#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ +#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ +#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ + +/*-------------------------- MCPWM CAPS --------------------------------------*/ +#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has +#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has +#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output +#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) +#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers + +/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ +// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 + +/*-------------------------- PARLIO CAPS --------------------------------------*/ +#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ +#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ +#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ +#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ +#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ +#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +// TODO: IDF-5353 (Copy from esp32c3, need check) +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +#ifdef SDMMC_DEFAULT_IOMUX +#define SOC_SDMMC_USE_IOMUX 1 +#else +#define SOC_SDMMC_USE_GPIO_MATRIX 1 +#endif +#define SOC_SDMMC_NUM_SLOTS 2 +#define SOC_SDMMC_IOMUX_FUNC 0 +#define SOC_SDMMC_DMA_NEED_CACHE_WB 1 + +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ +#define SOC_SDM_GROUPS 1U +#define SOC_SDM_CHANNELS_PER_GROUP 4 +#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1 +#define SOC_SDM_CLK_SUPPORT_XTAL 1 + +// TODO: IDF-5334 (Copy from esp32c3, need check) +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 0 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 +#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 +#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +#define SOC_SPI_MEM_SUPPORT_WRAP (1) + +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event //TODO: IDF-7486 + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define SOC_TIMER_SUPPORT_ETM (0) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_CONTROLLER_NUM 2 +#define SOC_TWAI_CLK_SUPPORT_XTAL 1 +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 32768 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +#define SOC_EFUSE_DIS_PAD_JTAG 1 +#define SOC_EFUSE_DIS_USB_JTAG 1 +#define SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define SOC_EFUSE_SOFT_DIS_JTAG 1 + +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 1 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*-------------------------- MEMPROT CAPS ------------------------------------*/ + + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-P4 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_HP_NUM (2) +// #define SOC_UART_LP_NUM (1U) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +// TODO: IDF-5351 (Copy from esp32c3, need check) +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +#define SOC_PM_SUPPORT_BT_WAKEUP (1) +#define SOC_PM_SUPPORT_CPU_PD (1) +#define SOC_PM_SUPPORT_MODEM_PD (1) +#define SOC_PM_SUPPORT_XTAL32K_PD (1) +#define SOC_PM_SUPPORT_RC32K_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) +#define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_PM_SUPPORT_TOP_PD (1) + +#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*! +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T +he bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the bit is set. The +bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when the bit is set. The + bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b +e cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will be triggered when t +he bit is set. The bit will be cleared once the operation done.1: enable 0: disa +ble..*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera +tion will be triggered when the bit is set. The bit will be cleared once the op +eration done .1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit +is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit + is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T +he bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered when the bit is set +. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat +e or high performance mode and obtains the devices ID. The bit will be cleared o +nce the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operat +ion done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat +ion will be triggered when the bit is set. The bit will be cleared once the oper +ation done.1: enable 0: disable..*/ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode, it is set to indicate that program/erase operation will be trigger +ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o +peration done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 +/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta +te, 2: send command state, 3: send address state, 4: wait state, 5: read data st +ate, 6:write data state, 7: done state, 8: read data end state..*/ +#define SPI_MEM_SLV_ST 0x0000000F +#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) +#define SPI_MEM_SLV_ST_V 0xF +#define SPI_MEM_SLV_ST_S 4 +/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT +, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se +nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ +#define SPI_MEM_MST_ST 0x0000000F +#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) +#define SPI_MEM_MST_ST_V 0xF +#define SPI_MEM_MST_ST_S 0 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory +address, the bit24-bit31 are the byte length of a transfer..*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a +lways 1. 0: Others..*/ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +s 1. 0: Others..*/ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is set. 1: enable 0: d +isable..*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with +spi_mem_flash_res bit. 1: enable 0: disable..*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO +UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +e.*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +e low..*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable.*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] +is output by the MSPI controller in the second half part of dummy phase. It is u +sed to pre-drive flash..*/ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_V 0x1 +#define SPI_MEM_FDUMMY_WOUT_S 3 +/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i +s output by the MSPI controller in the first half part of dummy phase. It is use +d to mask invalid SPI_DQS in the half part of dummy phase..*/ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_V 0x1 +#define SPI_MEM_FDUMMY_RIN_S 2 +/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) +/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + send signals to AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (BIT(31)) +#define SPI_MEM_TXFIFO_RST_V 0x1 +#define SPI_MEM_TXFIFO_RST_S 31 +/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + receive signals from AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to write data faster, do not wait write data has been stored in tx_ +bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored +in tx_bus_fifo_l2..*/ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_V 0x1 +#define SPI_MEM_FAST_WRITE_EN_S 29 +/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at +the same time..*/ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_V 0x1 +#define SPI_MEM_DUAL_RAM_EN_S 28 +/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac +cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi +ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac +cessed at the same time..*/ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (BIT(27)) +#define SPI_MEM_RAM0_EN_V 0x1 +#define SPI_MEM_RAM0_EN_S 27 +/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Write Splice-transfer..*/ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_V 0x1 +#define SPI_MEM_AW_SPLICE_EN_S 26 +/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Read Splice-transfer..*/ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_V 0x1 +#define SPI_MEM_AR_SPLICE_EN_S 25 +/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + when there is a ECC error in AXI read data. The ECC error information is record +ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/* SPI_MEM_SPI_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R +eply AXI read data to AXI bus when all the read data is available..*/ +#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_M (BIT(23)) +#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_V 0x1 +#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_S 23 +/* SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) +#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S 22 +/* SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl +y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) +#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S 21 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 +12) SPI_CLK cycles..*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on..*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The spi0_mst_st and spi0_slv_st will be reset..*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core + clock cycles..*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans +fers when one transfer will cross flash or EXT_RAM page corner, valid no matter +whether there is an ECC region or not..*/ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses flash..*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */ +/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w +hen accesses flash..*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + mode when accessed flash..*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi +th SPI_MEM_CS_HOLD bit..*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME +M_CS_SETUP bit..*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + clock..*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation..*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation..*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation..*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation..*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation..*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable..*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. +1: enable 0: disable..*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 +: enable 0: disable..*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals..*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals..*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals.*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals.*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */ +/*description: SPI0 USR_CMD read or write data byte length -1.*/ +#define SPI_MEM_USR_DBYTELEN 0x00000007 +#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) +#define SPI_MEM_USR_DBYTELEN_V 0x7 +#define SPI_MEM_USR_DBYTELEN_S 6 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy +cle_num-1)..*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command..*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b +it..*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: SPI_CS line keep low when the bit is set..*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0, sram is connected to SUBPINs..*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 +/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0, flash is connected to SUBPINs..*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1, the value of crc32..*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) +/* SPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV +_ERR will be replied to BRESP/RRESP..*/ +#define SPI_MEM_SPI_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_M (BIT(31)) +#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_V 0x1 +#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_S 31 +/* SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: Set this bit to check AXI read/write the same address region..*/ +#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) +#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x1 +#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_qio..*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th +e same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_dio..*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the +same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_V 0x1 +#define SPI_MEM_AXI_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas +e. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 +/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T +he register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase +. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma +nd..*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + operations..*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ +e operations..*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 +/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 +/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en +able, 0:disable..*/ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +/* SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 +] are always 1. 0: Others..*/ +#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar +e always 1. 0: Others..*/ +#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDOUT_HEX (BIT(27)) +#define SPI_MEM_SDOUT_HEX_M (BIT(27)) +#define SPI_MEM_SDOUT_HEX_V 0x1 +#define SPI_MEM_SDOUT_HEX_S 27 +/* SPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_HEX (BIT(26)) +#define SPI_MEM_SDIN_HEX_M (BIT(26)) +#define SPI_MEM_SDIN_HEX_V 0x1 +#define SPI_MEM_SDIN_HEX_S 26 +/* SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) +#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/* SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, +the signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_V 0x1 +#define SPI_MEM_SDUMMY_WOUT_S 23 +/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t +he signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_V 0x1 +#define SPI_MEM_SDUMMY_RIN_S 22 +/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 +/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 +/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 +/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 +/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 +/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 +/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 +/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 +/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */ +/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd +_mode bit..*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 +/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is always on..*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for + sram. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the read command value of command phase + for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. + The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the write command value of command phas +e for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) +/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +lk is divided from system clock..*/ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c +lk frequency is system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 +/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 +/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ +/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001F +#define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x1F +#define SPI_MEM_LOCK_DELAY_TIME_S 7 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: The command value to wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_CMD 0x0000FFFF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFFFF +#define SPI_MEM_WAITI_CMD_S 16 +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is + 8..*/ +#define SPI_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_V 0x1 +#define SPI_MEM_WAITI_CMD_2B_S 9 +/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI +_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when +SPI_MEM_WAITI_ADDR_EN is cleared..*/ +#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) +#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 +/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad +dress in RDSR or read SUS command transfer..*/ +#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_V 0x1 +#define SPI_MEM_WAITI_ADDR_EN_S 2 +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The dummy phase enable when wait flash idle (RDSR).*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto +Suspend/Resume are not supported..*/ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) +/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ +/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, + it will be treated as check pass..*/ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F +#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 +/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu +s of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (BIT(24)) +#define SPI_MEM_PES_END_EN_V 0x1 +#define SPI_MEM_PES_END_EN_S 24 +/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status + of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (BIT(23)) +#define SPI_MEM_PER_END_EN_V 0x1 +#define SPI_MEM_PER_END_EN_S 23 +/* SPI_MEM_SPI_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w +hen check flash SUS/SUS1/SUS2 status bit.*/ +#define SPI_MEM_SPI_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_SPI_FMEM_RD_SUS_2B_M (BIT(22)) +#define SPI_MEM_SPI_FMEM_RD_SUS_2B_V 0x1 +#define SPI_MEM_SPI_FMEM_RD_SUS_2B_S 22 +/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ +/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is +status_in[15:0](only status_in[7:0] is valid when only one byte of data is read +out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS +2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ +#define SPI_MEM_PESR_END_MSK 0x0000FFFF +#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) +#define SPI_MEM_PESR_END_MSK_V 0xFFFF +#define SPI_MEM_PESR_END_MSK_S 6 +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable Auto-suspending function..*/ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a +pplication should send PER after PES is done..*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase suspend command is sent. 0: SPI1 does not wait after program erase + suspend command is sent..*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase resume command is sent. 0: SPI1 does not wait after program erase +resume command is sent..*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit, program erase suspend operation will be triggered whe +n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +isable..*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit, program erase suspend operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: di +sable..*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) +/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS +/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash +..*/ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF +#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ +/*description: Program/Erase suspend command..*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PES_COMMAND_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ +/*description: Program/Erase resume command..*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PER_COMMAND_S 16 +/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng +th of Program/Erase Suspend/Resume command is 8..*/ +#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 +#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 +/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_V 0x1 +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com +mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles +after DP command is sent..*/ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after RES command is sent..*/ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after HPM command is sent..*/ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend, only used in SPI1..*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_V 0x1 +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_V 0x1 +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that +chip is loosing power and RTC module sends out brown out close flash request to +SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + and MSPI returns to idle state. 0: Others..*/ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr +ite flash request is received. 0: Others..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read +address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access +is rejected. 0: Others..*/ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s +et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error + times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM +. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t +his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq +ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP +I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times +of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E +RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare +d, this bit will not be triggered..*/ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st +is changed from non idle state to idle state. 0: Others..*/ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st +is changed from non idle state to idle state. It means that SPI_CS raises high. +0: Others.*/ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C +E is sent and flash is already idle. 0: Others..*/ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_V 0x1 +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com +mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com +mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_V 0x1 +#define SPI_MEM_WPE_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) +/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} +..*/ +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SPI_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to flash..*/ +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to flash..*/ +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the panda device..*/ +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) +/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 +]}..*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] +, 1'b0}..*/ +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SPI_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the DDR psram..*/ +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +/* SPI_MEM_SPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS0_ECC_S 2 +/* SPI_MEM_SPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_SPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +/* SPI_MEM_SPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS1_ECC_S 2 +/* SPI_MEM_SPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_SPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +/* SPI_MEM_SPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS2_ECC_S 2 +/* SPI_MEM_SPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_SPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) +/* SPI_MEM_SPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS3_ECC_S 2 +/* SPI_MEM_SPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_SPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +/* SPI_MEM_SPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +/* SPI_MEM_SPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +/* SPI_MEM_SPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) +/* SPI_MEM_SPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +/* SPI_MEM_SPI_FMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_FMEM_PMS0_SIZE 0x00007FFF +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_M ((SPI_MEM_SPI_FMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS0_SIZE_S)) +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_V 0x7FFF +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +/* SPI_MEM_SPI_FMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_FMEM_PMS1_SIZE 0x00007FFF +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_M ((SPI_MEM_SPI_FMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS1_SIZE_S)) +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_V 0x7FFF +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +/* SPI_MEM_SPI_FMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_FMEM_PMS2_SIZE 0x00007FFF +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_M ((SPI_MEM_SPI_FMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS2_SIZE_S)) +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_V 0x7FFF +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) +/* SPI_MEM_SPI_FMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_FMEM_PMS3_SIZE 0x00007FFF +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_M ((SPI_MEM_SPI_FMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS3_SIZE_S)) +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_V 0x7FFF +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +/* SPI_MEM_SPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS0_ECC_S 2 +/* SPI_MEM_SPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_SPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +/* SPI_MEM_SPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS1_ECC_S 2 +/* SPI_MEM_SPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_SPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +/* SPI_MEM_SPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS2_ECC_S 2 +/* SPI_MEM_SPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_SPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) +/* SPI_MEM_SPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SPI_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS3_ECC_S 2 +/* SPI_MEM_SPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_SPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +/* SPI_MEM_SPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +/* SPI_MEM_SPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +/* SPI_MEM_SPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) +/* SPI_MEM_SPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S 0x07FFFFFF +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V 0x7FFFFFF +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +/* SPI_MEM_SPI_SMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_SMEM_PMS0_SIZE 0x00007FFF +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_M ((SPI_MEM_SPI_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS0_SIZE_S)) +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_V 0x7FFF +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +/* SPI_MEM_SPI_SMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_SMEM_PMS1_SIZE 0x00007FFF +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_M ((SPI_MEM_SPI_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS1_SIZE_S)) +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_V 0x7FFF +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +/* SPI_MEM_SPI_SMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_SMEM_PMS2_SIZE 0x00007FFF +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_M ((SPI_MEM_SPI_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS2_SIZE_S)) +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_V 0x7FFF +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) +/* SPI_MEM_SPI_SMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SPI_SMEM_PMS3_SIZE 0x00007FFF +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_M ((SPI_MEM_SPI_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS3_SIZE_S)) +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_V 0x7FFF +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (BIT(31)) +#define SPI_MEM_PMS_IVD_V 0x1 +#define SPI_MEM_PMS_IVD_S 31 +/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It + is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_V 0x1 +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (BIT(29)) +#define SPI_MEM_PMS_ST_V 0x1 +#define SPI_MEM_PMS_ST_S 29 +/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI +_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (BIT(28)) +#define SPI_MEM_PMS_LD_V 0x1 +#define SPI_MEM_PMS_LD_S 28 +/* SPI_MEM_PM_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0/1 transfer permission control function..*/ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (BIT(27)) +#define SPI_MEM_PM_EN_V 0x1 +#define SPI_MEM_PM_EN_S 27 +/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_REJECT_ADDR 0x07FFFFFF +#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) +#define SPI_MEM_REJECT_ADDR_V 0x7FFFFFF +#define SPI_MEM_REJECT_ADDR_S 0 + +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */ +/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding + to byte 0 bit 0 to byte 15 bit 7).*/ +#define SPI_MEM_ECC_ERR_BITS 0x0000007F +#define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) +#define SPI_MEM_ECC_ERR_BITS_V 0x7F +#define SPI_MEM_ECC_ERR_BITS_S 25 +/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd +ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD +R record the first ECC error information..*/ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_USR_ECC_ADDR_EN_S 21 +/* SPI_MEM_SPI_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of flash. If there is no ECC region in flash, th +is bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_SPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: +1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_SPI_FMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_SPI_FMEM_PAGE_SIZE_M ((SPI_MEM_SPI_FMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_FMEM_PAGE_SIZE_S)) +#define SPI_MEM_SPI_FMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_SPI_FMEM_PAGE_SIZE_S 18 +/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas +h..*/ +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 17 +/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr +upt..*/ +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM 0x0000003F +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V 0x3F +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S 11 +/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[10:5] ;default: 6'd0 ; */ +/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_CNT 0x0000003F +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0x3F +#define SPI_MEM_ECC_ERR_CNT_S 5 + +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) +/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0x7FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: This bits show the first AXI write/read invalid error or AXI write flash error a +ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS +H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ +#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) +#define SPI_MEM_AXI_ERR_ADDR_V 0x7FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +/* SPI_MEM_SPI_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of external RAM. If there is no ECC region in ex +ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_SPI_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */ +/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt +es. 2: 1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_SPI_SMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_SPI_SMEM_PAGE_SIZE_M ((SPI_MEM_SPI_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_SMEM_PAGE_SIZE_S)) +#define SPI_MEM_SPI_SMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_SPI_SMEM_PAGE_SIZE_S 18 +/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte +rnal RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 17 + +#define SPI_MEM_SPI_SMEM_AXI_ADDR_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x178) +/* SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO +and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ +#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) +#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 +#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 +/* SPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M (BIT(30)) +#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S 30 +/* SPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_M (BIT(29)) +#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_S 29 +/* SPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ +/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_M (BIT(28)) +#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_S 28 +/* SPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_M (BIT(27)) +#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_S 27 +/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + and SPI0 transfers are done. 0: Others..*/ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 +/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f +lash..*/ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations..*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations..*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +/* SPI_MEM_SPI_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E +XT_RAM..*/ +#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SPI_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper +ations..*/ +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +ns..*/ +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +/* SPI_MEM_SPI_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SPI_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SPI_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SPI_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SPI_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SPI_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +/* SPI_MEM_SPI_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SPI_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SPI_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SPI_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SPI_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SPI_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SPI_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SPI_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SPI_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) +/* SPI_MEM_SPI_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 +/* SPI_MEM_SPI_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 +/* SPI_MEM_SPI_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 +/* SPI_MEM_SPI_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 +/* SPI_MEM_SPI_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 +/* SPI_MEM_SPI_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 +/* SPI_MEM_SPI_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) +/* SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt +er whether there is an ECC region or not..*/ +#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_M (BIT(31)) +#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_S 31 +/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M +SPI core clock cycles..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh +en accesses external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c +ycles in ECC mode when accessed external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */ +/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a +re combined with spi_mem_cs_hold bit..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 +/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */ +/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s +pi_mem_cs_setup bit..*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SPI_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab +le..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SPI_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d +isable..*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A4) +/* SPI_MEM_SPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_M ((SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S 24 +/* SPI_MEM_SPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN15_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN15_MODE_M ((SPI_MEM_SPI_SMEM_DIN15_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN15_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN15_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN15_MODE_S 21 +/* SPI_MEM_SPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN14_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN14_MODE_M ((SPI_MEM_SPI_SMEM_DIN14_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN14_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN14_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN14_MODE_S 18 +/* SPI_MEM_SPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN13_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN13_MODE_M ((SPI_MEM_SPI_SMEM_DIN13_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN13_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN13_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN13_MODE_S 15 +/* SPI_MEM_SPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN12_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN12_MODE_M ((SPI_MEM_SPI_SMEM_DIN12_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN12_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN12_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN12_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN11_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN11_MODE_M ((SPI_MEM_SPI_SMEM_DIN11_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN11_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN11_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN11_MODE_S 9 +/* SPI_MEM_SPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN10_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN10_MODE_M ((SPI_MEM_SPI_SMEM_DIN10_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN10_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN10_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN10_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN09_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN09_MODE_M ((SPI_MEM_SPI_SMEM_DIN09_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN09_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN09_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN09_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DIN08_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN08_MODE_M ((SPI_MEM_SPI_SMEM_DIN08_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN08_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN08_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN08_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_HEX_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A8) +/* SPI_MEM_SPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_M ((SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S 16 +/* SPI_MEM_SPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN15_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN15_NUM_M ((SPI_MEM_SPI_SMEM_DIN15_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN15_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN15_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN15_NUM_S 14 +/* SPI_MEM_SPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN14_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN14_NUM_M ((SPI_MEM_SPI_SMEM_DIN14_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN14_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN14_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN14_NUM_S 12 +/* SPI_MEM_SPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN13_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN13_NUM_M ((SPI_MEM_SPI_SMEM_DIN13_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN13_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN13_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN13_NUM_S 10 +/* SPI_MEM_SPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN12_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN12_NUM_M ((SPI_MEM_SPI_SMEM_DIN12_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN12_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN12_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN12_NUM_S 8 +/* SPI_MEM_SPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN11_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN11_NUM_M ((SPI_MEM_SPI_SMEM_DIN11_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN11_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN11_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN11_NUM_S 6 +/* SPI_MEM_SPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN10_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN10_NUM_M ((SPI_MEM_SPI_SMEM_DIN10_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN10_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN10_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN10_NUM_S 4 +/* SPI_MEM_SPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN09_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN09_NUM_M ((SPI_MEM_SPI_SMEM_DIN09_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN09_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN09_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN09_NUM_S 2 +/* SPI_MEM_SPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SPI_SMEM_DIN08_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN08_NUM_M ((SPI_MEM_SPI_SMEM_DIN08_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN08_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN08_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN08_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1AC) +/* SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_M (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_S 8 +/* SPI_MEM_SPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT15_MODE_M (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT15_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT15_MODE_S 7 +/* SPI_MEM_SPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT14_MODE_M (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT14_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT14_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT13_MODE_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT13_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT13_MODE_S 5 +/* SPI_MEM_SPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT12_MODE_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT12_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT12_MODE_S 4 +/* SPI_MEM_SPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT11_MODE_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT11_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT11_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT10_MODE_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT10_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT10_MODE_S 2 +/* SPI_MEM_SPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT09_MODE_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT09_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT09_MODE_S 1 +/* SPI_MEM_SPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SPI_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT08_MODE_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT08_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT08_MODE_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +/* SPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ +#define SPI_MEM_SPI_CLK_EN (BIT(0)) +#define SPI_MEM_SPI_CLK_EN_M (BIT(0)) +#define SPI_MEM_SPI_CLK_EN_V 0x1 +#define SPI_MEM_SPI_CLK_EN_S 0 + +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* SPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define SPI_MEM_SPI_XTS_PLAIN 0xFFFFFFFF +#define SPI_MEM_SPI_XTS_PLAIN_M ((SPI_MEM_SPI_XTS_PLAIN_V)<<(SPI_MEM_SPI_XTS_PLAIN_S)) +#define SPI_MEM_SPI_XTS_PLAIN_V 0xFFFFFFFF +#define SPI_MEM_SPI_XTS_PLAIN_S 0 + +#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* SPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define SPI_MEM_SPI_XTS_LINESIZE 0x00000003 +#define SPI_MEM_SPI_XTS_LINESIZE_M ((SPI_MEM_SPI_XTS_LINESIZE_V)<<(SPI_MEM_SPI_XTS_LINESIZE_S)) +#define SPI_MEM_SPI_XTS_LINESIZE_V 0x3 +#define SPI_MEM_SPI_XTS_LINESIZE_S 0 + +#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* SPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryptio +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define SPI_MEM_SPI_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_SPI_XTS_DESTINATION_M (BIT(0)) +#define SPI_MEM_SPI_XTS_DESTINATION_V 0x1 +#define SPI_MEM_SPI_XTS_DESTINATION_S 0 + +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFF +#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S)) +#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S 0 + +#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* SPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryptio +n status becomes 2..*/ +#define SPI_MEM_SPI_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_SPI_XTS_TRIGGER_M (BIT(0)) +#define SPI_MEM_SPI_XTS_TRIGGER_V 0x1 +#define SPI_MEM_SPI_XTS_TRIGGER_S 0 + +#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* SPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define SPI_MEM_SPI_XTS_RELEASE (BIT(0)) +#define SPI_MEM_SPI_XTS_RELEASE_M (BIT(0)) +#define SPI_MEM_SPI_XTS_RELEASE_V 0x1 +#define SPI_MEM_SPI_XTS_RELEASE_S 0 + +#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* SPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define SPI_MEM_SPI_XTS_DESTROY (BIT(0)) +#define SPI_MEM_SPI_XTS_DESTROY_M (BIT(0)) +#define SPI_MEM_SPI_XTS_DESTROY_V 0x1 +#define SPI_MEM_SPI_XTS_DESTROY_S 0 + +#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* SPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define SPI_MEM_SPI_XTS_STATE 0x00000003 +#define SPI_MEM_SPI_XTS_STATE_M ((SPI_MEM_SPI_XTS_STATE_V)<<(SPI_MEM_SPI_XTS_STATE_S)) +#define SPI_MEM_SPI_XTS_STATE_V 0x3 +#define SPI_MEM_SPI_XTS_STATE_S 0 + +#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* SPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define SPI_MEM_SPI_XTS_DATE 0x3FFFFFFF +#define SPI_MEM_SPI_XTS_DATE_M ((SPI_MEM_SPI_XTS_DATE_V)<<(SPI_MEM_SPI_XTS_DATE_S)) +#define SPI_MEM_SPI_XTS_DATE_V 0x3FFFFFFF +#define SPI_MEM_SPI_XTS_DATE_S 0 + +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) +/* SPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: MSPI-MMU item content.*/ +#define SPI_MEM_SPI_MMU_ITEM_CONTENT 0xFFFFFFFF +#define SPI_MEM_SPI_MMU_ITEM_CONTENT_M ((SPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(SPI_MEM_SPI_MMU_ITEM_CONTENT_S)) +#define SPI_MEM_SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFF +#define SPI_MEM_SPI_MMU_ITEM_CONTENT_S 0 + +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +/* SPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: MSPI-MMU item index.*/ +#define SPI_MEM_SPI_MMU_ITEM_INDEX 0xFFFFFFFF +#define SPI_MEM_SPI_MMU_ITEM_INDEX_M ((SPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(SPI_MEM_SPI_MMU_ITEM_INDEX_S)) +#define SPI_MEM_SPI_MMU_ITEM_INDEX_V 0xFFFFFFFF +#define SPI_MEM_SPI_MMU_ITEM_INDEX_S 0 + +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ +#define SPI_MEM_RDN_RESULT (BIT(31)) +#define SPI_MEM_RDN_RESULT_M (BIT(31)) +#define SPI_MEM_RDN_RESULT_V 0x1 +#define SPI_MEM_RDN_RESULT_S 31 +/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: ECO register enable bit.*/ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (BIT(30)) +#define SPI_MEM_RDN_ENA_V 0x1 +#define SPI_MEM_RDN_ENA_S 30 +/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */ +/*description: MMU PSRAM aux control register.*/ +#define SPI_MEM_AUX_CTRL 0x00003FFF +#define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) +#define SPI_MEM_AUX_CTRL_V 0x3FFF +#define SPI_MEM_AUX_CTRL_S 16 +/* SPI_MEM_SPI_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ +#define SPI_MEM_SPI_MMU_PAGE_SIZE 0x00000003 +#define SPI_MEM_SPI_MMU_PAGE_SIZE_M ((SPI_MEM_SPI_MMU_PAGE_SIZE_V)<<(SPI_MEM_SPI_MMU_PAGE_SIZE_S)) +#define SPI_MEM_SPI_MMU_PAGE_SIZE_V 0x3 +#define SPI_MEM_SPI_MMU_PAGE_SIZE_S 3 +/* SPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be + controlled by rtc..*/ +#define SPI_MEM_SPI_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_M (BIT(2)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_V 0x1 +#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_S 2 +/* SPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to force mmu-memory powerdown.*/ +#define SPI_MEM_SPI_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_M (BIT(1)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_V 0x1 +#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_S 1 +/* SPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable mmu-memory clock force on.*/ +#define SPI_MEM_SPI_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_M (BIT(0)) +#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_V 0x1 +#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_S 0 + +#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S 4 +/* SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V 0x1 +#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S 3 +/* SPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL 0x00000007 +#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S)) +#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V 0x7 +#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S 0 + +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) +/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO high register.*/ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 + +#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) +/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO low register.*/ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2212091 ; */ +/*description: SPI0 register version..*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h b/components/soc/esp32p4/include/soc/spi_mem_s_reg.h index 2e156ebe1c..9133d8694f 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h +++ b/components/soc/esp32p4/include/soc/spi_mem_s_reg.h @@ -11,2871 +11,2871 @@ extern "C" { #endif -/** SPI_MEM_CMD_REG register +/** SPI_MEM_S_CMD_REG register * SPI0 FSM status register */ -#define SPI_MEM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0) -/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; +#define SPI_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0) +/** SPI_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0; * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. */ -#define SPI_MEM_MST_ST 0x0000000FU -#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) -#define SPI_MEM_MST_ST_V 0x0000000FU -#define SPI_MEM_MST_ST_S 0 -/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; +#define SPI_MEM_S_MST_ST 0x0000000FU +#define SPI_MEM_S_MST_ST_M (SPI_MEM_S_MST_ST_V << SPI_MEM_S_MST_ST_S) +#define SPI_MEM_S_MST_ST_V 0x0000000FU +#define SPI_MEM_S_MST_ST_S 0 +/** SPI_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0; * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, * 2: send command state, 3: send address state, 4: wait state, 5: read data state, * 6:write data state, 7: done state, 8: read data end state. */ -#define SPI_MEM_SLV_ST 0x0000000FU -#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) -#define SPI_MEM_SLV_ST_V 0x0000000FU -#define SPI_MEM_SLV_ST_S 4 -/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation +#define SPI_MEM_S_SLV_ST 0x0000000FU +#define SPI_MEM_S_SLV_ST_M (SPI_MEM_S_SLV_ST_V << SPI_MEM_S_SLV_ST_S) +#define SPI_MEM_S_SLV_ST_V 0x0000000FU +#define SPI_MEM_S_SLV_ST_S 4 +/** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) -#define SPI_MEM_USR_V 0x00000001U -#define SPI_MEM_USR_S 18 +#define SPI_MEM_S_USR (BIT(18)) +#define SPI_MEM_S_USR_M (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S) +#define SPI_MEM_S_USR_V 0x00000001U +#define SPI_MEM_S_USR_S 18 -/** SPI_MEM_CTRL_REG register +/** SPI_MEM_S_CTRL_REG register * SPI0 control register. */ -#define SPI_MEM_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8) +/** SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 -/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_S_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_IO[7:0] is output by the MSPI controller. */ -#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 -/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is * output by the MSPI controller in the first half part of dummy phase. It is used to * mask invalid SPI_DQS in the half part of dummy phase. */ -#define SPI_MEM_FDUMMY_RIN (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) -#define SPI_MEM_FDUMMY_RIN_V 0x00000001U -#define SPI_MEM_FDUMMY_RIN_S 2 -/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; +#define SPI_MEM_S_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_S_FDUMMY_RIN_M (SPI_MEM_S_FDUMMY_RIN_V << SPI_MEM_S_FDUMMY_RIN_S) +#define SPI_MEM_S_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_S_FDUMMY_RIN_S 2 +/** SPI_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is * output by the MSPI controller in the second half part of dummy phase. It is used to * pre-drive flash. */ -#define SPI_MEM_FDUMMY_WOUT (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) -#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_S_FDUMMY_WOUT_M (SPI_MEM_S_FDUMMY_WOUT_V << SPI_MEM_S_FDUMMY_WOUT_S) +#define SPI_MEM_S_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_S_FDUMMY_WOUT_S 3 +/** SPI_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) -#define SPI_MEM_FDOUT_OCT_V 0x00000001U -#define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_FDOUT_OCT (BIT(4)) +#define SPI_MEM_S_FDOUT_OCT_M (SPI_MEM_S_FDOUT_OCT_V << SPI_MEM_S_FDOUT_OCT_S) +#define SPI_MEM_S_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_S_FDOUT_OCT_S 4 +/** SPI_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) -#define SPI_MEM_FDIN_OCT_V 0x00000001U -#define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_FDIN_OCT (BIT(5)) +#define SPI_MEM_S_FDIN_OCT_M (SPI_MEM_S_FDIN_OCT_V << SPI_MEM_S_FDIN_OCT_S) +#define SPI_MEM_S_FDIN_OCT_V 0x00000001U +#define SPI_MEM_S_FDIN_OCT_S 5 +/** SPI_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) -#define SPI_MEM_FADDR_OCT_V 0x00000001U -#define SPI_MEM_FADDR_OCT_S 6 -/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_FADDR_OCT (BIT(6)) +#define SPI_MEM_S_FADDR_OCT_M (SPI_MEM_S_FADDR_OCT_V << SPI_MEM_S_FADDR_OCT_S) +#define SPI_MEM_S_FADDR_OCT_V 0x00000001U +#define SPI_MEM_S_FADDR_OCT_S 6 +/** SPI_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0; * Apply 4 signals during command phase 1:enable 0: disable */ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) -#define SPI_MEM_FCMD_QUAD_V 0x00000001U -#define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; +#define SPI_MEM_S_FCMD_QUAD (BIT(8)) +#define SPI_MEM_S_FCMD_QUAD_M (SPI_MEM_S_FCMD_QUAD_V << SPI_MEM_S_FCMD_QUAD_S) +#define SPI_MEM_S_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_S_FCMD_QUAD_S 8 +/** SPI_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) -#define SPI_MEM_FCMD_OCT_V 0x00000001U -#define SPI_MEM_FCMD_OCT_S 9 -/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. +#define SPI_MEM_S_FCMD_OCT (BIT(9)) +#define SPI_MEM_S_FCMD_OCT_M (SPI_MEM_S_FCMD_OCT_V << SPI_MEM_S_FCMD_OCT_S) +#define SPI_MEM_S_FCMD_OCT_V 0x00000001U +#define SPI_MEM_S_FCMD_OCT_S 9 +/** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT + * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. */ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) -#define SPI_MEM_FASTRD_MODE_V 0x00000001U -#define SPI_MEM_FASTRD_MODE_S 13 -/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; +#define SPI_MEM_S_FASTRD_MODE (BIT(13)) +#define SPI_MEM_S_FASTRD_MODE_M (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S) +#define SPI_MEM_S_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_S_FASTRD_MODE_S 13 +/** SPI_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0; * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) -#define SPI_MEM_FREAD_DUAL_V 0x00000001U -#define SPI_MEM_FREAD_DUAL_S 14 -/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; +#define SPI_MEM_S_FREAD_DUAL (BIT(14)) +#define SPI_MEM_S_FREAD_DUAL_M (SPI_MEM_S_FREAD_DUAL_V << SPI_MEM_S_FREAD_DUAL_S) +#define SPI_MEM_S_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_S_FREAD_DUAL_S 14 +/** SPI_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1; * The bit is used to set MISO line polarity, 1: high 0, low */ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) -#define SPI_MEM_Q_POL_V 0x00000001U -#define SPI_MEM_Q_POL_S 18 -/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; +#define SPI_MEM_S_Q_POL (BIT(18)) +#define SPI_MEM_S_Q_POL_M (SPI_MEM_S_Q_POL_V << SPI_MEM_S_Q_POL_S) +#define SPI_MEM_S_Q_POL_V 0x00000001U +#define SPI_MEM_S_Q_POL_S 18 +/** SPI_MEM_S_D_POL : R/W; bitpos: [19]; default: 1; * The bit is used to set MOSI line polarity, 1: high 0, low */ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) -#define SPI_MEM_D_POL_V 0x00000001U -#define SPI_MEM_D_POL_S 19 -/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; +#define SPI_MEM_S_D_POL (BIT(19)) +#define SPI_MEM_S_D_POL_M (SPI_MEM_S_D_POL_V << SPI_MEM_S_D_POL_S) +#define SPI_MEM_S_D_POL_V 0x00000001U +#define SPI_MEM_S_D_POL_S 19 +/** SPI_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0; * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) -#define SPI_MEM_FREAD_QUAD_V 0x00000001U -#define SPI_MEM_FREAD_QUAD_S 20 -/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; +#define SPI_MEM_S_FREAD_QUAD (BIT(20)) +#define SPI_MEM_S_FREAD_QUAD_M (SPI_MEM_S_FREAD_QUAD_V << SPI_MEM_S_FREAD_QUAD_S) +#define SPI_MEM_S_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_S_FREAD_QUAD_S 20 +/** SPI_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1; * Write protect signal output when SPI is idle. 1: output high, 0: output low. */ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) -#define SPI_MEM_WP_REG_V 0x00000001U -#define SPI_MEM_WP_REG_S 21 -/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; +#define SPI_MEM_S_WP_REG (BIT(21)) +#define SPI_MEM_S_WP_REG_M (SPI_MEM_S_WP_REG_V << SPI_MEM_S_WP_REG_S) +#define SPI_MEM_S_WP_REG_V 0x00000001U +#define SPI_MEM_S_WP_REG_S 21 +/** SPI_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0; * In the read operations address phase and read-data phase apply 2 signals. 1: enable * 0: disable. */ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) -#define SPI_MEM_FREAD_DIO_V 0x00000001U -#define SPI_MEM_FREAD_DIO_S 23 -/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; +#define SPI_MEM_S_FREAD_DIO (BIT(23)) +#define SPI_MEM_S_FREAD_DIO_M (SPI_MEM_S_FREAD_DIO_V << SPI_MEM_S_FREAD_DIO_S) +#define SPI_MEM_S_FREAD_DIO_V 0x00000001U +#define SPI_MEM_S_FREAD_DIO_S 23 +/** SPI_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0; * In the read operations address phase and read-data phase apply 4 signals. 1: enable * 0: disable. */ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) -#define SPI_MEM_FREAD_QIO_V 0x00000001U -#define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; +#define SPI_MEM_S_FREAD_QIO (BIT(24)) +#define SPI_MEM_S_FREAD_QIO_M (SPI_MEM_S_FREAD_QIO_V << SPI_MEM_S_FREAD_QIO_S) +#define SPI_MEM_S_FREAD_QIO_V 0x00000001U +#define SPI_MEM_S_FREAD_QIO_S 24 +/** SPI_MEM_S_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ -#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) -#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; +#define SPI_MEM_S_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_M (SPI_MEM_S_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_S_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are * always 1. 0: Others. */ -#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) -#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 +#define SPI_MEM_S_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_M (SPI_MEM_S_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_S 31 -/** SPI_MEM_CTRL1_REG register +/** SPI_MEM_S_CTRL1_REG register * SPI0 control1 register. */ -#define SPI_MEM_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc) -/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc) +/** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is alwasy on. */ -#define SPI_MEM_CLK_MODE 0x00000003U -#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) -#define SPI_MEM_CLK_MODE_V 0x00000003U -#define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; +#define SPI_MEM_S_CLK_MODE 0x00000003U +#define SPI_MEM_S_CLK_MODE_M (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S) +#define SPI_MEM_S_CLK_MODE_V 0x00000003U +#define SPI_MEM_S_CLK_MODE_S 0 +/** SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) -#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) -#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) -#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) -#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: * Reply AXI read data to AXI bus when all the read data is available. */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 -/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; +#define SPI_MEM_S_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S) +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. + * in SPI_MEM_S_ECC_ERR_ADDR_REG. */ -#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) -#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U -#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; +#define SPI_MEM_S_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_S_RRESP_ECC_ERR_EN_M (SPI_MEM_S_RRESP_ECC_ERR_EN_V << SPI_MEM_S_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_S_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_S_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_S_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ -#define SPI_MEM_AR_SPLICE_EN (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) -#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; +#define SPI_MEM_S_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_S_AR_SPLICE_EN_M (SPI_MEM_S_AR_SPLICE_EN_V << SPI_MEM_S_AR_SPLICE_EN_S) +#define SPI_MEM_S_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_S_AR_SPLICE_EN_S 25 +/** SPI_MEM_S_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ -#define SPI_MEM_AW_SPLICE_EN (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) -#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AW_SPLICE_EN_S 26 -/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be +#define SPI_MEM_S_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_S_AW_SPLICE_EN_M (SPI_MEM_S_AW_SPLICE_EN_V << SPI_MEM_S_AW_SPLICE_EN_S) +#define SPI_MEM_S_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_S_AW_SPLICE_EN_S 26 +/** SPI_MEM_S_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ -#define SPI_MEM_RAM0_EN (BIT(27)) -#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) -#define SPI_MEM_RAM0_EN_V 0x00000001U -#define SPI_MEM_RAM0_EN_S 27 -/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; +#define SPI_MEM_S_RAM0_EN (BIT(27)) +#define SPI_MEM_S_RAM0_EN_M (SPI_MEM_S_RAM0_EN_V << SPI_MEM_S_RAM0_EN_S) +#define SPI_MEM_S_RAM0_EN_V 0x00000001U +#define SPI_MEM_S_RAM0_EN_S 27 +/** SPI_MEM_S_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the * same time. */ -#define SPI_MEM_DUAL_RAM_EN (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) -#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U -#define SPI_MEM_DUAL_RAM_EN_S 28 -/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; +#define SPI_MEM_S_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_S_DUAL_RAM_EN_M (SPI_MEM_S_DUAL_RAM_EN_V << SPI_MEM_S_DUAL_RAM_EN_S) +#define SPI_MEM_S_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_S_DUAL_RAM_EN_S 28 +/** SPI_MEM_S_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; * Set this bit to write data faster, do not wait write data has been stored in * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored * in tx_bus_fifo_l2. */ -#define SPI_MEM_FAST_WRITE_EN (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) -#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U -#define SPI_MEM_FAST_WRITE_EN_S 29 -/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; +#define SPI_MEM_S_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_S_FAST_WRITE_EN_M (SPI_MEM_S_FAST_WRITE_EN_V << SPI_MEM_S_FAST_WRITE_EN_S) +#define SPI_MEM_S_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_S_FAST_WRITE_EN_S 29 +/** SPI_MEM_S_RXFIFO_RST : WT; bitpos: [30]; default: 0; * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to * receive signals from AXI. Set this bit to reset these FIFO. */ -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) -#define SPI_MEM_RXFIFO_RST_V 0x00000001U -#define SPI_MEM_RXFIFO_RST_S 30 -/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; +#define SPI_MEM_S_RXFIFO_RST (BIT(30)) +#define SPI_MEM_S_RXFIFO_RST_M (SPI_MEM_S_RXFIFO_RST_V << SPI_MEM_S_RXFIFO_RST_S) +#define SPI_MEM_S_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_S_RXFIFO_RST_S 30 +/** SPI_MEM_S_TXFIFO_RST : WT; bitpos: [31]; default: 0; * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to * send signals to AXI. Set this bit to reset these FIFO. */ -#define SPI_MEM_TXFIFO_RST (BIT(31)) -#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) -#define SPI_MEM_TXFIFO_RST_V 0x00000001U -#define SPI_MEM_TXFIFO_RST_S 31 +#define SPI_MEM_S_TXFIFO_RST (BIT(31)) +#define SPI_MEM_S_TXFIFO_RST_M (SPI_MEM_S_TXFIFO_RST_V << SPI_MEM_S_TXFIFO_RST_S) +#define SPI_MEM_S_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_S_TXFIFO_RST_S 31 -/** SPI_MEM_CTRL2_REG register +/** SPI_MEM_S_CTRL2_REG register * SPI0 control2 register. */ -#define SPI_MEM_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10) -/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; +#define SPI_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10) +/** SPI_MEM_S_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. + * SPI_MEM_S_CS_SETUP bit. */ -#define SPI_MEM_CS_SETUP_TIME 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) -#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_S 0 -/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; +#define SPI_MEM_S_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_S_CS_SETUP_TIME_M (SPI_MEM_S_CS_SETUP_TIME_V << SPI_MEM_S_CS_SETUP_TIME_S) +#define SPI_MEM_S_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_S_CS_SETUP_TIME_S 0 +/** SPI_MEM_S_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. + * SPI_MEM_S_CS_HOLD bit. */ -#define SPI_MEM_CS_HOLD_TIME 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) -#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC +#define SPI_MEM_S_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_S_CS_HOLD_TIME_M (SPI_MEM_S_CS_HOLD_TIME_V << SPI_MEM_S_CS_HOLD_TIME_S) +#define SPI_MEM_S_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_S_CS_HOLD_TIME_S 5 +/** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; +#define SPI_MEM_S_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_S_ECC_CS_HOLD_TIME_M (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_S_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_S_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_S_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_S_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 -/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; +#define SPI_MEM_S_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_M (SPI_MEM_S_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_S_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI * transfers when one transfer will cross flash or EXT_RAM page corner, valid no * matter whether there is an ECC region or not. */ -#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) -#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_MEM_SPLIT_TRANS_EN_S 24 -/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; +#define SPI_MEM_S_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_S_SPLIT_TRANS_EN_M (SPI_MEM_S_SPLIT_TRANS_EN_V << SPI_MEM_S_SPLIT_TRANS_EN_S) +#define SPI_MEM_S_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_S_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_S_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ -#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) -#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_S 25 -/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; +#define SPI_MEM_S_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_S_CS_HOLD_DELAY_M (SPI_MEM_S_CS_HOLD_DELAY_V << SPI_MEM_S_CS_HOLD_DELAY_S) +#define SPI_MEM_S_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_S_CS_HOLD_DELAY_S 25 +/** SPI_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0; * The spi0_mst_st and spi0_slv_st will be reset. */ -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) -#define SPI_MEM_SYNC_RESET_V 0x00000001U -#define SPI_MEM_SYNC_RESET_S 31 +#define SPI_MEM_S_SYNC_RESET (BIT(31)) +#define SPI_MEM_S_SYNC_RESET_M (SPI_MEM_S_SYNC_RESET_V << SPI_MEM_S_SYNC_RESET_S) +#define SPI_MEM_S_SYNC_RESET_V 0x00000001U +#define SPI_MEM_S_SYNC_RESET_S 31 -/** SPI_MEM_CLOCK_REG register +/** SPI_MEM_S_CLOCK_REG register * SPI clock division control register. */ -#define SPI_MEM_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14) -/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. +#define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14) +/** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to SPI_MEM_S_clkcnt_N. */ -#define SPI_MEM_CLKCNT_L 0x000000FFU -#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) -#define SPI_MEM_CLKCNT_L_V 0x000000FFU -#define SPI_MEM_CLKCNT_L_S 0 -/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). +#define SPI_MEM_S_CLKCNT_L 0x000000FFU +#define SPI_MEM_S_CLKCNT_L_M (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S) +#define SPI_MEM_S_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_L_S 0 +/** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((SPI_MEM_S_clkcnt_N+1)/2-1). */ -#define SPI_MEM_CLKCNT_H 0x000000FFU -#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) -#define SPI_MEM_CLKCNT_H_V 0x000000FFU -#define SPI_MEM_CLKCNT_H_S 8 -/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) +#define SPI_MEM_S_CLKCNT_H 0x000000FFU +#define SPI_MEM_S_CLKCNT_H_M (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S) +#define SPI_MEM_S_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_H_S 8 +/** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of SPI_MEM_S_clk. So SPI_MEM_S_clk frequency is + * system/(SPI_MEM_S_clkcnt_N+1) */ -#define SPI_MEM_CLKCNT_N 0x000000FFU -#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) -#define SPI_MEM_CLKCNT_N_V 0x000000FFU -#define SPI_MEM_CLKCNT_N_S 16 -/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; +#define SPI_MEM_S_CLKCNT_N 0x000000FFU +#define SPI_MEM_S_CLKCNT_N_M (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S) +#define SPI_MEM_S_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_N_S 16 +/** SPI_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module * clock. */ -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +#define SPI_MEM_S_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_S_CLK_EQU_SYSCLK_M (SPI_MEM_S_CLK_EQU_SYSCLK_V << SPI_MEM_S_CLK_EQU_SYSCLK_S) +#define SPI_MEM_S_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_S_CLK_EQU_SYSCLK_S 31 -/** SPI_MEM_USER_REG register +/** SPI_MEM_S_USER_REG register * SPI0 user register. */ -#define SPI_MEM_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18) -/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18) +/** SPI_MEM_S_CS_HOLD : R/W; bitpos: [6]; default: 0; * spi cs keep low when spi is in done phase. 1: enable 0: disable. */ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) -#define SPI_MEM_CS_HOLD_V 0x00000001U -#define SPI_MEM_CS_HOLD_S 6 -/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_CS_HOLD (BIT(6)) +#define SPI_MEM_S_CS_HOLD_M (SPI_MEM_S_CS_HOLD_V << SPI_MEM_S_CS_HOLD_S) +#define SPI_MEM_S_CS_HOLD_V 0x00000001U +#define SPI_MEM_S_CS_HOLD_S 6 +/** SPI_MEM_S_CS_SETUP : R/W; bitpos: [7]; default: 0; * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) -#define SPI_MEM_CS_SETUP_V 0x00000001U -#define SPI_MEM_CS_SETUP_S 7 -/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. +#define SPI_MEM_S_CS_SETUP (BIT(7)) +#define SPI_MEM_S_CS_SETUP_M (SPI_MEM_S_CS_SETUP_V << SPI_MEM_S_CS_SETUP_S) +#define SPI_MEM_S_CS_SETUP_V 0x00000001U +#define SPI_MEM_S_CS_SETUP_S 7 +/** SPI_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) -#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U -#define SPI_MEM_CK_OUT_EDGE_S 9 -/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; +#define SPI_MEM_S_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_S_CK_OUT_EDGE_M (SPI_MEM_S_CK_OUT_EDGE_V << SPI_MEM_S_CK_OUT_EDGE_S) +#define SPI_MEM_S_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_S_CK_OUT_EDGE_S 9 +/** SPI_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; * spi clock is disable in dummy phase when the bit is enable. */ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U -#define SPI_MEM_USR_DUMMY_IDLE_S 26 -/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; +#define SPI_MEM_S_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_S_USR_DUMMY_IDLE_M (SPI_MEM_S_USR_DUMMY_IDLE_V << SPI_MEM_S_USR_DUMMY_IDLE_S) +#define SPI_MEM_S_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_S_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0; * This bit enable the dummy phase of an operation. */ -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) -#define SPI_MEM_USR_DUMMY_V 0x00000001U -#define SPI_MEM_USR_DUMMY_S 29 +#define SPI_MEM_S_USR_DUMMY (BIT(29)) +#define SPI_MEM_S_USR_DUMMY_M (SPI_MEM_S_USR_DUMMY_V << SPI_MEM_S_USR_DUMMY_S) +#define SPI_MEM_S_USR_DUMMY_V 0x00000001U +#define SPI_MEM_S_USR_DUMMY_S 29 -/** SPI_MEM_USER1_REG register +/** SPI_MEM_S_USER1_REG register * SPI0 user1 register. */ -#define SPI_MEM_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c) -/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be +#define SPI_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c) +/** SPI_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in SPI_MEM_S_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; +#define SPI_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_M (SPI_MEM_S_USR_DUMMY_CYCLELEN_V << SPI_MEM_S_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_S_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ -#define SPI_MEM_USR_DBYTELEN 0x00000007U -#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x00000007U -#define SPI_MEM_USR_DBYTELEN_S 6 -/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; +#define SPI_MEM_S_USR_DBYTELEN 0x00000007U +#define SPI_MEM_S_USR_DBYTELEN_M (SPI_MEM_S_USR_DBYTELEN_V << SPI_MEM_S_USR_DBYTELEN_S) +#define SPI_MEM_S_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_S_USR_DBYTELEN_S 6 +/** SPI_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). */ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_S 26 +#define SPI_MEM_S_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_S_USR_ADDR_BITLEN_M (SPI_MEM_S_USR_ADDR_BITLEN_V << SPI_MEM_S_USR_ADDR_BITLEN_S) +#define SPI_MEM_S_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_S_USR_ADDR_BITLEN_S 26 -/** SPI_MEM_USER2_REG register +/** SPI_MEM_S_USER2_REG register * SPI0 user2 register. */ -#define SPI_MEM_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20) -/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; +#define SPI_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20) +/** SPI_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. */ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) -#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_S 0 -/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; +#define SPI_MEM_S_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_S_USR_COMMAND_VALUE_M (SPI_MEM_S_USR_COMMAND_VALUE_V << SPI_MEM_S_USR_COMMAND_VALUE_S) +#define SPI_MEM_S_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_S_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; * The length in bits of command phase. The register value shall be (bit_num-1) */ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +#define SPI_MEM_S_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_S_USR_COMMAND_BITLEN_M (SPI_MEM_S_USR_COMMAND_BITLEN_V << SPI_MEM_S_USR_COMMAND_BITLEN_S) +#define SPI_MEM_S_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_S_USR_COMMAND_BITLEN_S 28 -/** SPI_MEM_MISC_REG register +/** SPI_MEM_S_MISC_REG register * SPI0 misc register */ -#define SPI_MEM_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34) -/** SPI_MEM_FSUB_PIN : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34) +/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) -#define SPI_MEM_FSUB_PIN_V 0x00000001U -#define SPI_MEM_FSUB_PIN_S 7 -/** SPI_MEM_SSUB_PIN : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_FSUB_PIN (BIT(7)) +#define SPI_MEM_S_FSUB_PIN_M (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S) +#define SPI_MEM_S_FSUB_PIN_V 0x00000001U +#define SPI_MEM_S_FSUB_PIN_S 7 +/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) -#define SPI_MEM_SSUB_PIN_V 0x00000001U -#define SPI_MEM_SSUB_PIN_S 8 -/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; +#define SPI_MEM_S_SSUB_PIN (BIT(8)) +#define SPI_MEM_S_SSUB_PIN_M (SPI_MEM_S_SSUB_PIN_V << SPI_MEM_S_SSUB_PIN_S) +#define SPI_MEM_S_SSUB_PIN_V 0x00000001U +#define SPI_MEM_S_SSUB_PIN_S 8 +/** SPI_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) -#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U -#define SPI_MEM_CK_IDLE_EDGE_S 9 -/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; +#define SPI_MEM_S_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_S_CK_IDLE_EDGE_M (SPI_MEM_S_CK_IDLE_EDGE_V << SPI_MEM_S_CK_IDLE_EDGE_S) +#define SPI_MEM_S_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_S_CK_IDLE_EDGE_S 9 +/** SPI_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; * SPI_CS line keep low when the bit is set. */ -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +#define SPI_MEM_S_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_S_CS_KEEP_ACTIVE_M (SPI_MEM_S_CS_KEEP_ACTIVE_V << SPI_MEM_S_CS_KEEP_ACTIVE_S) +#define SPI_MEM_S_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_S_CS_KEEP_ACTIVE_S 10 -/** SPI_MEM_CACHE_FCTRL_REG register +/** SPI_MEM_S_CACHE_FCTRL_REG register * SPI0 bit mode control register. */ -#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c) -/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; +#define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c) +/** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ -#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U -#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 -/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_MEM_S_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; * Set this bit to close AXI read/write transfer to MSPI, which means that only * SLV_ERR will be replied to BRESP/RRESP. */ -#define SPI_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) -#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U -#define SPI_CLOSE_AXI_INF_EN_S 31 +#define SPI_MEM_S_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_S_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_MEM_S_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_MEM_S_CLOSE_AXI_INF_EN_S 31 -/** SPI_MEM_SRAM_CMD_REG register +/** SPI_MEM_S_SRAM_CMD_REG register * SPI0 external RAM mode control register */ -#define SPI_MEM_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44) -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; +#define SPI_MEM_S_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44) +/** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. */ -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_IO[7:0] is output by the MSPI controller. */ -#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ -#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ -#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S 31 -/** SPI_MEM_FSM_REG register +/** SPI_MEM_S_FSM_REG register * SPI0 FSM status register */ -#define SPI_MEM_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +#define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54) +/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU -#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU -#define SPI_MEM_LOCK_DELAY_TIME_S 7 +#define SPI_MEM_S_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_M (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S) +#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_INT_ENA_REG register +/** SPI_MEM_S_INT_ENA_REG register * SPI0 interrupt enable register */ -#define SPI_MEM_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0) -/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. +#define SPI_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0) +/** SPI_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ -#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) -#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 -/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. +#define SPI_MEM_S_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_ENA_M (SPI_MEM_S_SLV_ST_END_INT_ENA_V << SPI_MEM_S_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_S_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ -#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) -#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. +#define SPI_MEM_S_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_ENA_M (SPI_MEM_S_MST_ST_END_INT_ENA_V << SPI_MEM_S_MST_ST_END_INT_ENA_S) +#define SPI_MEM_S_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_S_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ENA_S 5 -/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. +#define SPI_MEM_S_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_ENA_M (SPI_MEM_S_ECC_ERR_INT_ENA_V << SPI_MEM_S_ECC_ERR_INT_ENA_S) +#define SPI_MEM_S_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ -#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) -#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. +#define SPI_MEM_S_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_ENA_M (SPI_MEM_S_PMS_REJECT_INT_ENA_V << SPI_MEM_S_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_S_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S 31 -/** SPI_MEM_INT_CLR_REG register +/** SPI_MEM_S_INT_CLR_REG register * SPI0 interrupt clear register */ -#define SPI_MEM_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4) -/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. +#define SPI_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4) +/** SPI_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ -#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) -#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 -/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. +#define SPI_MEM_S_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_CLR_M (SPI_MEM_S_SLV_ST_END_INT_CLR_V << SPI_MEM_S_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_S_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ -#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) -#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. +#define SPI_MEM_S_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_CLR_M (SPI_MEM_S_MST_ST_END_INT_CLR_V << SPI_MEM_S_MST_ST_END_INT_CLR_S) +#define SPI_MEM_S_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_S_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_CLR_S 5 -/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. +#define SPI_MEM_S_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_CLR_M (SPI_MEM_S_ECC_ERR_INT_CLR_V << SPI_MEM_S_ECC_ERR_INT_CLR_S) +#define SPI_MEM_S_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ -#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) -#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. +#define SPI_MEM_S_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_CLR_M (SPI_MEM_S_PMS_REJECT_INT_CLR_V << SPI_MEM_S_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_S_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S 31 -/** SPI_MEM_INT_RAW_REG register +/** SPI_MEM_S_INT_RAW_REG register * SPI0 interrupt raw register */ -#define SPI_MEM_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8) -/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is +#define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8) +/** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ -#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) -#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 -/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is +#define SPI_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_RAW_M (SPI_MEM_S_SLV_ST_END_INT_RAW_V << SPI_MEM_S_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ -#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) -#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is +#define SPI_MEM_S_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_RAW_M (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S) +#define SPI_MEM_S_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set + * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_RAW_S 5 -/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is +#define SPI_MEM_S_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_RAW_M (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S) +#define SPI_MEM_S_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ -#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) -#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read +#define SPI_MEM_S_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_RAW_M (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_S_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS is overflow. */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is * underflow. */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is * underflow. */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S 31 -/** SPI_MEM_INT_ST_REG register +/** SPI_MEM_S_INT_ST_REG register * SPI0 interrupt status register */ -#define SPI_MEM_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc) -/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. +#define SPI_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc) +/** SPI_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ -#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) -#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ST_S 3 -/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. +#define SPI_MEM_S_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_ST_M (SPI_MEM_S_SLV_ST_END_INT_ST_V << SPI_MEM_S_SLV_ST_END_INT_ST_S) +#define SPI_MEM_S_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ -#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) -#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. +#define SPI_MEM_S_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_ST_M (SPI_MEM_S_MST_ST_END_INT_ST_V << SPI_MEM_S_MST_ST_END_INT_ST_S) +#define SPI_MEM_S_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_S_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ -#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ST_S 5 -/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. +#define SPI_MEM_S_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_ST_M (SPI_MEM_S_ECC_ERR_INT_ST_V << SPI_MEM_S_ECC_ERR_INT_ST_S) +#define SPI_MEM_S_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ -#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) -#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ST_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. +#define SPI_MEM_S_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_ST_M (SPI_MEM_S_PMS_REJECT_INT_ST_V << SPI_MEM_S_PMS_REJECT_INT_ST_S) +#define SPI_MEM_S_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ -#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S 31 -/** SPI_MEM_DDR_REG register +/** SPI_MEM_S_DDR_REG register * SPI0 flash DDR mode control register */ -#define SPI_MEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4) -/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4) +/** SPI_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ -#define SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) -#define SPI_FMEM_DDR_EN_V 0x00000001U -#define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_S_FMEM_DDR_EN_M (SPI_MEM_S_FMEM_DDR_EN_V << SPI_MEM_S_FMEM_DDR_EN_S) +#define SPI_MEM_S_FMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_EN_S 0 +/** SPI_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ -#define SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) -#define SPI_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_S_FMEM_VAR_DUMMY_M (SPI_MEM_S_FMEM_VAR_DUMMY_V << SPI_MEM_S_FMEM_VAR_DUMMY_S) +#define SPI_MEM_S_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_S_FMEM_VAR_DUMMY_S 1 +/** SPI_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ -#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) -#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_M (SPI_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI_MEM_S_FMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ -#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) -#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_M (SPI_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI_MEM_S_FMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ -#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) -#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; +#define SPI_MEM_S_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_M (SPI_MEM_S_FMEM_DDR_CMD_DIS_V << SPI_MEM_S_FMEM_DDR_CMD_DIS_S) +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ -#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) -#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; +#define SPI_MEM_S_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_M (SPI_MEM_S_FMEM_OUTMINBYTELEN_V << SPI_MEM_S_FMEM_OUTMINBYTELEN_S) +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_S_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to flash. */ -#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) -#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_M (SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S) +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_MEM_S_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to flash. */ -#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) -#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_M (SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S) +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ -#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) -#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ -#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) -#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_M (SPI_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI_MEM_S_FMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ -#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) -#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; +#define SPI_MEM_S_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_M (SPI_MEM_S_FMEM_CLK_DIFF_EN_V << SPI_MEM_S_FMEM_CLK_DIFF_EN_S) +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ -#define SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) -#define SPI_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; +#define SPI_MEM_S_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_S_FMEM_DQS_CA_IN_M (SPI_MEM_S_FMEM_DQS_CA_IN_V << SPI_MEM_S_FMEM_DQS_CA_IN_S) +#define SPI_MEM_S_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_S_FMEM_DQS_CA_IN_S 26 +/** SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ -#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ -#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) -#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; +#define SPI_MEM_S_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_M (SPI_MEM_S_FMEM_CLK_DIFF_INV_V << SPI_MEM_S_FMEM_CLK_DIFF_INV_S) +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ -#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) -#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ -#define SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) -#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_FMEM_HYPERBUS_CA_S 30 +#define SPI_MEM_S_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_S_FMEM_HYPERBUS_CA_M (SPI_MEM_S_FMEM_HYPERBUS_CA_V << SPI_MEM_S_FMEM_HYPERBUS_CA_S) +#define SPI_MEM_S_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_S_FMEM_HYPERBUS_CA_S 30 -/** SPI_SMEM_DDR_REG register +/** SPI_MEM_S_SMEM_DDR_REG register * SPI0 external RAM DDR mode control register */ -#define SPI_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8) -/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8) +/** SPI_MEM_S_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ -#define SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) -#define SPI_SMEM_DDR_EN_V 0x00000001U -#define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_S_SMEM_DDR_EN_M (SPI_MEM_S_SMEM_DDR_EN_V << SPI_MEM_S_SMEM_DDR_EN_S) +#define SPI_MEM_S_SMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_EN_S 0 +/** SPI_MEM_S_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ -#define SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) -#define SPI_SMEM_VAR_DUMMY_V 0x00000001U -#define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_S_SMEM_VAR_DUMMY_M (SPI_MEM_S_SMEM_VAR_DUMMY_V << SPI_MEM_S_SMEM_VAR_DUMMY_S) +#define SPI_MEM_S_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_S_SMEM_VAR_DUMMY_S 1 +/** SPI_MEM_S_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ -#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) -#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_M (SPI_MEM_S_SMEM_DDR_RDAT_SWP_V << SPI_MEM_S_SMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_S_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ -#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) -#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_M (SPI_MEM_S_SMEM_DDR_WDAT_SWP_V << SPI_MEM_S_SMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_S_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ -#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) -#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; +#define SPI_MEM_S_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_M (SPI_MEM_S_SMEM_DDR_CMD_DIS_V << SPI_MEM_S_SMEM_DDR_CMD_DIS_S) +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_S_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the DDR psram. */ -#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) -#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; +#define SPI_MEM_S_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_M (SPI_MEM_S_SMEM_OUTMINBYTELEN_V << SPI_MEM_S_SMEM_OUTMINBYTELEN_S) +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_S_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to external RAM. */ -#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) -#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_M (SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S) +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_MEM_S_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to external RAM. */ -#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) -#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_M (SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S) +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_MEM_S_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ -#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) -#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_M (SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ -#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) -#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_M (SPI_MEM_S_SMEM_DDR_DQS_LOOP_V << SPI_MEM_S_SMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_S_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ -#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) -#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; +#define SPI_MEM_S_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_M (SPI_MEM_S_SMEM_CLK_DIFF_EN_V << SPI_MEM_S_SMEM_CLK_DIFF_EN_S) +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_S_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ -#define SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) -#define SPI_SMEM_DQS_CA_IN_V 0x00000001U -#define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; +#define SPI_MEM_S_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_S_SMEM_DQS_CA_IN_M (SPI_MEM_S_SMEM_DQS_CA_IN_V << SPI_MEM_S_SMEM_DQS_CA_IN_S) +#define SPI_MEM_S_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_S_SMEM_DQS_CA_IN_S 26 +/** SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ -#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_S_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to external RAM. . */ -#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) -#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; +#define SPI_MEM_S_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_M (SPI_MEM_S_SMEM_CLK_DIFF_INV_V << SPI_MEM_S_SMEM_CLK_DIFF_INV_S) +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_S_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], * 1'b0}. */ -#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) -#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_M (SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_S_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ -#define SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) -#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_SMEM_HYPERBUS_CA_S 30 +#define SPI_MEM_S_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_S_SMEM_HYPERBUS_CA_M (SPI_MEM_S_SMEM_HYPERBUS_CA_V << SPI_MEM_S_SMEM_HYPERBUS_CA_S) +#define SPI_MEM_S_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_S_SMEM_HYPERBUS_CA_S 30 -/** SPI_FMEM_PMS0_ATTR_REG register +/** SPI_MEM_S_FMEM_PMS0_ATTR_REG register * MSPI flash PMS section 0 attribute register */ -#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100) -/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100) +/** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) -#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_RD_ATTR_S 0 -/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) -#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_WR_ATTR_S 1 -/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and - * SPI_FMEM_PMS0_SIZE_REG. + * section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and + * SPI_MEM_S_FMEM_PMS0_SIZE_REG. */ -#define SPI_FMEM_PMS0_ECC (BIT(2)) -#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) -#define SPI_FMEM_PMS0_ECC_V 0x00000001U -#define SPI_FMEM_PMS0_ECC_S 2 +#define SPI_MEM_S_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS0_ECC_M (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S) +#define SPI_MEM_S_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_ECC_S 2 -/** SPI_FMEM_PMS1_ATTR_REG register +/** SPI_MEM_S_FMEM_PMS1_ATTR_REG register * MSPI flash PMS section 1 attribute register */ -#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104) -/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104) +/** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) -#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_RD_ATTR_S 0 -/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) -#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_WR_ATTR_S 1 -/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and - * SPI_FMEM_PMS1_SIZE_REG. + * section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and + * SPI_MEM_S_FMEM_PMS1_SIZE_REG. */ -#define SPI_FMEM_PMS1_ECC (BIT(2)) -#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) -#define SPI_FMEM_PMS1_ECC_V 0x00000001U -#define SPI_FMEM_PMS1_ECC_S 2 +#define SPI_MEM_S_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS1_ECC_M (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S) +#define SPI_MEM_S_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_ECC_S 2 -/** SPI_FMEM_PMS2_ATTR_REG register +/** SPI_MEM_S_FMEM_PMS2_ATTR_REG register * MSPI flash PMS section 2 attribute register */ -#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108) -/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108) +/** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) -#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_RD_ATTR_S 0 -/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) -#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_WR_ATTR_S 1 -/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and - * SPI_FMEM_PMS2_SIZE_REG. + * section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and + * SPI_MEM_S_FMEM_PMS2_SIZE_REG. */ -#define SPI_FMEM_PMS2_ECC (BIT(2)) -#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) -#define SPI_FMEM_PMS2_ECC_V 0x00000001U -#define SPI_FMEM_PMS2_ECC_S 2 +#define SPI_MEM_S_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS2_ECC_M (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S) +#define SPI_MEM_S_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_ECC_S 2 -/** SPI_FMEM_PMS3_ATTR_REG register +/** SPI_MEM_S_FMEM_PMS3_ATTR_REG register * MSPI flash PMS section 3 attribute register */ -#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c) -/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c) +/** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) -#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_RD_ATTR_S 0 -/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. */ -#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) -#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_WR_ATTR_S 1 -/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and - * SPI_FMEM_PMS3_SIZE_REG. + * section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and + * SPI_MEM_S_FMEM_PMS3_SIZE_REG. */ -#define SPI_FMEM_PMS3_ECC (BIT(2)) -#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) -#define SPI_FMEM_PMS3_ECC_V 0x00000001U -#define SPI_FMEM_PMS3_ECC_S 2 +#define SPI_MEM_S_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS3_ECC_M (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S) +#define SPI_MEM_S_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_ECC_S 2 -/** SPI_FMEM_PMS0_ADDR_REG register +/** SPI_MEM_S_FMEM_PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110) +/** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 flash PMS section 0 start address value */ -#define SPI_FMEM_PMS0_ADDR_S 0x07FFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_S 0 +#define SPI_MEM_S_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_M (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_S 0 -/** SPI_FMEM_PMS1_ADDR_REG register +/** SPI_MEM_S_FMEM_PMS1_ADDR_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114) +/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 flash PMS section 1 start address value */ -#define SPI_FMEM_PMS1_ADDR_S 0x07FFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_S 0 +#define SPI_MEM_S_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_M (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_S 0 -/** SPI_FMEM_PMS2_ADDR_REG register +/** SPI_MEM_S_FMEM_PMS2_ADDR_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118) +/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 flash PMS section 2 start address value */ -#define SPI_FMEM_PMS2_ADDR_S 0x07FFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_S 0 +#define SPI_MEM_S_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_M (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_S 0 -/** SPI_FMEM_PMS3_ADDR_REG register +/** SPI_MEM_S_FMEM_PMS3_ADDR_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c) +/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 flash PMS section 3 start address value */ -#define SPI_FMEM_PMS3_ADDR_S 0x07FFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_S 0 +#define SPI_MEM_S_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_M (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_S 0 -/** SPI_FMEM_PMS0_SIZE_REG register +/** SPI_MEM_S_FMEM_PMS0_SIZE_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, - * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) +#define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120) +/** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_MEM_S_FMEM_PMS0_ADDR_S, + * SPI_MEM_S_FMEM_PMS0_ADDR_S + SPI_MEM_S_FMEM_PMS0_SIZE) */ -#define SPI_FMEM_PMS0_SIZE 0x00007FFFU -#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x00007FFFU -#define SPI_FMEM_PMS0_SIZE_S 0 +#define SPI_MEM_S_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS0_SIZE_M (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S) +#define SPI_MEM_S_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS0_SIZE_S 0 -/** SPI_FMEM_PMS1_SIZE_REG register +/** SPI_MEM_S_FMEM_PMS1_SIZE_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, - * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) +#define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124) +/** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_MEM_S_FMEM_PMS1_ADDR_S, + * SPI_MEM_S_FMEM_PMS1_ADDR_S + SPI_MEM_S_FMEM_PMS1_SIZE) */ -#define SPI_FMEM_PMS1_SIZE 0x00007FFFU -#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x00007FFFU -#define SPI_FMEM_PMS1_SIZE_S 0 +#define SPI_MEM_S_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS1_SIZE_M (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S) +#define SPI_MEM_S_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS1_SIZE_S 0 -/** SPI_FMEM_PMS2_SIZE_REG register +/** SPI_MEM_S_FMEM_PMS2_SIZE_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, - * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) +#define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128) +/** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_MEM_S_FMEM_PMS2_ADDR_S, + * SPI_MEM_S_FMEM_PMS2_ADDR_S + SPI_MEM_S_FMEM_PMS2_SIZE) */ -#define SPI_FMEM_PMS2_SIZE 0x00007FFFU -#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x00007FFFU -#define SPI_FMEM_PMS2_SIZE_S 0 +#define SPI_MEM_S_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS2_SIZE_M (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S) +#define SPI_MEM_S_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS2_SIZE_S 0 -/** SPI_FMEM_PMS3_SIZE_REG register +/** SPI_MEM_S_FMEM_PMS3_SIZE_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, - * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) +#define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c) +/** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_MEM_S_FMEM_PMS3_ADDR_S, + * SPI_MEM_S_FMEM_PMS3_ADDR_S + SPI_MEM_S_FMEM_PMS3_SIZE) */ -#define SPI_FMEM_PMS3_SIZE 0x00007FFFU -#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x00007FFFU -#define SPI_FMEM_PMS3_SIZE_S 0 +#define SPI_MEM_S_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS3_SIZE_M (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S) +#define SPI_MEM_S_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS3_SIZE_S 0 -/** SPI_SMEM_PMS0_ATTR_REG register +/** SPI_MEM_S_SMEM_PMS0_ATTR_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130) -/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130) +/** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) -#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_RD_ATTR_S 0 -/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) -#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_WR_ATTR_S 1 -/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and - * SPI_SMEM_PMS0_SIZE_REG. + * external RAM PMS section 0 is configured by registers SPI_MEM_S_SMEM_PMS0_ADDR_REG and + * SPI_MEM_S_SMEM_PMS0_SIZE_REG. */ -#define SPI_SMEM_PMS0_ECC (BIT(2)) -#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) -#define SPI_SMEM_PMS0_ECC_V 0x00000001U -#define SPI_SMEM_PMS0_ECC_S 2 +#define SPI_MEM_S_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS0_ECC_M (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S) +#define SPI_MEM_S_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_ECC_S 2 -/** SPI_SMEM_PMS1_ATTR_REG register +/** SPI_MEM_S_SMEM_PMS1_ATTR_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134) -/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134) +/** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) -#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_RD_ATTR_S 0 -/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) -#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_WR_ATTR_S 1 -/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and - * SPI_SMEM_PMS1_SIZE_REG. + * external RAM PMS section 1 is configured by registers SPI_MEM_S_SMEM_PMS1_ADDR_REG and + * SPI_MEM_S_SMEM_PMS1_SIZE_REG. */ -#define SPI_SMEM_PMS1_ECC (BIT(2)) -#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) -#define SPI_SMEM_PMS1_ECC_V 0x00000001U -#define SPI_SMEM_PMS1_ECC_S 2 +#define SPI_MEM_S_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS1_ECC_M (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S) +#define SPI_MEM_S_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_ECC_S 2 -/** SPI_SMEM_PMS2_ATTR_REG register +/** SPI_MEM_S_SMEM_PMS2_ATTR_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138) -/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138) +/** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) -#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_RD_ATTR_S 0 -/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) -#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_WR_ATTR_S 1 -/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and - * SPI_SMEM_PMS2_SIZE_REG. + * external RAM PMS section 2 is configured by registers SPI_MEM_S_SMEM_PMS2_ADDR_REG and + * SPI_MEM_S_SMEM_PMS2_SIZE_REG. */ -#define SPI_SMEM_PMS2_ECC (BIT(2)) -#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) -#define SPI_SMEM_PMS2_ECC_V 0x00000001U -#define SPI_SMEM_PMS2_ECC_S 2 +#define SPI_MEM_S_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS2_ECC_M (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S) +#define SPI_MEM_S_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_ECC_S 2 -/** SPI_SMEM_PMS3_ATTR_REG register +/** SPI_MEM_S_SMEM_PMS3_ATTR_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c) -/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c) +/** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) -#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_RD_ATTR_S 0 -/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. */ -#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) -#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_WR_ATTR_S 1 -/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and - * SPI_SMEM_PMS3_SIZE_REG. + * external RAM PMS section 3 is configured by registers SPI_MEM_S_SMEM_PMS3_ADDR_REG and + * SPI_MEM_S_SMEM_PMS3_SIZE_REG. */ -#define SPI_SMEM_PMS3_ECC (BIT(2)) -#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) -#define SPI_SMEM_PMS3_ECC_V 0x00000001U -#define SPI_SMEM_PMS3_ECC_S 2 +#define SPI_MEM_S_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS3_ECC_M (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S) +#define SPI_MEM_S_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_ECC_S 2 -/** SPI_SMEM_PMS0_ADDR_REG register +/** SPI_MEM_S_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140) +/** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 external RAM PMS section 0 start address value */ -#define SPI_SMEM_PMS0_ADDR_S 0x07FFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_S 0 +#define SPI_MEM_S_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_M (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_S 0 -/** SPI_SMEM_PMS1_ADDR_REG register +/** SPI_MEM_S_SMEM_PMS1_ADDR_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144) +/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 external RAM PMS section 1 start address value */ -#define SPI_SMEM_PMS1_ADDR_S 0x07FFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_S 0 +#define SPI_MEM_S_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_M (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_S 0 -/** SPI_SMEM_PMS2_ADDR_REG register +/** SPI_MEM_S_SMEM_PMS2_ADDR_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148) +/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 external RAM PMS section 2 start address value */ -#define SPI_SMEM_PMS2_ADDR_S 0x07FFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_S 0 +#define SPI_MEM_S_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_M (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_S 0 -/** SPI_SMEM_PMS3_ADDR_REG register +/** SPI_MEM_S_SMEM_PMS3_ADDR_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c) +/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; * SPI1 external RAM PMS section 3 start address value */ -#define SPI_SMEM_PMS3_ADDR_S 0x07FFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_S 0 +#define SPI_MEM_S_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_M (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_S 0 -/** SPI_SMEM_PMS0_SIZE_REG register +/** SPI_MEM_S_SMEM_PMS0_SIZE_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, - * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) +#define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150) +/** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_MEM_S_SMEM_PMS0_ADDR_S, + * SPI_MEM_S_SMEM_PMS0_ADDR_S + SPI_MEM_S_SMEM_PMS0_SIZE) */ -#define SPI_SMEM_PMS0_SIZE 0x00007FFFU -#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x00007FFFU -#define SPI_SMEM_PMS0_SIZE_S 0 +#define SPI_MEM_S_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS0_SIZE_M (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S) +#define SPI_MEM_S_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS0_SIZE_S 0 -/** SPI_SMEM_PMS1_SIZE_REG register +/** SPI_MEM_S_SMEM_PMS1_SIZE_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, - * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) +#define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154) +/** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_MEM_S_SMEM_PMS1_ADDR_S, + * SPI_MEM_S_SMEM_PMS1_ADDR_S + SPI_MEM_S_SMEM_PMS1_SIZE) */ -#define SPI_SMEM_PMS1_SIZE 0x00007FFFU -#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x00007FFFU -#define SPI_SMEM_PMS1_SIZE_S 0 +#define SPI_MEM_S_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS1_SIZE_M (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S) +#define SPI_MEM_S_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS1_SIZE_S 0 -/** SPI_SMEM_PMS2_SIZE_REG register +/** SPI_MEM_S_SMEM_PMS2_SIZE_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, - * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) +#define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158) +/** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_MEM_S_SMEM_PMS2_ADDR_S, + * SPI_MEM_S_SMEM_PMS2_ADDR_S + SPI_MEM_S_SMEM_PMS2_SIZE) */ -#define SPI_SMEM_PMS2_SIZE 0x00007FFFU -#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x00007FFFU -#define SPI_SMEM_PMS2_SIZE_S 0 +#define SPI_MEM_S_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS2_SIZE_M (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S) +#define SPI_MEM_S_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS2_SIZE_S 0 -/** SPI_SMEM_PMS3_SIZE_REG register +/** SPI_MEM_S_SMEM_PMS3_SIZE_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, - * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) +#define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c) +/** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_MEM_S_SMEM_PMS3_ADDR_S, + * SPI_MEM_S_SMEM_PMS3_ADDR_S + SPI_MEM_S_SMEM_PMS3_SIZE) */ -#define SPI_SMEM_PMS3_SIZE 0x00007FFFU -#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x00007FFFU -#define SPI_SMEM_PMS3_SIZE_S 0 +#define SPI_MEM_S_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS3_SIZE_M (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S) +#define SPI_MEM_S_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS3_SIZE_S 0 -/** SPI_MEM_PMS_REJECT_REG register +/** SPI_MEM_S_PMS_REJECT_REG register * SPI1 access reject register */ -#define SPI_MEM_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164) +/** SPI_MEM_S_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ -#define SPI_MEM_REJECT_ADDR 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_S 0 -/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; +#define SPI_MEM_S_REJECT_ADDR 0x07FFFFFFU +#define SPI_MEM_S_REJECT_ADDR_M (SPI_MEM_S_REJECT_ADDR_V << SPI_MEM_S_REJECT_ADDR_S) +#define SPI_MEM_S_REJECT_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_REJECT_ADDR_S 0 +/** SPI_MEM_S_PM_EN : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ -#define SPI_MEM_PM_EN (BIT(27)) -#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) -#define SPI_MEM_PM_EN_V 0x00000001U -#define SPI_MEM_PM_EN_S 27 -/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; +#define SPI_MEM_S_PM_EN (BIT(27)) +#define SPI_MEM_S_PM_EN_M (SPI_MEM_S_PM_EN_V << SPI_MEM_S_PM_EN_S) +#define SPI_MEM_S_PM_EN_V 0x00000001U +#define SPI_MEM_S_PM_EN_S 27 +/** SPI_MEM_S_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ -#define SPI_MEM_PMS_LD (BIT(28)) -#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) -#define SPI_MEM_PMS_LD_V 0x00000001U -#define SPI_MEM_PMS_LD_S 28 -/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; +#define SPI_MEM_S_PMS_LD (BIT(28)) +#define SPI_MEM_S_PMS_LD_M (SPI_MEM_S_PMS_LD_V << SPI_MEM_S_PMS_LD_S) +#define SPI_MEM_S_PMS_LD_V 0x00000001U +#define SPI_MEM_S_PMS_LD_S 28 +/** SPI_MEM_S_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ -#define SPI_MEM_PMS_ST (BIT(29)) -#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) -#define SPI_MEM_PMS_ST_V 0x00000001U -#define SPI_MEM_PMS_ST_S 29 -/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; +#define SPI_MEM_S_PMS_ST (BIT(29)) +#define SPI_MEM_S_PMS_ST_M (SPI_MEM_S_PMS_ST_V << SPI_MEM_S_PMS_ST_S) +#define SPI_MEM_S_PMS_ST_V 0x00000001U +#define SPI_MEM_S_PMS_ST_S 29 +/** SPI_MEM_S_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ -#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) -#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U -#define SPI_MEM_PMS_MULTI_HIT_S 30 -/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; +#define SPI_MEM_S_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_S_PMS_MULTI_HIT_M (SPI_MEM_S_PMS_MULTI_HIT_V << SPI_MEM_S_PMS_MULTI_HIT_S) +#define SPI_MEM_S_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_S_PMS_MULTI_HIT_S 30 +/** SPI_MEM_S_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ -#define SPI_MEM_PMS_IVD (BIT(31)) -#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) -#define SPI_MEM_PMS_IVD_V 0x00000001U -#define SPI_MEM_PMS_IVD_S 31 +#define SPI_MEM_S_PMS_IVD (BIT(31)) +#define SPI_MEM_S_PMS_IVD_M (SPI_MEM_S_PMS_IVD_V << SPI_MEM_S_PMS_IVD_S) +#define SPI_MEM_S_PMS_IVD_V 0x00000001U +#define SPI_MEM_S_PMS_IVD_S 31 -/** SPI_MEM_ECC_CTRL_REG register +/** SPI_MEM_S_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_MEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168) -/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; +#define SPI_MEM_S_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168) +/** SPI_MEM_S_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. */ -#define SPI_MEM_ECC_ERR_CNT 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) -#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. +#define SPI_MEM_S_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_S_ECC_ERR_CNT_M (SPI_MEM_S_ECC_ERR_CNT_V << SPI_MEM_S_ECC_ERR_CNT_S) +#define SPI_MEM_S_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_S_ECC_ERR_CNT_S 5 +/** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. */ -#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) -#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_MEM_S_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. */ -#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) -#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_FMEM_ECC_ERR_INT_EN_S 17 -/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_M (SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_MEM_S_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: * 1024 bytes. 3: 2048 bytes. */ -#define SPI_FMEM_PAGE_SIZE 0x00000003U -#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) -#define SPI_FMEM_PAGE_SIZE_V 0x00000003U -#define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; +#define SPI_MEM_S_FMEM_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_FMEM_PAGE_SIZE_M (SPI_MEM_S_FMEM_PAGE_SIZE_V << SPI_MEM_S_FMEM_PAGE_SIZE_S) +#define SPI_MEM_S_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_FMEM_PAGE_SIZE_S 18 +/** SPI_MEM_S_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit * should be 0. Otherwise, this bit should be 1. */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) -#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 20 -/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; +#define SPI_MEM_S_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_M (SPI_MEM_S_FMEM_ECC_ADDR_EN_V << SPI_MEM_S_FMEM_ECC_ADDR_EN_S) +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_S 20 +/** SPI_MEM_S_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) -#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) -#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 21 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. +#define SPI_MEM_S_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_S_USR_ECC_ADDR_EN_M (SPI_MEM_S_USR_ECC_ADDR_EN_V << SPI_MEM_S_USR_ECC_ADDR_EN_S) +#define SPI_MEM_S_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_USR_ECC_ADDR_EN_S 21 +/** SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and + * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. */ -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_S_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ -#define SPI_MEM_ECC_ERR_BITS 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) -#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_S 25 +#define SPI_MEM_S_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_S_ECC_ERR_BITS_M (SPI_MEM_S_ECC_ERR_BITS_V << SPI_MEM_S_ECC_ERR_BITS_S) +#define SPI_MEM_S_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_S_ECC_ERR_BITS_S 25 -/** SPI_MEM_ECC_ERR_ADDR_REG register +/** SPI_MEM_S_ECC_ERR_ADDR_REG register * MSPI ECC error address register */ -#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c) +/** SPI_MEM_S_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. */ -#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x07FFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_S 0 +#define SPI_MEM_S_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_S_ECC_ERR_ADDR_M (SPI_MEM_S_ECC_ERR_ADDR_V << SPI_MEM_S_ECC_ERR_ADDR_S) +#define SPI_MEM_S_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_ECC_ERR_ADDR_S 0 -/** SPI_MEM_AXI_ERR_ADDR_REG register +/** SPI_MEM_S_AXI_ERR_ADDR_REG register * SPI0 AXI request error address. */ -#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; +#define SPI_MEM_S_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170) +/** SPI_MEM_S_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set. */ -#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x07FFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_S 0 +#define SPI_MEM_S_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_S_AXI_ERR_ADDR_M (SPI_MEM_S_AXI_ERR_ADDR_V << SPI_MEM_S_AXI_ERR_ADDR_S) +#define SPI_MEM_S_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_AXI_ERR_ADDR_S 0 -/** SPI_SMEM_ECC_CTRL_REG register +/** SPI_MEM_S_SMEM_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; +#define SPI_MEM_S_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174) +/** SPI_MEM_S_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. */ -#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) -#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_M (SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S) +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_MEM_S_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. * 2: 1024 bytes. 3: 2048 bytes. */ -#define SPI_SMEM_PAGE_SIZE 0x00000003U -#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) -#define SPI_SMEM_PAGE_SIZE_V 0x00000003U -#define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; +#define SPI_MEM_S_SMEM_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_SMEM_PAGE_SIZE_M (SPI_MEM_S_SMEM_PAGE_SIZE_V << SPI_MEM_S_SMEM_PAGE_SIZE_S) +#define SPI_MEM_S_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_SMEM_PAGE_SIZE_S 18 +/** SPI_MEM_S_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of external RAM. If there is no ECC region in external * RAM, this bit should be 0. Otherwise, this bit should be 1. */ -#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) -#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_SMEM_ECC_ADDR_EN_S 20 +#define SPI_MEM_S_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_M (SPI_MEM_S_SMEM_ECC_ADDR_EN_V << SPI_MEM_S_SMEM_ECC_ADDR_EN_S) +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_S 20 -/** SPI_SMEM_AXI_ADDR_CTRL_REG register +/** SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG register * SPI0 AXI address control register */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178) -/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; +#define SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178) +/** SPI_MEM_S_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers * and SPI0 transfers are done. 0: Others. */ -#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) -#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U -#define SPI_MEM_ALL_FIFO_EMPTY_S 26 -/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; +#define SPI_MEM_S_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_S_ALL_FIFO_EMPTY_M (SPI_MEM_S_ALL_FIFO_EMPTY_V << SPI_MEM_S_ALL_FIFO_EMPTY_S) +#define SPI_MEM_S_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_S_ALL_FIFO_EMPTY_S 26 +/** SPI_MEM_S_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. */ -#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) -#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) -#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_RDATA_AFIFO_REMPTY_S 27 -/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; +#define SPI_MEM_S_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_M (SPI_MEM_S_RDATA_AFIFO_REMPTY_V << SPI_MEM_S_RDATA_AFIFO_REMPTY_S) +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_S 27 +/** SPI_MEM_S_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. */ -#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) -#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) -#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U -#define SPI_RADDR_AFIFO_REMPTY_S 28 -/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; +#define SPI_MEM_S_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_M (SPI_MEM_S_RADDR_AFIFO_REMPTY_V << SPI_MEM_S_RADDR_AFIFO_REMPTY_S) +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_S 28 +/** SPI_MEM_S_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. */ -#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) -#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) -#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_WDATA_AFIFO_REMPTY_S 29 -/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; +#define SPI_MEM_S_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_M (SPI_MEM_S_WDATA_AFIFO_REMPTY_V << SPI_MEM_S_WDATA_AFIFO_REMPTY_S) +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_S 29 +/** SPI_MEM_S_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. */ -#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) -#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) -#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U -#define SPI_WBLEN_AFIFO_REMPTY_S 30 -/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_M (SPI_MEM_S_WBLEN_AFIFO_REMPTY_V << SPI_MEM_S_WBLEN_AFIFO_REMPTY_S) +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and * RDATA_AFIFO are empty and spi0_mst_st is IDLE. */ -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 -/** SPI_MEM_AXI_ERR_RESP_EN_REG register +/** SPI_MEM_S_AXI_ERR_RESP_EN_REG register * SPI0 AXI error response enable register */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c) +/** SPI_MEM_S_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_M (SPI_MEM_S_AW_RESP_EN_MMU_VLD_V << SPI_MEM_S_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_S_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) -#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) -#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_M (SPI_MEM_S_AW_RESP_EN_MMU_GID_V << SPI_MEM_S_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_S_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_S_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_S_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_M (SPI_MEM_S_AW_RESP_EN_MMU_ECC_V << SPI_MEM_S_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_S_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ -#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_M (SPI_MEM_S_AW_RESP_EN_MMU_SENS_V << SPI_MEM_S_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_S_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 -/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_S_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi read trans. */ -#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 -/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_M (SPI_MEM_S_AR_RESP_EN_MMU_VLD_V << SPI_MEM_S_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_S_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi read trans. */ -#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) -#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) -#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 -/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; +#define SPI_MEM_S_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_M (SPI_MEM_S_AR_RESP_EN_MMU_GID_V << SPI_MEM_S_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_S_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi read trans. */ -#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 -/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_M (SPI_MEM_S_AR_RESP_EN_MMU_ECC_V << SPI_MEM_S_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_S_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; * Set this bit to enable AXI response function for mmu sensitive err in axi read * trans. */ -#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 -/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_M (SPI_MEM_S_AR_RESP_EN_MMU_SENS_V << SPI_MEM_S_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_S_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; * Set this bit to enable AXI response function for axi size err in axi read trans. */ -#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S 11 -/** SPI_MEM_TIMING_CALI_REG register +/** SPI_MEM_S_TIMING_CALI_REG register * SPI0 flash timing calibration register */ -#define SPI_MEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180) -/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180) +/** SPI_MEM_S_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * The bit is used to enable timing adjust clock for all reading operations. */ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) -#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_MEM_TIMING_CLK_ENA_S 0 -/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_S_TIMING_CLK_ENA_M (SPI_MEM_S_TIMING_CLK_ENA_V << SPI_MEM_S_TIMING_CLK_ENA_S) +#define SPI_MEM_S_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_S_TIMING_CLK_ENA_S 0 +/** SPI_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0; * The bit is used to enable timing auto-calibration for all reading operations. */ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) -#define SPI_MEM_TIMING_CALI_V 0x00000001U -#define SPI_MEM_TIMING_CALI_S 1 -/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; +#define SPI_MEM_S_TIMING_CALI (BIT(1)) +#define SPI_MEM_S_TIMING_CALI_M (SPI_MEM_S_TIMING_CALI_V << SPI_MEM_S_TIMING_CALI_S) +#define SPI_MEM_S_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_TIMING_CALI_S 1 +/** SPI_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; * add extra dummy spi clock cycle length for spi clock calibration. */ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_S_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ -#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) -#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_MEM_DLL_TIMING_CALI_S 5 -/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; +#define SPI_MEM_S_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_S_DLL_TIMING_CALI_M (SPI_MEM_S_DLL_TIMING_CALI_V << SPI_MEM_S_DLL_TIMING_CALI_S) +#define SPI_MEM_S_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_DLL_TIMING_CALI_S 5 +/** SPI_MEM_S_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; * Set this bit to update delay mode, delay num and extra dummy in MSPI. */ -#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) -#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U -#define SPI_MEM_TIMING_CALI_UPDATE_S 6 +#define SPI_MEM_S_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_S_TIMING_CALI_UPDATE_M (SPI_MEM_S_TIMING_CALI_UPDATE_V << SPI_MEM_S_TIMING_CALI_UPDATE_S) +#define SPI_MEM_S_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_S_TIMING_CALI_UPDATE_S 6 -/** SPI_MEM_DIN_MODE_REG register +/** SPI_MEM_S_DIN_MODE_REG register * MSPI flash input timing delay mode control register */ -#define SPI_MEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184) -/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; +#define SPI_MEM_S_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184) +/** SPI_MEM_S_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_MEM_DIN0_MODE 0x00000007U -#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) -#define SPI_MEM_DIN0_MODE_V 0x00000007U -#define SPI_MEM_DIN0_MODE_S 0 -/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; +#define SPI_MEM_S_DIN0_MODE 0x00000007U +#define SPI_MEM_S_DIN0_MODE_M (SPI_MEM_S_DIN0_MODE_V << SPI_MEM_S_DIN0_MODE_S) +#define SPI_MEM_S_DIN0_MODE_V 0x00000007U +#define SPI_MEM_S_DIN0_MODE_S 0 +/** SPI_MEM_S_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_MEM_DIN1_MODE 0x00000007U -#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) -#define SPI_MEM_DIN1_MODE_V 0x00000007U -#define SPI_MEM_DIN1_MODE_S 3 -/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; +#define SPI_MEM_S_DIN1_MODE 0x00000007U +#define SPI_MEM_S_DIN1_MODE_M (SPI_MEM_S_DIN1_MODE_V << SPI_MEM_S_DIN1_MODE_S) +#define SPI_MEM_S_DIN1_MODE_V 0x00000007U +#define SPI_MEM_S_DIN1_MODE_S 3 +/** SPI_MEM_S_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_MEM_DIN2_MODE 0x00000007U -#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) -#define SPI_MEM_DIN2_MODE_V 0x00000007U -#define SPI_MEM_DIN2_MODE_S 6 -/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; +#define SPI_MEM_S_DIN2_MODE 0x00000007U +#define SPI_MEM_S_DIN2_MODE_M (SPI_MEM_S_DIN2_MODE_V << SPI_MEM_S_DIN2_MODE_S) +#define SPI_MEM_S_DIN2_MODE_V 0x00000007U +#define SPI_MEM_S_DIN2_MODE_S 6 +/** SPI_MEM_S_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_MEM_DIN3_MODE 0x00000007U -#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) -#define SPI_MEM_DIN3_MODE_V 0x00000007U -#define SPI_MEM_DIN3_MODE_S 9 -/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; +#define SPI_MEM_S_DIN3_MODE 0x00000007U +#define SPI_MEM_S_DIN3_MODE_M (SPI_MEM_S_DIN3_MODE_V << SPI_MEM_S_DIN3_MODE_S) +#define SPI_MEM_S_DIN3_MODE_V 0x00000007U +#define SPI_MEM_S_DIN3_MODE_S 9 +/** SPI_MEM_S_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ -#define SPI_MEM_DIN4_MODE 0x00000007U -#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) -#define SPI_MEM_DIN4_MODE_V 0x00000007U -#define SPI_MEM_DIN4_MODE_S 12 -/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; +#define SPI_MEM_S_DIN4_MODE 0x00000007U +#define SPI_MEM_S_DIN4_MODE_M (SPI_MEM_S_DIN4_MODE_V << SPI_MEM_S_DIN4_MODE_S) +#define SPI_MEM_S_DIN4_MODE_V 0x00000007U +#define SPI_MEM_S_DIN4_MODE_S 12 +/** SPI_MEM_S_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ -#define SPI_MEM_DIN5_MODE 0x00000007U -#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) -#define SPI_MEM_DIN5_MODE_V 0x00000007U -#define SPI_MEM_DIN5_MODE_S 15 -/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; +#define SPI_MEM_S_DIN5_MODE 0x00000007U +#define SPI_MEM_S_DIN5_MODE_M (SPI_MEM_S_DIN5_MODE_V << SPI_MEM_S_DIN5_MODE_S) +#define SPI_MEM_S_DIN5_MODE_V 0x00000007U +#define SPI_MEM_S_DIN5_MODE_S 15 +/** SPI_MEM_S_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ -#define SPI_MEM_DIN6_MODE 0x00000007U -#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) -#define SPI_MEM_DIN6_MODE_V 0x00000007U -#define SPI_MEM_DIN6_MODE_S 18 -/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; +#define SPI_MEM_S_DIN6_MODE 0x00000007U +#define SPI_MEM_S_DIN6_MODE_M (SPI_MEM_S_DIN6_MODE_V << SPI_MEM_S_DIN6_MODE_S) +#define SPI_MEM_S_DIN6_MODE_V 0x00000007U +#define SPI_MEM_S_DIN6_MODE_S 18 +/** SPI_MEM_S_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ -#define SPI_MEM_DIN7_MODE 0x00000007U -#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) -#define SPI_MEM_DIN7_MODE_V 0x00000007U -#define SPI_MEM_DIN7_MODE_S 21 -/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; +#define SPI_MEM_S_DIN7_MODE 0x00000007U +#define SPI_MEM_S_DIN7_MODE_M (SPI_MEM_S_DIN7_MODE_V << SPI_MEM_S_DIN7_MODE_S) +#define SPI_MEM_S_DIN7_MODE_V 0x00000007U +#define SPI_MEM_S_DIN7_MODE_S 21 +/** SPI_MEM_S_DINS_MODE : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ -#define SPI_MEM_DINS_MODE 0x00000007U -#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) -#define SPI_MEM_DINS_MODE_V 0x00000007U -#define SPI_MEM_DINS_MODE_S 24 +#define SPI_MEM_S_DINS_MODE 0x00000007U +#define SPI_MEM_S_DINS_MODE_M (SPI_MEM_S_DINS_MODE_V << SPI_MEM_S_DINS_MODE_S) +#define SPI_MEM_S_DINS_MODE_V 0x00000007U +#define SPI_MEM_S_DINS_MODE_S 24 -/** SPI_MEM_DIN_NUM_REG register +/** SPI_MEM_S_DIN_NUM_REG register * MSPI flash input timing delay number control register */ -#define SPI_MEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188) -/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188) +/** SPI_MEM_S_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN0_NUM 0x00000003U -#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) -#define SPI_MEM_DIN0_NUM_V 0x00000003U -#define SPI_MEM_DIN0_NUM_S 0 -/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; +#define SPI_MEM_S_DIN0_NUM 0x00000003U +#define SPI_MEM_S_DIN0_NUM_M (SPI_MEM_S_DIN0_NUM_V << SPI_MEM_S_DIN0_NUM_S) +#define SPI_MEM_S_DIN0_NUM_V 0x00000003U +#define SPI_MEM_S_DIN0_NUM_S 0 +/** SPI_MEM_S_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN1_NUM 0x00000003U -#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) -#define SPI_MEM_DIN1_NUM_V 0x00000003U -#define SPI_MEM_DIN1_NUM_S 2 -/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; +#define SPI_MEM_S_DIN1_NUM 0x00000003U +#define SPI_MEM_S_DIN1_NUM_M (SPI_MEM_S_DIN1_NUM_V << SPI_MEM_S_DIN1_NUM_S) +#define SPI_MEM_S_DIN1_NUM_V 0x00000003U +#define SPI_MEM_S_DIN1_NUM_S 2 +/** SPI_MEM_S_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN2_NUM 0x00000003U -#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) -#define SPI_MEM_DIN2_NUM_V 0x00000003U -#define SPI_MEM_DIN2_NUM_S 4 -/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; +#define SPI_MEM_S_DIN2_NUM 0x00000003U +#define SPI_MEM_S_DIN2_NUM_M (SPI_MEM_S_DIN2_NUM_V << SPI_MEM_S_DIN2_NUM_S) +#define SPI_MEM_S_DIN2_NUM_V 0x00000003U +#define SPI_MEM_S_DIN2_NUM_S 4 +/** SPI_MEM_S_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN3_NUM 0x00000003U -#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) -#define SPI_MEM_DIN3_NUM_V 0x00000003U -#define SPI_MEM_DIN3_NUM_S 6 -/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; +#define SPI_MEM_S_DIN3_NUM 0x00000003U +#define SPI_MEM_S_DIN3_NUM_M (SPI_MEM_S_DIN3_NUM_V << SPI_MEM_S_DIN3_NUM_S) +#define SPI_MEM_S_DIN3_NUM_V 0x00000003U +#define SPI_MEM_S_DIN3_NUM_S 6 +/** SPI_MEM_S_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN4_NUM 0x00000003U -#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) -#define SPI_MEM_DIN4_NUM_V 0x00000003U -#define SPI_MEM_DIN4_NUM_S 8 -/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; +#define SPI_MEM_S_DIN4_NUM 0x00000003U +#define SPI_MEM_S_DIN4_NUM_M (SPI_MEM_S_DIN4_NUM_V << SPI_MEM_S_DIN4_NUM_S) +#define SPI_MEM_S_DIN4_NUM_V 0x00000003U +#define SPI_MEM_S_DIN4_NUM_S 8 +/** SPI_MEM_S_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN5_NUM 0x00000003U -#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) -#define SPI_MEM_DIN5_NUM_V 0x00000003U -#define SPI_MEM_DIN5_NUM_S 10 -/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; +#define SPI_MEM_S_DIN5_NUM 0x00000003U +#define SPI_MEM_S_DIN5_NUM_M (SPI_MEM_S_DIN5_NUM_V << SPI_MEM_S_DIN5_NUM_S) +#define SPI_MEM_S_DIN5_NUM_V 0x00000003U +#define SPI_MEM_S_DIN5_NUM_S 10 +/** SPI_MEM_S_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN6_NUM 0x00000003U -#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) -#define SPI_MEM_DIN6_NUM_V 0x00000003U -#define SPI_MEM_DIN6_NUM_S 12 -/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; +#define SPI_MEM_S_DIN6_NUM 0x00000003U +#define SPI_MEM_S_DIN6_NUM_M (SPI_MEM_S_DIN6_NUM_V << SPI_MEM_S_DIN6_NUM_S) +#define SPI_MEM_S_DIN6_NUM_V 0x00000003U +#define SPI_MEM_S_DIN6_NUM_S 12 +/** SPI_MEM_S_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DIN7_NUM 0x00000003U -#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) -#define SPI_MEM_DIN7_NUM_V 0x00000003U -#define SPI_MEM_DIN7_NUM_S 14 -/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; +#define SPI_MEM_S_DIN7_NUM 0x00000003U +#define SPI_MEM_S_DIN7_NUM_M (SPI_MEM_S_DIN7_NUM_V << SPI_MEM_S_DIN7_NUM_S) +#define SPI_MEM_S_DIN7_NUM_V 0x00000003U +#define SPI_MEM_S_DIN7_NUM_S 14 +/** SPI_MEM_S_DINS_NUM : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_MEM_DINS_NUM 0x00000003U -#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) -#define SPI_MEM_DINS_NUM_V 0x00000003U -#define SPI_MEM_DINS_NUM_S 16 +#define SPI_MEM_S_DINS_NUM 0x00000003U +#define SPI_MEM_S_DINS_NUM_M (SPI_MEM_S_DINS_NUM_V << SPI_MEM_S_DINS_NUM_S) +#define SPI_MEM_S_DINS_NUM_V 0x00000003U +#define SPI_MEM_S_DINS_NUM_S 16 -/** SPI_MEM_DOUT_MODE_REG register +/** SPI_MEM_S_DOUT_MODE_REG register * MSPI flash output timing adjustment control register */ -#define SPI_MEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c) -/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c) +/** SPI_MEM_S_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) -#define SPI_MEM_DOUT0_MODE_V 0x00000001U -#define SPI_MEM_DOUT0_MODE_S 0 -/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_DOUT0_MODE (BIT(0)) +#define SPI_MEM_S_DOUT0_MODE_M (SPI_MEM_S_DOUT0_MODE_V << SPI_MEM_S_DOUT0_MODE_S) +#define SPI_MEM_S_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT0_MODE_S 0 +/** SPI_MEM_S_DOUT1_MODE : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) -#define SPI_MEM_DOUT1_MODE_V 0x00000001U -#define SPI_MEM_DOUT1_MODE_S 1 -/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_DOUT1_MODE (BIT(1)) +#define SPI_MEM_S_DOUT1_MODE_M (SPI_MEM_S_DOUT1_MODE_V << SPI_MEM_S_DOUT1_MODE_S) +#define SPI_MEM_S_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT1_MODE_S 1 +/** SPI_MEM_S_DOUT2_MODE : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) -#define SPI_MEM_DOUT2_MODE_V 0x00000001U -#define SPI_MEM_DOUT2_MODE_S 2 -/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_DOUT2_MODE (BIT(2)) +#define SPI_MEM_S_DOUT2_MODE_M (SPI_MEM_S_DOUT2_MODE_V << SPI_MEM_S_DOUT2_MODE_S) +#define SPI_MEM_S_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT2_MODE_S 2 +/** SPI_MEM_S_DOUT3_MODE : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) -#define SPI_MEM_DOUT3_MODE_V 0x00000001U -#define SPI_MEM_DOUT3_MODE_S 3 -/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_DOUT3_MODE (BIT(3)) +#define SPI_MEM_S_DOUT3_MODE_M (SPI_MEM_S_DOUT3_MODE_V << SPI_MEM_S_DOUT3_MODE_S) +#define SPI_MEM_S_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT3_MODE_S 3 +/** SPI_MEM_S_DOUT4_MODE : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) -#define SPI_MEM_DOUT4_MODE_V 0x00000001U -#define SPI_MEM_DOUT4_MODE_S 4 -/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_DOUT4_MODE (BIT(4)) +#define SPI_MEM_S_DOUT4_MODE_M (SPI_MEM_S_DOUT4_MODE_V << SPI_MEM_S_DOUT4_MODE_S) +#define SPI_MEM_S_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT4_MODE_S 4 +/** SPI_MEM_S_DOUT5_MODE : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) -#define SPI_MEM_DOUT5_MODE_V 0x00000001U -#define SPI_MEM_DOUT5_MODE_S 5 -/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_DOUT5_MODE (BIT(5)) +#define SPI_MEM_S_DOUT5_MODE_M (SPI_MEM_S_DOUT5_MODE_V << SPI_MEM_S_DOUT5_MODE_S) +#define SPI_MEM_S_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT5_MODE_S 5 +/** SPI_MEM_S_DOUT6_MODE : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) -#define SPI_MEM_DOUT6_MODE_V 0x00000001U -#define SPI_MEM_DOUT6_MODE_S 6 -/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_DOUT6_MODE (BIT(6)) +#define SPI_MEM_S_DOUT6_MODE_M (SPI_MEM_S_DOUT6_MODE_V << SPI_MEM_S_DOUT6_MODE_S) +#define SPI_MEM_S_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT6_MODE_S 6 +/** SPI_MEM_S_DOUT7_MODE : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) -#define SPI_MEM_DOUT7_MODE_V 0x00000001U -#define SPI_MEM_DOUT7_MODE_S 7 -/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_DOUT7_MODE (BIT(7)) +#define SPI_MEM_S_DOUT7_MODE_M (SPI_MEM_S_DOUT7_MODE_V << SPI_MEM_S_DOUT7_MODE_S) +#define SPI_MEM_S_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT7_MODE_S 7 +/** SPI_MEM_S_DOUTS_MODE : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) -#define SPI_MEM_DOUTS_MODE_V 0x00000001U -#define SPI_MEM_DOUTS_MODE_S 8 +#define SPI_MEM_S_DOUTS_MODE (BIT(8)) +#define SPI_MEM_S_DOUTS_MODE_M (SPI_MEM_S_DOUTS_MODE_V << SPI_MEM_S_DOUTS_MODE_S) +#define SPI_MEM_S_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_S_DOUTS_MODE_S 8 -/** SPI_SMEM_TIMING_CALI_REG register +/** SPI_MEM_S_SMEM_TIMING_CALI_REG register * MSPI external RAM timing calibration register */ -#define SPI_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; +#define SPI_MEM_S_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190) +/** SPI_MEM_S_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ -#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) -#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_M (SPI_MEM_S_SMEM_TIMING_CLK_ENA_V << SPI_MEM_S_SMEM_TIMING_CLK_ENA_S) +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_S_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; * For sram, the bit is used to enable timing auto-calibration for all reading * operations. */ -#define SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) -#define SPI_SMEM_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; +#define SPI_MEM_S_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_S_SMEM_TIMING_CALI_M (SPI_MEM_S_SMEM_TIMING_CALI_V << SPI_MEM_S_SMEM_TIMING_CALI_S) +#define SPI_MEM_S_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_SMEM_TIMING_CALI_S 1 +/** SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; * For sram, add extra dummy spi clock cycle length for spi clock calibration. */ -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_S_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * EXT_RAM. */ -#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) -#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_DLL_TIMING_CALI_S 5 +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_M (SPI_MEM_S_SMEM_DLL_TIMING_CALI_V << SPI_MEM_S_SMEM_DLL_TIMING_CALI_S) +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DIN_MODE_REG register +/** SPI_MEM_S_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register */ -#define SPI_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194) -/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; +#define SPI_MEM_S_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194) +/** SPI_MEM_S_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN0_MODE 0x00000007U -#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) -#define SPI_SMEM_DIN0_MODE_V 0x00000007U -#define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; +#define SPI_MEM_S_SMEM_DIN0_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN0_MODE_M (SPI_MEM_S_SMEM_DIN0_MODE_V << SPI_MEM_S_SMEM_DIN0_MODE_S) +#define SPI_MEM_S_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN0_MODE_S 0 +/** SPI_MEM_S_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN1_MODE 0x00000007U -#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) -#define SPI_SMEM_DIN1_MODE_V 0x00000007U -#define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; +#define SPI_MEM_S_SMEM_DIN1_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN1_MODE_M (SPI_MEM_S_SMEM_DIN1_MODE_V << SPI_MEM_S_SMEM_DIN1_MODE_S) +#define SPI_MEM_S_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN1_MODE_S 3 +/** SPI_MEM_S_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN2_MODE 0x00000007U -#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) -#define SPI_SMEM_DIN2_MODE_V 0x00000007U -#define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; +#define SPI_MEM_S_SMEM_DIN2_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN2_MODE_M (SPI_MEM_S_SMEM_DIN2_MODE_V << SPI_MEM_S_SMEM_DIN2_MODE_S) +#define SPI_MEM_S_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN2_MODE_S 6 +/** SPI_MEM_S_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN3_MODE 0x00000007U -#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) -#define SPI_SMEM_DIN3_MODE_V 0x00000007U -#define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; +#define SPI_MEM_S_SMEM_DIN3_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN3_MODE_M (SPI_MEM_S_SMEM_DIN3_MODE_V << SPI_MEM_S_SMEM_DIN3_MODE_S) +#define SPI_MEM_S_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN3_MODE_S 9 +/** SPI_MEM_S_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN4_MODE 0x00000007U -#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) -#define SPI_SMEM_DIN4_MODE_V 0x00000007U -#define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; +#define SPI_MEM_S_SMEM_DIN4_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN4_MODE_M (SPI_MEM_S_SMEM_DIN4_MODE_V << SPI_MEM_S_SMEM_DIN4_MODE_S) +#define SPI_MEM_S_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN4_MODE_S 12 +/** SPI_MEM_S_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN5_MODE 0x00000007U -#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) -#define SPI_SMEM_DIN5_MODE_V 0x00000007U -#define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; +#define SPI_MEM_S_SMEM_DIN5_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN5_MODE_M (SPI_MEM_S_SMEM_DIN5_MODE_V << SPI_MEM_S_SMEM_DIN5_MODE_S) +#define SPI_MEM_S_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN5_MODE_S 15 +/** SPI_MEM_S_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN6_MODE 0x00000007U -#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) -#define SPI_SMEM_DIN6_MODE_V 0x00000007U -#define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; +#define SPI_MEM_S_SMEM_DIN6_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN6_MODE_M (SPI_MEM_S_SMEM_DIN6_MODE_V << SPI_MEM_S_SMEM_DIN6_MODE_S) +#define SPI_MEM_S_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN6_MODE_S 18 +/** SPI_MEM_S_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN7_MODE 0x00000007U -#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) -#define SPI_SMEM_DIN7_MODE_V 0x00000007U -#define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; +#define SPI_MEM_S_SMEM_DIN7_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN7_MODE_M (SPI_MEM_S_SMEM_DIN7_MODE_V << SPI_MEM_S_SMEM_DIN7_MODE_S) +#define SPI_MEM_S_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN7_MODE_S 21 +/** SPI_MEM_S_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DINS_MODE 0x00000007U -#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) -#define SPI_SMEM_DINS_MODE_V 0x00000007U -#define SPI_SMEM_DINS_MODE_S 24 +#define SPI_MEM_S_SMEM_DINS_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DINS_MODE_M (SPI_MEM_S_SMEM_DINS_MODE_V << SPI_MEM_S_SMEM_DINS_MODE_S) +#define SPI_MEM_S_SMEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DINS_MODE_S 24 -/** SPI_SMEM_DIN_NUM_REG register +/** SPI_MEM_S_SMEM_DIN_NUM_REG register * MSPI external RAM input timing delay number control register */ -#define SPI_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198) -/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198) +/** SPI_MEM_S_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN0_NUM 0x00000003U -#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) -#define SPI_SMEM_DIN0_NUM_V 0x00000003U -#define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; +#define SPI_MEM_S_SMEM_DIN0_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN0_NUM_M (SPI_MEM_S_SMEM_DIN0_NUM_V << SPI_MEM_S_SMEM_DIN0_NUM_S) +#define SPI_MEM_S_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN0_NUM_S 0 +/** SPI_MEM_S_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN1_NUM 0x00000003U -#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) -#define SPI_SMEM_DIN1_NUM_V 0x00000003U -#define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; +#define SPI_MEM_S_SMEM_DIN1_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN1_NUM_M (SPI_MEM_S_SMEM_DIN1_NUM_V << SPI_MEM_S_SMEM_DIN1_NUM_S) +#define SPI_MEM_S_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN1_NUM_S 2 +/** SPI_MEM_S_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN2_NUM 0x00000003U -#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) -#define SPI_SMEM_DIN2_NUM_V 0x00000003U -#define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; +#define SPI_MEM_S_SMEM_DIN2_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN2_NUM_M (SPI_MEM_S_SMEM_DIN2_NUM_V << SPI_MEM_S_SMEM_DIN2_NUM_S) +#define SPI_MEM_S_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN2_NUM_S 4 +/** SPI_MEM_S_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN3_NUM 0x00000003U -#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) -#define SPI_SMEM_DIN3_NUM_V 0x00000003U -#define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; +#define SPI_MEM_S_SMEM_DIN3_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN3_NUM_M (SPI_MEM_S_SMEM_DIN3_NUM_V << SPI_MEM_S_SMEM_DIN3_NUM_S) +#define SPI_MEM_S_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN3_NUM_S 6 +/** SPI_MEM_S_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN4_NUM 0x00000003U -#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) -#define SPI_SMEM_DIN4_NUM_V 0x00000003U -#define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; +#define SPI_MEM_S_SMEM_DIN4_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN4_NUM_M (SPI_MEM_S_SMEM_DIN4_NUM_V << SPI_MEM_S_SMEM_DIN4_NUM_S) +#define SPI_MEM_S_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN4_NUM_S 8 +/** SPI_MEM_S_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN5_NUM 0x00000003U -#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) -#define SPI_SMEM_DIN5_NUM_V 0x00000003U -#define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; +#define SPI_MEM_S_SMEM_DIN5_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN5_NUM_M (SPI_MEM_S_SMEM_DIN5_NUM_V << SPI_MEM_S_SMEM_DIN5_NUM_S) +#define SPI_MEM_S_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN5_NUM_S 10 +/** SPI_MEM_S_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN6_NUM 0x00000003U -#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) -#define SPI_SMEM_DIN6_NUM_V 0x00000003U -#define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; +#define SPI_MEM_S_SMEM_DIN6_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN6_NUM_M (SPI_MEM_S_SMEM_DIN6_NUM_V << SPI_MEM_S_SMEM_DIN6_NUM_S) +#define SPI_MEM_S_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN6_NUM_S 12 +/** SPI_MEM_S_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN7_NUM 0x00000003U -#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) -#define SPI_SMEM_DIN7_NUM_V 0x00000003U -#define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; +#define SPI_MEM_S_SMEM_DIN7_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN7_NUM_M (SPI_MEM_S_SMEM_DIN7_NUM_V << SPI_MEM_S_SMEM_DIN7_NUM_S) +#define SPI_MEM_S_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN7_NUM_S 14 +/** SPI_MEM_S_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DINS_NUM 0x00000003U -#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) -#define SPI_SMEM_DINS_NUM_V 0x00000003U -#define SPI_SMEM_DINS_NUM_S 16 +#define SPI_MEM_S_SMEM_DINS_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DINS_NUM_M (SPI_MEM_S_SMEM_DINS_NUM_V << SPI_MEM_S_SMEM_DINS_NUM_S) +#define SPI_MEM_S_SMEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DINS_NUM_S 16 -/** SPI_SMEM_DOUT_MODE_REG register +/** SPI_MEM_S_SMEM_DOUT_MODE_REG register * MSPI external RAM output timing adjustment control register */ -#define SPI_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c) -/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c) +/** SPI_MEM_S_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) -#define SPI_SMEM_DOUT0_MODE_V 0x00000001U -#define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_S_SMEM_DOUT0_MODE_M (SPI_MEM_S_SMEM_DOUT0_MODE_V << SPI_MEM_S_SMEM_DOUT0_MODE_S) +#define SPI_MEM_S_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT0_MODE_S 0 +/** SPI_MEM_S_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) -#define SPI_SMEM_DOUT1_MODE_V 0x00000001U -#define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_S_SMEM_DOUT1_MODE_M (SPI_MEM_S_SMEM_DOUT1_MODE_V << SPI_MEM_S_SMEM_DOUT1_MODE_S) +#define SPI_MEM_S_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT1_MODE_S 1 +/** SPI_MEM_S_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) -#define SPI_SMEM_DOUT2_MODE_V 0x00000001U -#define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_S_SMEM_DOUT2_MODE_M (SPI_MEM_S_SMEM_DOUT2_MODE_V << SPI_MEM_S_SMEM_DOUT2_MODE_S) +#define SPI_MEM_S_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT2_MODE_S 2 +/** SPI_MEM_S_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) -#define SPI_SMEM_DOUT3_MODE_V 0x00000001U -#define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_S_SMEM_DOUT3_MODE_M (SPI_MEM_S_SMEM_DOUT3_MODE_V << SPI_MEM_S_SMEM_DOUT3_MODE_S) +#define SPI_MEM_S_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT3_MODE_S 3 +/** SPI_MEM_S_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) -#define SPI_SMEM_DOUT4_MODE_V 0x00000001U -#define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_S_SMEM_DOUT4_MODE_M (SPI_MEM_S_SMEM_DOUT4_MODE_V << SPI_MEM_S_SMEM_DOUT4_MODE_S) +#define SPI_MEM_S_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT4_MODE_S 4 +/** SPI_MEM_S_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) -#define SPI_SMEM_DOUT5_MODE_V 0x00000001U -#define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_S_SMEM_DOUT5_MODE_M (SPI_MEM_S_SMEM_DOUT5_MODE_V << SPI_MEM_S_SMEM_DOUT5_MODE_S) +#define SPI_MEM_S_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT5_MODE_S 5 +/** SPI_MEM_S_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) -#define SPI_SMEM_DOUT6_MODE_V 0x00000001U -#define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_S_SMEM_DOUT6_MODE_M (SPI_MEM_S_SMEM_DOUT6_MODE_V << SPI_MEM_S_SMEM_DOUT6_MODE_S) +#define SPI_MEM_S_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT6_MODE_S 6 +/** SPI_MEM_S_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) -#define SPI_SMEM_DOUT7_MODE_V 0x00000001U -#define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_S_SMEM_DOUT7_MODE_M (SPI_MEM_S_SMEM_DOUT7_MODE_V << SPI_MEM_S_SMEM_DOUT7_MODE_S) +#define SPI_MEM_S_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT7_MODE_S 7 +/** SPI_MEM_S_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) -#define SPI_SMEM_DOUTS_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_MODE_S 8 +#define SPI_MEM_S_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_S_SMEM_DOUTS_MODE_M (SPI_MEM_S_SMEM_DOUTS_MODE_V << SPI_MEM_S_SMEM_DOUTS_MODE_S) +#define SPI_MEM_S_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUTS_MODE_S 8 -/** SPI_SMEM_AC_REG register +/** SPI_MEM_S_SMEM_AC_REG register * MSPI external RAM ECC and SPI CS timing control register */ -#define SPI_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0) -/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0) +/** SPI_MEM_S_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. */ -#define SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) -#define SPI_SMEM_CS_SETUP_V 0x00000001U -#define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_S_SMEM_CS_SETUP_M (SPI_MEM_S_SMEM_CS_SETUP_V << SPI_MEM_S_SMEM_CS_SETUP_S) +#define SPI_MEM_S_SMEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_S_SMEM_CS_SETUP_S 0 +/** SPI_MEM_S_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ -#define SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) -#define SPI_SMEM_CS_HOLD_V 0x00000001U -#define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; +#define SPI_MEM_S_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_S_SMEM_CS_HOLD_M (SPI_MEM_S_SMEM_CS_HOLD_V << SPI_MEM_S_SMEM_CS_HOLD_S) +#define SPI_MEM_S_SMEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_S_SMEM_CS_HOLD_S 1 +/** SPI_MEM_S_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. + * SPI_MEM_S_cs_setup bit. */ -#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) -#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; +#define SPI_MEM_S_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_M (SPI_MEM_S_SMEM_CS_SETUP_TIME_V << SPI_MEM_S_SMEM_CS_SETUP_TIME_S) +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_S 2 +/** SPI_MEM_S_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. + * combined with SPI_MEM_S_cs_hold bit. */ -#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) -#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold +#define SPI_MEM_S_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_CS_HOLD_TIME_S) +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_S 7 +/** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ -#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) -#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when * accesses external RAM. */ -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses external RAM. */ -#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ -#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) -#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1; +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S) +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_S_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1; * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter * whether there is an ECC region or not. */ -#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) -#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) -#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_SMEM_SPLIT_TRANS_EN_S 31 +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_M (SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S 31 -/** SPI_SMEM_DIN_HEX_MODE_REG register +/** SPI_MEM_S_SMEM_DIN_HEX_MODE_REG register * MSPI 16x external RAM input timing delay mode control register */ -#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4) -/** SPI_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0; +#define SPI_MEM_S_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4) +/** SPI_MEM_S_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN08_MODE 0x00000007U -#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) -#define SPI_SMEM_DIN08_MODE_V 0x00000007U -#define SPI_SMEM_DIN08_MODE_S 0 -/** SPI_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0; +#define SPI_MEM_S_SMEM_DIN08_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN08_MODE_M (SPI_MEM_S_SMEM_DIN08_MODE_V << SPI_MEM_S_SMEM_DIN08_MODE_S) +#define SPI_MEM_S_SMEM_DIN08_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN08_MODE_S 0 +/** SPI_MEM_S_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN09_MODE 0x00000007U -#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) -#define SPI_SMEM_DIN09_MODE_V 0x00000007U -#define SPI_SMEM_DIN09_MODE_S 3 -/** SPI_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0; +#define SPI_MEM_S_SMEM_DIN09_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN09_MODE_M (SPI_MEM_S_SMEM_DIN09_MODE_V << SPI_MEM_S_SMEM_DIN09_MODE_S) +#define SPI_MEM_S_SMEM_DIN09_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN09_MODE_S 3 +/** SPI_MEM_S_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN10_MODE 0x00000007U -#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) -#define SPI_SMEM_DIN10_MODE_V 0x00000007U -#define SPI_SMEM_DIN10_MODE_S 6 -/** SPI_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0; +#define SPI_MEM_S_SMEM_DIN10_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN10_MODE_M (SPI_MEM_S_SMEM_DIN10_MODE_V << SPI_MEM_S_SMEM_DIN10_MODE_S) +#define SPI_MEM_S_SMEM_DIN10_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN10_MODE_S 6 +/** SPI_MEM_S_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN11_MODE 0x00000007U -#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) -#define SPI_SMEM_DIN11_MODE_V 0x00000007U -#define SPI_SMEM_DIN11_MODE_S 9 -/** SPI_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0; +#define SPI_MEM_S_SMEM_DIN11_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN11_MODE_M (SPI_MEM_S_SMEM_DIN11_MODE_V << SPI_MEM_S_SMEM_DIN11_MODE_S) +#define SPI_MEM_S_SMEM_DIN11_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN11_MODE_S 9 +/** SPI_MEM_S_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN12_MODE 0x00000007U -#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) -#define SPI_SMEM_DIN12_MODE_V 0x00000007U -#define SPI_SMEM_DIN12_MODE_S 12 -/** SPI_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0; +#define SPI_MEM_S_SMEM_DIN12_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN12_MODE_M (SPI_MEM_S_SMEM_DIN12_MODE_V << SPI_MEM_S_SMEM_DIN12_MODE_S) +#define SPI_MEM_S_SMEM_DIN12_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN12_MODE_S 12 +/** SPI_MEM_S_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN13_MODE 0x00000007U -#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) -#define SPI_SMEM_DIN13_MODE_V 0x00000007U -#define SPI_SMEM_DIN13_MODE_S 15 -/** SPI_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0; +#define SPI_MEM_S_SMEM_DIN13_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN13_MODE_M (SPI_MEM_S_SMEM_DIN13_MODE_V << SPI_MEM_S_SMEM_DIN13_MODE_S) +#define SPI_MEM_S_SMEM_DIN13_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN13_MODE_S 15 +/** SPI_MEM_S_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN14_MODE 0x00000007U -#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) -#define SPI_SMEM_DIN14_MODE_V 0x00000007U -#define SPI_SMEM_DIN14_MODE_S 18 -/** SPI_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0; +#define SPI_MEM_S_SMEM_DIN14_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN14_MODE_M (SPI_MEM_S_SMEM_DIN14_MODE_V << SPI_MEM_S_SMEM_DIN14_MODE_S) +#define SPI_MEM_S_SMEM_DIN14_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN14_MODE_S 18 +/** SPI_MEM_S_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DIN15_MODE 0x00000007U -#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) -#define SPI_SMEM_DIN15_MODE_V 0x00000007U -#define SPI_SMEM_DIN15_MODE_S 21 -/** SPI_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0; +#define SPI_MEM_S_SMEM_DIN15_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN15_MODE_M (SPI_MEM_S_SMEM_DIN15_MODE_V << SPI_MEM_S_SMEM_DIN15_MODE_S) +#define SPI_MEM_S_SMEM_DIN15_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN15_MODE_S 21 +/** SPI_MEM_S_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ -#define SPI_SMEM_DINS_HEX_MODE 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) -#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_S 24 +#define SPI_MEM_S_SMEM_DINS_HEX_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_M (SPI_MEM_S_SMEM_DINS_HEX_MODE_V << SPI_MEM_S_SMEM_DINS_HEX_MODE_S) +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_S 24 -/** SPI_SMEM_DIN_HEX_NUM_REG register +/** SPI_MEM_S_SMEM_DIN_HEX_NUM_REG register * MSPI 16x external RAM input timing delay number control register */ -#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8) -/** SPI_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8) +/** SPI_MEM_S_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN08_NUM 0x00000003U -#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) -#define SPI_SMEM_DIN08_NUM_V 0x00000003U -#define SPI_SMEM_DIN08_NUM_S 0 -/** SPI_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0; +#define SPI_MEM_S_SMEM_DIN08_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN08_NUM_M (SPI_MEM_S_SMEM_DIN08_NUM_V << SPI_MEM_S_SMEM_DIN08_NUM_S) +#define SPI_MEM_S_SMEM_DIN08_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN08_NUM_S 0 +/** SPI_MEM_S_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN09_NUM 0x00000003U -#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) -#define SPI_SMEM_DIN09_NUM_V 0x00000003U -#define SPI_SMEM_DIN09_NUM_S 2 -/** SPI_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0; +#define SPI_MEM_S_SMEM_DIN09_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN09_NUM_M (SPI_MEM_S_SMEM_DIN09_NUM_V << SPI_MEM_S_SMEM_DIN09_NUM_S) +#define SPI_MEM_S_SMEM_DIN09_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN09_NUM_S 2 +/** SPI_MEM_S_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN10_NUM 0x00000003U -#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) -#define SPI_SMEM_DIN10_NUM_V 0x00000003U -#define SPI_SMEM_DIN10_NUM_S 4 -/** SPI_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0; +#define SPI_MEM_S_SMEM_DIN10_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN10_NUM_M (SPI_MEM_S_SMEM_DIN10_NUM_V << SPI_MEM_S_SMEM_DIN10_NUM_S) +#define SPI_MEM_S_SMEM_DIN10_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN10_NUM_S 4 +/** SPI_MEM_S_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN11_NUM 0x00000003U -#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) -#define SPI_SMEM_DIN11_NUM_V 0x00000003U -#define SPI_SMEM_DIN11_NUM_S 6 -/** SPI_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0; +#define SPI_MEM_S_SMEM_DIN11_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN11_NUM_M (SPI_MEM_S_SMEM_DIN11_NUM_V << SPI_MEM_S_SMEM_DIN11_NUM_S) +#define SPI_MEM_S_SMEM_DIN11_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN11_NUM_S 6 +/** SPI_MEM_S_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN12_NUM 0x00000003U -#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) -#define SPI_SMEM_DIN12_NUM_V 0x00000003U -#define SPI_SMEM_DIN12_NUM_S 8 -/** SPI_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0; +#define SPI_MEM_S_SMEM_DIN12_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN12_NUM_M (SPI_MEM_S_SMEM_DIN12_NUM_V << SPI_MEM_S_SMEM_DIN12_NUM_S) +#define SPI_MEM_S_SMEM_DIN12_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN12_NUM_S 8 +/** SPI_MEM_S_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN13_NUM 0x00000003U -#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) -#define SPI_SMEM_DIN13_NUM_V 0x00000003U -#define SPI_SMEM_DIN13_NUM_S 10 -/** SPI_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0; +#define SPI_MEM_S_SMEM_DIN13_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN13_NUM_M (SPI_MEM_S_SMEM_DIN13_NUM_V << SPI_MEM_S_SMEM_DIN13_NUM_S) +#define SPI_MEM_S_SMEM_DIN13_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN13_NUM_S 10 +/** SPI_MEM_S_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN14_NUM 0x00000003U -#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) -#define SPI_SMEM_DIN14_NUM_V 0x00000003U -#define SPI_SMEM_DIN14_NUM_S 12 -/** SPI_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0; +#define SPI_MEM_S_SMEM_DIN14_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN14_NUM_M (SPI_MEM_S_SMEM_DIN14_NUM_V << SPI_MEM_S_SMEM_DIN14_NUM_S) +#define SPI_MEM_S_SMEM_DIN14_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN14_NUM_S 12 +/** SPI_MEM_S_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DIN15_NUM 0x00000003U -#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) -#define SPI_SMEM_DIN15_NUM_V 0x00000003U -#define SPI_SMEM_DIN15_NUM_S 14 -/** SPI_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0; +#define SPI_MEM_S_SMEM_DIN15_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN15_NUM_M (SPI_MEM_S_SMEM_DIN15_NUM_V << SPI_MEM_S_SMEM_DIN15_NUM_S) +#define SPI_MEM_S_SMEM_DIN15_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN15_NUM_S 14 +/** SPI_MEM_S_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ -#define SPI_SMEM_DINS_HEX_NUM 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) -#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_S 16 +#define SPI_MEM_S_SMEM_DINS_HEX_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_M (SPI_MEM_S_SMEM_DINS_HEX_NUM_V << SPI_MEM_S_SMEM_DINS_HEX_NUM_S) +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_S 16 -/** SPI_SMEM_DOUT_HEX_MODE_REG register +/** SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG register * MSPI 16x external RAM output timing adjustment control register */ -#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac) -/** SPI_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac) +/** SPI_MEM_S_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT08_MODE (BIT(0)) -#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) -#define SPI_SMEM_DOUT08_MODE_V 0x00000001U -#define SPI_SMEM_DOUT08_MODE_S 0 -/** SPI_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_MEM_S_SMEM_DOUT08_MODE_M (SPI_MEM_S_SMEM_DOUT08_MODE_V << SPI_MEM_S_SMEM_DOUT08_MODE_S) +#define SPI_MEM_S_SMEM_DOUT08_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT08_MODE_S 0 +/** SPI_MEM_S_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT09_MODE (BIT(1)) -#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) -#define SPI_SMEM_DOUT09_MODE_V 0x00000001U -#define SPI_SMEM_DOUT09_MODE_S 1 -/** SPI_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0; +#define SPI_MEM_S_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_MEM_S_SMEM_DOUT09_MODE_M (SPI_MEM_S_SMEM_DOUT09_MODE_V << SPI_MEM_S_SMEM_DOUT09_MODE_S) +#define SPI_MEM_S_SMEM_DOUT09_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT09_MODE_S 1 +/** SPI_MEM_S_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT10_MODE (BIT(2)) -#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) -#define SPI_SMEM_DOUT10_MODE_V 0x00000001U -#define SPI_SMEM_DOUT10_MODE_S 2 -/** SPI_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0; +#define SPI_MEM_S_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_MEM_S_SMEM_DOUT10_MODE_M (SPI_MEM_S_SMEM_DOUT10_MODE_V << SPI_MEM_S_SMEM_DOUT10_MODE_S) +#define SPI_MEM_S_SMEM_DOUT10_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT10_MODE_S 2 +/** SPI_MEM_S_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT11_MODE (BIT(3)) -#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) -#define SPI_SMEM_DOUT11_MODE_V 0x00000001U -#define SPI_SMEM_DOUT11_MODE_S 3 -/** SPI_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_MEM_S_SMEM_DOUT11_MODE_M (SPI_MEM_S_SMEM_DOUT11_MODE_V << SPI_MEM_S_SMEM_DOUT11_MODE_S) +#define SPI_MEM_S_SMEM_DOUT11_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT11_MODE_S 3 +/** SPI_MEM_S_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT12_MODE (BIT(4)) -#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) -#define SPI_SMEM_DOUT12_MODE_V 0x00000001U -#define SPI_SMEM_DOUT12_MODE_S 4 -/** SPI_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0; +#define SPI_MEM_S_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_MEM_S_SMEM_DOUT12_MODE_M (SPI_MEM_S_SMEM_DOUT12_MODE_V << SPI_MEM_S_SMEM_DOUT12_MODE_S) +#define SPI_MEM_S_SMEM_DOUT12_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT12_MODE_S 4 +/** SPI_MEM_S_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT13_MODE (BIT(5)) -#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) -#define SPI_SMEM_DOUT13_MODE_V 0x00000001U -#define SPI_SMEM_DOUT13_MODE_S 5 -/** SPI_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0; +#define SPI_MEM_S_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_MEM_S_SMEM_DOUT13_MODE_M (SPI_MEM_S_SMEM_DOUT13_MODE_V << SPI_MEM_S_SMEM_DOUT13_MODE_S) +#define SPI_MEM_S_SMEM_DOUT13_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT13_MODE_S 5 +/** SPI_MEM_S_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT14_MODE (BIT(6)) -#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) -#define SPI_SMEM_DOUT14_MODE_V 0x00000001U -#define SPI_SMEM_DOUT14_MODE_S 6 -/** SPI_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0; +#define SPI_MEM_S_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_MEM_S_SMEM_DOUT14_MODE_M (SPI_MEM_S_SMEM_DOUT14_MODE_V << SPI_MEM_S_SMEM_DOUT14_MODE_S) +#define SPI_MEM_S_SMEM_DOUT14_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT14_MODE_S 6 +/** SPI_MEM_S_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUT15_MODE (BIT(7)) -#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) -#define SPI_SMEM_DOUT15_MODE_V 0x00000001U -#define SPI_SMEM_DOUT15_MODE_S 7 -/** SPI_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0; +#define SPI_MEM_S_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_MEM_S_SMEM_DOUT15_MODE_M (SPI_MEM_S_SMEM_DOUT15_MODE_V << SPI_MEM_S_SMEM_DOUT15_MODE_S) +#define SPI_MEM_S_SMEM_DOUT15_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT15_MODE_S 7 +/** SPI_MEM_S_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ -#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) -#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_HEX_MODE_S 8 +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_M (SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V << SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S) +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S 8 -/** SPI_MEM_CLOCK_GATE_REG register +/** SPI_MEM_S_CLOCK_GATE_REG register * SPI0 clock gate register */ -#define SPI_MEM_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200) +#define SPI_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ @@ -2884,121 +2884,121 @@ extern "C" { #define SPI_CLK_EN_V 0x00000001U #define SPI_CLK_EN_S 0 -/** SPI_MEM_XTS_PLAIN_BASE_REG register +/** SPI_MEM_S_XTS_PLAIN_BASE_REG register * The base address of the memory that stores plaintext in Manual Encryption */ -#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300) -/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; +#define SPI_MEM_S_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300) +/** SPI_MEM_S_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; * This field is only used to generate include file in c case. This field is useless. * Please do not use this field. */ -#define SPI_XTS_PLAIN 0xFFFFFFFFU -#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) -#define SPI_XTS_PLAIN_V 0xFFFFFFFFU -#define SPI_XTS_PLAIN_S 0 +#define SPI_MEM_S_XTS_PLAIN 0xFFFFFFFFU +#define SPI_MEM_S_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_MEM_S_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_MEM_S_XTS_PLAIN_S 0 -/** SPI_MEM_XTS_LINESIZE_REG register +/** SPI_MEM_S_XTS_LINESIZE_REG register * Manual Encryption Line-Size register */ -#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340) -/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340) +/** SPI_MEM_S_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; * This bits stores the line-size parameter which will be used in manual encryption * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: * 32-bytes, 2: 64-bytes, 3:reserved. */ -#define SPI_XTS_LINESIZE 0x00000003U -#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) -#define SPI_XTS_LINESIZE_V 0x00000003U -#define SPI_XTS_LINESIZE_S 0 +#define SPI_MEM_S_XTS_LINESIZE 0x00000003U +#define SPI_MEM_S_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_MEM_S_XTS_LINESIZE_V 0x00000003U +#define SPI_MEM_S_XTS_LINESIZE_S 0 -/** SPI_MEM_XTS_DESTINATION_REG register +/** SPI_MEM_S_XTS_DESTINATION_REG register * Manual Encryption destination register */ -#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344) -/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344) +/** SPI_MEM_S_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; * This bit stores the destination parameter which will be used in manual encryption * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. */ -#define SPI_XTS_DESTINATION (BIT(0)) -#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) -#define SPI_XTS_DESTINATION_V 0x00000001U -#define SPI_XTS_DESTINATION_S 0 +#define SPI_MEM_S_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_S_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_MEM_S_XTS_DESTINATION_V 0x00000001U +#define SPI_MEM_S_XTS_DESTINATION_S 0 -/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348) -/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348) +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ -#define SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_S 0 +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S 0 -/** SPI_MEM_XTS_TRIGGER_REG register +/** SPI_MEM_S_XTS_TRIGGER_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; +#define SPI_MEM_S_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c) +/** SPI_MEM_S_XTS_TRIGGER : WT; bitpos: [0]; default: 0; * Set this bit to trigger the process of manual encryption calculation. This action * should only be asserted when manual encryption status is 0. After this action, * manual encryption status becomes 1. After calculation is done, manual encryption * status becomes 2. */ -#define SPI_XTS_TRIGGER (BIT(0)) -#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) -#define SPI_XTS_TRIGGER_V 0x00000001U -#define SPI_XTS_TRIGGER_S 0 +#define SPI_MEM_S_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_S_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_MEM_S_XTS_TRIGGER_V 0x00000001U +#define SPI_MEM_S_XTS_TRIGGER_S 0 -/** SPI_MEM_XTS_RELEASE_REG register +/** SPI_MEM_S_XTS_RELEASE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350) -/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; +#define SPI_MEM_S_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350) +/** SPI_MEM_S_XTS_RELEASE : WT; bitpos: [0]; default: 0; * Set this bit to release encrypted result to mspi. This action should only be * asserted when manual encryption status is 2. After this action, manual encryption * status will become 3. */ -#define SPI_XTS_RELEASE (BIT(0)) -#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) -#define SPI_XTS_RELEASE_V 0x00000001U -#define SPI_XTS_RELEASE_S 0 +#define SPI_MEM_S_XTS_RELEASE (BIT(0)) +#define SPI_MEM_S_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_MEM_S_XTS_RELEASE_V 0x00000001U +#define SPI_MEM_S_XTS_RELEASE_S 0 -/** SPI_MEM_XTS_DESTROY_REG register +/** SPI_MEM_S_XTS_DESTROY_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354) -/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; +#define SPI_MEM_S_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354) +/** SPI_MEM_S_XTS_DESTROY : WT; bitpos: [0]; default: 0; * Set this bit to destroy encrypted result. This action should be asserted only when * manual encryption status is 3. After this action, manual encryption status will * become 0. */ -#define SPI_XTS_DESTROY (BIT(0)) -#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) -#define SPI_XTS_DESTROY_V 0x00000001U -#define SPI_XTS_DESTROY_S 0 +#define SPI_MEM_S_XTS_DESTROY (BIT(0)) +#define SPI_MEM_S_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_MEM_S_XTS_DESTROY_V 0x00000001U +#define SPI_MEM_S_XTS_DESTROY_S 0 -/** SPI_MEM_XTS_STATE_REG register +/** SPI_MEM_S_XTS_STATE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358) -/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; +#define SPI_MEM_S_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358) +/** SPI_MEM_S_XTS_STATE : RO; bitpos: [1:0]; default: 0; * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption * calculation, 2: encryption calculation is done but the encrypted result is * invisible to mspi, 3: the encrypted result is visible to mspi. */ -#define SPI_XTS_STATE 0x00000003U -#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) -#define SPI_XTS_STATE_V 0x00000003U -#define SPI_XTS_STATE_S 0 +#define SPI_MEM_S_XTS_STATE 0x00000003U +#define SPI_MEM_S_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_MEM_S_XTS_STATE_V 0x00000003U +#define SPI_MEM_S_XTS_STATE_S 0 -/** SPI_MEM_XTS_DATE_REG register +/** SPI_MEM_S_XTS_DATE_REG register * Manual Encryption version register */ -#define SPI_MEM_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c) +#define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c) /** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; * This bits stores the last modified-time of manual encryption feature. */ @@ -3007,106 +3007,106 @@ extern "C" { #define SPI_XTS_DATE_V 0x3FFFFFFFU #define SPI_XTS_DATE_S 0 -/** SPI_MEM_MMU_ITEM_CONTENT_REG register +/** SPI_MEM_S_MMU_ITEM_CONTENT_REG register * MSPI-MMU item content register */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c) -/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; +#define SPI_MEM_S_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c) +/** SPI_MEM_S_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; * MSPI-MMU item content */ -#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) -#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_S 0 +#define SPI_MEM_S_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MEM_S_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_CONTENT_S 0 -/** SPI_MEM_MMU_ITEM_INDEX_REG register +/** SPI_MEM_S_MMU_ITEM_INDEX_REG register * MSPI-MMU item index register */ -#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380) -/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; +#define SPI_MEM_S_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380) +/** SPI_MEM_S_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; * MSPI-MMU item index */ -#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) -#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_S 0 +#define SPI_MEM_S_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MEM_S_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_INDEX_S 0 -/** SPI_MEM_MMU_POWER_CTRL_REG register +/** SPI_MEM_S_MMU_POWER_CTRL_REG register * MSPI MMU power control register */ -#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384) -/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; +#define SPI_MEM_S_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384) +/** SPI_MEM_S_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; * Set this bit to enable mmu-memory clock force on */ -#define SPI_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) -#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U -#define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; +#define SPI_MEM_S_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_S_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MEM_S_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_ON_S 0 +/** SPI_MEM_S_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ -#define SPI_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) -#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; +#define SPI_MEM_S_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_S_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MEM_S_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_PD_S 1 +/** SPI_MEM_S_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; * Set this bit to force mmu-memory powerup, in this case, the power should also be * controlled by rtc. */ -#define SPI_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) -#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; +#define SPI_MEM_S_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_S_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MEM_S_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_PU_S 2 +/** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ -#define SPI_MEM_AUX_CTRL 0x00003FFFU -#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) -#define SPI_MEM_AUX_CTRL_V 0x00003FFFU -#define SPI_MEM_AUX_CTRL_S 16 +#define SPI_MEM_S_AUX_CTRL 0x00003FFFU +#define SPI_MEM_S_AUX_CTRL_M (SPI_MEM_S_AUX_CTRL_V << SPI_MEM_S_AUX_CTRL_S) +#define SPI_MEM_S_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_S_AUX_CTRL_S 16 -/** SPI_MEM_DPA_CTRL_REG register +/** SPI_MEM_S_DPA_CTRL_REG register * SPI memory cryption DPA register */ -#define SPI_MEM_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388) -/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; +#define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388) +/** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the * performance of cryption will decrease together with this number increasing) */ -#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) -#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_S 0 -/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_MEM_S_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that * using key 1. */ -#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) -#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U -#define SPI_CRYPT_CALC_D_DPA_EN_S 3 -/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ -#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) -#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U -#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S 4 -/** SPI_MEM_DATE_REG register +/** SPI_MEM_S_DATE_REG register * SPI0 version control register */ -#define SPI_MEM_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712704; +#define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc) +/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704; * SPI0 register version. */ -#define SPI_MEM_DATE 0x0FFFFFFFU -#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) -#define SPI_MEM_DATE_V 0x0FFFFFFFU -#define SPI_MEM_DATE_S 0 +#define SPI_MEM_S_DATE 0x0FFFFFFFU +#define SPI_MEM_S_DATE_M (SPI_MEM_S_DATE_V << SPI_MEM_S_DATE_S) +#define SPI_MEM_S_DATE_V 0x0FFFFFFFU +#define SPI_MEM_S_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h b/components/soc/esp32p4/include/soc/spi_mem_s_struct.h index ead95c5e04..fd28bddac6 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h +++ b/components/soc/esp32p4/include/soc/spi_mem_s_struct.h @@ -30,7 +30,7 @@ typedef union { uint32_t mem_slv_st:4; uint32_t reserved_8:10; /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ @@ -38,7 +38,7 @@ typedef union { uint32_t reserved_19:13; }; uint32_t val; -} spi_mem_cmd_reg_t; +} spi_mem_s_cmd_reg_t; /** Type of mem_axi_err_addr register * SPI0 AXI request error address. @@ -47,14 +47,14 @@ typedef union { struct { /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set. */ uint32_t mem_axi_err_addr:27; uint32_t reserved_27:5; }; uint32_t val; -} spi_mem_axi_err_addr_reg_t; +} spi_mem_s_axi_err_addr_reg_t; /** Group: Flash Control and configuration registers */ @@ -108,8 +108,8 @@ typedef union { uint32_t mem_fcmd_oct:1; uint32_t reserved_10:3; /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT + * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. */ uint32_t mem_fastrd_mode:1; /** mem_fread_dual : R/W; bitpos: [14]; default: 0; @@ -157,7 +157,7 @@ typedef union { uint32_t mem_data_ie_always_on:1; }; uint32_t val; -} spi_mem_ctrl_reg_t; +} spi_mem_s_ctrl_reg_t; /** Type of mem_ctrl1 register * SPI0 control1 register. @@ -188,7 +188,7 @@ typedef union { /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. + * in SPI_MEM_S_ECC_ERR_ADDR_REG. */ uint32_t mem_rresp_ecc_err_en:1; /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; @@ -200,9 +200,9 @@ typedef union { */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -229,7 +229,7 @@ typedef union { uint32_t mem_txfifo_rst:1; }; uint32_t val; -} spi_mem_ctrl1_reg_t; +} spi_mem_s_ctrl1_reg_t; /** Type of mem_ctrl2 register * SPI0 control2 register. @@ -238,16 +238,16 @@ typedef union { struct { /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. + * SPI_MEM_S_CS_SETUP bit. */ uint32_t mem_cs_setup_time:5; /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. + * SPI_MEM_S_CS_HOLD bit. */ uint32_t mem_cs_hold_time:5; /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ uint32_t mem_ecc_cs_hold_time:3; @@ -270,7 +270,7 @@ typedef union { uint32_t mem_split_trans_en:1; /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t mem_cs_hold_delay:6; @@ -280,7 +280,7 @@ typedef union { uint32_t mem_sync_reset:1; }; uint32_t val; -} spi_mem_ctrl2_reg_t; +} spi_mem_s_ctrl2_reg_t; /** Type of mem_misc register * SPI0 misc register @@ -307,7 +307,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} spi_mem_misc_reg_t; +} spi_mem_s_misc_reg_t; /** Type of mem_cache_fctrl register * SPI0 bit mode control register. @@ -326,7 +326,7 @@ typedef union { uint32_t close_axi_inf_en:1; }; uint32_t val; -} spi_mem_cache_fctrl_reg_t; +} spi_mem_s_cache_fctrl_reg_t; /** Type of mem_ddr register * SPI0 flash DDR mode control register @@ -373,7 +373,7 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -410,7 +410,7 @@ typedef union { uint32_t reserved_31:1; }; uint32_t val; -} spi_mem_ddr_reg_t; +} spi_mem_s_ddr_reg_t; /** Group: Clock control and configuration registers */ @@ -420,16 +420,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to spi_mem_s_clkcnt_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is + * system/(spi_mem_s_clkcnt_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -440,7 +440,7 @@ typedef union { uint32_t mem_clk_equ_sysclk:1; }; uint32_t val; -} spi_mem_clock_reg_t; +} spi_mem_s_clock_reg_t; /** Type of mem_clock_gate register * SPI0 clock gate register @@ -454,7 +454,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} spi_mem_clock_gate_reg_t; +} spi_mem_s_clock_gate_reg_t; /** Group: Flash User-defined control registers */ @@ -474,7 +474,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -490,7 +490,7 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} spi_mem_user_reg_t; +} spi_mem_s_user_reg_t; /** Type of mem_user1 register * SPI0 user1 register. @@ -498,7 +498,7 @@ typedef union { typedef union { struct { /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_s_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t mem_usr_dummy_cyclelen:6; @@ -513,7 +513,7 @@ typedef union { uint32_t mem_usr_addr_bitlen:6; }; uint32_t val; -} spi_mem_user1_reg_t; +} spi_mem_s_user1_reg_t; /** Type of mem_user2 register * SPI0 user2 register. @@ -531,7 +531,7 @@ typedef union { uint32_t mem_usr_command_bitlen:4; }; uint32_t val; -} spi_mem_user2_reg_t; +} spi_mem_s_user2_reg_t; /** Group: External RAM Control and configuration registers */ @@ -564,7 +564,7 @@ typedef union { uint32_t smem_data_ie_always_on:1; }; uint32_t val; -} spi_mem_sram_cmd_reg_t; +} spi_mem_s_sram_cmd_reg_t; /** Type of smem_ddr register * SPI0 external RAM DDR mode control register @@ -611,7 +611,7 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -649,7 +649,7 @@ typedef union { uint32_t reserved_31:1; }; uint32_t val; -} spi_smem_ddr_reg_t; +} spi_mem_s_smem_ddr_reg_t; /** Type of smem_ac register * MSPI external RAM ECC and SPI CS timing control register @@ -667,16 +667,16 @@ typedef union { uint32_t smem_cs_hold:1; /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. + * spi_mem_s_cs_setup bit. */ uint32_t smem_cs_setup_time:5; /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. + * combined with spi_mem_s_cs_hold bit. */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; @@ -693,7 +693,7 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; @@ -705,7 +705,7 @@ typedef union { uint32_t smem_split_trans_en:1; }; uint32_t val; -} spi_smem_ac_reg_t; +} spi_mem_s_smem_ac_reg_t; /** Group: State control register */ @@ -722,7 +722,7 @@ typedef union { uint32_t reserved_12:20; }; uint32_t val; -} spi_mem_fsm_reg_t; +} spi_mem_s_fsm_reg_t; /** Group: Interrupt registers */ @@ -733,53 +733,53 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_ena:1; /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_ena:1; /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_ena:1; /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_ena:1; /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_ena:1; /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_ena:1; /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_ena:1; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_ena:1; /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + * The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_ena:1; /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + * The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_ena:1; }; uint32_t val; -} spi_mem_int_ena_reg_t; +} spi_mem_s_int_ena_reg_t; /** Type of mem_int_clr register * SPI0 interrupt clear register @@ -788,53 +788,53 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_clr:1; /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_clr:1; /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + * The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_clr:1; /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_clr:1; /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_clr:1; /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + * The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_clr:1; /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_clr:1; /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_clr:1; /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + * The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_clr:1; /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + * The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_clr:1; }; uint32_t val; -} spi_mem_int_clr_reg_t; +} spi_mem_s_int_clr_reg_t; /** Type of mem_int_raw register * SPI0 interrupt raw register @@ -843,73 +843,73 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t mem_slv_st_end_int_raw:1; /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ uint32_t mem_mst_st_end_int_raw:1; /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set + * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ uint32_t mem_ecc_err_int_raw:1; /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ uint32_t mem_pms_reject_int_raw:1; /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_raddr_err_int_raw:1; /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ uint32_t mem_axi_wr_flash_err_int_raw:1; /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. */ uint32_t mem_dqs0_afifo_ovf_int_raw:1; /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS is overflow. */ uint32_t mem_dqs1_afifo_ovf_int_raw:1; /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is * underflow. */ uint32_t mem_bus_fifo1_udf_int_raw:1; /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is * underflow. */ uint32_t mem_bus_fifo0_udf_int_raw:1; }; uint32_t val; -} spi_mem_int_raw_reg_t; +} spi_mem_s_int_raw_reg_t; /** Type of mem_int_st register * SPI0 interrupt status register @@ -918,53 +918,53 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_st:1; /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_S_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_st:1; /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + * The status bit for SPI_MEM_S_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_st:1; /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_st:1; /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_st:1; /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_st:1; /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_st:1; /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_st:1; /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + * The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_st:1; /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + * The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_st:1; }; uint32_t val; -} spi_mem_int_st_reg_t; +} spi_mem_s_int_st_reg_t; /** Group: PMS control and configuration registers */ @@ -983,14 +983,14 @@ typedef union { uint32_t fmem_pmsn_wr_attr:1; /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and - * SPI_FMEM_PMSn_SIZE_REG. + * section n is configured by registers SPI_MEM_S_FMEM_PMSn_ADDR_REG and + * SPI_MEM_S_FMEM_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; uint32_t reserved_3:29; }; uint32_t val; -} spi_fmem_pmsn_attr_reg_t; +} spi_mem_s_fmem_pmsn_attr_reg_t; /** Type of fmem_pmsn_addr register * SPI1 flash PMS section n start address register @@ -1004,7 +1004,7 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_fmem_pmsn_addr_reg_t; +} spi_mem_s_fmem_pmsn_addr_reg_t; /** Type of fmem_pmsn_size register * SPI1 flash PMS section n start address register @@ -1012,14 +1012,14 @@ typedef union { typedef union { struct { /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, - * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) + * SPI1 flash PMS section n address region is (SPI_MEM_S_FMEM_PMSn_ADDR_S, + * SPI_MEM_S_FMEM_PMSn_ADDR_S + SPI_MEM_S_FMEM_PMSn_SIZE) */ uint32_t fmem_pmsn_size:15; uint32_t reserved_15:17; }; uint32_t val; -} spi_fmem_pmsn_size_reg_t; +} spi_mem_s_fmem_pmsn_size_reg_t; /** Type of smem_pmsn_attr register * SPI1 flash PMS section n start address register @@ -1036,14 +1036,14 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and - * SPI_SMEM_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_MEM_S_SMEM_PMSn_ADDR_REG and + * SPI_MEM_S_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; uint32_t reserved_3:29; }; uint32_t val; -} spi_smem_pmsn_attr_reg_t; +} spi_mem_s_smem_pmsn_attr_reg_t; /** Type of smem_pmsn_addr register * SPI1 external RAM PMS section n start address register @@ -1057,7 +1057,7 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_smem_pmsn_addr_reg_t; +} spi_mem_s_smem_pmsn_addr_reg_t; /** Type of smem_pmsn_size register * SPI1 external RAM PMS section n start address register @@ -1065,14 +1065,14 @@ typedef union { typedef union { struct { /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, - * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) + * SPI1 external RAM PMS section n address region is (SPI_MEM_S_SMEM_PMSn_ADDR_S, + * SPI_MEM_S_SMEM_PMSn_ADDR_S + SPI_MEM_S_SMEM_PMSn_SIZE) */ uint32_t smem_pmsn_size:15; uint32_t reserved_15:17; }; uint32_t val; -} spi_smem_pmsn_size_reg_t; +} spi_mem_s_smem_pmsn_size_reg_t; /** Type of mem_pms_reject register * SPI1 access reject register @@ -1081,7 +1081,7 @@ typedef union { struct { /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_reject_addr:27; /** mem_pm_en : R/W; bitpos: [27]; default: 0; @@ -1090,27 +1090,27 @@ typedef union { uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; uint32_t val; -} spi_mem_pms_reject_reg_t; +} spi_mem_s_pms_reject_reg_t; /** Group: MSPI ECC registers */ @@ -1122,11 +1122,11 @@ typedef union { uint32_t reserved_0:5; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; @@ -1150,9 +1150,9 @@ typedef union { uint32_t mem_usr_ecc_addr_en:1; uint32_t reserved_22:2; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and + * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; @@ -1162,7 +1162,7 @@ typedef union { uint32_t mem_ecc_err_bits:7; }; uint32_t val; -} spi_mem_ecc_ctrl_reg_t; +} spi_mem_s_ecc_ctrl_reg_t; /** Type of mem_ecc_err_addr register * MSPI ECC error address register @@ -1171,13 +1171,13 @@ typedef union { struct { /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_addr:27; uint32_t reserved_27:5; }; uint32_t val; -} spi_mem_ecc_err_addr_reg_t; +} spi_mem_s_ecc_err_addr_reg_t; /** Type of smem_ecc_ctrl register * MSPI ECC control register @@ -1204,7 +1204,7 @@ typedef union { uint32_t reserved_21:11; }; uint32_t val; -} spi_smem_ecc_ctrl_reg_t; +} spi_mem_s_smem_ecc_ctrl_reg_t; /** Group: Status and state control registers */ @@ -1242,7 +1242,7 @@ typedef union { uint32_t all_axi_trans_afifo_empty:1; }; uint32_t val; -} spi_smem_axi_addr_ctrl_reg_t; +} spi_mem_s_smem_axi_addr_ctrl_reg_t; /** Type of mem_axi_err_resp_en register * SPI0 AXI error response enable register @@ -1301,7 +1301,7 @@ typedef union { uint32_t reserved_12:20; }; uint32_t val; -} spi_mem_axi_err_resp_en_reg_t; +} spi_mem_s_axi_err_resp_en_reg_t; /** Group: Flash timing registers */ @@ -1334,7 +1334,7 @@ typedef union { uint32_t reserved_7:25; }; uint32_t val; -} spi_mem_timing_cali_reg_t; +} spi_mem_s_timing_cali_reg_t; /** Type of mem_din_mode register * MSPI flash input timing delay mode control register @@ -1402,7 +1402,7 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_mem_din_mode_reg_t; +} spi_mem_s_din_mode_reg_t; /** Type of mem_din_num register * MSPI flash input timing delay number control register @@ -1457,7 +1457,7 @@ typedef union { uint32_t reserved_18:14; }; uint32_t val; -} spi_mem_din_num_reg_t; +} spi_mem_s_din_num_reg_t; /** Type of mem_dout_mode register * MSPI flash output timing adjustment control register @@ -1525,7 +1525,7 @@ typedef union { uint32_t reserved_9:23; }; uint32_t val; -} spi_mem_dout_mode_reg_t; +} spi_mem_s_dout_mode_reg_t; /** Group: External RAM timing registers */ @@ -1555,7 +1555,7 @@ typedef union { uint32_t reserved_6:26; }; uint32_t val; -} spi_smem_timing_cali_reg_t; +} spi_mem_s_smem_timing_cali_reg_t; /** Type of smem_din_mode register * MSPI external RAM input timing delay mode control register @@ -1628,7 +1628,7 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_smem_din_mode_reg_t; +} spi_mem_s_smem_din_mode_reg_t; /** Type of smem_din_num register * MSPI external RAM input timing delay number control register @@ -1683,7 +1683,7 @@ typedef union { uint32_t reserved_18:14; }; uint32_t val; -} spi_smem_din_num_reg_t; +} spi_mem_s_smem_din_num_reg_t; /** Type of smem_dout_mode register * MSPI external RAM output timing adjustment control register @@ -1756,7 +1756,7 @@ typedef union { uint32_t reserved_9:23; }; uint32_t val; -} spi_smem_dout_mode_reg_t; +} spi_mem_s_smem_dout_mode_reg_t; /** Type of smem_din_hex_mode register * MSPI 16x external RAM input timing delay mode control register @@ -1829,7 +1829,7 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_smem_din_hex_mode_reg_t; +} spi_mem_s_smem_din_hex_mode_reg_t; /** Type of smem_din_hex_num register * MSPI 16x external RAM input timing delay number control register @@ -1884,7 +1884,7 @@ typedef union { uint32_t reserved_18:14; }; uint32_t val; -} spi_smem_din_hex_num_reg_t; +} spi_mem_s_smem_din_hex_num_reg_t; /** Type of smem_dout_hex_mode register * MSPI 16x external RAM output timing adjustment control register @@ -1957,7 +1957,7 @@ typedef union { uint32_t reserved_9:23; }; uint32_t val; -} spi_smem_dout_hex_mode_reg_t; +} spi_mem_s_smem_dout_hex_mode_reg_t; /** Group: Manual Encryption plaintext Memory */ @@ -1973,7 +1973,7 @@ typedef union { uint32_t xts_plain:32; }; uint32_t val; -} spi_mem_xts_plain_base_reg_t; +} spi_mem_s_xts_plain_base_reg_t; /** Group: Manual Encryption configuration registers */ @@ -1991,7 +1991,7 @@ typedef union { uint32_t reserved_2:30; }; uint32_t val; -} spi_mem_xts_linesize_reg_t; +} spi_mem_s_xts_linesize_reg_t; /** Type of mem_xts_destination register * Manual Encryption destination register @@ -2006,7 +2006,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} spi_mem_xts_destination_reg_t; +} spi_mem_s_xts_destination_reg_t; /** Type of mem_xts_physical_address register * Manual Encryption physical address register @@ -2022,7 +2022,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} spi_mem_xts_physical_address_reg_t; +} spi_mem_s_xts_physical_address_reg_t; /** Group: Manual Encryption control and status registers */ @@ -2041,7 +2041,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} spi_mem_xts_trigger_reg_t; +} spi_mem_s_xts_trigger_reg_t; /** Type of mem_xts_release register * Manual Encryption physical address register @@ -2057,7 +2057,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} spi_mem_xts_release_reg_t; +} spi_mem_s_xts_release_reg_t; /** Type of mem_xts_destroy register * Manual Encryption physical address register @@ -2073,7 +2073,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} spi_mem_xts_destroy_reg_t; +} spi_mem_s_xts_destroy_reg_t; /** Type of mem_xts_state register * Manual Encryption physical address register @@ -2089,7 +2089,7 @@ typedef union { uint32_t reserved_2:30; }; uint32_t val; -} spi_mem_xts_state_reg_t; +} spi_mem_s_xts_state_reg_t; /** Group: Manual Encryption version control register */ @@ -2105,7 +2105,7 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} spi_mem_xts_date_reg_t; +} spi_mem_s_xts_date_reg_t; /** Group: MMU access registers */ @@ -2120,7 +2120,7 @@ typedef union { uint32_t mmu_item_content:32; }; uint32_t val; -} spi_mem_mmu_item_content_reg_t; +} spi_mem_s_mmu_item_content_reg_t; /** Type of mem_mmu_item_index register * MSPI-MMU item index register @@ -2133,7 +2133,7 @@ typedef union { uint32_t mmu_item_index:32; }; uint32_t val; -} spi_mem_mmu_item_index_reg_t; +} spi_mem_s_mmu_item_index_reg_t; /** Group: MMU power control and configuration registers */ @@ -2163,7 +2163,7 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} spi_mem_mmu_power_ctrl_reg_t; +} spi_mem_s_mmu_power_ctrl_reg_t; /** Group: External mem cryption DPA registers */ @@ -2192,7 +2192,7 @@ typedef union { uint32_t reserved_5:27; }; uint32_t val; -} spi_mem_dpa_ctrl_reg_t; +} spi_mem_s_dpa_ctrl_reg_t; /** Group: Version control register */ @@ -2208,87 +2208,87 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} spi_mem_date_reg_t; +} spi_mem_s_date_reg_t; -typedef struct { - volatile spi_mem_cmd_reg_t mem_cmd; +typedef struct spi_mem_s_dev_s { + volatile spi_mem_s_cmd_reg_t mem_cmd; uint32_t reserved_004; - volatile spi_mem_ctrl_reg_t mem_ctrl; - volatile spi_mem_ctrl1_reg_t mem_ctrl1; - volatile spi_mem_ctrl2_reg_t mem_ctrl2; - volatile spi_mem_clock_reg_t mem_clock; - volatile spi_mem_user_reg_t mem_user; - volatile spi_mem_user1_reg_t mem_user1; - volatile spi_mem_user2_reg_t mem_user2; + volatile spi_mem_s_ctrl_reg_t mem_ctrl; + volatile spi_mem_s_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_s_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_s_clock_reg_t mem_clock; + volatile spi_mem_s_user_reg_t mem_user; + volatile spi_mem_s_user1_reg_t mem_user1; + volatile spi_mem_s_user2_reg_t mem_user2; uint32_t reserved_024[4]; - volatile spi_mem_misc_reg_t mem_misc; + volatile spi_mem_s_misc_reg_t mem_misc; uint32_t reserved_038; - volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; + volatile spi_mem_s_cache_fctrl_reg_t mem_cache_fctrl; uint32_t reserved_040; - volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; + volatile spi_mem_s_sram_cmd_reg_t mem_sram_cmd; uint32_t reserved_048[3]; - volatile spi_mem_fsm_reg_t mem_fsm; + volatile spi_mem_s_fsm_reg_t mem_fsm; uint32_t reserved_058[26]; - volatile spi_mem_int_ena_reg_t mem_int_ena; - volatile spi_mem_int_clr_reg_t mem_int_clr; - volatile spi_mem_int_raw_reg_t mem_int_raw; - volatile spi_mem_int_st_reg_t mem_int_st; + volatile spi_mem_s_int_ena_reg_t mem_int_ena; + volatile spi_mem_s_int_clr_reg_t mem_int_clr; + volatile spi_mem_s_int_raw_reg_t mem_int_raw; + volatile spi_mem_s_int_st_reg_t mem_int_st; uint32_t reserved_0d0; - volatile spi_mem_ddr_reg_t mem_ddr; - volatile spi_smem_ddr_reg_t smem_ddr; + volatile spi_mem_s_ddr_reg_t mem_ddr; + volatile spi_mem_s_smem_ddr_reg_t smem_ddr; uint32_t reserved_0dc[9]; - volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; - volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; - volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; + volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_mem_s_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_mem_s_smem_pmsn_size_reg_t smem_pmsn_size[4]; uint32_t reserved_160; - volatile spi_mem_pms_reject_reg_t mem_pms_reject; - volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; - volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; - volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; - volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; - volatile spi_mem_timing_cali_reg_t mem_timing_cali; - volatile spi_mem_din_mode_reg_t mem_din_mode; - volatile spi_mem_din_num_reg_t mem_din_num; - volatile spi_mem_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_din_mode_reg_t smem_din_mode; - volatile spi_smem_din_num_reg_t smem_din_num; - volatile spi_smem_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_ac_reg_t smem_ac; - volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; - volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; - volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; + volatile spi_mem_s_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_s_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_s_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_s_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_mem_s_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_mem_s_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_s_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_s_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_s_din_mode_reg_t mem_din_mode; + volatile spi_mem_s_din_num_reg_t mem_din_num; + volatile spi_mem_s_dout_mode_reg_t mem_dout_mode; + volatile spi_mem_s_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_mem_s_smem_din_mode_reg_t smem_din_mode; + volatile spi_mem_s_smem_din_num_reg_t smem_din_num; + volatile spi_mem_s_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_mem_s_smem_ac_reg_t smem_ac; + volatile spi_mem_s_smem_din_hex_mode_reg_t smem_din_hex_mode; + volatile spi_mem_s_smem_din_hex_num_reg_t smem_din_hex_num; + volatile spi_mem_s_smem_dout_hex_mode_reg_t smem_dout_hex_mode; uint32_t reserved_1b0[20]; - volatile spi_mem_clock_gate_reg_t mem_clock_gate; + volatile spi_mem_s_clock_gate_reg_t mem_clock_gate; uint32_t reserved_204[63]; - volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; + volatile spi_mem_s_xts_plain_base_reg_t mem_xts_plain_base; uint32_t reserved_304[15]; - volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; - volatile spi_mem_xts_destination_reg_t mem_xts_destination; - volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; - volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; - volatile spi_mem_xts_release_reg_t mem_xts_release; - volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; - volatile spi_mem_xts_state_reg_t mem_xts_state; - volatile spi_mem_xts_date_reg_t mem_xts_date; + volatile spi_mem_s_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_s_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_s_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_s_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_s_xts_release_reg_t mem_xts_release; + volatile spi_mem_s_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_s_xts_state_reg_t mem_xts_state; + volatile spi_mem_s_xts_date_reg_t mem_xts_date; uint32_t reserved_360[7]; - volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; - volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; - volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; - volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; + volatile spi_mem_s_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl; uint32_t reserved_38c[28]; - volatile spi_mem_date_reg_t mem_date; + volatile spi_mem_s_date_reg_t mem_date; } spi_mem_s_dev_t; #ifndef __cplusplus -_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); +_Static_assert(sizeof(spi_mem_s_dev_t) == 0x400, "Invalid size of spi_mem_s_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..73af7d2536 --- /dev/null +++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h @@ -0,0 +1,1139 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct spi_mem_dev_s { + union { + struct { + uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ + uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/ + uint32_t reserved8 : 9; /*reserved*/ + uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ + uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + }; + uint32_t val; + } cmd; + uint32_t addr; + union { + struct { + uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t fdummy_rin : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/ + uint32_t fdummy_wout : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/ + uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t reserved7 : 1; /*reserved*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12 : 1; /*reserved*/ + uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t reserved16 : 2; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ + uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */ + uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t reserved25 : 5; /*reserved*/ + uint32_t dqs_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t data_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ + uint32_t reserved2 : 9; /*reserved*/ + uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_axi_rdata_back_fast : 1; /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/ + uint32_t rresp_ecc_err_en : 1; /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/ + uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/ + uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/ + uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t dual_ram_en : 1; /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t fast_write_en : 1; /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.*/ + uint32_t rxfifo_rst : 1; /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.*/ + uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/ + uint32_t cs_hold_time : 5; /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/ + uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner : 1; /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15 : 9; /*reserved*/ + uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset : 1; /*The spi0_mst_st and spi0_slv_st will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */ + uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */ + uint32_t clk_equ_sysclk : 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reserved8 : 1; /*reserved*/ + uint32_t ck_out_edge : 1; /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t reserved16 : 8; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t usr_dbytelen : 3; /*SPI0 USR_CMD read or write data byte length -1*/ + uint32_t reserved9 : 17; /*reserved*/ + uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value : 16; /*The value of command.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + union { + struct { + uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24 : 8; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t reserved_30; + union { + struct { + uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t reserved0 : 5; /*reserved*/ + uint32_t fsub_pin : 1; /*For SPI0, flash is connected to SUBPINs.*/ + uint32_t ssub_pin : 1; /*For SPI0, sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ + uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; + union { + struct { + uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/ + uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/ + uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/ + uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9 : 21; /*reserved*/ + uint32_t reg_same_aw_ar_addr_chk_en : 1; /*Set this bit to check AXI read/write the same address region.*/ + uint32_t reg_close_axi_inf_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/ + uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/ + uint32_t sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/ + uint32_t sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved12 : 2; /*reserved*/ + uint32_t sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/ + uint32_t sram_oct : 1; /*reserved*/ + uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ + uint32_t swb_mode : 8; /*Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t saddr_dual : 1; /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t reserved13 : 1; /*reserved*/ + uint32_t sdin_quad : 1; /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdout_quad : 1; /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t saddr_quad : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdin_oct : 1; /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdout_oct : 1; /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */ + uint32_t saddr_oct : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */ + uint32_t scmd_oct : 1; /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdummy_rin : 1; /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t sdin_hex : 1; /*For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. */ + uint32_t sdout_hex : 1; /*For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. */ + uint32_t reserved28 : 2; /*reserved*/ + uint32_t dqs_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t data_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_rd_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t usr_wr_cmd_value : 16; /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t cnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/ + uint32_t cnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t cnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + }; + uint32_t val; + } sram_clk; + union { + struct { + uint32_t reserved0 : 7; /*reserved*/ + uint32_t lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t data_buf[16]; + union { + struct { + uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/ + uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/ + uint32_t waiti_addr_en : 1; /*1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/ + uint32_t waiti_addr_cyclelen : 2; /*When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/ + uint32_t reserved5 : 4; /*reserved*/ + uint32_t waiti_cmd_2b : 1; /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/ + uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/ + uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/ + }; + uint32_t val; + } flash_waiti_ctrl; + union { + struct { + uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */ + uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */ + uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/ + uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/ + uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ + uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ + uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ + uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ + uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/ + }; + uint32_t val; + } flash_sus_ctrl; + union { + struct { + uint32_t flash_pes_command : 16; /*Program/Erase suspend command.*/ + uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ + }; + uint32_t val; + } flash_sus_cmd; + union { + struct { + uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/ + uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ + uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ + uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ + uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ + uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ + uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ + uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ + uint32_t reserved8 : 7; /*reserved*/ + uint32_t flash_pesr_cmd_2b : 1; /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/ + uint32_t flash_per_command : 16; /*Program/Erase resume command.*/ + }; + uint32_t val; + } sus_status; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + union { + struct { + uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err_en : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ + uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ + uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ + uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ + uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/ + uint32_t ecc_err : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ + uint32_t pms_reject : 1; /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/ + uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ + uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow.*/ + uint32_t dqs1_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow.*/ + uint32_t bus_fifo1_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow.*/ + uint32_t bus_fifo0_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_st; + uint32_t reserved_d0; + union { + struct { + uint32_t fmem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ + uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/ + uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/ + uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t fmem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t outminbytelen : 7; /*It is the minimum output data length in the DDR psram.*/ + uint32_t tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/ + uint32_t rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/ + uint32_t usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + union { + struct { + uint32_t fmem_pms0_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t fmem_pms0_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t fmem_pms0_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_attr; + union { + struct { + uint32_t fmem_pms1_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t fmem_pms1_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t fmem_pms1_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_attr; + union { + struct { + uint32_t fmem_pms2_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t fmem_pms2_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t fmem_pms2_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_attr; + union { + struct { + uint32_t fmem_pms3_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t fmem_pms3_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t fmem_pms3_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_attr; + union { + struct { + uint32_t fmem_pms0_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_addr; + union { + struct { + uint32_t fmem_pms1_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_addr; + union { + struct { + uint32_t fmem_pms2_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_addr; + union { + struct { + uint32_t fmem_pms3_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_addr; + union { + struct { + uint32_t fmem_pms0_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_size; + union { + struct { + uint32_t fmem_pms1_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_size; + union { + struct { + uint32_t fmem_pms2_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_size; + union { + struct { + uint32_t fmem_pms3_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_size; + union { + struct { + uint32_t pms0_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t pms0_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t pms0_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_attr; + union { + struct { + uint32_t pms1_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t pms1_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t pms1_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_attr; + union { + struct { + uint32_t pms2_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t pms2_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t pms2_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_attr; + union { + struct { + uint32_t pms3_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t pms3_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t pms3_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_attr; + union { + struct { + uint32_t pms0_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_addr; + union { + struct { + uint32_t pms1_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_addr; + union { + struct { + uint32_t pms2_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_addr; + union { + struct { + uint32_t pms3_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_addr; + union { + struct { + uint32_t pms0_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_size; + union { + struct { + uint32_t pms1_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_size; + union { + struct { + uint32_t pms2_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_size; + union { + struct { + uint32_t pms3_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_size; + uint32_t reserved_160; + union { + struct { + uint32_t reject_addr : 26; /*This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/ + uint32_t reserved27 : 1; /*reserved*/ + uint32_t pms_ld : 1; /*1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_st : 1; /*1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_multi_hit : 1; /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_ivd : 1; /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + }; + uint32_t val; + } pms_reject; + union { + struct { + uint32_t reserved0 : 11; /*reserved*/ + uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ + uint32_t fmem_page_size : 2; /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t fmem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t usr_ecc_addr_en : 1; /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/ + uint32_t ecc_err_bits : 7; /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/ + }; + uint32_t val; + } ecc_ctrl; + union { + struct { + uint32_t ecc_err_addr : 26; /*This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t ecc_err_cnt : 6; /*This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + }; + uint32_t val; + } ecc_err_addr; + union { + struct { + uint32_t axi_err_addr : 26; /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ + uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/ + uint32_t reg_rdata_afifo_rempty : 1; /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_raddr_afifo_rempty : 1; /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_wdata_afifo_rempty : 1; /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_wblen_afifo_rempty : 1; /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_all_axi_trans_afifo_empty : 1; /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/ + }; + uint32_t val; + } axi_err_addr; + union { + struct { + uint32_t reserved0 : 17; /*reserved*/ + uint32_t ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ + uint32_t page_size : 2; /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } spi_smem_ecc_ctrl; + uint32_t reserved_178; + uint32_t reserved_17c; + union { + struct { + uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/ + uint32_t timing_cali_update : 1; /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/ + uint32_t reserved7 : 25; /*reserved*/ + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t timing_clk_ena : 1; /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/ + uint32_t reserved6 : 26; /*reserved*/ + }; + uint32_t val; + } spi_smem_timing_cali; + union { + struct { + uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_num; + union { + struct { + uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_mode; + union { + struct { + uint32_t cs_setup : 1; /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t cs_hold_time : 5; /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/ + uint32_t ecc_skip_page_corner : 1; /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ + uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ + uint32_t reserved17 : 8; /*reserved*/ + uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + }; + uint32_t val; + } spi_smem_ac; + union { + struct { + uint32_t din08_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din09_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din10_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din11_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din12_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din13_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din14_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din15_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t dins_hex_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_hex_mode; + union { + struct { + uint32_t din08_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din09_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din10_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din11_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din12_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din13_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din14_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din15_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_hex_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_hex_num; + union { + struct { + uint32_t dout08_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout09_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout10_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout11_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout12_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout13_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout14_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout15_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t douts_hex_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_hex_mode; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + union { + struct { + uint32_t reg_clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t xts_plain_base; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + union { + struct { + uint32_t reg_xts_linesize : 2; /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_linesize; + union { + struct { + uint32_t reg_xts_destination : 1; /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destination; + union { + struct { + uint32_t reg_xts_physical_address : 26; /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } xts_physical_address; + union { + struct { + uint32_t reg_xts_trigger : 1; /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_trigger; + union { + struct { + uint32_t reg_xts_release : 1; /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_release; + union { + struct { + uint32_t reg_xts_destroy : 1; /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destroy; + union { + struct { + uint32_t reg_xts_state : 2; /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_state; + union { + struct { + uint32_t reg_xts_date : 30; /*This bits stores the last modified-time of manual encryption feature.*/ + uint32_t reserved30 : 2; /*reserved*/ + }; + uint32_t val; + } xts_date; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t mmu_item_content; + uint32_t mmu_item_index; + union { + struct { + uint32_t mem_force_on : 1; /*Set this bit to enable mmu-memory clock force on*/ + uint32_t mem_force_pd : 1; /*Set this bit to force mmu-memory powerdown*/ + uint32_t mem_force_pu : 1; /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/ + uint32_t reserved3 : 13; /*reserved*/ + uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/ + uint32_t rdn_ena : 1; /*ECO register enable bit*/ + uint32_t rdn_result : 1; /*MSPI module clock domain and AXI clock domain ECO register result register*/ + }; + uint32_t val; + } mmu_power_ctrl; + union { + struct { + uint32_t crtyp_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t crtyp_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ + uint32_t crtyp_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } dpa_ctrl; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t registeredrnd_eco_high; + uint32_t registeredrnd_eco_low; + uint32_t reserved_3f8; + union { + struct { + uint32_t date : 28; /*SPI0 register version.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_mem_dev_t; +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/spi_pins.h b/components/soc/esp32p4/include/soc/spi_pins.h new file mode 100644 index 0000000000..d2aa55b41e --- /dev/null +++ b/components/soc/esp32p4/include/soc/spi_pins.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32p4/include/soc/system_reg.h b/components/soc/esp32p4/include/soc/system_reg.h new file mode 100644 index 0000000000..195ca330c6 --- /dev/null +++ b/components/soc/esp32p4/include/soc/system_reg.h @@ -0,0 +1,6 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "soc/hp_system_reg.h" diff --git a/components/soc/esp32p4/include/soc/systimer_reg.h b/components/soc/esp32p4/include/soc/systimer_reg.h new file mode 100644 index 0000000000..f7ea02d025 --- /dev/null +++ b/components/soc/esp32p4/include/soc/systimer_reg.h @@ -0,0 +1,558 @@ +/** + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * SYSTIMER_CONF. + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * SYSTIMER_UNIT0_OP. + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * SYSTIMER_UNIT1_OP. + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * SYSTIMER_UNIT0_LOAD_HI. + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * SYSTIMER_UNIT0_LOAD_LO. + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * SYSTIMER_UNIT1_LOAD_HI. + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * SYSTIMER_UNIT1_LOAD_LO. + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * SYSTIMER_TARGET0_HI. + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * SYSTIMER_TARGET0_LO. + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * SYSTIMER_TARGET1_HI. + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * SYSTIMER_TARGET1_LO. + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * SYSTIMER_TARGET2_HI. + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * SYSTIMER_TARGET2_LO. + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * SYSTIMER_TARGET0_CONF. + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * SYSTIMER_TARGET1_CONF. + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * SYSTIMER_TARGET2_CONF. + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * SYSTIMER_UNIT0_VALUE_HI. + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * SYSTIMER_UNIT0_VALUE_LO. + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * SYSTIMER_UNIT1_VALUE_HI. + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * SYSTIMER_UNIT1_VALUE_LO. + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * SYSTIMER_COMP0_LOAD. + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 load value + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * SYSTIMER_COMP1_LOAD. + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 load value + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * SYSTIMER_COMP2_LOAD. + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 load value + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * SYSTIMER_UNIT0_LOAD. + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 load value + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * SYSTIMER_UNIT1_LOAD. + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 load value + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * SYSTIMER_INT_ENA. + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * SYSTIMER_INT_RAW. + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * SYSTIMER_INT_CLR. + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * SYSTIMER_INT_ST. + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_DATE_REG register + * SYSTIMER_DATE. + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/systimer_struct.h b/components/soc/esp32p4/include/soc/systimer_struct.h new file mode 100644 index 0000000000..cd4cf5d507 --- /dev/null +++ b/components/soc/esp32p4/include/soc/systimer_struct.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Configuration Register */ +/** Type of conf register + * SYSTIMER_CONF. + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + uint32_t reserved31: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_comp_load_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_unit_load_reg_t; + +/** Interrupt Register */ +/** Type of int_ena register + * SYSTIMER_INT_ENA. + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * SYSTIMER_INT_RAW. + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * SYSTIMER_INT_CLR. + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * SYSTIMER_INT_ST. + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ + uint32_t target2_int_st: 1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Version Register */ +/** Type of date register + * SYSTIMER_DATE. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct systimer_dev_t { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/touch_reg.h b/components/soc/esp32p4/include/soc/touch_reg.h new file mode 100644 index 0000000000..9decb192d8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/touch_reg.h @@ -0,0 +1,764 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RTC_TOUCH_INT_RAW_REG register + * need_des + */ +#define RTC_TOUCH_INT_RAW_REG (DR_REG_RTC_TOUCH_BASE + 0x0) +/** RTC_TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_RAW (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_RAW_M (RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_TOUCH_SCAN_DONE_INT_RAW_S) +#define RTC_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_RAW_S 0 +/** RTC_TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_RAW (BIT(1)) +#define RTC_TOUCH_DONE_INT_RAW_M (RTC_TOUCH_DONE_INT_RAW_V << RTC_TOUCH_DONE_INT_RAW_S) +#define RTC_TOUCH_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_DONE_INT_RAW_S 1 +/** RTC_TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_RAW_M (RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_TOUCH_ACTIVE_INT_RAW_S) +#define RTC_TOUCH_ACTIVE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_RAW_S 2 +/** RTC_TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_RAW (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_RAW_M (RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_TOUCH_INACTIVE_INT_RAW_S) +#define RTC_TOUCH_INACTIVE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_RAW_S 3 +/** RTC_TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_RAW (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_RAW_M (RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_TOUCH_TIMEOUT_INT_RAW_S) +#define RTC_TOUCH_TIMEOUT_INT_RAW_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_RAW_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5 + +/** RTC_TOUCH_INT_ST_REG register + * need_des + */ +#define RTC_TOUCH_INT_ST_REG (DR_REG_RTC_TOUCH_BASE + 0x4) +/** RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_ST (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_ST_M (RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_TOUCH_SCAN_DONE_INT_ST_S) +#define RTC_TOUCH_SCAN_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_ST_S 0 +/** RTC_TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_ST (BIT(1)) +#define RTC_TOUCH_DONE_INT_ST_M (RTC_TOUCH_DONE_INT_ST_V << RTC_TOUCH_DONE_INT_ST_S) +#define RTC_TOUCH_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_DONE_INT_ST_S 1 +/** RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_ST_M (RTC_TOUCH_ACTIVE_INT_ST_V << RTC_TOUCH_ACTIVE_INT_ST_S) +#define RTC_TOUCH_ACTIVE_INT_ST_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_ST_S 2 +/** RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_ST (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_ST_M (RTC_TOUCH_INACTIVE_INT_ST_V << RTC_TOUCH_INACTIVE_INT_ST_S) +#define RTC_TOUCH_INACTIVE_INT_ST_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_ST_S 3 +/** RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_ST (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_ST_M (RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_TOUCH_TIMEOUT_INT_ST_S) +#define RTC_TOUCH_TIMEOUT_INT_ST_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_ST_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5 + +/** RTC_TOUCH_INT_ENA_REG register + * need_des + */ +#define RTC_TOUCH_INT_ENA_REG (DR_REG_RTC_TOUCH_BASE + 0x8) +/** RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_ENA (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_ENA_M (RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_TOUCH_SCAN_DONE_INT_ENA_S) +#define RTC_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_ENA_S 0 +/** RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_ENA (BIT(1)) +#define RTC_TOUCH_DONE_INT_ENA_M (RTC_TOUCH_DONE_INT_ENA_V << RTC_TOUCH_DONE_INT_ENA_S) +#define RTC_TOUCH_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_DONE_INT_ENA_S 1 +/** RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_ENA_M (RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_TOUCH_ACTIVE_INT_ENA_S) +#define RTC_TOUCH_ACTIVE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_ENA_S 2 +/** RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_ENA (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_ENA_M (RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_TOUCH_INACTIVE_INT_ENA_S) +#define RTC_TOUCH_INACTIVE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_ENA_S 3 +/** RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_ENA (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_ENA_M (RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_TOUCH_TIMEOUT_INT_ENA_S) +#define RTC_TOUCH_TIMEOUT_INT_ENA_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_ENA_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5 + +/** RTC_TOUCH_INT_CLR_REG register + * need_des + */ +#define RTC_TOUCH_INT_CLR_REG (DR_REG_RTC_TOUCH_BASE + 0xc) +/** RTC_TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_CLR (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_CLR_M (RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_TOUCH_SCAN_DONE_INT_CLR_S) +#define RTC_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_CLR_S 0 +/** RTC_TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_CLR (BIT(1)) +#define RTC_TOUCH_DONE_INT_CLR_M (RTC_TOUCH_DONE_INT_CLR_V << RTC_TOUCH_DONE_INT_CLR_S) +#define RTC_TOUCH_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_DONE_INT_CLR_S 1 +/** RTC_TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_CLR_M (RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_TOUCH_ACTIVE_INT_CLR_S) +#define RTC_TOUCH_ACTIVE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_CLR_S 2 +/** RTC_TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_CLR (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_CLR_M (RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_TOUCH_INACTIVE_INT_CLR_S) +#define RTC_TOUCH_INACTIVE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_CLR_S 3 +/** RTC_TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_CLR (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_CLR_M (RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_TOUCH_TIMEOUT_INT_CLR_S) +#define RTC_TOUCH_TIMEOUT_INT_CLR_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_CLR_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5 + +/** RTC_TOUCH_CHN_STATUS_REG register + * need_des + */ +#define RTC_TOUCH_CHN_STATUS_REG (DR_REG_RTC_TOUCH_BASE + 0x10) +/** RTC_TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_ACTIVE 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_M (RTC_TOUCH_PAD_ACTIVE_V << RTC_TOUCH_PAD_ACTIVE_S) +#define RTC_TOUCH_PAD_ACTIVE_V 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_S 0 +/** RTC_TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define RTC_TOUCH_MEAS_DONE (BIT(15)) +#define RTC_TOUCH_MEAS_DONE_M (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S) +#define RTC_TOUCH_MEAS_DONE_V 0x00000001U +#define RTC_TOUCH_MEAS_DONE_S 15 +/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_CURR 0x0000000FU +#define RTC_TOUCH_SCAN_CURR_M (RTC_TOUCH_SCAN_CURR_V << RTC_TOUCH_SCAN_CURR_S) +#define RTC_TOUCH_SCAN_CURR_V 0x0000000FU +#define RTC_TOUCH_SCAN_CURR_S 16 + +/** RTC_TOUCH_STATUS_0_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_0_REG (DR_REG_RTC_TOUCH_BASE + 0x14) +/** RTC_TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD0_DATA_M (RTC_TOUCH_PAD0_DATA_V << RTC_TOUCH_PAD0_DATA_S) +#define RTC_TOUCH_PAD0_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD0_DATA_S 0 +/** RTC_TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_M (RTC_TOUCH_PAD0_DEBOUNCE_CNT_V << RTC_TOUCH_PAD0_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD0_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_M (RTC_TOUCH_PAD0_NEG_NOISE_CNT_V << RTC_TOUCH_PAD0_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_1_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_1_REG (DR_REG_RTC_TOUCH_BASE + 0x18) +/** RTC_TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD1_DATA_M (RTC_TOUCH_PAD1_DATA_V << RTC_TOUCH_PAD1_DATA_S) +#define RTC_TOUCH_PAD1_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD1_DATA_S 0 +/** RTC_TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_M (RTC_TOUCH_PAD1_DEBOUNCE_CNT_V << RTC_TOUCH_PAD1_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD1_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_M (RTC_TOUCH_PAD1_NEG_NOISE_CNT_V << RTC_TOUCH_PAD1_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_2_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_2_REG (DR_REG_RTC_TOUCH_BASE + 0x1c) +/** RTC_TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD2_DATA_M (RTC_TOUCH_PAD2_DATA_V << RTC_TOUCH_PAD2_DATA_S) +#define RTC_TOUCH_PAD2_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD2_DATA_S 0 +/** RTC_TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_M (RTC_TOUCH_PAD2_DEBOUNCE_CNT_V << RTC_TOUCH_PAD2_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD2_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_M (RTC_TOUCH_PAD2_NEG_NOISE_CNT_V << RTC_TOUCH_PAD2_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_3_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_3_REG (DR_REG_RTC_TOUCH_BASE + 0x20) +/** RTC_TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD3_DATA_M (RTC_TOUCH_PAD3_DATA_V << RTC_TOUCH_PAD3_DATA_S) +#define RTC_TOUCH_PAD3_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD3_DATA_S 0 +/** RTC_TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_M (RTC_TOUCH_PAD3_DEBOUNCE_CNT_V << RTC_TOUCH_PAD3_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD3_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_M (RTC_TOUCH_PAD3_NEG_NOISE_CNT_V << RTC_TOUCH_PAD3_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_4_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_4_REG (DR_REG_RTC_TOUCH_BASE + 0x24) +/** RTC_TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD4_DATA_M (RTC_TOUCH_PAD4_DATA_V << RTC_TOUCH_PAD4_DATA_S) +#define RTC_TOUCH_PAD4_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD4_DATA_S 0 +/** RTC_TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_M (RTC_TOUCH_PAD4_DEBOUNCE_CNT_V << RTC_TOUCH_PAD4_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD4_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_M (RTC_TOUCH_PAD4_NEG_NOISE_CNT_V << RTC_TOUCH_PAD4_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_5_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_5_REG (DR_REG_RTC_TOUCH_BASE + 0x28) +/** RTC_TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD5_DATA_M (RTC_TOUCH_PAD5_DATA_V << RTC_TOUCH_PAD5_DATA_S) +#define RTC_TOUCH_PAD5_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD5_DATA_S 0 +/** RTC_TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_M (RTC_TOUCH_PAD5_DEBOUNCE_CNT_V << RTC_TOUCH_PAD5_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD5_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_M (RTC_TOUCH_PAD5_NEG_NOISE_CNT_V << RTC_TOUCH_PAD5_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_6_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_6_REG (DR_REG_RTC_TOUCH_BASE + 0x2c) +/** RTC_TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD6_DATA_M (RTC_TOUCH_PAD6_DATA_V << RTC_TOUCH_PAD6_DATA_S) +#define RTC_TOUCH_PAD6_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD6_DATA_S 0 +/** RTC_TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_M (RTC_TOUCH_PAD6_DEBOUNCE_CNT_V << RTC_TOUCH_PAD6_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD6_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_M (RTC_TOUCH_PAD6_NEG_NOISE_CNT_V << RTC_TOUCH_PAD6_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_7_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_7_REG (DR_REG_RTC_TOUCH_BASE + 0x30) +/** RTC_TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD7_DATA_M (RTC_TOUCH_PAD7_DATA_V << RTC_TOUCH_PAD7_DATA_S) +#define RTC_TOUCH_PAD7_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD7_DATA_S 0 +/** RTC_TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_M (RTC_TOUCH_PAD7_DEBOUNCE_CNT_V << RTC_TOUCH_PAD7_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD7_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_M (RTC_TOUCH_PAD7_NEG_NOISE_CNT_V << RTC_TOUCH_PAD7_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_8_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_8_REG (DR_REG_RTC_TOUCH_BASE + 0x34) +/** RTC_TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD8_DATA_M (RTC_TOUCH_PAD8_DATA_V << RTC_TOUCH_PAD8_DATA_S) +#define RTC_TOUCH_PAD8_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD8_DATA_S 0 +/** RTC_TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_M (RTC_TOUCH_PAD8_DEBOUNCE_CNT_V << RTC_TOUCH_PAD8_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD8_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_M (RTC_TOUCH_PAD8_NEG_NOISE_CNT_V << RTC_TOUCH_PAD8_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_9_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_9_REG (DR_REG_RTC_TOUCH_BASE + 0x38) +/** RTC_TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD9_DATA_M (RTC_TOUCH_PAD9_DATA_V << RTC_TOUCH_PAD9_DATA_S) +#define RTC_TOUCH_PAD9_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD9_DATA_S 0 +/** RTC_TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_M (RTC_TOUCH_PAD9_DEBOUNCE_CNT_V << RTC_TOUCH_PAD9_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD9_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_M (RTC_TOUCH_PAD9_NEG_NOISE_CNT_V << RTC_TOUCH_PAD9_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_10_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_10_REG (DR_REG_RTC_TOUCH_BASE + 0x3c) +/** RTC_TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD10_DATA_M (RTC_TOUCH_PAD10_DATA_V << RTC_TOUCH_PAD10_DATA_S) +#define RTC_TOUCH_PAD10_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD10_DATA_S 0 +/** RTC_TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_M (RTC_TOUCH_PAD10_DEBOUNCE_CNT_V << RTC_TOUCH_PAD10_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD10_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_M (RTC_TOUCH_PAD10_NEG_NOISE_CNT_V << RTC_TOUCH_PAD10_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_11_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_11_REG (DR_REG_RTC_TOUCH_BASE + 0x40) +/** RTC_TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD11_DATA_M (RTC_TOUCH_PAD11_DATA_V << RTC_TOUCH_PAD11_DATA_S) +#define RTC_TOUCH_PAD11_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD11_DATA_S 0 +/** RTC_TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_M (RTC_TOUCH_PAD11_DEBOUNCE_CNT_V << RTC_TOUCH_PAD11_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD11_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_M (RTC_TOUCH_PAD11_NEG_NOISE_CNT_V << RTC_TOUCH_PAD11_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_12_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_12_REG (DR_REG_RTC_TOUCH_BASE + 0x44) +/** RTC_TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD12_DATA_M (RTC_TOUCH_PAD12_DATA_V << RTC_TOUCH_PAD12_DATA_S) +#define RTC_TOUCH_PAD12_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD12_DATA_S 0 +/** RTC_TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_M (RTC_TOUCH_PAD12_DEBOUNCE_CNT_V << RTC_TOUCH_PAD12_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD12_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_M (RTC_TOUCH_PAD12_NEG_NOISE_CNT_V << RTC_TOUCH_PAD12_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_13_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_13_REG (DR_REG_RTC_TOUCH_BASE + 0x48) +/** RTC_TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD13_DATA_M (RTC_TOUCH_PAD13_DATA_V << RTC_TOUCH_PAD13_DATA_S) +#define RTC_TOUCH_PAD13_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD13_DATA_S 0 +/** RTC_TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_M (RTC_TOUCH_PAD13_DEBOUNCE_CNT_V << RTC_TOUCH_PAD13_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD13_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_M (RTC_TOUCH_PAD13_NEG_NOISE_CNT_V << RTC_TOUCH_PAD13_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_14_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_14_REG (DR_REG_RTC_TOUCH_BASE + 0x4c) +/** RTC_TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD14_DATA_M (RTC_TOUCH_PAD14_DATA_V << RTC_TOUCH_PAD14_DATA_S) +#define RTC_TOUCH_PAD14_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD14_DATA_S 0 +/** RTC_TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_M (RTC_TOUCH_PAD14_DEBOUNCE_CNT_V << RTC_TOUCH_PAD14_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD14_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_M (RTC_TOUCH_PAD14_NEG_NOISE_CNT_V << RTC_TOUCH_PAD14_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_15_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_15_REG (DR_REG_RTC_TOUCH_BASE + 0x50) +/** RTC_TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_DATA 0x0000FFFFU +#define RTC_TOUCH_SLP_DATA_M (RTC_TOUCH_SLP_DATA_V << RTC_TOUCH_SLP_DATA_S) +#define RTC_TOUCH_SLP_DATA_V 0x0000FFFFU +#define RTC_TOUCH_SLP_DATA_S 0 +/** RTC_TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_M (RTC_TOUCH_SLP_DEBOUNCE_CNT_V << RTC_TOUCH_SLP_DEBOUNCE_CNT_S) +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_SLP_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_M (RTC_TOUCH_SLP_NEG_NOISE_CNT_V << RTC_TOUCH_SLP_NEG_NOISE_CNT_S) +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_16_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_16_REG (DR_REG_RTC_TOUCH_BASE + 0x54) +/** RTC_TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD2_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD2_CNT_M (RTC_TOUCH_APPROACH_PAD2_CNT_V << RTC_TOUCH_APPROACH_PAD2_CNT_S) +#define RTC_TOUCH_APPROACH_PAD2_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD2_CNT_S 0 +/** RTC_TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD1_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD1_CNT_M (RTC_TOUCH_APPROACH_PAD1_CNT_V << RTC_TOUCH_APPROACH_PAD1_CNT_S) +#define RTC_TOUCH_APPROACH_PAD1_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD1_CNT_S 8 +/** RTC_TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD0_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD0_CNT_M (RTC_TOUCH_APPROACH_PAD0_CNT_V << RTC_TOUCH_APPROACH_PAD0_CNT_S) +#define RTC_TOUCH_APPROACH_PAD0_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD0_CNT_S 16 +/** RTC_TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_APPROACH_CNT 0x000000FFU +#define RTC_TOUCH_SLP_APPROACH_CNT_M (RTC_TOUCH_SLP_APPROACH_CNT_V << RTC_TOUCH_SLP_APPROACH_CNT_S) +#define RTC_TOUCH_SLP_APPROACH_CNT_V 0x000000FFU +#define RTC_TOUCH_SLP_APPROACH_CNT_S 24 + +/** RTC_TOUCH_STATUS_17_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_17_REG (DR_REG_RTC_TOUCH_BASE + 0x58) +/** RTC_TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0; + * Reserved + */ +#define RTC_TOUCH_DCAP_LPF 0x0000007FU +#define RTC_TOUCH_DCAP_LPF_M (RTC_TOUCH_DCAP_LPF_V << RTC_TOUCH_DCAP_LPF_S) +#define RTC_TOUCH_DCAP_LPF_V 0x0000007FU +#define RTC_TOUCH_DCAP_LPF_S 0 +/** RTC_TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRES_LPF 0x00000003U +#define RTC_TOUCH_DRES_LPF_M (RTC_TOUCH_DRES_LPF_V << RTC_TOUCH_DRES_LPF_S) +#define RTC_TOUCH_DRES_LPF_V 0x00000003U +#define RTC_TOUCH_DRES_LPF_S 7 +/** RTC_TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRV_LS 0x0000000FU +#define RTC_TOUCH_DRV_LS_M (RTC_TOUCH_DRV_LS_V << RTC_TOUCH_DRV_LS_S) +#define RTC_TOUCH_DRV_LS_V 0x0000000FU +#define RTC_TOUCH_DRV_LS_S 9 +/** RTC_TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRV_HS 0x0000001FU +#define RTC_TOUCH_DRV_HS_M (RTC_TOUCH_DRV_HS_V << RTC_TOUCH_DRV_HS_S) +#define RTC_TOUCH_DRV_HS_V 0x0000001FU +#define RTC_TOUCH_DRV_HS_S 13 +/** RTC_TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define RTC_TOUCH_DBIAS 0x0000001FU +#define RTC_TOUCH_DBIAS_M (RTC_TOUCH_DBIAS_V << RTC_TOUCH_DBIAS_S) +#define RTC_TOUCH_DBIAS_V 0x0000001FU +#define RTC_TOUCH_DBIAS_S 18 +/** RTC_TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0; + * need_des + */ +#define RTC_TOUCH_FREQ_SCAN_CNT 0x00000003U +#define RTC_TOUCH_FREQ_SCAN_CNT_M (RTC_TOUCH_FREQ_SCAN_CNT_V << RTC_TOUCH_FREQ_SCAN_CNT_S) +#define RTC_TOUCH_FREQ_SCAN_CNT_V 0x00000003U +#define RTC_TOUCH_FREQ_SCAN_CNT_S 23 + +/** RTC_TOUCH_CHN_TMP_STATUS_REG register + * need_des + */ +#define RTC_TOUCH_CHN_TMP_STATUS_REG (DR_REG_RTC_TOUCH_BASE + 0x5c) +/** RTC_TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_INACTIVE_STATUS 0x00007FFFU +#define RTC_TOUCH_PAD_INACTIVE_STATUS_M (RTC_TOUCH_PAD_INACTIVE_STATUS_V << RTC_TOUCH_PAD_INACTIVE_STATUS_S) +#define RTC_TOUCH_PAD_INACTIVE_STATUS_V 0x00007FFFU +#define RTC_TOUCH_PAD_INACTIVE_STATUS_S 0 +/** RTC_TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_ACTIVE_STATUS 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_STATUS_M (RTC_TOUCH_PAD_ACTIVE_STATUS_V << RTC_TOUCH_PAD_ACTIVE_STATUS_S) +#define RTC_TOUCH_PAD_ACTIVE_STATUS_V 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_STATUS_S 15 + +/** RTC_TOUCH_DATE_REG register + * need_des + */ +#define RTC_TOUCH_DATE_REG (DR_REG_RTC_TOUCH_BASE + 0x100) +/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548; + * need_des + */ +#define RTC_TOUCH_DATE 0x0FFFFFFFU +#define RTC_TOUCH_DATE_M (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S) +#define RTC_TOUCH_DATE_V 0x0FFFFFFFU +#define RTC_TOUCH_DATE_S 0 +/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TOUCH_CLK_EN (BIT(31)) +#define RTC_TOUCH_CLK_EN_M (RTC_TOUCH_CLK_EN_V << RTC_TOUCH_CLK_EN_S) +#define RTC_TOUCH_CLK_EN_V 0x00000001U +#define RTC_TOUCH_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/touch_struct.h b/components/soc/esp32p4/include/soc/touch_struct.h new file mode 100644 index 0000000000..d94b69cfe6 --- /dev/null +++ b/components/soc/esp32p4/include/soc/touch_struct.h @@ -0,0 +1,658 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + /** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_raw:1; + /** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_raw:1; + /** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_raw:1; + /** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_raw:1; + /** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_raw:1; + /** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + /** scan_done_int_st : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_st:1; + /** done_int_st : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_st:1; + /** active_int_st : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_st:1; + /** inactive_int_st : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_st:1; + /** timeout_int_st : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_st:1; + /** approach_loop_done_int_st : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + /** scan_done_int_ena : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_ena:1; + /** done_int_ena : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_ena:1; + /** active_int_ena : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_ena:1; + /** inactive_int_ena : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_ena:1; + /** timeout_int_ena : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_ena:1; + /** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + /** scan_done_int_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_clr:1; + /** done_int_clr : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_clr:1; + /** active_int_clr : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_clr:1; + /** inactive_int_clr : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_clr:1; + /** timeout_int_clr : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_clr:1; + /** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_clr_reg_t; + +/** Type of chn_status register + * need_des + */ +typedef union { + struct { + /** pad_active : RO; bitpos: [14:0]; default: 0; + * need_des + */ + uint32_t pad_active:15; + /** meas_done : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t meas_done:1; + /** scan_curr : RO; bitpos: [19:16]; default: 0; + * need_des + */ + uint32_t scan_curr:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_touch_chn_status_reg_t; + +/** Type of status_0 register + * need_des + */ +typedef union { + struct { + /** pad0_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad0_data:16; + /** pad0_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad0_debounce_cnt:3; + /** pad0_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad0_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_0_reg_t; + +/** Type of status_1 register + * need_des + */ +typedef union { + struct { + /** pad1_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad1_data:16; + /** pad1_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad1_debounce_cnt:3; + /** pad1_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad1_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_1_reg_t; + +/** Type of status_2 register + * need_des + */ +typedef union { + struct { + /** pad2_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad2_data:16; + /** pad2_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad2_debounce_cnt:3; + /** pad2_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad2_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_2_reg_t; + +/** Type of status_3 register + * need_des + */ +typedef union { + struct { + /** pad3_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad3_data:16; + /** pad3_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad3_debounce_cnt:3; + /** pad3_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad3_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_3_reg_t; + +/** Type of status_4 register + * need_des + */ +typedef union { + struct { + /** pad4_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad4_data:16; + /** pad4_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad4_debounce_cnt:3; + /** pad4_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad4_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_4_reg_t; + +/** Type of status_5 register + * need_des + */ +typedef union { + struct { + /** pad5_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad5_data:16; + /** pad5_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad5_debounce_cnt:3; + /** pad5_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad5_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_5_reg_t; + +/** Type of status_6 register + * need_des + */ +typedef union { + struct { + /** pad6_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad6_data:16; + /** pad6_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad6_debounce_cnt:3; + /** pad6_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad6_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_6_reg_t; + +/** Type of status_7 register + * need_des + */ +typedef union { + struct { + /** pad7_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad7_data:16; + /** pad7_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad7_debounce_cnt:3; + /** pad7_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad7_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_7_reg_t; + +/** Type of status_8 register + * need_des + */ +typedef union { + struct { + /** pad8_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad8_data:16; + /** pad8_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad8_debounce_cnt:3; + /** pad8_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad8_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_8_reg_t; + +/** Type of status_9 register + * need_des + */ +typedef union { + struct { + /** pad9_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad9_data:16; + /** pad9_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad9_debounce_cnt:3; + /** pad9_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad9_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_9_reg_t; + +/** Type of status_10 register + * need_des + */ +typedef union { + struct { + /** pad10_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad10_data:16; + /** pad10_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad10_debounce_cnt:3; + /** pad10_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad10_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_10_reg_t; + +/** Type of status_11 register + * need_des + */ +typedef union { + struct { + /** pad11_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad11_data:16; + /** pad11_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad11_debounce_cnt:3; + /** pad11_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad11_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_11_reg_t; + +/** Type of status_12 register + * need_des + */ +typedef union { + struct { + /** pad12_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad12_data:16; + /** pad12_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad12_debounce_cnt:3; + /** pad12_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad12_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_12_reg_t; + +/** Type of status_13 register + * need_des + */ +typedef union { + struct { + /** pad13_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad13_data:16; + /** pad13_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad13_debounce_cnt:3; + /** pad13_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad13_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_13_reg_t; + +/** Type of status_14 register + * need_des + */ +typedef union { + struct { + /** pad14_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad14_data:16; + /** pad14_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad14_debounce_cnt:3; + /** pad14_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad14_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_14_reg_t; + +/** Type of status_15 register + * need_des + */ +typedef union { + struct { + /** slp_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t slp_data:16; + /** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t slp_debounce_cnt:3; + /** slp_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t slp_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_status_15_reg_t; + +/** Type of status_16 register + * need_des + */ +typedef union { + struct { + /** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t approach_pad2_cnt:8; + /** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t approach_pad1_cnt:8; + /** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t approach_pad0_cnt:8; + /** slp_approach_cnt : RO; bitpos: [31:24]; default: 0; + * need_des + */ + uint32_t slp_approach_cnt:8; + }; + uint32_t val; +} rtc_touch_status_16_reg_t; + +/** Type of status_17 register + * need_des + */ +typedef union { + struct { + /** dcap_lpf : RO; bitpos: [6:0]; default: 0; + * Reserved + */ + uint32_t dcap_lpf:7; + /** dres_lpf : RO; bitpos: [8:7]; default: 0; + * need_des + */ + uint32_t dres_lpf:2; + /** drv_ls : RO; bitpos: [12:9]; default: 0; + * need_des + */ + uint32_t drv_ls:4; + /** drv_hs : RO; bitpos: [17:13]; default: 0; + * need_des + */ + uint32_t drv_hs:5; + /** dbias : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t dbias:5; + /** freq_scan_cnt : RO; bitpos: [24:23]; default: 0; + * need_des + */ + uint32_t freq_scan_cnt:2; + uint32_t reserved_25:7; + }; + uint32_t val; +} rtc_touch_status_17_reg_t; + +/** Type of chn_tmp_status register + * need_des + */ +typedef union { + struct { + /** pad_inactive_status : RO; bitpos: [14:0]; default: 0; + * need_des + */ + uint32_t pad_inactive_status:15; + /** pad_active_status : RO; bitpos: [29:15]; default: 0; + * need_des + */ + uint32_t pad_active_status:15; + uint32_t reserved_30:2; + }; + uint32_t val; +} rtc_touch_chn_tmp_status_reg_t; + + +/** Group: Version */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 2294548; + * need_des + */ + uint32_t date:28; + uint32_t reserved_28:3; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rtc_touch_date_reg_t; + + +typedef struct { + volatile rtc_touch_int_raw_reg_t int_raw; + volatile rtc_touch_int_st_reg_t int_st; + volatile rtc_touch_int_ena_reg_t int_ena; + volatile rtc_touch_int_clr_reg_t int_clr; + volatile rtc_touch_chn_status_reg_t chn_status; + volatile rtc_touch_status_0_reg_t status_0; + volatile rtc_touch_status_1_reg_t status_1; + volatile rtc_touch_status_2_reg_t status_2; + volatile rtc_touch_status_3_reg_t status_3; + volatile rtc_touch_status_4_reg_t status_4; + volatile rtc_touch_status_5_reg_t status_5; + volatile rtc_touch_status_6_reg_t status_6; + volatile rtc_touch_status_7_reg_t status_7; + volatile rtc_touch_status_8_reg_t status_8; + volatile rtc_touch_status_9_reg_t status_9; + volatile rtc_touch_status_10_reg_t status_10; + volatile rtc_touch_status_11_reg_t status_11; + volatile rtc_touch_status_12_reg_t status_12; + volatile rtc_touch_status_13_reg_t status_13; + volatile rtc_touch_status_14_reg_t status_14; + volatile rtc_touch_status_15_reg_t status_15; + volatile rtc_touch_status_16_reg_t status_16; + volatile rtc_touch_status_17_reg_t status_17; + volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status; + uint32_t reserved_060[40]; + volatile rtc_touch_date_reg_t date; +} rtc_touch_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/trace_reg.h b/components/soc/esp32p4/include/soc/trace_reg.h new file mode 100644 index 0000000000..c0f45143e9 --- /dev/null +++ b/components/soc/esp32p4/include/soc/trace_reg.h @@ -0,0 +1,463 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_START_ADDR 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S) +#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ +#define TRACE_WORK_STATUS 0x00000003U +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000003U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_CONFIG_REG register + * trace configuration register + */ +#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ +#define TRACE_DM_TRIGGER_ENA (BIT(0)) +#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) +#define TRACE_DM_TRIGGER_ENA_V 0x00000001U +#define TRACE_DM_TRIGGER_ENA_S 0 +/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ +#define TRACE_RESET_ENA (BIT(1)) +#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) +#define TRACE_RESET_ENA_V 0x00000001U +#define TRACE_RESET_ENA_S 1 +/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ +#define TRACE_HALT_ENA (BIT(2)) +#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) +#define TRACE_HALT_ENA_V 0x00000001U +#define TRACE_HALT_ENA_S 2 +/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ +#define TRACE_STALL_ENA (BIT(3)) +#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) +#define TRACE_STALL_ENA_V 0x00000001U +#define TRACE_STALL_ENA_S 3 +/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ +#define TRACE_FULL_ADDRESS (BIT(4)) +#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) +#define TRACE_FULL_ADDRESS_V 0x00000001U +#define TRACE_FULL_ADDRESS_S 4 +/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ +#define TRACE_IMPLICIT_EXCEPT (BIT(5)) +#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) +#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U +#define TRACE_IMPLICIT_EXCEPT_S 5 + +/** TRACE_FILTER_CONTROL_REG register + * filter control register + */ +#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ +#define TRACE_FILTER_EN (BIT(0)) +#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) +#define TRACE_FILTER_EN_V 0x00000001U +#define TRACE_FILTER_EN_S 0 +/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ +#define TRACE_MATCH_COMP (BIT(1)) +#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) +#define TRACE_MATCH_COMP_V 0x00000001U +#define TRACE_MATCH_COMP_S 1 +/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ +#define TRACE_MATCH_PRIVILEGE (BIT(2)) +#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S) +#define TRACE_MATCH_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_PRIVILEGE_S 2 +/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ +#define TRACE_MATCH_ECAUSE (BIT(3)) +#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S) +#define TRACE_MATCH_ECAUSE_V 0x00000001U +#define TRACE_MATCH_ECAUSE_S 3 +/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ +#define TRACE_MATCH_INTERRUPT (BIT(4)) +#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S) +#define TRACE_MATCH_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_INTERRUPT_S 4 + +/** TRACE_FILTER_MATCH_CONTROL_REG register + * filter match control register + */ +#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) +/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ +#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) +#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) +#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 +/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ +#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) +#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) +#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_VALUE_INTERRUPT_S 1 +/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ +#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S) +#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_S 2 + +/** TRACE_FILTER_COMPARATOR_CONTROL_REG register + * filter comparator match control register + */ +#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) +/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ +#define TRACE_P_INPUT (BIT(0)) +#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) +#define TRACE_P_INPUT_V 0x00000001U +#define TRACE_P_INPUT_S 0 +/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ +#define TRACE_P_FUNCTION 0x00000007U +#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) +#define TRACE_P_FUNCTION_V 0x00000007U +#define TRACE_P_FUNCTION_S 2 +/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ +#define TRACE_P_NOTIFY (BIT(5)) +#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) +#define TRACE_P_NOTIFY_V 0x00000001U +#define TRACE_P_NOTIFY_S 5 +/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ +#define TRACE_S_INPUT (BIT(8)) +#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) +#define TRACE_S_INPUT_V 0x00000001U +#define TRACE_S_INPUT_S 8 +/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ +#define TRACE_S_FUNCTION 0x00000007U +#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) +#define TRACE_S_FUNCTION_V 0x00000007U +#define TRACE_S_FUNCTION_S 10 +/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ +#define TRACE_S_NOTIFY (BIT(13)) +#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S) +#define TRACE_S_NOTIFY_V 0x00000001U +#define TRACE_S_NOTIFY_S 13 +/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ +#define TRACE_MATCH_MODE 0x00000003U +#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) +#define TRACE_MATCH_MODE_V 0x00000003U +#define TRACE_MATCH_MODE_S 16 + +/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register + * primary comparator match value + */ +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34) +/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ +#define TRACE_P_MATCH 0xFFFFFFFFU +#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S) +#define TRACE_P_MATCH_V 0xFFFFFFFFU +#define TRACE_P_MATCH_S 0 + +/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register + * secondary comparator match value + */ +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38) +/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ +#define TRACE_S_MATCH 0xFFFFFFFFU +#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S) +#define TRACE_S_MATCH_V 0xFFFFFFFFU +#define TRACE_S_MATCH_S 0 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ +#define TRACE_RESYNC_MODE 0x00000003U +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000003U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_AHB_CONFIG_REG register + * AHB config register + */ +#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) +/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ +#define TRACE_HBURST 0x00000007U +#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) +#define TRACE_HBURST_V 0x00000007U +#define TRACE_HBURST_S 0 +/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ +#define TRACE_MAX_INCR 0x00000007U +#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S) +#define TRACE_MAX_INCR_V 0x00000007U +#define TRACE_MAX_INCR_S 3 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/trace_struct.h b/components/soc/esp32p4/include/soc/trace_struct.h new file mode 100644 index 0000000000..08667b8cbc --- /dev/null +++ b/components/soc/esp32p4/include/soc/trace_struct.h @@ -0,0 +1,461 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ + uint32_t work_status:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of config register + * trace configuration register + */ +typedef union { + struct { + /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ + uint32_t dm_trigger_ena:1; + /** reset_ena : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ + uint32_t reset_ena:1; + /** halt_ena : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ + uint32_t halt_ena:1; + /** stall_ena : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ + uint32_t stall_ena:1; + /** full_address : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ + uint32_t full_address:1; + /** implicit_except : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ + uint32_t implicit_except:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_config_reg_t; + +/** Type of filter_control register + * filter control register + */ +typedef union { + struct { + /** filter_en : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ + uint32_t filter_en:1; + /** match_comp : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ + uint32_t match_comp:1; + /** match_privilege : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ + uint32_t match_privilege:1; + /** match_ecause : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ + uint32_t match_ecause:1; + /** match_interrupt : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ + uint32_t match_interrupt:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} trace_filter_control_reg_t; + +/** Type of filter_match_control register + * filter match control register + */ +typedef union { + struct { + /** match_choice_privilege : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ + uint32_t match_choice_privilege:1; + /** match_value_interrupt : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ + uint32_t match_value_interrupt:1; + /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ + uint32_t match_choice_ecause:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} trace_filter_match_control_reg_t; + +/** Type of filter_comparator_control register + * filter comparator match control register + */ +typedef union { + struct { + /** p_input : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ + uint32_t p_input:1; + uint32_t reserved_1:1; + /** p_function : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ + uint32_t p_function:3; + /** p_notify : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ + uint32_t p_notify:1; + uint32_t reserved_6:2; + /** s_input : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ + uint32_t s_input:1; + uint32_t reserved_9:1; + /** s_function : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ + uint32_t s_function:3; + /** s_notify : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ + uint32_t s_notify:1; + uint32_t reserved_14:2; + /** match_mode : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ + uint32_t match_mode:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} trace_filter_comparator_control_reg_t; + +/** Type of filter_p_comparator_match register + * primary comparator match value + */ +typedef union { + struct { + /** p_match : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ + uint32_t p_match:32; + }; + uint32_t val; +} trace_filter_p_comparator_match_reg_t; + +/** Type of filter_s_comparator_match register + * secondary comparator match value + */ +typedef union { + struct { + /** s_match : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ + uint32_t s_match:32; + }; + uint32_t val; +} trace_filter_s_comparator_match_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ + uint32_t resync_mode:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + +/** Type of ahb_config register + * AHB config register + */ +typedef union { + struct { + /** hburst : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ + uint32_t hburst:3; + /** max_incr : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ + uint32_t max_incr:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_ahb_config_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_config_reg_t config; + volatile trace_filter_control_reg_t filter_control; + volatile trace_filter_match_control_reg_t filter_match_control; + volatile trace_filter_comparator_control_reg_t filter_comparator_control; + volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match; + volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_ahb_config_reg_t ahb_config; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_048[237]; + volatile trace_date_reg_t date; +} trace_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/tsens_reg.h b/components/soc/esp32p4/include/soc/tsens_reg.h new file mode 100644 index 0000000000..279688bc82 --- /dev/null +++ b/components/soc/esp32p4/include/soc/tsens_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TSENS_CTRL_REG register + * Tsens configuration. + */ +#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0) +/** TSENS_OUT : RO; bitpos: [7:0]; default: 0; + * Temperature sensor data out. + */ +#define TSENS_OUT 0x000000FFU +#define TSENS_OUT_M (TSENS_OUT_V << TSENS_OUT_S) +#define TSENS_OUT_V 0x000000FFU +#define TSENS_OUT_S 0 +/** TSENS_READY : RO; bitpos: [8]; default: 0; + * Indicate temperature sensor out ready. + */ +#define TSENS_READY (BIT(8)) +#define TSENS_READY_M (TSENS_READY_V << TSENS_READY_S) +#define TSENS_READY_V 0x00000001U +#define TSENS_READY_S 8 +/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0; + * Enable sample signal for wakeup module. + */ +#define TSENS_SAMPLE_EN (BIT(9)) +#define TSENS_SAMPLE_EN_M (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S) +#define TSENS_SAMPLE_EN_V 0x00000001U +#define TSENS_SAMPLE_EN_S 9 +/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1; + * Wake up signal mask. + */ +#define TSENS_WAKEUP_MASK (BIT(10)) +#define TSENS_WAKEUP_MASK_M (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S) +#define TSENS_WAKEUP_MASK_V 0x00000001U +#define TSENS_WAKEUP_MASK_S 10 +/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1; + * Enable temperature sensor to send out interrupt. + */ +#define TSENS_INT_EN (BIT(12)) +#define TSENS_INT_EN_M (TSENS_INT_EN_V << TSENS_INT_EN_S) +#define TSENS_INT_EN_V 0x00000001U +#define TSENS_INT_EN_S 12 +/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * Invert temperature sensor data. + */ +#define TSENS_IN_INV (BIT(13)) +#define TSENS_IN_INV_M (TSENS_IN_INV_V << TSENS_IN_INV_S) +#define TSENS_IN_INV_V 0x00000001U +#define TSENS_IN_INV_S 13 +/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * Temperature sensor clock divider. + */ +#define TSENS_CLK_DIV 0x000000FFU +#define TSENS_CLK_DIV_M (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S) +#define TSENS_CLK_DIV_V 0x000000FFU +#define TSENS_CLK_DIV_S 14 +/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0; + * Temperature sensor power up. + */ +#define TSENS_POWER_UP (BIT(22)) +#define TSENS_POWER_UP_M (TSENS_POWER_UP_V << TSENS_POWER_UP_S) +#define TSENS_POWER_UP_V 0x00000001U +#define TSENS_POWER_UP_S 22 +/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0; + * 1: dump out & power up controlled by SW, 0: by FSM. + */ +#define TSENS_POWER_UP_FORCE (BIT(23)) +#define TSENS_POWER_UP_FORCE_M (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S) +#define TSENS_POWER_UP_FORCE_V 0x00000001U +#define TSENS_POWER_UP_FORCE_S 23 + +/** TSENS_INT_RAW_REG register + * Tsens interrupt raw registers. + */ +#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8) +/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Tsens wakeup interrupt raw. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_RAW (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S) +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S 0 + +/** TSENS_INT_ST_REG register + * Tsens interrupt status registers. + */ +#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc) +/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0; + * Tsens wakeup interrupt status. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ST (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ST_M (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ST_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ST_S 0 + +/** TSENS_INT_ENA_REG register + * Tsens interrupt enable registers. + */ +#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0; + * Tsens wakeup interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S 0 + +/** TSENS_INT_CLR_REG register + * Tsens interrupt clear registers. + */ +#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14) +/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0; + * Tsens wakeup interrupt clear. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_CLR (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S) +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S 0 + +/** TSENS_CLK_CONF_REG register + * Tsens regbank configuration registers. + */ +#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18) +/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0; + * Tsens regbank clock gating enable. + */ +#define TSENS_CLK_EN (BIT(0)) +#define TSENS_CLK_EN_M (TSENS_CLK_EN_V << TSENS_CLK_EN_S) +#define TSENS_CLK_EN_V 0x00000001U +#define TSENS_CLK_EN_S 0 + +/** TSENS_INT_ENA_W1TS_REG register + * Tsens wakeup interrupt enable assert. + */ +#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0; + * Write 1 to this field to assert interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S 0 + +/** TSENS_INT_ENA_W1TC_REG register + * Tsens wakeup interrupt enable deassert. + */ +#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0; + * Write 1 to this field to deassert interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S 0 + +/** TSENS_WAKEUP_CTRL_REG register + * Tsens wakeup control registers. + */ +#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24) +/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * Lower threshold. + */ +#define TSENS_WAKEUP_TH_LOW 0x000000FFU +#define TSENS_WAKEUP_TH_LOW_M (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S) +#define TSENS_WAKEUP_TH_LOW_V 0x000000FFU +#define TSENS_WAKEUP_TH_LOW_S 0 +/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255; + * Upper threshold. + */ +#define TSENS_WAKEUP_TH_HIGH 0x000000FFU +#define TSENS_WAKEUP_TH_HIGH_M (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S) +#define TSENS_WAKEUP_TH_HIGH_V 0x000000FFU +#define TSENS_WAKEUP_TH_HIGH_S 14 +/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ +#define TSENS_WAKEUP_OVER_UPPER_TH (BIT(29)) +#define TSENS_WAKEUP_OVER_UPPER_TH_M (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S) +#define TSENS_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define TSENS_WAKEUP_OVER_UPPER_TH_S 29 +/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0; + * Tsens wakeup enable. + */ +#define TSENS_WAKEUP_EN (BIT(30)) +#define TSENS_WAKEUP_EN_M (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S) +#define TSENS_WAKEUP_EN_V 0x00000001U +#define TSENS_WAKEUP_EN_S 30 +/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ +#define TSENS_WAKEUP_MODE (BIT(31)) +#define TSENS_WAKEUP_MODE_M (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S) +#define TSENS_WAKEUP_MODE_V 0x00000001U +#define TSENS_WAKEUP_MODE_S 31 + +/** TSENS_SAMPLE_RATE_REG register + * Hardware automatic sampling control registers. + */ +#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28) +/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * Hardware automatic sampling rate. + */ +#define TSENS_SAMPLE_RATE 0x0000FFFFU +#define TSENS_SAMPLE_RATE_M (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S) +#define TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define TSENS_SAMPLE_RATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/tsens_struct.h b/components/soc/esp32p4/include/soc/tsens_struct.h new file mode 100644 index 0000000000..671e88faa8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/tsens_struct.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tsens control registers. */ +/** Type of ctrl register + * Tsens configuration. + */ +typedef union { + struct { + /** out : RO; bitpos: [7:0]; default: 0; + * Temperature sensor data out. + */ + uint32_t out:8; + /** ready : RO; bitpos: [8]; default: 0; + * Indicate temperature sensor out ready. + */ + uint32_t ready:1; + /** sample_en : R/W; bitpos: [9]; default: 0; + * Enable sample signal for wakeup module. + */ + uint32_t sample_en:1; + /** wakeup_mask : R/W; bitpos: [10]; default: 1; + * Wake up signal mask. + */ + uint32_t wakeup_mask:1; + uint32_t reserved_11:1; + /** int_en : R/W; bitpos: [12]; default: 1; + * Enable temperature sensor to send out interrupt. + */ + uint32_t int_en:1; + /** in_inv : R/W; bitpos: [13]; default: 0; + * Invert temperature sensor data. + */ + uint32_t in_inv:1; + /** clk_div : R/W; bitpos: [21:14]; default: 6; + * Temperature sensor clock divider. + */ + uint32_t clk_div:8; + /** power_up : R/W; bitpos: [22]; default: 0; + * Temperature sensor power up. + */ + uint32_t power_up:1; + /** power_up_force : R/W; bitpos: [23]; default: 0; + * 1: dump out & power up controlled by SW, 0: by FSM. + */ + uint32_t power_up_force:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} tsens_ctrl_reg_t; + + +/** Group: Tsens interrupt registers. */ +/** Type of int_raw register + * Tsens interrupt raw registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Tsens wakeup interrupt raw. + */ + uint32_t cocpu_tsens_wake_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_raw_reg_t; + +/** Type of int_st register + * Tsens interrupt status registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_st : RO; bitpos: [0]; default: 0; + * Tsens wakeup interrupt status. + */ + uint32_t cocpu_tsens_wake_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_st_reg_t; + +/** Type of int_ena register + * Tsens interrupt enable registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena : R/WTC; bitpos: [0]; default: 0; + * Tsens wakeup interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_reg_t; + +/** Type of int_clr register + * Tsens interrupt clear registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_clr : WT; bitpos: [0]; default: 0; + * Tsens wakeup interrupt clear. + */ + uint32_t cocpu_tsens_wake_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_clr_reg_t; + +/** Type of int_ena_w1ts register + * Tsens wakeup interrupt enable assert. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena_w1ts : WT; bitpos: [0]; default: 0; + * Write 1 to this field to assert interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena_w1ts:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_w1ts_reg_t; + +/** Type of int_ena_w1tc register + * Tsens wakeup interrupt enable deassert. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena_w1tc : WT; bitpos: [0]; default: 0; + * Write 1 to this field to deassert interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena_w1tc:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_w1tc_reg_t; + + +/** Group: Tsens regbank clock control registers. */ +/** Type of clk_conf register + * Tsens regbank configuration registers. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Tsens regbank clock gating enable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_clk_conf_reg_t; + + +/** Group: Tsens wakeup control registers. */ +/** Type of wakeup_ctrl register + * Tsens wakeup control registers. + */ +typedef union { + struct { + /** wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * Lower threshold. + */ + uint32_t wakeup_th_low:8; + uint32_t reserved_8:6; + /** wakeup_th_high : R/W; bitpos: [21:14]; default: 255; + * Upper threshold. + */ + uint32_t wakeup_th_high:8; + uint32_t reserved_22:7; + /** wakeup_over_upper_th : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ + uint32_t wakeup_over_upper_th:1; + /** wakeup_en : R/W; bitpos: [30]; default: 0; + * Tsens wakeup enable. + */ + uint32_t wakeup_en:1; + /** wakeup_mode : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ + uint32_t wakeup_mode:1; + }; + uint32_t val; +} tsens_wakeup_ctrl_reg_t; + +/** Type of sample_rate register + * Hardware automatic sampling control registers. + */ +typedef union { + struct { + /** sample_rate : R/W; bitpos: [15:0]; default: 20; + * Hardware automatic sampling rate. + */ + uint32_t sample_rate:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} tsens_sample_rate_reg_t; + + +typedef struct { + volatile tsens_ctrl_reg_t ctrl; + uint32_t reserved_004; + volatile tsens_int_raw_reg_t int_raw; + volatile tsens_int_st_reg_t int_st; + volatile tsens_int_ena_reg_t int_ena; + volatile tsens_int_clr_reg_t int_clr; + volatile tsens_clk_conf_reg_t clk_conf; + volatile tsens_int_ena_w1ts_reg_t int_ena_w1ts; + volatile tsens_int_ena_w1tc_reg_t int_ena_w1tc; + volatile tsens_wakeup_ctrl_reg_t wakeup_ctrl; + volatile tsens_sample_rate_reg_t sample_rate; +} tsens_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(tsens_dev_t) == 0x2c, "Invalid size of tsens_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/twai_struct.h b/components/soc/esp32p4/include/soc/twai_struct.h new file mode 100644 index 0000000000..758d6462fc --- /dev/null +++ b/components/soc/esp32p4/include/soc/twai_struct.h @@ -0,0 +1,796 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ + uint32_t ts_counter_ovfl_int_st:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ + uint32_t ts_counter_ovfl_int_ena:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of data_0 register + * Data register 0. + */ +typedef union { + struct { + /** data_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t data_0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_0_reg_t; + +/** Type of data_1 register + * Data register 1. + */ +typedef union { + struct { + /** data_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ + uint32_t data_1:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_1_reg_t; + +/** Type of data_2 register + * Data register 2. + */ +typedef union { + struct { + /** data_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ + uint32_t data_2:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_2_reg_t; + +/** Type of data_3 register + * Data register 3. + */ +typedef union { + struct { + /** data_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ + uint32_t data_3:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_3_reg_t; + +/** Type of data_4 register + * Data register 4. + */ +typedef union { + struct { + /** data_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ + uint32_t data_4:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_4_reg_t; + +/** Type of data_5 register + * Data register 5. + */ +typedef union { + struct { + /** data_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ + uint32_t data_5:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_5_reg_t; + +/** Type of data_6 register + * Data register 6. + */ +typedef union { + struct { + /** data_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ + uint32_t data_6:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_6_reg_t; + +/** Type of data_7 register + * Data register 7. + */ +typedef union { + struct { + /** data_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ + uint32_t data_7:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_7_reg_t; + +/** Type of data_8 register + * Data register 8. + */ +typedef union { + struct { + /** data_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ + uint32_t data_8:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_8_reg_t; + +/** Type of data_9 register + * Data register 9. + */ +typedef union { + struct { + /** data_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ + uint32_t data_9:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_9_reg_t; + +/** Type of data_10 register + * Data register 10. + */ +typedef union { + struct { + /** data_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ + uint32_t data_10:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_10_reg_t; + +/** Type of data_11 register + * Data register 11. + */ +typedef union { + struct { + /** data_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ + uint32_t data_11:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_11_reg_t; + +/** Type of data_12 register + * Data register 12. + */ +typedef union { + struct { + /** data_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ + uint32_t data_12:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_12_reg_t; + + +/** Group: Timestamp Register */ +/** Type of timestamp_data register + * Timestamp data register + */ +typedef union { + struct { + /** timestamp_data : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ + uint32_t timestamp_data:32; + }; + uint32_t val; +} twai_timestamp_data_reg_t; + +/** Type of timestamp_prescaler register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_div_num : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ + uint32_t ts_div_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_timestamp_prescaler_reg_t; + +/** Type of timestamp_cfg register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_enable : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ + uint32_t ts_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_timestamp_cfg_reg_t; + + +typedef struct { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile twai_data_0_reg_t data_0; + volatile twai_data_1_reg_t data_1; + volatile twai_data_2_reg_t data_2; + volatile twai_data_3_reg_t data_3; + volatile twai_data_4_reg_t data_4; + volatile twai_data_5_reg_t data_5; + volatile twai_data_6_reg_t data_6; + volatile twai_data_7_reg_t data_7; + volatile twai_data_8_reg_t data_8; + volatile twai_data_9_reg_t data_9; + volatile twai_data_10_reg_t data_10; + volatile twai_data_11_reg_t data_11; + volatile twai_data_12_reg_t data_12; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; + volatile twai_timestamp_data_reg_t timestamp_data; + volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; + volatile twai_timestamp_cfg_reg_t timestamp_cfg; +} twai_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/uart_channel.h b/components/soc/esp32p4/include/soc/uart_channel.h new file mode 100644 index 0000000000..c04136b38d --- /dev/null +++ b/components/soc/esp32p4/include/soc/uart_channel.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6. + +#pragma once diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h new file mode 100644 index 0000000000..a5d49ea6e7 --- /dev/null +++ b/components/soc/esp32p4/include/soc/uart_pins.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/io_mux_reg.h" + +/* Specify the number of pins for UART */ +#define SOC_UART_PINS_COUNT (4) diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h new file mode 100644 index 0000000000..735f4ad96a --- /dev/null +++ b/components/soc/esp32p4/include/soc/uart_struct.h @@ -0,0 +1,1271 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/uhci_reg.h b/components/soc/esp32p4/include/soc/uhci_reg.h new file mode 100644 index 0000000000..84a244c530 --- /dev/null +++ b/components/soc/esp32p4/include/soc/uhci_reg.h @@ -0,0 +1,966 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * UHCI Configuration Register0 + */ +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 0; + * Select which uart to connect with GDMA. + */ +#define UHCI_UART_SEL 0x00000007U +#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S) +#define UHCI_UART_SEL_V 0x00000007U +#define UHCI_UART_SEL_S 2 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * UHCI Interrupt Raw Register + */ +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * UHCI Interrupt Status Register + */ +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * UHCI Interrupt Enable Register + */ +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * UHCI Interrupt Clear Register + */ +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * UHCI Configuration Register1 + */ +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * UHCI Receive Status Register + */ +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * UHCI Transmit Status Register + */ +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * UHCI Escapes Configuration Register0 + */ +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * UHCI Hung Configuration Register0 + */ +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * UHCI Ack Value Configuration Register0 + */ +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * UHCI Head Register + */ +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * UCHI Quick send Register + */ +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * UHCI Q0_WORD0 Quick Send Register + */ +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * UHCI Q0_WORD1 Quick Send Register + */ +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * UHCI Q1_WORD0 Quick Send Register + */ +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * UHCI Q1_WORD1 Quick Send Register + */ +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * UHCI Q2_WORD0 Quick Send Register + */ +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * UHCI Q2_WORD1 Quick Send Register + */ +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * UHCI Q3_WORD0 Quick Send Register + */ +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * UHCI Q3_WORD1 Quick Send Register + */ +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * UHCI Q4_WORD0 Quick Send Register + */ +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * UHCI Q4_WORD1 Quick Send Register + */ +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * UHCI Q5_WORD0 Quick Send Register + */ +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * UHCI Q5_WORD1 Quick Send Register + */ +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * UHCI Q6_WORD0 Quick Send Register + */ +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * UHCI Q6_WORD1 Quick Send Register + */ +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * UHCI Escapes Sequence Configuration Register0 + */ +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * UHCI Escapes Sequence Configuration Register1 + */ +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * UHCI Escapes Sequence Configuration Register2 + */ +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * UHCI Escapes Sequence Configuration Register3 + */ +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * UCHI Packet Length Configuration Register + */ +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * UHCI Version Register + */ +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/uhci_struct.h b/components/soc/esp32p4/include/soc/uhci_struct.h new file mode 100644 index 0000000000..850747a199 --- /dev/null +++ b/components/soc/esp32p4/include/soc/uhci_struct.h @@ -0,0 +1,843 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * UHCI Configuration Register0 + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart_sel : R/W; bitpos: [4:2]; default: 0; + * Select which uart to connect with GDMA. + */ + uint32_t uart_sel:3; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * UHCI Configuration Register1 + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * UHCI Escapes Configuration Register0 + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * UHCI Hung Configuration Register0 + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * UHCI Ack Value Configuration Register0 + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * UCHI Quick send Register + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_q0_word0 register + * UHCI Q0_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word0:32; + }; + uint32_t val; +} uhci_reg_q0_word0_reg_t; + +/** Type of reg_q0_word1 register + * UHCI Q0_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word1:32; + }; + uint32_t val; +} uhci_reg_q0_word1_reg_t; + +/** Type of reg_q1_word0 register + * UHCI Q1_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word0:32; + }; + uint32_t val; +} uhci_reg_q1_word0_reg_t; + +/** Type of reg_q1_word1 register + * UHCI Q1_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word1:32; + }; + uint32_t val; +} uhci_reg_q1_word1_reg_t; + +/** Type of reg_q2_word0 register + * UHCI Q2_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word0:32; + }; + uint32_t val; +} uhci_reg_q2_word0_reg_t; + +/** Type of reg_q2_word1 register + * UHCI Q2_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word1:32; + }; + uint32_t val; +} uhci_reg_q2_word1_reg_t; + +/** Type of reg_q3_word0 register + * UHCI Q3_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word0:32; + }; + uint32_t val; +} uhci_reg_q3_word0_reg_t; + +/** Type of reg_q3_word1 register + * UHCI Q3_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word1:32; + }; + uint32_t val; +} uhci_reg_q3_word1_reg_t; + +/** Type of reg_q4_word0 register + * UHCI Q4_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word0:32; + }; + uint32_t val; +} uhci_reg_q4_word0_reg_t; + +/** Type of reg_q4_word1 register + * UHCI Q4_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word1:32; + }; + uint32_t val; +} uhci_reg_q4_word1_reg_t; + +/** Type of reg_q5_word0 register + * UHCI Q5_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word0:32; + }; + uint32_t val; +} uhci_reg_q5_word0_reg_t; + +/** Type of reg_q5_word1 register + * UHCI Q5_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word1:32; + }; + uint32_t val; +} uhci_reg_q5_word1_reg_t; + +/** Type of reg_q6_word0 register + * UHCI Q6_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word0:32; + }; + uint32_t val; +} uhci_reg_q6_word0_reg_t; + +/** Type of reg_q6_word1 register + * UHCI Q6_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word1:32; + }; + uint32_t val; +} uhci_reg_q6_word1_reg_t; + +/** Type of esc_conf0 register + * UHCI Escapes Sequence Configuration Register0 + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * UHCI Escapes Sequence Configuration Register1 + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * UHCI Escapes Sequence Configuration Register2 + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * UHCI Escapes Sequence Configuration Register3 + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * UCHI Packet Length Configuration Register + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * UHCI Interrupt Raw Register + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * UHCI Interrupt Status Register + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * UHCI Interrupt Enable Register + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * UHCI Interrupt Clear Register + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * UHCI Receive Status Register + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * UHCI Transmit Status Register + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * UHCI Head Register + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UHCI Version Register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile uhci_reg_q0_word0_reg_t reg_q0_word0; + volatile uhci_reg_q0_word1_reg_t reg_q0_word1; + volatile uhci_reg_q1_word0_reg_t reg_q1_word0; + volatile uhci_reg_q1_word1_reg_t reg_q1_word1; + volatile uhci_reg_q2_word0_reg_t reg_q2_word0; + volatile uhci_reg_q2_word1_reg_t reg_q2_word1; + volatile uhci_reg_q3_word0_reg_t reg_q3_word0; + volatile uhci_reg_q3_word1_reg_t reg_q3_word1; + volatile uhci_reg_q4_word0_reg_t reg_q4_word0; + volatile uhci_reg_q4_word1_reg_t reg_q4_word1; + volatile uhci_reg_q5_word0_reg_t reg_q5_word0; + volatile uhci_reg_q5_word1_reg_t reg_q5_word1; + volatile uhci_reg_q6_word0_reg_t reg_q6_word0; + volatile uhci_reg_q6_word1_reg_t reg_q6_word1; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..478c734ea8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1282 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is + * received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_ECO_LOW_48_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 + +/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 + +/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) +/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_48_M (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S) +#define USB_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_48_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_48_M (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S) +#define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_48_S 1 + +/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) +/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 + +/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 + +/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register + * Reserved. + */ +#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_M (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_APB_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define USB_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_APB_M (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S) +#define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 + +/** USB_SERIAL_JTAG_SRAM_CTRL_REG register + * PPA SRAM Control Register + */ +#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) +/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ +#define USB_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S) +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..ed400ae548 --- /dev/null +++ b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,1044 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : RO; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is + * received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + +/** Type of eco_low_48 register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rnd_eco_low_48:32; + }; + uint32_t val; +} usb_serial_jtag_eco_low_48_reg_t; + +/** Type of eco_high_48 register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t rnd_eco_high_48:32; + }; + uint32_t val; +} usb_serial_jtag_eco_high_48_reg_t; + +/** Type of eco_low_apb register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rnd_eco_low_apb:32; + }; + uint32_t val; +} usb_serial_jtag_eco_low_apb_reg_t; + +/** Type of eco_high_apb register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t rnd_eco_high_apb:32; + }; + uint32_t val; +} usb_serial_jtag_eco_high_apb_reg_t; + +/** Type of sram_ctrl register + * PPA SRAM Control Register + */ +typedef union { + struct { + /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ + uint32_t mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_serial_jtag_sram_ctrl_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + +/** Type of eco_cell_ctrl_48 register + * Reserved. + */ +typedef union { + struct { + /** rdn_result_48 : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t rdn_result_48:1; + /** rdn_ena_48 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t rdn_ena_48:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_eco_cell_ctrl_48_reg_t; + +/** Type of eco_cell_ctrl_apb register + * Reserved. + */ +typedef union { + struct { + /** rdn_result_apb : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t rdn_result_apb:1; + /** rdn_ena_apb : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t rdn_ena_apb:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_eco_cell_ctrl_apb_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34676752; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48; + volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48; + volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48; + volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb; + volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb; + volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb; + volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/usbwrap_reg.h b/components/soc/esp32p4/include/soc/usbwrap_reg.h new file mode 100644 index 0000000000..68e7c5852b --- /dev/null +++ b/components/soc/esp32p4/include/soc/usbwrap_reg.h @@ -0,0 +1,182 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_WRAP_OTG_CONF_REG register + * USB wrapper configuration registers. + */ +#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0) +/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ +#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0)) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0 +/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ +#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1)) +#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S) +#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_VALUE_S 1 +/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ +#define USB_WRAP_PHY_SEL (BIT(2)) +#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S) +#define USB_WRAP_PHY_SEL_V 0x00000001U +#define USB_WRAP_PHY_SEL_S 2 +/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PD (BIT(3)) +#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S) +#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001U +#define USB_WRAP_DFIFO_FORCE_PD_S 3 +/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ +#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4)) +#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S) +#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001U +#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4 +/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ +#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5)) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5 +/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ +#define USB_WRAP_EXCHG_PINS (BIT(6)) +#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S) +#define USB_WRAP_EXCHG_PINS_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_S 6 +/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ +#define USB_WRAP_VREFH 0x00000003U +#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S) +#define USB_WRAP_VREFH_V 0x00000003U +#define USB_WRAP_VREFH_S 7 +/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ +#define USB_WRAP_VREFL 0x00000003U +#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S) +#define USB_WRAP_VREFL_V 0x00000003U +#define USB_WRAP_VREFL_S 9 +/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ +#define USB_WRAP_VREF_OVERRIDE (BIT(11)) +#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S) +#define USB_WRAP_VREF_OVERRIDE_V 0x00000001U +#define USB_WRAP_VREF_OVERRIDE_S 11 +/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ +#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12)) +#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S) +#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_WRAP_PAD_PULL_OVERRIDE_S 12 +/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DP_PULLUP (BIT(13)) +#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S) +#define USB_WRAP_DP_PULLUP_V 0x00000001U +#define USB_WRAP_DP_PULLUP_S 13 +/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DP_PULLDOWN (BIT(14)) +#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S) +#define USB_WRAP_DP_PULLDOWN_V 0x00000001U +#define USB_WRAP_DP_PULLDOWN_S 14 +/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DM_PULLUP (BIT(15)) +#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S) +#define USB_WRAP_DM_PULLUP_V 0x00000001U +#define USB_WRAP_DM_PULLUP_S 15 +/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DM_PULLDOWN (BIT(16)) +#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S) +#define USB_WRAP_DM_PULLDOWN_V 0x00000001U +#define USB_WRAP_DM_PULLDOWN_S 16 +/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ +#define USB_WRAP_PULLUP_VALUE (BIT(17)) +#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S) +#define USB_WRAP_PULLUP_VALUE_V 0x00000001U +#define USB_WRAP_PULLUP_VALUE_S 17 +/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ +#define USB_WRAP_USB_PAD_ENABLE (BIT(18)) +#define USB_WRAP_USB_PAD_ENABLE_M (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S) +#define USB_WRAP_USB_PAD_ENABLE_V 0x00000001U +#define USB_WRAP_USB_PAD_ENABLE_S 18 +/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ +#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19)) +#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S) +#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_AHB_CLK_FORCE_ON_S 19 +/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ +#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20)) +#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S) +#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_PHY_CLK_FORCE_ON_S 20 +/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PU (BIT(22)) +#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S) +#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001U +#define USB_WRAP_DFIFO_FORCE_PU_S 22 +/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ +#define USB_WRAP_CLK_EN (BIT(31)) +#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S) +#define USB_WRAP_CLK_EN_V 0x00000001U +#define USB_WRAP_CLK_EN_S 31 + +/** USB_WRAP_DATE_REG register + * Date register. + */ +#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc) +/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452; + * Date register. + */ +#define USB_WRAP_USB_WRAP_DATE 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_M (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S) +#define USB_WRAP_USB_WRAP_DATE_V 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/usbwrap_struct.h b/components/soc/esp32p4/include/soc/usbwrap_struct.h new file mode 100644 index 0000000000..d99347df55 --- /dev/null +++ b/components/soc/esp32p4/include/soc/usbwrap_struct.h @@ -0,0 +1,138 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: USB wrapper registers. */ +/** Type of otg_conf register + * USB wrapper configuration registers. + */ +typedef union { + struct { + /** srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ + uint32_t srp_sessend_override:1; + /** srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ + uint32_t srp_sessend_value:1; + /** phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ + uint32_t phy_sel:1; + /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pd:1; + /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ + uint32_t dbnce_fltr_bypass:1; + /** exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ + uint32_t ahb_clk_force_on:1; + /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ + uint32_t phy_clk_force_on:1; + uint32_t reserved_21:1; + /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pu:1; + uint32_t reserved_23:8; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452; + * Date register. + */ + uint32_t usb_wrap_date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct { + volatile usb_wrap_otg_conf_reg_t otg_conf; + uint32_t reserved_004[254]; + volatile usb_wrap_date_reg_t date; +} usb_wrap_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/interrupts.c b/components/soc/esp32p4/interrupts.c index e69de29bb2..30ae62bf57 100644 --- a/components/soc/esp32p4/interrupts.c +++ b/components/soc/esp32p4/interrupts.c @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "LP_RTC", + [1] = "LP_WDT", + [2] = "LP_TIMER0", + [3] = "LP_TIMER1", + [4] = "MB_HP", + [5] = "MB_LP", + [6] = "PMU0", + [7] = "PMU1", + [8] = "LP_ANA", + [9] = "LP_ADC", + [10] = "LP_GPIO", + [11] = "LP_I2C", + [12] = "LP_I2S", + [13] = "LP_SPI", + [14] = "LP_TOUCH", + [15] = "LP_TSENS", + [16] = "LP_UART", + [17] = "LP_EFUSE", + [18] = "LP_SW", + [19] = "LP_SYSREG", + [20] = "LP_HUK", + [21] = "SYS_ICM", + [22] = "USB_DEVICE", + [23] = "SDIO_HOST", + [24] = "GDMA", + [25] = "GPSPI2", + [26] = "GPSPI3", + [27] = "I2S0", + [28] = "I2S1", + [29] = "I2S2", + [30] = "UHCI0", + [31] = "UART0", + [32] = "UART1", + [33] = "UART2", + [34] = "UART3", + [35] = "UART4", + [36] = "LCD_CAM", + [37] = "ADC", + [38] = "PWM0", + [39] = "PWM1", + [40] = "CAN0", + [41] = "CAN1", + [42] = "CAN2", + [43] = "RMT", + [44] = "I2C0", + [45] = "I2C1", + [46] = "TG0_T0", + [47] = "TG0_T1", + [48] = "TG0_WDT", + [49] = "TG1_T0", + [50] = "TG1_T1", + [51] = "TG1_WDT", + [52] = "LEDC", + [53] = "SYSTIMER_TARGET0", + [54] = "SYSTIMER_TARGET1", + [55] = "SYSTIMER_TARGET2", + [56] = "AHB_PDMA_IN_CH0", + [57] = "AHB_PDMA_IN_CH1", + [58] = "AHB_PDMA_IN_CH2", + [59] = "AHB_PDMA_OUT_CH0", + [60] = "AHB_PDMA_OUT_CH1", + [61] = "AHB_PDMA_OUT_CH2", + [62] = "AXI_PDMA_IN_CH0", + [63] = "AXI_PDMA_IN_CH1", + [64] = "AXI_PDMA_IN_CH2", + [65] = "AXI_PDMA_OUT_CH0", + [66] = "AXI_PDMA_OUT_CH1", + [67] = "AXI_PDMA_OUT_CH2", + [68] = "RSA", + [69] = "AES", + [70] = "SHA", + [71] = "ECC", + [72] = "ECDSA", + [73] = "KM", + [74] = "GPIO_INT0", + [75] = "GPIO_INT1", + [76] = "GPIO_INT2", + [77] = "GPIO_INT3", + [78] = "GPIO_PAD_COMP", + [79] = "CPU_INT_FROM_CPU_0", + [80] = "CPU_INT_FROM_CPU_1", + [81] = "CPU_INT_FROM_CPU_2", + [82] = "CPU_INT_FROM_CPU_3", + [83] = "CACHE", + [84] = "FLASH_MSPI", + [85] = "CSI_BRIDGE", + [86] = "DSI_BRIDGE", + [87] = "CSI", + [88] = "DSI", + [89] = "GMII_PHY", + [90] = "LPI", + [91] = "PMT", + [92] = "SBD", + [93] = "USB_OTG", + [94] = "USB_OTG_ENDP_MULTI_PROC", + [95] = "JPEG", + [96] = "PPA", + [97] = "CORE0_TRACE", + [98] = "CORE1_TRACE", + [99] = "HP_CORE", + [100] = "ISP", + [101] = "I3C", + [102] = "I3C_SLV", + [103] = "USB_OTG11", + [104] = "DMA2D_IN_CH0", + [105] = "DMA2D_IN_CH1", + [106] = "DMA2D_OUT_CH0", + [107] = "DMA2D_OUT_CH1", + [108] = "DMA2D_OUT_CH2", + [109] = "PSRAM_MSPI", + [110] = "HP_SYSREG", + [111] = "PCNT", + [112] = "HP_PAU", + [113] = "HP_PARLIO_RX", + [114] = "HP_PARLIO_TX", + [115] = "H264_DMA2D_OUT_CH0", + [116] = "H264_DMA2D_OUT_CH1", + [117] = "H264_DMA2D_OUT_CH2", + [118] = "H264_DMA2D_OUT_CH3", + [119] = "H264_DMA2D_OUT_CH4", + [120] = "H264_DMA2D_IN_CH0", + [121] = "H264_DMA2D_IN_CH1", + [122] = "H264_DMA2D_IN_CH2", + [123] = "H264_DMA2D_IN_CH3", + [124] = "H264_DMA2D_IN_CH4", + [125] = "H264_DMA2D_IN_CH5", + [126] = "H264_REG", + [127] = "ASSIST_DEBUG", +}; diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld new file mode 100644 index 0000000000..0f3e87e1e5 --- /dev/null +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +PROVIDE ( UART0 = 0x500CA000 ); +PROVIDE ( UART1 = 0x500CB000 ); +PROVIDE ( UART2 = 0x500CC000 ); +PROVIDE ( UART3 = 0x500CD000 ); +PROVIDE ( UART4 = 0x500CE000 ); +PROVIDE ( SPIMEM0 = 0x5008C000 ); +PROVIDE ( SPIMEM1 = 0x5008D000 ); +PROVIDE ( I2C0 = 0x500C4000 ); +PROVIDE ( I2C1 = 0x500C5000 ); +PROVIDE ( UHCI0 = 0x500DF000 ); +PROVIDE ( RMT = 0x500D4000 ); +PROVIDE ( RMTMEM = 0x500D4800 ); +PROVIDE ( LEDC = 0x500D3000 ); +PROVIDE ( TIMERG0 = 0x500C2000 ); +PROVIDE ( TIMERG1 = 0x500C3000 ); +PROVIDE ( SYSTIMER = 0x500E2000 ); +PROVIDE ( TWAI0 = 0x500D7000 ); +PROVIDE ( I2S0 = 0x500C6000 ); +PROVIDE ( I2S1 = 0x500C7000 ); +PROVIDE ( I2S2 = 0x500C8000 ); +PROVIDE ( TWAI1 = 0x500D8000 ); +PROVIDE ( TWAI2 = 0x500D9000 ); +PROVIDE ( ADC = 0x500DE000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x500D2000 ); +PROVIDE ( SDMMC = 0x50083000 ); + +PROVIDE ( INTMTX = 0x500D6000 ); +PROVIDE ( PCNT = 0x500C9000 ); +PROVIDE ( SOC_ETM = 0x500D5000 ); +PROVIDE ( MCPWM0 = 0x500C0000 ); +PROVIDE ( MCPWM1 = 0x500C1000 ); +PROVIDE ( PARL_IO = 0x500CF000 ); +PROVIDE ( PVT_MONITOR = 0x5009E000 ); + +PROVIDE ( GDMA = 0x50081000 ); +PROVIDE ( GPSPI2 = 0x500D0000 ); +PROVIDE ( GPSPI3 = 0x500D1000 ); + +PROVIDE ( AES = 0x50090000 ); +PROVIDE ( SHA = 0x50091000 ); +PROVIDE ( RSA = 0x50092000 ); +PROVIDE ( ECC = 0x50093000 ); +PROVIDE ( DS = 0x50094000 ); +PROVIDE ( HMAC = 0x50095000 ); +PROVIDE ( ECDSA = 0x50096000 ); + +PROVIDE ( IOMUX = 0x500e1000 ); +PROVIDE ( GPIO = 0x500E0000 ); +PROVIDE ( SIGMADELTA = 0x500E0F00 ); + +PROVIDE ( HP_SYSTEM = 0x500E5000 ); +PROVIDE ( TEE = 0x60098000 ); /* TODO: IDF-7542 */ +PROVIDE ( HP_APM = 0x60099000 ); /* TODO: IDF-7542 */ + +PROVIDE ( PMU = 0x50115000 ); +PROVIDE ( LP_AON_CLKRST = 0x50111000 ); +PROVIDE ( EFUSE = 0x5012D000 ); +PROVIDE ( LP_TIMER = 0x50112000 ); +PROVIDE ( LP_UART = 0x50121000 ); +PROVIDE ( LP_I2C = 0x50122000 ); +PROVIDE ( LP_SPI = 0x50123000 ); +PROVIDE ( LP_WDT = 0x50116000 ); +PROVIDE ( LP_I2S = 0x50125000 ); +PROVIDE ( LP_GPIO = 0x5012A000 ); +PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); +PROVIDE ( LP_ANA_PERI = 0x50113000 ); +PROVIDE ( LP_APM = 0x600B3800 ); /* TODO: IDF-7542 */ +PROVIDE ( AHB_DMA = 0x50085000 ); +PROVIDE ( AXI_DMA = 0x5008a000 ); +PROVIDE ( LCD_CAM = 0x500dc000 ); +PROVIDE ( LP_IOMUX = 0x5012B000 ); + +PROVIDE ( MIPI_CSI_BRIDGE = 0x5009F800 ); +PROVIDE ( MIPI_CSI_HOST = 0x5009F000 ); +PROVIDE ( MIPI_DSI_BRIDGE = 0x500A0800 ); +PROVIDE ( MIPI_DSI_HOST = 0x500A0000 ); +PROVIDE ( MIPI_CSI_MEM = 0x50104000 ); +PROVIDE ( MIPI_DSI_MEM = 0x50105000 ); +PROVIDE ( ISP = 0x500A1000 ); +PROVIDE ( GDMA = 0x50081000 ); +PROVIDE ( I3C_MST = 0x500DA000 ); +PROVIDE ( I3C_MST_MEM = 0x500DA000 ); +PROVIDE ( I3C_SLV = 0x500DB000 ); + +PROVIDE ( PPA = 0x50087000 ); +PROVIDE ( DMA2D = 0x50088000 ); +PROVIDE ( JPEG = 0x50086000 ); diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c new file mode 100644 index 0000000000..867ad4bfd6 --- /dev/null +++ b/components/soc/esp32p4/ledc_periph.c @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + +}; diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c new file mode 100644 index 0000000000..fea03e5a8d --- /dev/null +++ b/components/soc/esp32p4/mcpwm_periph.c @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/mcpwm_periph.h" +#include "soc/gpio_sig_map.h" + +const mcpwm_signal_conn_t mcpwm_periph_signals = { + +}; diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c new file mode 100644 index 0000000000..827c614415 --- /dev/null +++ b/components/soc/esp32p4/parlio_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/parlio_periph.h" +#include "soc/gpio_sig_map.h" + +const parlio_signal_conn_t parlio_periph_signals = { + +}; diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c new file mode 100644 index 0000000000..ca289c2e28 --- /dev/null +++ b/components/soc/esp32p4/pcnt_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/pcnt_periph.h" +#include "soc/gpio_sig_map.h" + +const pcnt_signal_conn_t pcnt_periph_signals = { + +}; diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c new file mode 100644 index 0000000000..650b4ddcf1 --- /dev/null +++ b/components/soc/esp32p4/rmt_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/rmt_periph.h" +#include "soc/gpio_sig_map.h" + +const rmt_signal_conn_t rmt_periph_signals = { + +}; diff --git a/components/soc/esp32p4/sdio_slave_periph.c b/components/soc/esp32p4/sdio_slave_periph.c new file mode 100644 index 0000000000..e5f5a19fc5 --- /dev/null +++ b/components/soc/esp32p4/sdio_slave_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/sdio_slave_periph.h" +#include "soc/sdio_slave_pins.h" + +const sdio_slave_slot_info_t sdio_slave_slot_info[1] = { + +}; diff --git a/components/soc/esp32p4/sdm_periph.c b/components/soc/esp32p4/sdm_periph.c new file mode 100644 index 0000000000..da3f711ad8 --- /dev/null +++ b/components/soc/esp32p4/sdm_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/sdm_periph.h" +#include "soc/gpio_sig_map.h" + +const sigma_delta_signal_conn_t sigma_delta_periph_signals = { + +}; diff --git a/components/soc/esp32p4/sdmmc_periph.c b/components/soc/esp32p4/sdmmc_periph.c new file mode 100644 index 0000000000..1fb72fb2c3 --- /dev/null +++ b/components/soc/esp32p4/sdmmc_periph.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/sdmmc_periph.h" +// ESP32P4-TODO: need new iomux and sig map +const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS] = { + +}; + +const sdmmc_slot_io_info_t sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS] = { + +}; + +const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS] = { + +}; diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c new file mode 100644 index 0000000000..3534bb9428 --- /dev/null +++ b/components/soc/esp32p4/spi_periph.c @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/spi_periph.h" +#include "stddef.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + +}; diff --git a/components/soc/esp32p4/temperature_sensor_periph.c b/components/soc/esp32p4/temperature_sensor_periph.c new file mode 100644 index 0000000000..a9812ecc72 --- /dev/null +++ b/components/soc/esp32p4/temperature_sensor_periph.c @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/temperature_sensor_periph.h" + +const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { + +}; diff --git a/components/soc/esp32p4/timer_periph.c b/components/soc/esp32p4/timer_periph.c new file mode 100644 index 0000000000..96eb286c20 --- /dev/null +++ b/components/soc/esp32p4/timer_periph.c @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/timer_periph.h" + +const timer_group_signal_conn_t timer_group_periph_signals = { + +}; diff --git a/components/soc/esp32p4/twai_periph.c b/components/soc/esp32p4/twai_periph.c new file mode 100644 index 0000000000..061cd4a4d7 --- /dev/null +++ b/components/soc/esp32p4/twai_periph.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/twai_periph.h" +#include "soc/gpio_sig_map.h" + +const twai_controller_signal_conn_t twai_controller_periph_signals = { + +}; diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c index e69de29bb2..2b0c63eb1b 100644 --- a/components/soc/esp32p4/uart_periph.c +++ b/components/soc/esp32p4/uart_periph.c @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/uart_periph.h" + +/* + Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { + +}; diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h index cb4de430f1..80fd7187e1 100644 --- a/components/soc/include/soc/rtc_cntl_periph.h +++ b/components/soc/include/soc/rtc_cntl_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,14 +10,27 @@ // TODO: IDF-5645 #if CONFIG_IDF_TARGET_ESP32C6 +#include "soc/lp_io_reg.h" +#include "soc/lp_io_struct.h" #include "soc/lp_aon_reg.h" + +// ESP32H2-TODO: IDF-6327 +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "soc/lp_aon_reg.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "soc/lp_gpio_reg.h" +#include "soc/lp_gpio_struct.h" +#include "soc/lp_iomux_reg.h" +#include "soc/lp_iomux_struct.h" +#endif + +// TODO: IDF-5645 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 #include "soc/lp_analog_peri_reg.h" #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" #include "soc/lp_i2c_reg.h" #include "soc/lp_i2c_struct.h" -#include "soc/lp_io_reg.h" -#include "soc/lp_io_struct.h" #include "soc/lp_timer_reg.h" #include "soc/lp_timer_struct.h" #include "soc/lp_uart_reg.h" @@ -26,7 +39,6 @@ #include "soc/lp_wdt_struct.h" #elif CONFIG_IDF_TARGET_ESP32H2 // ESP32H2-TODO: IDF-6327 -#include "soc/lp_aon_reg.h" #include "soc/lp_analog_peri_reg.h" #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index ab8b54c347..5752cbd62f 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -186,3 +186,7 @@ tools/test_apps/system/unicore_bootloader: enable: - if: SOC_CPU_CORES_NUM > 1 reason: the test should be run on multicore chips + disable: + - if: IDF_TARGET in ["esp32p4"] # TODO: IDF-7692 + temporary: true + reason: not supported on esp32p4 yet