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Brownout works (in as far brownout can work...), int wdt works.

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This commit is contained in:
Jeroen Domburg
2016-10-21 19:30:29 +08:00
parent 53146799a0
commit ae5c563080
5 changed files with 23 additions and 26 deletions
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9
components/esp32/Kconfig
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@@ -151,16 +151,13 @@ config INT_WDT
interrupt handler did not return. It will try to invoke the panic handler first and failing that interrupt handler did not return. It will try to invoke the panic handler first and failing that
reset the SoC. reset the SoC.
config INT_WDT_TIMEOUT_MS_MIN
default (2000/CONFIG_FREERTOS_HZ)
config INT_WDT_TIMEOUT_MS config INT_WDT_TIMEOUT_MS
int "Interrupt watchdog timeout (ms)" int "Interrupt watchdog timeout (ms)"
depends on INT_WDT depends on INT_WDT
default 100 default 10
range INT_WDT_TIMEOUT_MS_MIN 10000 range INT_WDT_TIMEOUT_MIN 10000
help help
The timeout of the watchdog, in miliseconds. The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
config TASK_WDT config TASK_WDT
bool "Task watchdog" bool "Task watchdog"

12
components/esp32/brownout.c
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@@ -23,15 +23,9 @@
void esp_brownout_init() { void esp_brownout_init() {
// WRITE_PERI_REG(RTC_CNTL_BROWN_OUT_REG,
// RTC_CNTL_BROWN_OUT_ENA | (CONFIG_BROWNOUT_DET_LVL << RTC_CNTL_DBROWN_OUT_THRES_S) |
// RTC_CNTL_BROWN_OUT_RST_ENA | (((CONFIG_BROWNOUT_DET_RESETDELAY*150)/1000) << RTC_CNTL_BROWN_OUT_RST_WAIT_S) |
// RTC_CNTL_BROWN_OUT_PD_RF_ENA|RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA);
WRITE_PERI_REG(RTC_CNTL_BROWN_OUT_REG, WRITE_PERI_REG(RTC_CNTL_BROWN_OUT_REG,
RTC_CNTL_BROWN_OUT_ENA | (4 << RTC_CNTL_DBROWN_OUT_THRES_S) | RTC_CNTL_BROWN_OUT_ENA | (CONFIG_BROWNOUT_DET_LVL << RTC_CNTL_DBROWN_OUT_THRES_S) |
RTC_CNTL_BROWN_OUT_RST_ENA | (0x3FF << RTC_CNTL_BROWN_OUT_RST_WAIT_S) | RTC_CNTL_BROWN_OUT_RST_ENA | (((CONFIG_BROWNOUT_DET_RESETDELAY*150)/1000) << RTC_CNTL_BROWN_OUT_RST_WAIT_S) |
RTC_CNTL_BROWN_OUT_PD_RF_ENA | RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA); RTC_CNTL_BROWN_OUT_PD_RF_ENA|RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA);
} }

6
components/esp32/cpu_start.c
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@@ -44,6 +44,8 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp_brownout.h" #include "esp_brownout.h"
#include "esp_int_wdt.h"
#include "esp_task_wdt.h"
void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))); void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
void start_cpu0_default(void) IRAM_ATTR; void start_cpu0_default(void) IRAM_ATTR;
@@ -143,10 +145,10 @@ void start_cpu0_default(void)
esp_brownout_init(); esp_brownout_init();
#endif #endif
#if CONFIG_INT_WDT #if CONFIG_INT_WDT
int_wdt_init() int_wdt_init();
#endif #endif
#if CONFIG_TASK_WDT #if CONFIG_TASK_WDT
task_wdt_init() task_wdt_init();
#endif #endif
xTaskCreatePinnedToCore(&main_task, "main", xTaskCreatePinnedToCore(&main_task, "main",

9
components/esp32/int_wdt.c
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@@ -47,11 +47,6 @@ This uses the TIMERG1 WDT.
#define WDT_WRITE_KEY 0x50D83AA1 #define WDT_WRITE_KEY 0x50D83AA1
static void esp_int_wdt_isr(void *arg) {
abort();
}
void int_wdt_init() { void int_wdt_init() {
TIMERG1.wdt_wprotect=WDT_WRITE_KEY; TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
TIMERG1.wdt_config0.sys_reset_length=7; //3.2uS TIMERG1.wdt_config0.sys_reset_length=7; //3.2uS
@@ -67,7 +62,9 @@ void int_wdt_init() {
TIMERG1.wdt_wprotect=0; TIMERG1.wdt_wprotect=0;
ESP_INTR_DISABLE(WDT_INT_NUM); ESP_INTR_DISABLE(WDT_INT_NUM);
intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM); intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
xt_set_interrupt_handler(WDT_INT_NUM, int_wdt_isr, NULL); //We do not register a handler for the interrupt because it is interrupt level 4 which
//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
//this interrupt.
ESP_INTR_ENABLE(WDT_INT_NUM); ESP_INTR_ENABLE(WDT_INT_NUM);
} }

13
components/freertos/xtensa_vectors.S
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@@ -339,12 +339,12 @@ _xt_panic:
rsr a0, EXCSAVE_1 /* save interruptee's a0 */ rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0 s32i a0, sp, XT_STK_A0
/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ /* Set up PS for C, disable all interrupts, and clear EXCM. */
movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE movi a0, PS_INTLEVEL(7) | PS_UM | PS_WOE
wsr a0, PS wsr a0, PS
//Call panic handler //Call panic handler
mov a2,sp mov a6,sp
call4 panicHandler call4 panicHandler
1: j 1b /* loop infinitely */ 1: j 1b /* loop infinitely */
@@ -1607,6 +1607,13 @@ _xt_highint4:
ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
*/ */
/* On the ESP32, this level is used for the INT_WDT handler. If that triggers, the program is stuck with interrupts
off and the CPU should panic. */
rsr a0, EXCSAVE_4
wsr a0, EXCSAVE_1 /* panic handler reads this register */
call0 _xt_panic
.align 4 .align 4
.L_xt_highint4_exit: .L_xt_highint4_exit:
rsr a0, EXCSAVE_4 /* restore a0 */ rsr a0, EXCSAVE_4 /* restore a0 */