From c56eb8646bbaf3078389737623da2ab20c106e57 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 22 Feb 2023 12:33:02 +0800 Subject: [PATCH] g0: resolve MMU_PAGE_SIZE not defined in g0 build issue --- components/esp_hw_support/Kconfig | 40 ----------------- components/soc/CMakeLists.txt | 5 +++ components/soc/Kconfig | 45 +++++++++++++++++++ .../soc/esp32/include/soc/ext_mem_defs.h | 2 +- .../soc/esp32c2/include/soc/ext_mem_defs.h | 24 ++++++---- .../soc/esp32c3/include/soc/ext_mem_defs.h | 2 +- .../soc/esp32c6/include/soc/ext_mem_defs.h | 28 +++++++----- components/soc/esp32c6/include/soc/soc.h | 2 +- .../soc/esp32h2/include/soc/ext_mem_defs.h | 29 +++++++----- components/soc/esp32h2/include/soc/soc.h | 2 +- .../soc/esp32h4/include/soc/ext_mem_defs.h | 2 +- .../soc/esp32s2/include/soc/ext_mem_defs.h | 2 +- .../soc/esp32s3/include/soc/ext_mem_defs.h | 2 +- .../system/g0_components/CMakeLists.txt | 7 --- 14 files changed, 105 insertions(+), 87 deletions(-) create mode 100644 components/soc/Kconfig diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 3bd8928347..b15cf931e6 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -181,46 +181,6 @@ menu "Hardware Settings" Note that, this option only controls the ETM related driver log, won't affect other drivers. endmenu # ETM Configuration - menu "MMU Config" - # This Config is used for configure the MMU. - # Be configured based on flash size selection. - # Invisible to users. - - config MMU_PAGE_SIZE_16KB - bool - default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB - default n - - config MMU_PAGE_SIZE_32KB - bool - default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB - default n - - config MMU_PAGE_SIZE_64KB - bool - default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB - default n - - config MMU_PAGE_MODE - string - default "8KB" if MMU_PAGE_SIZE_8KB - default "16KB" if MMU_PAGE_SIZE_16KB - default "32KB" if MMU_PAGE_SIZE_32KB - default "64KB" if MMU_PAGE_SIZE_64KB - - config MMU_PAGE_SIZE - # Some chips support different flash MMU page sizes: 64k, 32k, 16k. - # Since the number of MMU pages is limited, the maximum flash size supported - # for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best - # use of small flash sizes (reducing the wasted space due to alignment), we - # need to use the smallest possible MMU page size for the given flash size. - hex - default 0x2000 if MMU_PAGE_SIZE_8KB - default 0x4000 if MMU_PAGE_SIZE_16KB - default 0x8000 if MMU_PAGE_SIZE_32KB - default 0x10000 if MMU_PAGE_SIZE_64KB - endmenu - menu "GDMA Configuration" depends on SOC_GDMA_SUPPORTED config GDMA_CTRL_FUNC_IN_IRAM diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index e40c7c04b9..162664116c 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -115,6 +115,11 @@ idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} LDFRAGMENTS "linker.lf") +# For an embedded system, the MMU page size should always be defined statically +# For IDF, we define it according to the Flash size that user selects +# Replace this value in an adaptive way, if Kconfig isn't available on your platform +target_compile_definitions(${COMPONENT_LIB} INTERFACE SOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE) + if(target STREQUAL "esp32") # esp_dport_access_reg_read is added as an undefined symbol because otherwise # the linker can ignore dport_access.c as it would no other files depending on any symbols in it. diff --git a/components/soc/Kconfig b/components/soc/Kconfig new file mode 100644 index 0000000000..26e916a637 --- /dev/null +++ b/components/soc/Kconfig @@ -0,0 +1,45 @@ +menu "SoC Settings" + # No visible menu/configs for now + visible if 0 + + menu "MMU Config" + # This Config is used for configure the MMU. + # Be configured based on flash size selection. + # Invisible to users. + + config MMU_PAGE_SIZE_16KB + bool + default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB + default n + + config MMU_PAGE_SIZE_32KB + bool + default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB + default n + + config MMU_PAGE_SIZE_64KB + bool + default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB + default n + + config MMU_PAGE_MODE + string + default "8KB" if MMU_PAGE_SIZE_8KB + default "16KB" if MMU_PAGE_SIZE_16KB + default "32KB" if MMU_PAGE_SIZE_32KB + default "64KB" if MMU_PAGE_SIZE_64KB + + config MMU_PAGE_SIZE + # Some chips support different flash MMU page sizes: 64k, 32k, 16k. + # Since the number of MMU pages is limited, the maximum flash size supported + # for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best + # use of small flash sizes (reducing the wasted space due to alignment), we + # need to use the smallest possible MMU page size for the given flash size. + hex + default 0x2000 if MMU_PAGE_SIZE_8KB + default 0x4000 if MMU_PAGE_SIZE_16KB + default 0x8000 if MMU_PAGE_SIZE_32KB + default 0x10000 if MMU_PAGE_SIZE_64KB + endmenu + +endmenu diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index 305b97e72b..3d60f8a3fc 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -41,7 +41,7 @@ extern "C" { /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 256 * 64KB, means MMU can support 16MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 256 diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index c343b118b6..533fa55243 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -7,26 +7,32 @@ #include -#include "sdkconfig.h" #include "esp_bit_defs.h" #ifdef __cplusplus extern "C" { #endif +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif /*IRAM0 is connected with Cache IBUS0*/ #define IRAM0_ADDRESS_LOW 0x4037C000 #define IRAM0_ADDRESS_HIGH 0x403C0000 #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages +#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages /*DRAM0 is connected with Cache DBUS0*/ #define DRAM0_ADDRESS_LOW 0x3FCA0000 #define DRAM0_ADDRESS_HIGH 0x3FCE0000 #define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 -#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages +#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages #define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) @@ -82,7 +88,7 @@ extern "C" { /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 64 * 64KB, means MMU can support 4MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 64 @@ -90,7 +96,7 @@ extern "C" { * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ -#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * 64 - 1) +#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * 64 - 1) //MMU entry num #define MMU_ENTRY_NUM 64 @@ -109,7 +115,7 @@ extern "C" { /*------------------------------------------------------------------------------ * MMU Linear Address *----------------------------------------------------------------------------*/ -#if (CONFIG_MMU_PAGE_SIZE == 0x10000) +#if (SOC_MMU_PAGE_SIZE == 0x10000) /** * - 64KB MMU page size: the last 0xFFFF, which is the offset * - 64 MMU entries, needs 0x3F to hold it. @@ -118,7 +124,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x8000) +#elif (SOC_MMU_PAGE_SIZE == 0x8000) /** * - 32KB MMU page size: the last 0x7FFF, which is the offset * - 64 MMU entries, needs 0x3F to hold it. @@ -127,7 +133,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x4000) +#elif (SOC_MMU_PAGE_SIZE == 0x4000) /** * - 16KB MMU page size: the last 0x3FFF, which is the offset * - 64 MMU entries, needs 0x3F to hold it. @@ -135,7 +141,7 @@ extern "C" { * Therefore, 0xF,FFFF */ #define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFF -#endif //CONFIG_MMU_PAGE_SIZE +#endif //SOC_MMU_PAGE_SIZE /** * - If high linear address isn't 0, this means MMU can recognize these addresses diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index d14e74daf3..82eae100a7 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -77,7 +77,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0xff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 256 * 64KB, means MMU can support 16MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 256 diff --git a/components/soc/esp32c6/include/soc/ext_mem_defs.h b/components/soc/esp32c6/include/soc/ext_mem_defs.h index 9be2303cbd..8e5022a23a 100644 --- a/components/soc/esp32c6/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c6/include/soc/ext_mem_defs.h @@ -3,19 +3,25 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _CACHE_MEMORY_H_ -#define _CACHE_MEMORY_H_ +#pragma once #include "esp_bit_defs.h" -#include "sdkconfig.h" #ifdef __cplusplus extern "C" { #endif +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) +#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) #define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range #define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range @@ -74,7 +80,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0x1ff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 256 * 64KB, means MMU can support 16MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 256 @@ -85,7 +91,7 @@ extern "C" { * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ -#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1) +#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1) #define CACHE_MEMORY_IBANK0_ADDR 0x40800000 @@ -96,7 +102,7 @@ extern "C" { /*------------------------------------------------------------------------------ * MMU Linear Address *----------------------------------------------------------------------------*/ -#if (CONFIG_MMU_PAGE_SIZE == 0x10000) +#if (SOC_MMU_PAGE_SIZE == 0x10000) /** * - 64KB MMU page size: the last 0xFFFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -105,7 +111,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x8000) +#elif (SOC_MMU_PAGE_SIZE == 0x8000) /** * - 32KB MMU page size: the last 0x7FFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -114,7 +120,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x4000) +#elif (SOC_MMU_PAGE_SIZE == 0x4000) /** * - 16KB MMU page size: the last 0x3FFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -122,7 +128,7 @@ extern "C" { * Therefore, 0x1F,FFFF */ #define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF -#endif //CONFIG_MMU_PAGE_SIZE +#endif //SOC_MMU_PAGE_SIZE /** * - If high linear address isn't 0, this means MMU can recognize these addresses @@ -152,5 +158,3 @@ _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_ #ifdef __cplusplus } #endif - -#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 6917112e0f..44096ea86d 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -155,7 +155,7 @@ */ #define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) +#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8)) #define SOC_DROM_LOW SOC_IROM_LOW #define SOC_DROM_HIGH SOC_IROM_HIGH #define SOC_IROM_MASK_LOW 0x40000000 diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index 3d9abf1274..6d5e3ce451 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -3,18 +3,25 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _CACHE_MEMORY_H_ -#define _CACHE_MEMORY_H_ +#pragma once #include "esp_bit_defs.h" -#include "sdkconfig.h" #ifdef __cplusplus extern "C" { #endif +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + + #define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) +#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) #define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range #define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range @@ -73,7 +80,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0x1ff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 256 * 64KB, means MMU can support 16MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 256 @@ -84,7 +91,7 @@ extern "C" { * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ -#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1) +#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1) #define CACHE_MEMORY_IBANK0_ADDR 0x40800000 @@ -95,7 +102,7 @@ extern "C" { /*------------------------------------------------------------------------------ * MMU Linear Address *----------------------------------------------------------------------------*/ -#if (CONFIG_MMU_PAGE_SIZE == 0x10000) +#if (SOC_MMU_PAGE_SIZE == 0x10000) /** * - 64KB MMU page size: the last 0xFFFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -104,7 +111,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x8000) +#elif (SOC_MMU_PAGE_SIZE == 0x8000) /** * - 32KB MMU page size: the last 0x7FFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -113,7 +120,7 @@ extern "C" { */ #define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF -#elif (CONFIG_MMU_PAGE_SIZE == 0x4000) +#elif (SOC_MMU_PAGE_SIZE == 0x4000) /** * - 16KB MMU page size: the last 0x3FFF, which is the offset * - 128 MMU entries, needs 0x7F to hold it. @@ -121,7 +128,7 @@ extern "C" { * Therefore, 0x1F,FFFF */ #define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF -#endif //CONFIG_MMU_PAGE_SIZE +#endif //SOC_MMU_PAGE_SIZE /** * - If high linear address isn't 0, this means MMU can recognize these addresses @@ -151,5 +158,3 @@ _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_ #ifdef __cplusplus } #endif - -#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index b9a913a95b..2b61061dcc 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -152,7 +152,7 @@ */ #define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) +#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8)) #define SOC_DROM_LOW SOC_IROM_LOW #define SOC_DROM_HIGH SOC_IROM_HIGH #define SOC_IROM_MASK_LOW 0x40000000 diff --git a/components/soc/esp32h4/include/soc/ext_mem_defs.h b/components/soc/esp32h4/include/soc/ext_mem_defs.h index 1c2eae3293..0bde2f7b4f 100644 --- a/components/soc/esp32h4/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h4/include/soc/ext_mem_defs.h @@ -77,7 +77,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0xff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 256 * 64KB, means MMU can support 16MB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 256 diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index a46b22584d..b7f4af4d00 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -106,7 +106,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0x3fff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 16384 * 64KB, means MMU can support 1GB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 16384 diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index 9d55694007..b5ba5e38b3 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -77,7 +77,7 @@ extern "C" { #define MMU_VALID_VAL_MASK 0x3fff /** * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: * 16384 * 64KB, means MMU can support 1GB paddr at most */ #define MMU_MAX_PADDR_PAGE_NUM 16384 diff --git a/tools/test_apps/system/g0_components/CMakeLists.txt b/tools/test_apps/system/g0_components/CMakeLists.txt index 5b71435e8d..4751f860e9 100644 --- a/tools/test_apps/system/g0_components/CMakeLists.txt +++ b/tools/test_apps/system/g0_components/CMakeLists.txt @@ -26,13 +26,6 @@ idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1) project(g0_components) -# As a workaround, we need to define the MMU page size here, until MMU hal-driver -# is refactored. -# IDF-5219 -if(CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE) - idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_MMU_PAGE_SIZE=0x10000" APPEND) -endif() - if(CONFIG_IDF_TARGET_ESP32C2) # clk_tree hal-driver needs CONFIG_XTAL_FREQ idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_XTAL_FREQ=26" APPEND)