From 622593220102e88860a722a25c1180c3e5e54793 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 29 Jul 2020 22:03:46 +0800 Subject: [PATCH 01/11] bootloader_support: add esp32-s3 initial support --- components/bootloader_support/component.mk | 4 +- .../include/bootloader_common.h | 2 + .../include/esp_flash_encrypt.h | 2 +- .../src/bootloader_clock_init.c | 22 +- .../src/bootloader_common.c | 2 + .../src/bootloader_console.c | 6 +- .../src/bootloader_efuse_esp32s3.c | 21 + .../bootloader_support/src/bootloader_flash.c | 43 +- .../src/bootloader_flash_config_esp32s3.c | 80 ++++ .../src/bootloader_random.c | 41 +- .../src/bootloader_utility.c | 25 +- .../src/esp32s2/bootloader_esp32s2.c | 5 +- .../src/esp32s3/bootloader_esp32s3.c | 341 +++++++++++++++ .../src/esp32s3/bootloader_sha.c | 48 ++ .../src/esp32s3/flash_encrypt.c | 414 ++++++++++++++++++ .../src/esp32s3/secure_boot.c | 325 ++++++++++++++ .../src/esp32s3/secure_boot_signatures.c | 93 ++++ .../bootloader_support/src/esp_image_format.c | 5 +- .../bootloader_support/src/flash_encrypt.c | 3 + .../bootloader_support/src/flash_qio_mode.c | 5 +- components/esp32s3/CMakeLists.txt | 1 - components/esp32s3/clk.c | 6 - components/esp_common/CMakeLists.txt | 15 +- components/esp_common/Kconfig | 5 +- components/esp_common/component.mk | 4 + components/esp_common/include/esp_pm.h | 2 + components/esp_common/src/fpga_overrides.c | 57 +++ components/esp_common/src/int_wdt.c | 2 +- components/esp_common/src/mac_addr.c | 8 +- components/esp_rom/include/esp32s3/rom/aes.h | 2 - components/esp_rom/include/esp32s3/rom/rtc.h | 3 +- components/esp_system/port/esp32/clk.c | 4 +- components/esp_system/port/esp32s2/clk.c | 4 +- .../esp_system/port/esp32s3/CMakeLists.txt | 2 + components/esp_system/port/esp32s3/clk.c | 12 +- .../esp_system/port/esp32s3/reset_reason.c | 13 +- 36 files changed, 1550 insertions(+), 77 deletions(-) create mode 100644 components/bootloader_support/src/bootloader_efuse_esp32s3.c create mode 100644 components/bootloader_support/src/bootloader_flash_config_esp32s3.c create mode 100644 components/bootloader_support/src/esp32s3/bootloader_esp32s3.c create mode 100644 components/bootloader_support/src/esp32s3/bootloader_sha.c create mode 100644 components/bootloader_support/src/esp32s3/flash_encrypt.c create mode 100644 components/bootloader_support/src/esp32s3/secure_boot.c create mode 100644 components/bootloader_support/src/esp32s3/secure_boot_signatures.c create mode 100644 components/esp_common/src/fpga_overrides.c diff --git a/components/bootloader_support/component.mk b/components/bootloader_support/component.mk index dd1c16ceb0..1d678b7a0a 100644 --- a/components/bootloader_support/component.mk +++ b/components/bootloader_support/component.mk @@ -24,7 +24,9 @@ COMPONENT_OBJEXCLUDE := src/bootloader_init.o \ endif COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \ - src/bootloader_efuse_esp32s2.o + src/bootloader_flash_config_esp32s3.o \ + src/bootloader_efuse_esp32s2.o \ + src/bootloader_efuse_esp32s3.o \ ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME ifndef CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME diff --git a/components/bootloader_support/include/bootloader_common.h b/components/bootloader_support/include/bootloader_common.h index eaab4c2625..baf36702c1 100644 --- a/components/bootloader_support/include/bootloader_common.h +++ b/components/bootloader_support/include/bootloader_common.h @@ -21,6 +21,8 @@ #include "esp32/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" #endif #ifdef __cplusplus diff --git a/components/bootloader_support/include/esp_flash_encrypt.h b/components/bootloader_support/include/esp_flash_encrypt.h index fc1b3729d1..ef3b802715 100644 --- a/components/bootloader_support/include/esp_flash_encrypt.h +++ b/components/bootloader_support/include/esp_flash_encrypt.h @@ -49,7 +49,7 @@ typedef enum { */ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_enabled(void) { - uint32_t flash_crypt_cnt; + uint32_t flash_crypt_cnt = 0; #if CONFIG_IDF_TARGET_ESP32 flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); #elif CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 9d641ddd63..283e207f83 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -24,10 +24,13 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" #define CPU_RESET_REASON RTC_SW_CPU_RESET +#elif CONFIG_IDF_TARGET_ESP32S3 +#define CPU_RESET_REASON RTC_SW_CPU_RESET +#include "esp32s3/rom/rtc.h" #endif #include "esp_rom_uart.h" -void bootloader_clock_configure(void) +__attribute__((weak)) void bootloader_clock_configure(void) { // ROM bootloader may have put a lot of text into UART0 FIFO. // Wait for it to be printed. @@ -38,7 +41,7 @@ void bootloader_clock_configure(void) /* Set CPU to 80MHz. Keep other clocks unmodified. */ int cpu_freq_mhz = 80; - + #if CONFIG_IDF_TARGET_ESP32 /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to * 240 MHz may cause the chip to lock up (see section 3.5 of the errata @@ -51,23 +54,24 @@ void bootloader_clock_configure(void) cpu_freq_mhz = 240; } #endif + if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); - #if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; - #endif +#endif /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */ clk_cfg.cpu_freq_mhz = cpu_freq_mhz; clk_cfg.slow_freq = rtc_clk_slow_freq_get(); clk_cfg.fast_freq = rtc_clk_fast_freq_get(); rtc_clk_init(clk_cfg); - /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable - * it here. Usually it needs some time to start up, so we amortize at least - * part of the start up time by enabling 32k XTAL early. - * App startup code will wait until the oscillator has started up. - */ } + /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable + * it here. Usually it needs some time to start up, so we amortize at least + * part of the start up time by enabling 32k XTAL early. + * App startup code will wait until the oscillator has started up. + */ #if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL if (!rtc_clk_32k_enabled()) { rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES); diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c index cc57d13273..729da47b2b 100644 --- a/components/bootloader_support/src/bootloader_common.c +++ b/components/bootloader_support/src/bootloader_common.c @@ -21,6 +21,8 @@ #include "esp32/rom/spi_flash.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/spi_flash.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" #endif #include "esp_rom_crc.h" #include "esp_rom_gpio.h" diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 1609994a6b..b6730cebdc 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -74,7 +74,11 @@ void bootloader_console_init(void) #endif // CONFIG_ESP_CONSOLE_UART_CUSTOM // Set configured UART console baud rate - esp_rom_uart_set_clock_baudrate(uart_num, rtc_clk_apb_freq_get(), CONFIG_ESP_CONSOLE_UART_BAUDRATE); + uint32_t clock_hz = rtc_clk_apb_freq_get(); +#if CONFIG_IDF_TARGET_ESP32S3 + clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM +#endif + esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); } #endif // CONFIG_ESP_CONSOLE_UART diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s3.c b/components/bootloader_support/src/bootloader_efuse_esp32s3.c new file mode 100644 index 0000000000..0096c64315 --- /dev/null +++ b/components/bootloader_support/src/bootloader_efuse_esp32s3.c @@ -0,0 +1,21 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +uint8_t bootloader_common_get_chip_revision(void) +{ + /* No other revisions for ESP32-S3 */ + return 0; +} diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index d91c1cb4f3..45f6f5645b 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -32,7 +32,9 @@ #endif #if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/spi_flash.h" //For SPI_Encrypt_Write +#include "esp32s2/rom/spi_flash.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" #endif @@ -87,7 +89,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool if (write_encrypted) { #if CONFIG_IDF_TARGET_ESP32 return spi_flash_write_encrypted(dest_addr, src, size); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 return SPI_Encrypt_Write(dest_addr, src, size); #endif } else { @@ -115,6 +117,10 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size) #include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/cache.h" #include "soc/cache_memory.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "soc/cache_memory.h" #endif static const char *TAG = "bootloader_flash"; @@ -126,7 +132,7 @@ static const char *TAG = "bootloader_flash"; #define MMU_SIZE (0x320000) #define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) #define FLASH_READ_VADDR MMU_BLOCK50_VADDR -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 /* Use first 63 blocks in MMU for bootloader_mmap, 63th block for bootloader_flash_read */ @@ -171,6 +177,9 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) #elif CONFIG_IDF_TARGET_ESP32S2 uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t autoload = Cache_Suspend_DCache(); + Cache_Invalidate_DCache_All(); #endif ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x", src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned ); @@ -178,6 +187,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count); #elif CONFIG_IDF_TARGET_ESP32S2 int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); +#elif CONFIG_IDF_TARGET_ESP32S3 + int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); @@ -185,6 +196,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif return NULL; } @@ -192,6 +205,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif mapped = true; @@ -212,6 +227,11 @@ void bootloader_munmap(const void *mapping) Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); Cache_MMU_Init(); +#elif CONFIG_IDF_TARGET_ESP32S3 + //TODO, save the autoload value. + Cache_Suspend_DCache(); + Cache_Invalidate_DCache_All(); + Cache_MMU_Init(); #endif mapped = false; current_read_mapping = UINT32_MAX; @@ -239,12 +259,16 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s Cache_Flush(0); #elif CONFIG_IDF_TARGET_ESP32S2 uint32_t autoload = Cache_Suspend_ICache(); +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t autoload = Cache_Suspend_DCache(); #endif esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size); #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif return spi_to_esp_err(r); @@ -266,12 +290,17 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest #elif CONFIG_IDF_TARGET_ESP32S2 uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t autoload = Cache_Suspend_DCache(); + Cache_Invalidate_DCache_All(); #endif ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping); #if CONFIG_IDF_TARGET_ESP32 int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1); #elif CONFIG_IDF_TARGET_ESP32S2 int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); +#elif CONFIG_IDF_TARGET_ESP32S3 + int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); @@ -279,6 +308,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif return ESP_FAIL; } @@ -287,6 +318,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif } map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at)); @@ -342,8 +375,8 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool if (write_encrypted) { #if CONFIG_IDF_TARGET_ESP32 return spi_to_esp_err(esp_rom_spiflash_write_encrypted(dest_addr, src, size)); -#elif CONFIG_IDF_TARGET_ESP32S2 - // TODO: use the same ROM AP here +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + // TODO: use the same ROM API here return spi_to_esp_err(SPI_Encrypt_Write(dest_addr, src, size)); #endif } else { diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c new file mode 100644 index 0000000000..0dc0e3f5f1 --- /dev/null +++ b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c @@ -0,0 +1,80 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include +#include "string.h" +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp32s3/rom/spi_flash.h" +#include "soc/efuse_reg.h" +#include "soc/spi_reg.h" +#include "soc/spi_mem_reg.h" +#include "soc/spi_caps.h" +#include "flash_qio_mode.h" +#include "bootloader_flash_config.h" +#include "bootloader_common.h" + +#define FLASH_IO_MATRIX_DUMMY_40M 0 +#define FLASH_IO_MATRIX_DUMMY_80M 0 +#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3 + +void bootloader_flash_update_id() +{ + g_rom_flashchip.device_id = bootloader_read_flash_id(); +} + +void IRAM_ATTR bootloader_flash_cs_timing_config() +{ + SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); +} + +void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) +{ + uint32_t spi_clk_div = 0; + switch (pfhdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_80M: + spi_clk_div = 1; + break; + case ESP_IMAGE_SPI_SPEED_40M: + spi_clk_div = 2; + break; + case ESP_IMAGE_SPI_SPEED_26M: + spi_clk_div = 3; + break; + case ESP_IMAGE_SPI_SPEED_20M: + spi_clk_div = 4; + break; + default: + break; + } + esp_rom_spiflash_config_clk(spi_clk_div, 0); +} + +void IRAM_ATTR bootloader_flash_set_dummy_out(void) +{ + REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); + REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); +} + +void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) +{ + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); +} diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index 2a1d242d4b..a5a55d0c37 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -22,7 +22,7 @@ #include "soc/i2s_periph.h" #include "esp_log.h" #include "soc/io_mux_reg.h" -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #include "soc/apb_saradc_reg.h" #endif @@ -30,13 +30,13 @@ #include "esp_system.h" #include "driver/periph_ctrl.h" -void bootloader_fill_random(void *buffer, size_t length) + __attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length) { return esp_fill_random(buffer, length); } #else -void bootloader_fill_random(void *buffer, size_t length) + __attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length) { uint8_t *buffer_bytes = (uint8_t *)buffer; uint32_t random; @@ -71,7 +71,11 @@ void bootloader_random_enable(void) never disabled while the CPU is running), this is a "belts and braces" type check. */ #ifdef BOOTLOADER_BUILD +#if CONFIG_IDF_TARGET_ESP32S3 + SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_RNG_EN); +#else DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); +#endif #else periph_module_enable(PERIPH_RNG_MODULE); #endif // BOOTLOADER_BUILD @@ -105,6 +109,17 @@ void bootloader_random_enable(void) DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP); +#elif CONFIG_IDF_TARGET_ESP32S3 + /* Disable IO1 digital function for random function. */ + PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U); + WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF); + + SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); + SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); + CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP); #endif // Test pattern configuration byte 0xAD: @@ -119,7 +134,7 @@ void bootloader_random_enable(void) SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); @@ -147,15 +162,18 @@ void bootloader_random_enable(void) SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S); #endif +#if !CONFIG_IDF_TARGET_ESP32S3 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); +#endif } void bootloader_random_disable(void) { +#if !CONFIG_IDF_TARGET_ESP32S3 /* Reset some i2s configuration (possibly redundant as we reset entire I2S peripheral further down). */ CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); @@ -165,10 +183,14 @@ void bootloader_random_disable(void) CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); - +#endif /* Disable i2s clock */ #ifdef BOOTLOADER_BUILD +#if CONFIG_IDF_TARGET_ESP32S3 + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN); +#else DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); +#endif #else periph_module_disable(PERIPH_I2S0_MODULE); #endif // BOOTLOADER_BUILD @@ -177,7 +199,7 @@ void bootloader_random_disable(void) #if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); #endif @@ -187,7 +209,7 @@ void bootloader_random_disable(void) CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S); SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); @@ -199,8 +221,13 @@ void bootloader_random_disable(void) /* Reset i2s peripheral */ #ifdef BOOTLOADER_BUILD +#if CONFIG_IDF_TARGET_ESP32S3 + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST); + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST); +#else DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); +#endif #else periph_module_reset(PERIPH_I2S0_MODULE); #endif diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 6c4662695e..badbc8d3d6 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -20,6 +20,7 @@ #include "esp_log.h" #include "esp_rom_sys.h" +#include "esp_rom_uart.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" #include "esp32/rom/spi_flash.h" @@ -32,10 +33,16 @@ #include "esp32s2/rom/secure_boot.h" #include "soc/extmem_reg.h" #include "soc/cache_memory.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/rtc.h" +#include "esp32s3/rom/secure_boot.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #else #error "Unsupported IDF_TARGET" #endif -#include "esp_rom_uart.h" #include "soc/soc.h" #include "soc/cpu.h" @@ -683,6 +690,9 @@ static void set_cache_and_start_app( #elif CONFIG_IDF_TARGET_ESP32S2 uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t autoload = Cache_Suspend_DCache(); + Cache_Invalidate_DCache_All(); #endif /* Clear the MMU entries that are already set up, @@ -692,7 +702,7 @@ static void set_cache_and_start_app( for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) { DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; } -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; } @@ -705,6 +715,8 @@ static void set_cache_and_start_app( rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); #elif CONFIG_IDF_TARGET_ESP32S2 rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); +#elif CONFIG_IDF_TARGET_ESP32S3 + rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); #if CONFIG_IDF_TARGET_ESP32 @@ -728,6 +740,8 @@ static void set_cache_and_start_app( REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1); } rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); +#elif CONFIG_IDF_TARGET_ESP32S3 + rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); #if CONFIG_IDF_TARGET_ESP32 @@ -743,11 +757,18 @@ static void set_cache_and_start_app( DPORT_APP_CACHE_MASK_DRAM1 ); #elif CONFIG_IDF_TARGET_ESP32S2 REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 ); +#elif CONFIG_IDF_TARGET_ESP32S3 + REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS); +#if !CONFIG_FREERTOS_UNICORE + REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS); +#endif #endif #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(autoload); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(autoload); #endif // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 47c1a18020..aa089531c3 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -18,9 +18,6 @@ #include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" -#include "esp_rom_gpio.h" -#include "esp_rom_efuse.h" -#include "esp32s2/rom/spi_flash.h" #include "bootloader_init.h" #include "bootloader_clock.h" @@ -29,6 +26,8 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp_rom_sys.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/spi_flash.h" diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c new file mode 100644 index 0000000000..f6e0c2e853 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -0,0 +1,341 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_image_format.h" +#include "flash_qio_mode.h" +#include "soc/efuse_reg.h" +#include "soc/gpio_sig_map.h" +#include "soc/io_mux_reg.h" +#include "soc/assist_debug_reg.h" +#include "soc/cpu.h" +#include "soc/dport_reg.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/spi_periph.h" +#include "soc/extmem_reg.h" + +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" +#include "esp_rom_sys.h" +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" + +#include "bootloader_common.h" +#include "bootloader_init.h" +#include "bootloader_clock.h" +#include "bootloader_flash_config.h" +#include "bootloader_mem.h" +#include "bootloader_console.h" +#include "bootloader_flash_priv.h" + + +static const char *TAG = "boot.esp32s3"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void bootloader_reset_mmu(void) +{ + Cache_Suspend_DCache(); + Cache_Invalidate_DCache_All(); + Cache_MMU_Init(); + + REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); +#if !CONFIG_FREERTOS_UNICORE + REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); +#endif +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + uint32_t autoload = Cache_Suspend_DCache(); + // Set flash chip size + esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); + // TODO: set mode + // TODO: set frequency + Cache_Resume_DCache(autoload); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_40M: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_26M: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_20M: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_80M: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +static esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + + esp_rom_spiflash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} + +static void wdt_reset_cpu0_info_enable(void) +{ + REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG); + REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); + REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1); + REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1); +} + +static void wdt_reset_info_dump(int cpu) +{ + uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0, + lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0; + const char *cpu_name = cpu ? "APP" : "PRO"; + + stat = 0xdeadbeef; + pid = 0; + if (cpu == 0) { + inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG); + dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG); + data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG); + pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG); + lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG); + lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); + lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); + } else { +#if !CONFIG_FREERTOS_UNICORE + inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG); + dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG); + data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG); + pc = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG); + lsstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG); + lsaddr = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG); + lsdata = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG); +#else + ESP_LOGE(TAG, "WDT reset info: %s CPU not support!\n", cpu_name); + return; +#endif + } + + ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat); + ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr); + ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata); +} + +static void bootloader_check_wdt_reset(void) +{ + int wdt_rst = 0; + RESET_REASON rst_reas[2]; + + rst_reas[0] = rtc_get_reset_reason(0); + if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET || + rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) { + ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); + wdt_rst = 1; + } + if (wdt_rst) { + // if reset by WDT dump info from trace port + wdt_reset_info_dump(0); + wdt_reset_info_dump(1); + } + wdt_reset_cpu0_info_enable(); +} + +static void bootloader_super_wdt_auto_feed(void) +{ + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); +} + +esp_err_t bootloader_init(void) +{ + esp_err_t ret = ESP_OK; + bootloader_super_wdt_auto_feed(); + // protect memory region + bootloader_init_mem(); + /* check that static RAM is after the stack */ +#ifndef NDEBUG + { + assert(&_bss_start <= &_bss_end); + assert(&_data_start <= &_data_end); + } +#endif + // clear bss section + bootloader_clear_bss_section(); + // reset MMU + bootloader_reset_mmu(); + // config clock + bootloader_clock_configure(); + // initialize console, from now on, we can use esp_log + bootloader_console_init(); + /* print 2nd bootloader banner */ + bootloader_print_banner(); + // update flash ID + bootloader_flash_update_id(); + // read bootloader header + if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { + goto err; + } + // read chip revision and check if it's compatible to bootloader + if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { + goto err; + } + // initialize spi flash + if ((ret = bootloader_init_spi_flash()) != ESP_OK) { + goto err; + } + // check whether a WDT reset happend + bootloader_check_wdt_reset(); + // config WDT + bootloader_config_wdt(); + // enable RNG early entropy source + bootloader_enable_random(); +err: + return ret; +} diff --git a/components/bootloader_support/src/esp32s3/bootloader_sha.c b/components/bootloader_support/src/esp32s3/bootloader_sha.c new file mode 100644 index 0000000000..b0d5b9b124 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/bootloader_sha.c @@ -0,0 +1,48 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "bootloader_sha.h" +#include +#include +#include +#include + +#include "esp32s3/rom/sha.h" + +static SHA_CTX ctx; + +bootloader_sha256_handle_t bootloader_sha256_start() +{ + // Enable SHA hardware + ets_sha_enable(); + ets_sha_init(&ctx, SHA2_256); + return &ctx; // Meaningless non-NULL value +} + +void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len) +{ + assert(handle != NULL); + assert(data_len % 4 == 0); + ets_sha_update(&ctx, data, data_len, false); +} + +void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest) +{ + assert(handle != NULL); + + if (digest == NULL) { + bzero(&ctx, sizeof(ctx)); + return; + } + ets_sha_finish(&ctx, digest); +} diff --git a/components/bootloader_support/src/esp32s3/flash_encrypt.c b/components/bootloader_support/src/esp32s3/flash_encrypt.c new file mode 100644 index 0000000000..52e08293e0 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/flash_encrypt.c @@ -0,0 +1,414 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include "bootloader_flash_priv.h" +#include "bootloader_random.h" +#include "bootloader_utility.h" +#include "esp_image_format.h" +#include "esp_flash_encrypt.h" +#include "esp_flash_partitions.h" +#include "esp_secure_boot.h" +#include "esp_log.h" +#include "esp32s3/rom/secure_boot.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/efuse.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "hal/wdt_hal.h" + +static const char *TAG = "flash_encrypt"; + +/* Static functions for stages of flash encryption */ +static esp_err_t initialise_flash_encryption(void); +static esp_err_t encrypt_flash_contents(uint32_t flash_crypt_cnt, bool flash_crypt_wr_dis) __attribute__((unused)); +static esp_err_t encrypt_bootloader(void); +static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions); +static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition); + +esp_err_t esp_flash_encrypt_check_and_update(void) +{ + uint8_t flash_crypt_wr_dis = 0; + uint32_t flash_crypt_cnt = 0; + + esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, 3); + esp_efuse_read_field_blob(ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT, &flash_crypt_wr_dis, 1); + + ESP_LOGV(TAG, "SPI_BOOT_CRYPT_CNT 0x%x", flash_crypt_cnt); + ESP_LOGV(TAG, "EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT 0x%x", flash_crypt_wr_dis); + + if (__builtin_parity(flash_crypt_cnt) == 1) { + /* Flash is already encrypted */ + int left = (flash_crypt_cnt == 1) ? 1 : 0; + if (flash_crypt_wr_dis) { + left = 0; /* can't update FLASH_CRYPT_CNT, no more flashes */ + } + ESP_LOGI(TAG, "flash encryption is enabled (%d plaintext flashes left)", left); + return ESP_OK; + } else { + +#ifndef CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED + /* Flash is not encrypted, so encrypt it! */ + return encrypt_flash_contents(flash_crypt_cnt, flash_crypt_wr_dis); +#else + ESP_LOGE(TAG, "flash encryption is not enabled, and SECURE_FLASH_REQUIRE_ALREADY_ENABLED " + "is set, refusing to boot."); + return ESP_ERR_INVALID_STATE; +#endif // CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED + + } +} + +static bool s_key_dis_read(ets_efuse_block_t block) +{ + // TODO: eFuse support on ESP32-S3 + // unsigned key_num = block - ETS_EFUSE_BLOCK_KEY0; + // return REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG, EFUSE_RD_DIS) & (EFUSE_RD_DIS_KEY0 << key_num); + return true; +} + +static bool s_key_dis_write(ets_efuse_block_t block) +{ + // TODO: eFuse support on ESP32-S3 + // unsigned key_num = block - ETS_EFUSE_BLOCK_KEY0; + // return REG_GET_FIELD(EFUSE_RD_WR_DIS_REG, EFUSE_WR_DIS) & (EFUSE_WR_DIS_KEY0 << key_num); + return true; +} + +static esp_err_t check_and_generate_encryption_keys(void) +{ + esp_err_t err = ESP_ERR_INVALID_STATE; + ets_efuse_block_t aes_128_key_block; + ets_efuse_block_t aes_256_key_block_1; + ets_efuse_block_t aes_256_key_block_2; + + bool has_aes128 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, &aes_128_key_block); + bool has_aes256_1 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1, &aes_256_key_block_1); + bool has_aes256_2 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2, &aes_256_key_block_2); + bool has_key = has_aes128 || (has_aes256_1 && has_aes256_2); + bool dis_write = false; + bool dis_read = false; + + // If there are keys set, they must be write and read protected! + if(has_key && has_aes128) { + dis_write = s_key_dis_write(aes_128_key_block); + dis_read = s_key_dis_read(aes_128_key_block); + } else if (has_key && has_aes256_1 && has_aes256_2) { + dis_write = s_key_dis_write(aes_256_key_block_1) && s_key_dis_write(aes_256_key_block_2); + dis_read = s_key_dis_read(aes_256_key_block_1) && s_key_dis_read(aes_256_key_block_2); + } + + if (!has_key && (has_aes256_1 || has_aes256_2)) { + ESP_LOGE(TAG, "Invalid efuse key blocks: Both AES-256 key blocks must be set."); + return ESP_ERR_INVALID_STATE; + } + + if(has_key && (!dis_read || !dis_write)) { + ESP_LOGE(TAG, "Invalid key state, a key was set but not read and write protected."); + return ESP_ERR_INVALID_STATE; + } + + if(!has_key && !dis_write && !dis_read) { + ESP_LOGI(TAG, "Generating new flash encryption key..."); +#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_AES256 + const unsigned BLOCKS_NEEDED = 2; + const ets_efuse_purpose_t PURPOSE_START = ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1; + const ets_efuse_purpose_t PURPOSE_END = ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2; +#else + const unsigned BLOCKS_NEEDED = 1; + const ets_efuse_purpose_t PURPOSE_START = ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY; + const ets_efuse_purpose_t PURPOSE_END = ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY; +#endif + + if (ets_efuse_count_unused_key_blocks() < BLOCKS_NEEDED) { + ESP_LOGE(TAG, "Not enough free efuse key blocks (need %d) to continue", BLOCKS_NEEDED); + return ESP_ERR_INVALID_STATE; + } + + for(ets_efuse_purpose_t purpose = PURPOSE_START; purpose <= PURPOSE_END; purpose++) { + uint32_t buf[8] = {0}; + bootloader_fill_random(buf, sizeof(buf)); + ets_efuse_block_t block = ets_efuse_find_unused_key_block(); + ESP_LOGD(TAG, "Writing ETS_EFUSE_BLOCK_KEY%d with purpose %d", + block - ETS_EFUSE_BLOCK_KEY0, purpose); + + /* Note: everything else in this function is deferred as a batch write, but we write the + key (and write protect it) immediately as it's too fiddly to manage unused key blocks, etc. + in bootloader size footprint otherwise. */ + int r = ets_efuse_write_key(block, purpose, buf, sizeof(buf)); + if (r != 0) { + ESP_LOGE(TAG, "Failed to write efuse block %d with purpose %d. Can't continue.", + block, purpose); + return ESP_FAIL; + } + + /* assuming numbering of esp_efuse_block_t matches ets_efuse_block_t */ + _Static_assert((int)EFUSE_BLK_KEY0 == (int)ETS_EFUSE_BLOCK_KEY0, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + _Static_assert((int)EFUSE_BLK_KEY1 == (int)ETS_EFUSE_BLOCK_KEY1, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + _Static_assert((int)EFUSE_BLK_KEY2 == (int)ETS_EFUSE_BLOCK_KEY2, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + _Static_assert((int)EFUSE_BLK_KEY3 == (int)ETS_EFUSE_BLOCK_KEY3, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + _Static_assert((int)EFUSE_BLK_KEY4 == (int)ETS_EFUSE_BLOCK_KEY4, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + _Static_assert((int)EFUSE_BLK_KEY5 == (int)ETS_EFUSE_BLOCK_KEY5, "esp_efuse_block_t doesn't match ets_efuse_block_t"); + + // protect this block against reading after key is set (writing is done by ets_efuse_write_key) + err = esp_efuse_set_read_protect(block); + if(err != ESP_OK) { + ESP_LOGE(TAG, "Failed to set read protect to efuse block %d. Can't continue.", block); + return err; + } + } + ESP_LOGD(TAG, "Key generation complete"); + return ESP_OK; + + } else { + ESP_LOGI(TAG, "Using pre-existing key in efuse"); + return ESP_OK; + } +} + +static esp_err_t initialise_flash_encryption(void) +{ + esp_efuse_batch_write_begin(); /* Batch all efuse writes at the end of this function */ + + esp_err_t key_state = check_and_generate_encryption_keys(); + if(key_state != ESP_OK) { + esp_efuse_batch_write_cancel(); + return key_state; + } + +#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC + ESP_LOGI(TAG, "Disable UART bootloader encryption..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); +#else + ESP_LOGW(TAG, "Not disabling UART bootloader encryption"); +#endif + +#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE + ESP_LOGI(TAG, "Disable UART bootloader cache..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); +#else + ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED"); +#endif + +#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG + ESP_LOGI(TAG, "Disable JTAG..."); + esp_efuse_write_field_bit(ESP_EFUSE_HARD_DIS_JTAG); +#else + ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); +#endif + + esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT); + + esp_err_t err = esp_efuse_batch_write_commit(); + + return err; +} + +/* Encrypt all flash data that should be encrypted */ +static esp_err_t encrypt_flash_contents(uint32_t spi_boot_crypt_cnt, bool flash_crypt_wr_dis) +{ + esp_err_t err; + esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES]; + int num_partitions; + + /* If the last spi_boot_crypt_cnt bit is burned or write-disabled, the + device can't re-encrypt itself. */ + if (flash_crypt_wr_dis) { + ESP_LOGE(TAG, "Cannot re-encrypt data SPI_BOOT_CRYPT_CNT 0x%02x write disabled %d", spi_boot_crypt_cnt, flash_crypt_wr_dis); + return ESP_FAIL; + } + + if (spi_boot_crypt_cnt == 0) { + /* Very first flash of encrypted data: generate keys, etc. */ + err = initialise_flash_encryption(); + if (err != ESP_OK) { + return err; + } + } + + err = encrypt_bootloader(); + if (err != ESP_OK) { + return err; + } + + err = encrypt_and_load_partition_table(partition_table, &num_partitions); + if (err != ESP_OK) { + return err; + } + + /* Now iterate the just-loaded partition table, looking for entries to encrypt */ + for (int i = 0; i < num_partitions; i++) { + err = encrypt_partition(i, &partition_table[i]); + if (err != ESP_OK) { + return err; + } + } + + ESP_LOGD(TAG, "All flash regions checked for encryption pass"); + + /* Set least significant 0-bit in spi_boot_crypt_cnt */ + int ffs_inv = __builtin_ffs((~spi_boot_crypt_cnt) & 0x7); + /* ffs_inv shouldn't be zero, as zero implies spi_boot_crypt_cnt == 0xFF */ + uint32_t new_spi_boot_crypt_cnt = (1 << (ffs_inv - 1)); + ESP_LOGD(TAG, "SPI_BOOT_CRYPT_CNT 0x%x -> 0x%x", spi_boot_crypt_cnt, new_spi_boot_crypt_cnt + spi_boot_crypt_cnt); + + esp_efuse_write_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &new_spi_boot_crypt_cnt, 3); + +#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE + //Secure SPI boot cnt after its update if needed. + const uint32_t spi_boot_cnt_wr_dis = 1; + ESP_LOGI(TAG, "Write protecting SPI_CRYPT_CNT eFuse"); + esp_efuse_write_field_blob(ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT, &spi_boot_cnt_wr_dis, 1); +#endif + ESP_LOGI(TAG, "Flash encryption completed"); + + return ESP_OK; +} + +static esp_err_t encrypt_bootloader(void) +{ + esp_err_t err; + uint32_t image_length; + /* Check for plaintext bootloader (verification will fail if it's already encrypted) */ + if (esp_image_verify_bootloader(&image_length) == ESP_OK) { + ESP_LOGD(TAG, "bootloader is plaintext. Encrypting..."); + +#if CONFIG_SECURE_BOOT_V2_ENABLED + // Account for the signature sector after the bootloader + image_length = (image_length + FLASH_SECTOR_SIZE - 1) & ~(FLASH_SECTOR_SIZE - 1); + image_length += FLASH_SECTOR_SIZE; + if (ESP_BOOTLOADER_OFFSET + image_length > ESP_PARTITION_TABLE_OFFSET) { + ESP_LOGE(TAG, "Bootloader is too large to fit Secure Boot V2 signature sector and partition table (configured offset 0x%x)", ESP_PARTITION_TABLE_OFFSET); + return ESP_ERR_INVALID_SIZE; + } +#endif // CONFIG_SECURE_BOOT_V2_ENABLED + + err = esp_flash_encrypt_region(ESP_BOOTLOADER_OFFSET, image_length); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to encrypt bootloader in place: 0x%x", err); + return err; + } + + ESP_LOGI(TAG, "bootloader encrypted successfully"); + return err; + } + else { + ESP_LOGW(TAG, "no valid bootloader was found"); + return ESP_ERR_NOT_FOUND; + } +} + +static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions) +{ + esp_err_t err; + /* Check for plaintext partition table */ + err = bootloader_flash_read(ESP_PARTITION_TABLE_OFFSET, partition_table, ESP_PARTITION_TABLE_MAX_LEN, false); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to read partition table data"); + return err; + } + if (esp_partition_table_verify(partition_table, false, num_partitions) == ESP_OK) { + ESP_LOGD(TAG, "partition table is plaintext. Encrypting..."); + esp_err_t err = esp_flash_encrypt_region(ESP_PARTITION_TABLE_OFFSET, + FLASH_SECTOR_SIZE); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to encrypt partition table in place. %x", err); + return err; + } + } + else { + ESP_LOGE(TAG, "Failed to read partition table data - not plaintext?"); + return ESP_ERR_INVALID_STATE; + } + + /* Valid partition table loded */ + ESP_LOGI(TAG, "partition table encrypted and loaded successfully"); + return ESP_OK; +} + + +static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition) +{ + esp_err_t err; + bool should_encrypt = (partition->flags & PART_FLAG_ENCRYPTED); + + if (partition->type == PART_TYPE_APP) { + /* check if the partition holds a valid unencrypted app */ + esp_image_metadata_t data_ignored; + err = esp_image_verify(ESP_IMAGE_VERIFY, + &partition->pos, + &data_ignored); + should_encrypt = (err == ESP_OK); + } else if (partition->type == PART_TYPE_DATA && partition->subtype == PART_SUBTYPE_DATA_OTA) { + /* check if we have ota data partition and the partition should be encrypted unconditionally */ + should_encrypt = true; + } + + if (!should_encrypt) { + return ESP_OK; + } + else { + /* should_encrypt */ + ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%x (length 0x%x)...", index, partition->pos.offset, partition->pos.size); + + err = esp_flash_encrypt_region(partition->pos.offset, partition->pos.size); + ESP_LOGI(TAG, "Done encrypting"); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to encrypt partition %d", index); + } + return err; + } +} + + +esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length) +{ + esp_err_t err; + uint32_t buf[FLASH_SECTOR_SIZE / sizeof(uint32_t)]; + + if (src_addr % FLASH_SECTOR_SIZE != 0) { + ESP_LOGE(TAG, "esp_flash_encrypt_region bad src_addr 0x%x",src_addr); + return ESP_FAIL; + } + + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) { + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_feed(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + + uint32_t sec_start = i + src_addr; + err = bootloader_flash_read(sec_start, buf, FLASH_SECTOR_SIZE, false); + if (err != ESP_OK) { + goto flash_failed; + } + err = bootloader_flash_erase_sector(sec_start / FLASH_SECTOR_SIZE); + if (err != ESP_OK) { + goto flash_failed; + } + err = bootloader_flash_write(sec_start, buf, FLASH_SECTOR_SIZE, true); + if (err != ESP_OK) { + goto flash_failed; + } + } + return ESP_OK; + + flash_failed: + ESP_LOGE(TAG, "flash operation failed: 0x%x", err); + return err; +} diff --git a/components/bootloader_support/src/esp32s3/secure_boot.c b/components/bootloader_support/src/esp32s3/secure_boot.c new file mode 100644 index 0000000000..0406c48381 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/secure_boot.c @@ -0,0 +1,325 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include + +#include "esp_log.h" +#include "esp_secure_boot.h" +#include "soc/efuse_reg.h" + +#include "bootloader_flash_priv.h" +#include "bootloader_sha.h" +#include "bootloader_utility.h" + +#include "esp_rom_crc.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" + +#include "esp32s3/rom/efuse.h" +#include "esp32s3/rom/secure_boot.h" + +static const char *TAG = "secure_boot_v2"; +#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) + +#define SIG_BLOCK_MAGIC_BYTE 0xe7 +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 + +#define DIGEST_LEN 32 + +/* A signature block is valid when it has correct magic byte, crc and image digest. */ +static esp_err_t validate_signature_block(const ets_secure_boot_sig_block_t *block, int block_num, const uint8_t *image_digest) +{ + uint32_t crc = esp_rom_crc32_le(0, (uint8_t *)block, CRC_SIGN_BLOCK_LEN); + if (block->magic_byte != SIG_BLOCK_MAGIC_BYTE) { + // All signature blocks have been parsed, no new signature block present. + ESP_LOGD(TAG, "Signature block(%d) invalid/absent.", block_num); + return ESP_FAIL; + } + if (block->block_crc != crc) { + ESP_LOGE(TAG, "Magic byte correct but incorrect crc."); + return ESP_FAIL; + } + if (memcmp(image_digest, block->image_digest, DIGEST_LEN)) { + ESP_LOGE(TAG, "Magic byte & CRC correct but incorrect image digest."); + return ESP_FAIL; + } else { + ESP_LOGD(TAG, "valid signature block(%d) found", block_num); + return ESP_OK; + } + + return ESP_FAIL; +} + +/* Structure to hold public key digests calculated from the signature blocks of a single image. + + Each image can have one or more signature blocks (up to SECURE_BOOT_NUM_BLOCKS). Each signature block + includes a public key. + + Different to the ROM ets_secure_boot_key_digests_t structure which holds pointers to eFuse data with digests, + in this data structure the digest data is included. +*/ +typedef struct { + uint8_t key_digests[SECURE_BOOT_NUM_BLOCKS][DIGEST_LEN]; + unsigned num_digests; /* Number of valid digests, starting at index 0 */ +} image_sig_public_key_digests_t; + +/* Generates the public key digests of the valid public keys in an image's + signature block, verifies each signature, and stores the key digests in the + public_key_digests structure. + + @param flash_offset Image offset in flash + @param flash_size Image size in flash (not including signature block) + @param[out] public_key_digests Pointer to structure to hold the key digests for valid sig blocks + + + Note that this function doesn't read any eFuses, so it doesn't know if the + keys are ultimately trusted by the hardware or not + + @return - ESP_OK if no signatures failed to verify, or if no valid signature blocks are found at all. + - ESP_FAIL if there's a valid signature block that doesn't verify using the included public key (unexpected!) +*/ +static esp_err_t s_calculate_image_public_key_digests(uint32_t flash_offset, uint32_t flash_size, image_sig_public_key_digests_t *public_key_digests) +{ + esp_err_t ret; + uint8_t image_digest[DIGEST_LEN] = {0}; + uint8_t __attribute__((aligned(4))) key_digest[DIGEST_LEN] = {0}; + size_t sig_block_addr = flash_offset + ALIGN_UP(flash_size, FLASH_SECTOR_SIZE); + + ESP_LOGD(TAG, "calculating public key digests for sig blocks of image offset 0x%x (sig block offset 0x%x)", flash_offset, sig_block_addr); + + bzero(public_key_digests, sizeof(image_sig_public_key_digests_t)); + + ret = bootloader_sha256_flash_contents(flash_offset, sig_block_addr - flash_offset, image_digest); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "error generating image digest, %d", ret); + return ret; + } + + ESP_LOGD(TAG, "reading signatures"); + const ets_secure_boot_signature_t *signatures = bootloader_mmap(sig_block_addr, sizeof(ets_secure_boot_signature_t)); + if (signatures == NULL) { + ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", sig_block_addr, sizeof(ets_secure_boot_signature_t)); + return ESP_FAIL; + } + + for (int i = 0; i < SECURE_BOOT_NUM_BLOCKS; i++) { + const ets_secure_boot_sig_block_t *block = &signatures->block[i]; + + ret = validate_signature_block(block, i, image_digest); + if (ret != ESP_OK) { + ret = ESP_OK; // past the last valid signature block + break; + } + + /* Generating the SHA of the public key components in the signature block */ + bootloader_sha256_handle_t sig_block_sha; + sig_block_sha = bootloader_sha256_start(); + bootloader_sha256_data(sig_block_sha, &block->key, sizeof(block->key)); + bootloader_sha256_finish(sig_block_sha, key_digest); + + // Check we can verify the image using this signature and this key + uint8_t temp_verified_digest[DIGEST_LEN]; + bool verified = ets_rsa_pss_verify(&block->key, block->signature, image_digest, temp_verified_digest); + + if (!verified) { + /* We don't expect this: the signature blocks before we enable secure boot should all be verifiable or invalid, + so this is a fatal error + */ + ret = ESP_FAIL; + ESP_LOGE(TAG, "Secure boot key (%d) verification failed.", i); + break; + } + ESP_LOGD(TAG, "Signature block (%d) is verified", i); + /* Copy the key digest to the buffer provided by the caller */ + memcpy((void *)public_key_digests->key_digests[i], key_digest, DIGEST_LEN); + public_key_digests->num_digests++; + } + + if (ret == ESP_OK && public_key_digests->num_digests > 0) { + ESP_LOGI(TAG, "Digests successfully calculated, %d valid signatures (image offset 0x%x)", + public_key_digests->num_digests, flash_offset); + } + + bootloader_munmap(signatures); + return ret; +} + +esp_err_t esp_secure_boot_v2_permanently_enable(const esp_image_metadata_t *image_data) +{ + ESP_LOGI(TAG, "enabling secure boot v2 - ESP32-S2..."); + + if (esp_secure_boot_enabled()) { + ESP_LOGI(TAG, "secure boot v2 is already enabled, continuing.."); + return ESP_OK; + } + + esp_err_t ret; + /* Verify the bootloader */ + esp_image_metadata_t bootloader_data = { 0 }; + ret = esp_image_verify_bootloader_data(&bootloader_data); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "bootloader image appears invalid! error %d", ret); + return ret; + } + + /* Check if secure boot digests are present */ + bool has_secure_boot_digest = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0, NULL); + has_secure_boot_digest |= ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1, NULL); + has_secure_boot_digest |= ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2, NULL); + ESP_LOGI(TAG, "Secure boot digests %s", has_secure_boot_digest ? "already present":"absent, generating.."); + + ets_efuse_clear_program_registers(); + if (!has_secure_boot_digest) { + image_sig_public_key_digests_t boot_key_digests = {0}; + image_sig_public_key_digests_t app_key_digests = {0}; + + /* Generate the bootloader public key digests */ + ret = s_calculate_image_public_key_digests(bootloader_data.start_addr, bootloader_data.image_len - SIG_BLOCK_PADDING, &boot_key_digests); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Bootloader signature block is invalid"); + return ret; + } + + if (boot_key_digests.num_digests == 0) { + ESP_LOGE(TAG, "No valid bootloader signature blocks found."); + return ESP_FAIL; + } + ESP_LOGI(TAG, "%d signature block(s) found appended to the bootloader.", boot_key_digests.num_digests); + + int unused_key_slots = ets_efuse_count_unused_key_blocks(); + if (boot_key_digests.num_digests > unused_key_slots) { + ESP_LOGE(TAG, "Bootloader signatures(%d) more than available key slots(%d).", boot_key_digests.num_digests, unused_key_slots); + return ESP_FAIL; + } + + for (int i = 0; i < boot_key_digests.num_digests; i++) { + ets_efuse_block_t block; + const uint32_t secure_boot_key_purpose[SECURE_BOOT_NUM_BLOCKS] = { ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1, ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 }; + + block = ets_efuse_find_unused_key_block(); + if (block == ETS_EFUSE_BLOCK_MAX) { + ESP_LOGE(TAG, "No more unused key blocks available."); + return ESP_FAIL; + } + + int r = ets_efuse_write_key(block, secure_boot_key_purpose[i], boot_key_digests.key_digests[i], DIGEST_LEN); + if (r != 0) { + ESP_LOGE(TAG, "Failed to write efuse block %d with purpose %d. Can't continue.", block, secure_boot_key_purpose[i]); + return ESP_FAIL; + } + + // Note: write key will write protect both the block and the purpose eFuse, always + } + + /* Generate the application public key digests */ + ret = s_calculate_image_public_key_digests(image_data->start_addr, image_data->image_len - SIG_BLOCK_PADDING, &app_key_digests); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "App signature block is invalid."); + return ret; + } + + if (app_key_digests.num_digests == 0) { + ESP_LOGE(TAG, "No valid applications signature blocks found."); + return ESP_FAIL; + } + + ESP_LOGI(TAG, "%d signature block(s) found appended to the app.", app_key_digests.num_digests); + if (app_key_digests.num_digests > boot_key_digests.num_digests) { + ESP_LOGW(TAG, "App has %d signature blocks but bootloader only has %d. Some keys missing from bootloader?"); + } + + /* Confirm if at least one public key from the application matches a public key in the bootloader + (Also, ensure if that public revoke bit is not set for the matched key) */ + bool match = false; + const uint32_t revoke_bits[SECURE_BOOT_NUM_BLOCKS] = { EFUSE_SECURE_BOOT_KEY_REVOKE0, + EFUSE_SECURE_BOOT_KEY_REVOKE1, EFUSE_SECURE_BOOT_KEY_REVOKE2 }; + + for (int i = 0; i < boot_key_digests.num_digests; i++) { + + if (REG_GET_BIT(EFUSE_RD_REPEAT_DATA1_REG, revoke_bits[i])) { + ESP_LOGI(TAG, "Key block(%d) has been revoked.", i); + continue; // skip if the key block is revoked + } + + for (int j = 0; j < app_key_digests.num_digests; j++) { + if (!memcmp(boot_key_digests.key_digests[i], app_key_digests.key_digests[j], DIGEST_LEN)) { + ESP_LOGI(TAG, "Application key(%d) matches with bootloader key(%d).", j, i); + match = true; + } + } + } + + if (match == false) { + ESP_LOGE(TAG, "No application key digest matches the bootloader key digest."); + return ESP_FAIL; + } + + /* Revoke the empty signature blocks */ + if (boot_key_digests.num_digests < SECURE_BOOT_NUM_BLOCKS) { + /* The revocation index can be 0, 1, 2. Bootloader count can be 1,2,3. */ + for (uint8_t i = boot_key_digests.num_digests; i < SECURE_BOOT_NUM_BLOCKS; i++) { + ESP_LOGI(TAG, "Revoking empty key digest slot (%d)...", i); + ets_secure_boot_revoke_public_key_digest(i); + } + } + } + + esp_err_t err = esp_efuse_batch_write_begin(); + if (err != ESP_OK) { + ESP_LOGI(TAG, "Error batch programming security eFuses."); + return err; + } + + __attribute__((unused)) static const uint8_t enable = 1; + + esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT); + +#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE + ESP_LOGI(TAG, "Enabling Security download mode..."); + esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); +#else + ESP_LOGW(TAG, "Not enabling Security download mode - SECURITY COMPROMISED"); +#endif + +#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG + ESP_LOGI(TAG, "Disable hardware & software JTAG..."); + esp_efuse_write_field_bit(ESP_EFUSE_HARD_DIS_JTAG); + esp_efuse_write_field_bit(ESP_EFUSE_SOFT_DIS_JTAG); +#else + ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); +#endif + +#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE); +#endif + + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN); + + err = esp_efuse_batch_write_commit(); + if (err != ESP_OK) { + ESP_LOGI(TAG, "Error programming security eFuses."); + return err; + } + +#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE + assert(ets_efuse_secure_boot_aggressive_revoke_enabled()); +#endif + + assert(esp_rom_efuse_is_secure_boot_enabled()); + ESP_LOGI(TAG, "Secure boot permanently enabled"); + + return ESP_OK; +} diff --git a/components/bootloader_support/src/esp32s3/secure_boot_signatures.c b/components/bootloader_support/src/esp32s3/secure_boot_signatures.c new file mode 100644 index 0000000000..7bd377d480 --- /dev/null +++ b/components/bootloader_support/src/esp32s3/secure_boot_signatures.c @@ -0,0 +1,93 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "sdkconfig.h" +#include "esp_fault.h" +#include "bootloader_flash_priv.h" +#include "bootloader_sha.h" +#include "bootloader_utility.h" +#include "esp_log.h" +#include "esp_image_format.h" +#include "esp_secure_boot.h" +#include "esp32s3/rom/secure_boot.h" + +static const char* TAG = "secure_boot"; + +#define DIGEST_LEN 32 +#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) + +esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length) +{ + uint8_t digest[DIGEST_LEN]; + uint8_t verified_digest[DIGEST_LEN] = { 0 }; /* Note: this function doesn't do any anti-FI checks on this buffer */ + const uint8_t *data; + + ESP_LOGD(TAG, "verifying signature src_addr 0x%x length 0x%x", src_addr, length); + + /* Padding to round off the input to the nearest 4k boundary */ + int padded_length = ALIGN_UP(length, FLASH_SECTOR_SIZE); + ESP_LOGD(TAG, "verifying src_addr 0x%x length", src_addr, padded_length); + + data = bootloader_mmap(src_addr, length + sizeof(struct ets_secure_boot_sig_block)); + if (data == NULL) { + ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", src_addr, length+sizeof(ets_secure_boot_signature_t)); + return ESP_FAIL; + } + + /* Calculate digest of main image */ + esp_err_t err = bootloader_sha256_flash_contents(src_addr, padded_length, digest); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Digest calculation failed 0x%x, 0x%x", src_addr, padded_length); + bootloader_munmap(data); + return err; + } + + const ets_secure_boot_signature_t *sig = (const ets_secure_boot_signature_t *)(data + length); + int r = esp_secure_boot_verify_rsa_signature_block(sig, digest, verified_digest); + bootloader_munmap(data); + + return (r == ETS_OK) ? ESP_OK : ESP_FAIL; +} + +esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest) +{ + ets_secure_boot_key_digests_t trusted_keys; + ets_secure_boot_key_digests_t trusted_key_copies[2]; + ETS_STATUS r; + ets_secure_boot_status_t sb_result; + + memset(&trusted_keys, 0, sizeof(ets_secure_boot_key_digests_t)); + memset(trusted_key_copies, 0, 2 * sizeof(ets_secure_boot_key_digests_t)); + + if (!esp_secure_boot_enabled()) { + return ESP_OK; + } + + r = ets_secure_boot_read_key_digests(&trusted_keys); + if (r != ETS_OK) { + ESP_LOGI(TAG, "Could not read secure boot digests!"); + return ESP_FAIL; + } + + // Create the copies for FI checks (assuming result is ETS_OK, if it's not then it'll fail the fault check anyhow) + ets_secure_boot_read_key_digests(&trusted_key_copies[0]); + ets_secure_boot_read_key_digests(&trusted_key_copies[1]); + ESP_FAULT_ASSERT(memcmp(&trusted_keys, &trusted_key_copies[0], sizeof(ets_secure_boot_key_digests_t)) == 0); + ESP_FAULT_ASSERT(memcmp(&trusted_keys, &trusted_key_copies[1], sizeof(ets_secure_boot_key_digests_t)) == 0); + + ESP_LOGI(TAG, "Verifying with RSA-PSS boot..."); + sb_result = ets_secure_boot_verify_signature(sig_block, image_digest, &trusted_keys, verified_digest); + return (sb_result == SB_SUCCESS) ? ESP_OK : ESP_FAIL; +} diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index eb03a2e581..e76b3cee29 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -32,6 +32,9 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" #include "esp32s2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" +#include "esp32s3/rom/secure_boot.h" #endif /* Checking signatures as part of verifying images is necessary: @@ -209,7 +212,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_ bool verify_sha; #if CONFIG_SECURE_BOOT_V2_ENABLED verify_sha = true; -#else // ESP32, or ESP32S2 without secure boot enabled +#else // Secure boot not enabled verify_sha = (data->start_addr != ESP_BOOTLOADER_OFFSET); #endif diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index a41fe8ee2d..465fb8483d 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -26,6 +26,9 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT #define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT +#elif CONFIG_IDF_TARGET_ESP32S3 +#define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT +#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT #endif #ifndef BOOTLOADER_BUILD diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c index f142f7c284..140e64da61 100644 --- a/components/bootloader_support/src/flash_qio_mode.c +++ b/components/bootloader_support/src/flash_qio_mode.c @@ -15,10 +15,12 @@ #include #include "bootloader_flash_config.h" #include "flash_qio_mode.h" +#include "sdkconfig.h" #include "bootloader_flash_priv.h" #include "esp_log.h" #include "esp_err.h" #include "esp_rom_efuse.h" +#include "flash_qio_mode.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/spi_flash.h" #elif CONFIG_IDF_TARGET_ESP32S2 @@ -28,7 +30,6 @@ #endif #include "soc/efuse_periph.h" #include "soc/io_mux_reg.h" -#include "sdkconfig.h" static const char *TAG = "qio_mode"; @@ -194,7 +195,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, #if CONFIG_IDF_TARGET_ESP32 int wp_pin = bootloader_flash_get_wp_pin(); esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), spiconfig); #endif return ESP_OK; diff --git a/components/esp32s3/CMakeLists.txt b/components/esp32s3/CMakeLists.txt index 34c91b07a5..65a277a7cf 100644 --- a/components/esp32s3/CMakeLists.txt +++ b/components/esp32s3/CMakeLists.txt @@ -16,7 +16,6 @@ else() "clk.c" "crosscore_int.c" "dport_access.c" - "esp_crypto_lock.c" "hw_random.c" "intr_alloc.c" "memprot.c" diff --git a/components/esp32s3/clk.c b/components/esp32s3/clk.c index e3a4c8a7fc..65dacbe58b 100644 --- a/components/esp32s3/clk.c +++ b/components/esp32s3/clk.c @@ -23,9 +23,6 @@ // g_ticks_us defined in ROMs for PRO and APP CPU extern uint32_t g_ticks_per_us_pro; -#ifndef CONFIG_FREERTOS_UNICORE -extern uint32_t g_ticks_per_us_app; -#endif int IRAM_ATTR esp_clk_cpu_freq(void) { @@ -46,7 +43,4 @@ void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us) { /* Update scale factors used by esp_rom_delay_us */ g_ticks_per_us_pro = ticks_per_us; -#ifndef CONFIG_FREERTOS_UNICORE - g_ticks_per_us_app = ticks_per_us; -#endif } \ No newline at end of file diff --git a/components/esp_common/CMakeLists.txt b/components/esp_common/CMakeLists.txt index 8e16313dd7..3382345769 100644 --- a/components/esp_common/CMakeLists.txt +++ b/components/esp_common/CMakeLists.txt @@ -1,12 +1,18 @@ idf_build_get_property(target IDF_TARGET) +if(CONFIG_IDF_ENV_FPGA) + list(APPEND srcs "src/fpga_overrides.c") +endif() + if(BOOTLOADER_BUILD) # For bootloader, all we need from esp_common is headers - idf_component_register(INCLUDE_DIRS include) + idf_component_register(SRCS ${srcs} + INCLUDE_DIRS include + PRIV_REQUIRES soc) set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-Wl,--gc-sections") else() # Regular app build - set(srcs "src/brownout.c" + list(APPEND srcs "src/brownout.c" "src/esp_err.c" "src/dbg_stubs.c" "src/esp_err_to_name.c" @@ -61,3 +67,8 @@ else() endforeach() endif() + +if(CONFIG_IDF_ENV_FPGA) + # Forces the linker to include fpga stubs from this component + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides") +endif() diff --git a/components/esp_common/Kconfig b/components/esp_common/Kconfig index 31b2742c67..a05bd2cad8 100644 --- a/components/esp_common/Kconfig +++ b/components/esp_common/Kconfig @@ -125,7 +125,7 @@ menu "Common ESP-related" depends on ESP_CONSOLE_UART_CUSTOM range 0 46 default 1 if IDF_TARGET_ESP32 - default 43 if IDF_TARGET_ESP32S2 + default 43 help This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including boot log output and default standard output and standard error of the app). @@ -138,7 +138,7 @@ menu "Common ESP-related" depends on ESP_CONSOLE_UART_CUSTOM range 0 46 default 3 if IDF_TARGET_ESP32 - default 44 if IDF_TARGET_ESP32S2 + default 44 help This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including default default standard input of the app). @@ -292,6 +292,7 @@ menu "Common ESP-related" int default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR default 1 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 1 config ESP_MAC_ADDR_UNIVERSE_ETH bool diff --git a/components/esp_common/component.mk b/components/esp_common/component.mk index 64c67abcc5..da494c4b94 100644 --- a/components/esp_common/component.mk +++ b/components/esp_common/component.mk @@ -5,5 +5,9 @@ COMPONENT_ADD_INCLUDEDIRS := include COMPONENT_SRCDIRS := src +ifndef CONFIG_IDF_ENV_FPGA +COMPONENT_OBJEXCLUDE += src/fpga_overrides.o +endif + # disable stack protection in files which are involved in initialization of that feature src/stack_check.o: CFLAGS := $(filter-out -fstack-protector%, $(CFLAGS)) diff --git a/components/esp_common/include/esp_pm.h b/components/esp_common/include/esp_pm.h index 15af6a4aca..5c85188107 100644 --- a/components/esp_common/include/esp_pm.h +++ b/components/esp_common/include/esp_pm.h @@ -21,6 +21,8 @@ #include "esp32/pm.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/pm.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/pm.h" #endif #ifdef __cplusplus diff --git a/components/esp_common/src/fpga_overrides.c b/components/esp_common/src/fpga_overrides.c new file mode 100644 index 0000000000..e35ed52158 --- /dev/null +++ b/components/esp_common/src/fpga_overrides.c @@ -0,0 +1,57 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "sdkconfig.h" +#include "soc/soc.h" +#include "soc/system_reg.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "esp_rom_sys.h" +#include "esp_rom_uart.h" + +extern void ets_update_cpu_frequency(uint32_t ticks_per_us); + +void bootloader_clock_configure(void) +{ + esp_rom_uart_tx_wait_idle(0); + + uint32_t clock = 40000000; + ets_update_cpu_frequency(clock / 1000000); + REG_WRITE(RTC_CNTL_STORE5_REG, (clock >> 12) | ((clock >> 12) << 16)); +} + +void bootloader_fill_random(void *buffer, size_t length) +{ + uint8_t *buffer_bytes = (uint8_t *)buffer; + for (int i = 0; i < length; i++) { + buffer_bytes[i] = 0x5A; + } +} + +void esp_clk_init(void) +{ + +} + +void esp_perip_clk_init(void) +{ + +} + +/** + * @brief No-op function, used to force linking this file + * + */ +void esp_common_include_fpga_overrides(void) +{ +} \ No newline at end of file diff --git a/components/esp_common/src/int_wdt.c b/components/esp_common/src/int_wdt.c index 77b2e09389..c6d3cc8e5d 100644 --- a/components/esp_common/src/int_wdt.c +++ b/components/esp_common/src/int_wdt.c @@ -82,7 +82,7 @@ static void IRAM_ATTR tick_hook(void) { } #else static void IRAM_ATTR tick_hook(void) { -#if CONFIG_IDF_TARGET_ESP32 +#if !CONFIG_FREERTOS_UNICORE if (xPortGetCoreID()!=0) { return; } diff --git a/components/esp_common/src/mac_addr.c b/components/esp_common/src/mac_addr.c index f54c955843..f441245de8 100644 --- a/components/esp_common/src/mac_addr.c +++ b/components/esp_common/src/mac_addr.c @@ -56,8 +56,8 @@ esp_err_t esp_base_mac_addr_get(uint8_t *mac) esp_err_t esp_efuse_mac_get_custom(uint8_t *mac) { -#ifdef CONFIG_IDF_TARGET_ESP32S2 - return ESP_ERR_NOT_SUPPORTED; // TODO: support custom MAC in efuse +#if !CONFIG_IDF_TARGET_ESP32 + return ESP_ERR_NOT_SUPPORTED; #else uint8_t version; esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM_VER, &version, 8); @@ -76,7 +76,7 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac) return ESP_ERR_INVALID_CRC; } return ESP_OK; -#endif // IDF_TARGET_ESP32S2 +#endif } esp_err_t esp_efuse_mac_get_default(uint8_t* mac) @@ -86,7 +86,7 @@ esp_err_t esp_efuse_mac_get_default(uint8_t* mac) return err; } #ifdef CONFIG_IDF_TARGET_ESP32 -// Only ESP32 has MAC CRC in efuse, ESP32-S2 has internal efuse consistency checks +// Only ESP32 has MAC CRC in efuse uint8_t efuse_crc; esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &efuse_crc, 8); uint8_t calc_crc = esp_rom_efuse_mac_address_crc8(mac, 6); diff --git a/components/esp_rom/include/esp32s3/rom/aes.h b/components/esp_rom/include/esp32s3/rom/aes.h index 432c65efa2..1df00a1d6d 100644 --- a/components/esp_rom/include/esp32s3/rom/aes.h +++ b/components/esp_rom/include/esp32s3/rom/aes.h @@ -21,8 +21,6 @@ extern "C" { #endif -#define AES_BLOCK_SIZE (16) - enum AES_TYPE { AES_ENC, AES_DEC, diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h index 15adc528dc..a5a1ecb6a1 100644 --- a/components/esp_rom/include/esp32s3/rom/rtc.h +++ b/components/esp_rom/include/esp32s3/rom/rtc.h @@ -16,8 +16,7 @@ #include #include -#include "ets_sys.h" -#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" #ifdef __cplusplus extern "C" { diff --git a/components/esp_system/port/esp32/clk.c b/components/esp_system/port/esp32/clk.c index a75ecf7a48..7f1c769266 100644 --- a/components/esp_system/port/esp32/clk.c +++ b/components/esp_system/port/esp32/clk.c @@ -121,7 +121,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) esp_clk_slowclk_cal_set(cal_val); } -void esp_clk_init(void) + __attribute__((weak)) void esp_clk_init(void) { rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_init(cfg); @@ -203,7 +203,7 @@ void esp_clk_init(void) * These peripheral clocks are enabled when the peripherals are initialized * and disabled when they are de-initialized. */ -void esp_perip_clk_init(void) +__attribute__((weak)) void esp_perip_clk_init(void) { uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; diff --git a/components/esp_system/port/esp32s2/clk.c b/components/esp_system/port/esp32s2/clk.c index 0306d5d029..8ce2e4dd9e 100644 --- a/components/esp_system/port/esp32s2/clk.c +++ b/components/esp_system/port/esp32s2/clk.c @@ -73,7 +73,7 @@ typedef enum { static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); -void esp_clk_init(void) + __attribute__((weak)) void esp_clk_init(void) { rtc_config_t cfg = RTC_CONFIG_DEFAULT(); RESET_REASON rst_reas; @@ -206,7 +206,7 @@ void rtc_clk_select_rtc_slow_clk(void) * These peripheral clocks are enabled when the peripherals are initialized * and disabled when they are de-initialized. */ -void esp_perip_clk_init(void) +__attribute__((weak)) void esp_perip_clk_init(void) { uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk1 = 0; diff --git a/components/esp_system/port/esp32s3/CMakeLists.txt b/components/esp_system/port/esp32s3/CMakeLists.txt index 039081b6f4..3726d76e29 100644 --- a/components/esp_system/port/esp32s3/CMakeLists.txt +++ b/components/esp_system/port/esp32s3/CMakeLists.txt @@ -1,6 +1,8 @@ set(srcs "../async_memcpy_impl_gdma.c" "dport_panic_highint_hdl.S" "clk.c" "reset_reason.c") add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs}) +target_sources(${COMPONENT_LIB} PRIVATE ${srcs}) + #ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the #linker will ignore panic_highint_hdl.S as it has no other files depending on any #symbols in it. diff --git a/components/esp_system/port/esp32s3/clk.c b/components/esp_system/port/esp32s3/clk.c index d449399fbf..9bf1d1e5f5 100644 --- a/components/esp_system/port/esp32s3/clk.c +++ b/components/esp_system/port/esp32s3/clk.c @@ -74,7 +74,7 @@ typedef enum { static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); -void esp_clk_init(void) + __attribute__((weak)) void esp_clk_init(void) { rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_init(cfg); @@ -202,7 +202,7 @@ void rtc_clk_select_rtc_slow_clk(void) * These peripheral clocks are enabled when the peripherals are initialized * and disabled when they are de-initialized. */ -void esp_perip_clk_init(void) +__attribute__((weak)) void esp_perip_clk_init(void) { uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk1 = 0; @@ -252,7 +252,7 @@ void esp_perip_clk_init(void) SYSTEM_SPI3_CLK_EN | SYSTEM_SPI4_CLK_EN | SYSTEM_PWM0_CLK_EN | - SYSTEM_CAN_CLK_EN | + SYSTEM_TWAI_CLK_EN | SYSTEM_PWM1_CLK_EN | SYSTEM_I2S1_CLK_EN | SYSTEM_SPI2_DMA_CLK_EN | @@ -295,12 +295,6 @@ void esp_perip_clk_init(void) SYSTEM_SPI3_DMA_CLK_EN; common_perip_clk1 = 0; - /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, - * the current is not reduced when disable I2S clock. - */ - REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - /* Disable some peripheral clocks. */ CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); diff --git a/components/esp_system/port/esp32s3/reset_reason.c b/components/esp_system/port/esp32s3/reset_reason.c index 25f8f0a90d..b53641ca7b 100644 --- a/components/esp_system/port/esp32s3/reset_reason.c +++ b/components/esp_system/port/esp32s3/reset_reason.c @@ -97,24 +97,13 @@ esp_reset_reason_t esp_reset_reason(void) /* in IRAM, can be called from panic handler */ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) { - assert((hint & (~RST_REASON_MASK)) == 0); - uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT; - REG_WRITE(RTC_RESET_CAUSE_REG, val); } /* in IRAM, can be called from panic handler */ esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) { - uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); - uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; - uint32_t low = reset_reason_hint & RST_REASON_MASK; - if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) { - return ESP_RST_UNKNOWN; - } - return (esp_reset_reason_t) low; + return ESP_RST_UNKNOWN; } static void esp_reset_reason_clear_hint(void) { - REG_WRITE(RTC_RESET_CAUSE_REG, 0); } - From f19cabb7e4073a215e4b87bf3e0338cbafc9fca1 Mon Sep 17 00:00:00 2001 From: chenjianqiang Date: Mon, 10 Aug 2020 19:33:00 +0800 Subject: [PATCH 02/11] psram: support psram for esp32s3 --- components/esp32s3/CMakeLists.txt | 2 + components/esp32s3/Kconfig | 32 +- components/esp32s3/spiram.c | 323 +++++++++++ components/esp32s3/spiram_psram.c | 541 ++++++++++++++++++ components/esp32s3/spiram_psram.h | 80 +++ .../esp_rom/include/esp32s3/rom/opi_flash.h | 299 ++++++++++ components/esp_system/startup.c | 3 + components/freertos/xtensa/port.c | 2 + .../soc/soc/esp32s3/include/soc/io_mux_reg.h | 1 + 9 files changed, 1261 insertions(+), 22 deletions(-) create mode 100644 components/esp32s3/spiram.c create mode 100644 components/esp32s3/spiram_psram.c create mode 100644 components/esp32s3/spiram_psram.h create mode 100644 components/esp_rom/include/esp32s3/rom/opi_flash.h diff --git a/components/esp32s3/CMakeLists.txt b/components/esp32s3/CMakeLists.txt index 65a277a7cf..911dee42b9 100644 --- a/components/esp32s3/CMakeLists.txt +++ b/components/esp32s3/CMakeLists.txt @@ -22,6 +22,8 @@ else() "pm_esp32s3.c" "pm_trace.c" "sleep_modes.c" + "spiram.c" + "spiram_psram.c" "system_api_esp32s3.c") set(include_dirs "include") diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index e50d18c53a..2fcf3f2b68 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -171,16 +171,25 @@ menu "ESP32S3-Specific" choice SPIRAM_TYPE prompt "Type of SPI RAM chip in use" - default SPIRAM_TYPE_ESPPSRAM32 + default SPIRAM_TYPE_AUTO + + config SPIRAM_TYPE_AUTO + bool "Auto-detect" + + config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" config SPIRAM_TYPE_ESPPSRAM32 bool "ESP-PSRAM32 or IS25WP032" + config SPIRAM_TYPE_ESPPSRAM64 bool "ESP-PSRAM64 or LY68L6400" endchoice config SPIRAM_SIZE int + default -1 if SPIRAM_TYPE_AUTO + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 default 4194304 if SPIRAM_TYPE_ESPPSRAM32 default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 0 @@ -201,22 +210,6 @@ menu "ESP32S3-Specific" help The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. endmenu - - config SPIRAM_SPIWP_SD3_PIN - int "SPI PSRAM WP(SD3) Pin when customizing pins via eFuse (read help)" - depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT - range 0 33 - default 28 - help - This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been - overridden by setting the eFuses SPI_PAD_CONFIG_xxx. - - Different from esp32 chip, on esp32-s3, the WP pin would also be defined in efuse. - This value would only be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid. - - When flash mode is set to QIO or QOUT, - the PSRAM WP pin will be set as the value configured in bootloader. - config SPIRAM_FETCH_INSTRUCTIONS bool "Cache fetch instructions from SPI RAM" default n @@ -237,11 +230,6 @@ menu "ESP32S3-Specific" default SPIRAM_SPEED_40M help Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz - 2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz - 3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz config SPIRAM_SPEED_80M bool "80MHz clock speed" diff --git a/components/esp32s3/spiram.c b/components/esp32s3/spiram.c new file mode 100644 index 0000000000..f1711a5bff --- /dev/null +++ b/components/esp32s3/spiram.c @@ -0,0 +1,323 @@ +/* +Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if +we add more types of external RAM memory, this can be made into a more intelligent dispatcher. +*/ + +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_err.h" +#include "esp32s3/spiram.h" +#include "spiram_psram.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "soc/soc.h" +#include "esp_heap_caps_init.h" +#include "soc/soc_memory_layout.h" +#include "soc/dport_reg.h" +#include "esp32s3/rom/cache.h" +#include "soc/cache_memory.h" +#include "soc/extmem_reg.h" + +#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL + +#if CONFIG_SPIRAM + +static const char* TAG = "spiram"; + +#if CONFIG_SPIRAM_SPEED_40M +#define PSRAM_SPEED PSRAM_CACHE_S40M +#elif CONFIG_SPIRAM_SPEED_80M +#define PSRAM_SPEED PSRAM_CACHE_S80M +#else +#define PSRAM_SPEED PSRAM_CACHE_S20M +#endif + +#define SPIRAM_SIZE esp_spiram_get_size() + +static bool spiram_inited=false; + + +/* + Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns + true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been + initialized (in a two-core system) or after the heap allocator has taken ownership of the memory. +*/ +bool esp_spiram_test(void) +{ + volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE); + size_t p; + size_t s=SPIRAM_SIZE; + int errct=0; + int initial_err=-1; + + if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < SPIRAM_SIZE) { + ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH); + spiram=(volatile int*)SOC_EXTRAM_DATA_LOW; + s = SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW; + } + for (p=0; p<(s/sizeof(int)); p+=8) { + spiram[p]=p^0xAAAAAAAA; + } + for (p=0; p<(s/sizeof(int)); p+=8) { + if (spiram[p]!=(p^0xAAAAAAAA)) { + errct++; + if (errct==1) initial_err=p*4; + if (errct < 4) { + ESP_EARLY_LOGE(TAG, "SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], p^0xAAAAAAAA); + } + } + } + if (errct) { + ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW); + return false; + } else { + ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK"); + return true; + } +} + +void IRAM_ATTR esp_spiram_init_cache(void) +{ + Cache_Suspend_DCache(); + if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >= SPIRAM_SIZE) { + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE, 0, 64, SPIRAM_SIZE >> 16, 0); + } else { + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE, 0, 64, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >> 16, 0); + } + REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS); +#if !CONFIG_FREERTOS_UNICORE + REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS); +#endif + Cache_Resume_DCache(0); +} + +static uint32_t pages_for_flash = 0; +static uint32_t page0_mapped = 0; +static uint32_t page0_page = INVALID_PHY_PAGE; +static uint32_t instrcution_in_spiram = 0; +static uint32_t rodata_in_spiram = 0; + +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS +static int instr_flash2spiram_offs = 0; +static uint32_t instr_start_page = 0; +static uint32_t instr_end_page = 0; +#endif + +#if CONFIG_SPIRAM_RODATA +static int rodata_flash2spiram_offs = 0; +static uint32_t rodata_start_page = 0; +static uint32_t rodata_end_page = 0; +#endif + +uint32_t esp_spiram_instruction_access_enabled(void) +{ + return instrcution_in_spiram; +} + +uint32_t esp_spiram_rodata_access_enabled(void) +{ + return rodata_in_spiram; +} + +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS +esp_err_t esp_spiram_enable_instruction_access(void) +{ + uint32_t pages_in_flash = 0; + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped); + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped); + if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { + ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (SPIRAM_SIZE >> 16), (pages_in_flash + pages_for_flash)); + return ESP_FAIL; + } + ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM"); + uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START + instr_mmu_offset*sizeof(uint32_t)); + mmu_value &= MMU_ADDRESS_MASK; + instr_flash2spiram_offs = mmu_value - pages_for_flash; + ESP_EARLY_LOGV(TAG, "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, instr_flash2spiram_offs); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); + instrcution_in_spiram = 1; + return ESP_OK; +} +#endif + +#if CONFIG_SPIRAM_RODATA +esp_err_t esp_spiram_enable_rodata_access(void) +{ + uint32_t pages_in_flash = 0; + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped); + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS0, &page0_mapped); + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped); + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped); + + if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { + ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data."); + return ESP_FAIL; + } + + ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM"); + uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START + rodata_mmu_offset*sizeof(uint32_t)); + mmu_value &= MMU_ADDRESS_MASK; + rodata_flash2spiram_offs = mmu_value - pages_for_flash; + ESP_EARLY_LOGV(TAG, "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, rodata_flash2spiram_offs); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, pages_for_flash, &page0_page); + rodata_in_spiram = 1; + return ESP_OK; +} +#endif + +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS +void instruction_flash_page_info_init(void) +{ + uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE; + uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + + instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START + instr_mmu_offset*sizeof(uint32_t)); + instr_start_page &= MMU_ADDRESS_MASK; + instr_end_page = instr_start_page + instr_page_cnt - 1; +} + +uint32_t IRAM_ATTR instruction_flash_start_page_get(void) +{ + return instr_start_page; +} + +uint32_t IRAM_ATTR instruction_flash_end_page_get(void) +{ + return instr_end_page; +} + +int IRAM_ATTR instruction_flash2spiram_offset(void) +{ + return instr_flash2spiram_offs; +} +#endif + +#if CONFIG_SPIRAM_RODATA +void rodata_flash_page_info_init(void) +{ + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - SOC_DROM_LOW + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE; + uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + + rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START + rodata_mmu_offset*sizeof(uint32_t)); + rodata_start_page &= MMU_ADDRESS_MASK; + rodata_end_page = rodata_start_page + rodata_page_cnt - 1; +} + +uint32_t IRAM_ATTR rodata_flash_start_page_get(void) +{ + return rodata_start_page; +} + +uint32_t IRAM_ATTR rodata_flash_end_page_get(void) +{ + return rodata_end_page; +} + +int IRAM_ATTR rodata_flash2spiram_offset(void) +{ + return rodata_flash2spiram_offs; +} +#endif + +esp_err_t esp_spiram_init(void) +{ + esp_err_t r; + r = psram_enable(PSRAM_SPEED, PSRAM_MODE); + if (r != ESP_OK) { +#if CONFIG_SPIRAM_IGNORE_NOTFOUND + ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out."); +#endif + return r; + } + + spiram_inited=true; +#if (CONFIG_SPIRAM_SIZE != -1) + if (esp_spiram_get_size()!=CONFIG_SPIRAM_SIZE) { + ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE/1024, esp_spiram_get_size()/1024); + return ESP_ERR_INVALID_SIZE; + } +#endif + + ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device", + (esp_spiram_get_size()*8)/(1024*1024)); + ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : \ + PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m"); + ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \ + (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \ + (PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \ + (PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR"); + return ESP_OK; +} + + +esp_err_t esp_spiram_add_to_heapalloc(void) +{ + uint32_t size_for_flash = (pages_for_flash << 16); + ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (SPIRAM_SIZE - (pages_for_flash << 16))/1024); + //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's + //no need to explicitly specify them. + + return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE + size_for_flash, (intptr_t)SOC_EXTRAM_DATA_HIGH -1); +} + + +static uint8_t *dma_heap; + +esp_err_t esp_spiram_reserve_dma_pool(size_t size) { + if (size==0) return ESP_OK; //no-op + ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024); + dma_heap=heap_caps_malloc(size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL); + if (!dma_heap) return ESP_ERR_NO_MEM; + uint32_t caps[]={MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}; + return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1); +} + +size_t esp_spiram_get_size(void) +{ + if (!spiram_inited) { + ESP_EARLY_LOGE(TAG, "SPI RAM not initialized"); + abort(); + } + + psram_size_t size=psram_get_size(); + if (size==PSRAM_SIZE_16MBITS) return 2*1024*1024; + if (size==PSRAM_SIZE_32MBITS) return 4*1024*1024; + if (size==PSRAM_SIZE_64MBITS) return 8*1024*1024; + return SPIRAM_SIZE; +} + +/* + Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first, + otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this. +*/ +void IRAM_ATTR esp_spiram_writeback_cache(void) +{ + extern void Cache_WriteBack_All(void); + Cache_WriteBack_All(); +} + +#endif diff --git a/components/esp32s3/spiram_psram.c b/components/esp32s3/spiram_psram.c new file mode 100644 index 0000000000..cdc2089a8c --- /dev/null +++ b/components/esp32s3/spiram_psram.c @@ -0,0 +1,541 @@ +/* + Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip). +*/ + +// Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include "sdkconfig.h" +#include "string.h" +#include "esp_attr.h" +#include "esp_err.h" +#include "esp_types.h" +#include "esp_log.h" +#include "spiram_psram.h" +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/opi_flash.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/efuse.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" +#include "soc/dport_reg.h" +#include "soc/efuse_periph.h" +#include "soc/spi_caps.h" +#include "soc/io_mux_reg.h" +#include "soc/apb_ctrl_reg.h" +#include "soc/efuse_reg.h" +#include "soc/soc.h" +#include "soc/io_mux_reg.h" +#include "driver/gpio.h" +#include "driver/spi_common_internal.h" +#include "driver/spi_common.h" +#include "driver/periph_ctrl.h" +#include "bootloader_common.h" + +#if CONFIG_SPIRAM +#include "soc/rtc.h" + +static const char* TAG = "psram"; + +//Commands for PSRAM chip +#define PSRAM_READ 0x03 +#define PSRAM_FAST_READ 0x0B +#define PSRAM_FAST_READ_DUMMY 0x3 +#define PSRAM_FAST_READ_QUAD 0xEB +#define PSRAM_FAST_READ_QUAD_DUMMY 0x5 +#define PSRAM_WRITE 0x02 +#define PSRAM_QUAD_WRITE 0x38 +#define PSRAM_ENTER_QMODE 0x35 +#define PSRAM_EXIT_QMODE 0xF5 +#define PSRAM_RESET_EN 0x66 +#define PSRAM_RESET 0x99 +#define PSRAM_SET_BURST_LEN 0xC0 +#define PSRAM_DEVICE_ID 0x9F +// ID +#define PSRAM_ID_KGD_M 0xff +#define PSRAM_ID_KGD_S 8 +#define PSRAM_ID_KGD 0x5d +#define PSRAM_ID_EID_M 0xff +#define PSRAM_ID_EID_S 16 + +// Use the [7:5](bit7~bit5) of EID to distinguish the psram size: +// +// BIT7 | BIT6 | BIT5 | SIZE(MBIT) +// ------------------------------------- +// 0 | 0 | 0 | 16 +// 0 | 0 | 1 | 32 +// 0 | 1 | 0 | 64 +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 + +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +// For the old version 32Mbit psram, using the spicial driver */ +#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) + +// IO-pins for PSRAM. +// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines +// hardcode the flash pins as well, making this code incompatible with either a setup +// that has the flash on non-standard pins or ESP32s with built-in flash. +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM +// PSRAM clock and cs IO should be configured based on hardware design. +#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 +#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM +#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM +#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM +#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM + +#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M +#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M + +#define PSRAM_IO_MATRIX_DUMMY_20M 0 +#define PSRAM_IO_MATRIX_DUMMY_40M 0 +#define PSRAM_IO_MATRIX_DUMMY_80M 0 +#define _SPI_CACHE_PORT 0 +#define _SPI_FLASH_PORT 1 +#define _SPI_80M_CLK_DIV 1 +#define _SPI_40M_CLK_DIV 2 +#define _SPI_20M_CLK_DIV 4 + +typedef enum { + PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */ + PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_ALON, /*!< clock always on */ + PSRAM_CLK_MODE_MAX, +} psram_clk_mode_t; + + +typedef enum { + PSRAM_EID_SIZE_16MBITS = 0, + PSRAM_EID_SIZE_32MBITS = 1, + PSRAM_EID_SIZE_64MBITS = 2, +} psram_eid_size_t; + +typedef struct { + uint8_t flash_clk_io; + uint8_t flash_cs_io; + uint8_t psram_clk_io; + uint8_t psram_cs_io; + uint8_t psram_spiq_sd0_io; + uint8_t psram_spid_sd1_io; + uint8_t psram_spiwp_sd3_io; + uint8_t psram_spihd_sd2_io; +} psram_io_t; + +#define PSRAM_IO_CONF_DEFAULT() { \ + .flash_clk_io = FLASH_CLK_IO, \ + .flash_cs_io = FLASH_CS_IO, \ + .psram_clk_io = PSRAM_CLK_IO, \ + .psram_cs_io = PSRAM_CS_IO, \ + .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \ + .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \ + .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \ + .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \ +} + +typedef enum { + PSRAM_SPI_1 = 0x1, + /* PSRAM_SPI_2, */ + /* PSRAM_SPI_3, */ + PSRAM_SPI_MAX , +} psram_spi_num_t; + +typedef enum { + PSRAM_CMD_QPI, + PSRAM_CMD_SPI, +} psram_cmd_mode_t; + +typedef esp_rom_spi_cmd_t psram_cmd_t; + +static uint32_t s_psram_id = 0; +static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); +extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) +{ + if (mode == PSRAM_CMD_QPI) { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); + SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); + } else if (mode == PSRAM_CMD_SPI) { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); + } +} +static void _psram_exec_cmd(int spi_num, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len) +{ + esp_rom_spi_cmd_t conf; + uint32_t _addr = addr; + conf.addr = &_addr; + conf.addrBitLen = addr_bit_len; + conf.cmd = cmd; + conf.cmdBitLen = cmd_bit_len; + conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723 + conf.txData = (uint32_t*) mosi_data; + conf.txDataBitLen = mosi_bit_len; + conf.rxData = (uint32_t*) miso_data; + conf.rxDataBitLen = miso_bit_len; + esp_rom_spi_cmd_config(spi_num, &conf); +} + +void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation) +{ + uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); + uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); + uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); + uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); + psram_set_op_mode(spi_num, mode); + _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len, + dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); + esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation); + + WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); + WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); + WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); + WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); +} + +//exit QPI mode(set back to SPI mode) +static void psram_disable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_QPI, + PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ +} + +//switch psram burst length(32 bytes or 1024 bytes) +//datasheet says it should be 1024 bytes by default +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) +{ + psram_exec_cmd(spi_num, mode, + PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ +} + +//send reset command to psram, in spi mode +static void psram_reset_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET_EN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ + + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ +} + +esp_err_t psram_enable_wrap(uint32_t wrap_size) +{ + static int current_wrap_size = 0; + if (current_wrap_size == wrap_size) { + return ESP_OK; + } + switch (wrap_size) { + case 32: + case 0: + psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return ESP_OK; + case 16: + case 64: + default: + return ESP_FAIL; + } +} + +bool psram_support_wrap_size(uint32_t wrap_size) +{ + switch (wrap_size) { + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; + } + +} + +//read psram id, should issue `psram_disable_qio_mode` before calling this +static void psram_read_id(int spi_num, uint32_t* dev_id) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + 0, 24, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ +} + +//enter QPI mode +static void IRAM_ATTR psram_enable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ +} + +static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) { + // SPI1 Flash Operation port + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } else { + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } +} + +static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) { + // SPI0 SRAM Cache port + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); + // SPI0 Flash Cache port + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } else { + CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); + } +} + +//psram gpio init , different working frequency we have different solutions +static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) +{ + psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { + /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ + } else { + // FLASH pins are all configured via GPIO matrix in ROM. + psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig); + psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig); + psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); + psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); + psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); + psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio(); + } + esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); + + if (psram_io.psram_cs_io == SPI_CS1_GPIO_NUM) { + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], FUNC_SPICS1_SPICS1); + } else { + esp_rom_gpio_connect_out_signal(psram_io.psram_cs_io, SPICS1_OUT_IDX, 0, 0); + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], PIN_FUNC_GPIO); + } +} + +psram_size_t psram_get_size(void) +{ + if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) { + return PSRAM_SIZE_64MBITS; + } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) { + return PSRAM_SIZE_32MBITS; + } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) { + return PSRAM_SIZE_16MBITS; + } else { + return PSRAM_SIZE_MAX; + } + return PSRAM_SIZE_MAX; +} + +//used in UT only +bool psram_is_32mbit_ver0(void) +{ + return PSRAM_IS_32MBIT_VER0(s_psram_id); +} + +static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) +{ + if (spi_num == _SPI_CACHE_PORT) { + REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode); + } else if (spi_num == _SPI_FLASH_PORT) { + REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode); + } +} + +/* + * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA. + * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode. + */ +esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init +{ + assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now."); + // GPIO related settings + psram_gpio_config(mode); + + /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */ + /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */ + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); + + int spi_num = PSRAM_SPI_1; + psram_disable_qio_mode(spi_num); + psram_read_id(spi_num, &s_psram_id); + if (!PSRAM_IS_VALID(s_psram_id)) { + /* 16Mbit psram ID read error workaround: + * treat the first read id as a dummy one as the pre-condition, + * Send Read ID command again + */ + psram_read_id(spi_num, &s_psram_id); + if (!PSRAM_IS_VALID(s_psram_id)) { + ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id); + return ESP_FAIL; + } + } + + psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; + if (psram_is_32mbit_ver0()) { + clk_mode = PSRAM_CLK_MODE_A1C; + // SPI1: keep clock mode and cs timing for spi1 + } else { + // For other psram, we don't need any extra clock cycles after cs get back to high level + clk_mode = PSRAM_CLK_MODE_NORM; + // SPI1: set clock mode and cs timing to normal mode + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); + } + + /* SPI1: send psram reset command */ + /* SPI1: send QPI enable command */ + psram_reset_mode(PSRAM_SPI_1); + psram_enable_qio_mode(PSRAM_SPI_1); + + // after sending commands, set spi1 clock mode and cs timing to normal mode. + // since all the operations are sent via SPI0 Cache + /* SPI1: set clock mode to normal mode. */ + /* SPI1: set cs timing to normal */ + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); + + /* SPI0: set spi0 clock mode */ + /* SPI0: set spi0 flash/cache cs timing */ + psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); + psram_set_spi0_cache_cs_timing(clk_mode); + + // SPI0: init SPI commands for Cache + psram_cache_init(mode, vaddrmode); + + return ESP_OK; +} + +static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) +{ + uint32_t freqbits; + if (1 >= freqdiv) { + WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); + } else { + freqbits = (((freqdiv-1)< +#include +#include +#include "spi_flash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint16_t cmd; /*!< Command value */ + uint16_t cmdBitLen; /*!< Command byte length*/ + uint32_t *addr; /*!< Point to address value*/ + uint32_t addrBitLen; /*!< Address byte length*/ + uint32_t *txData; /*!< Point to send data buffer*/ + uint32_t txDataBitLen; /*!< Send data byte length.*/ + uint32_t *rxData; /*!< Point to recevie data buffer*/ + uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ + uint32_t dummyBitLen; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +// Definition of MX25UM25645G Octa Flash +// SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +// FLASH commands +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +// Definitions for GigaDevice GD25LX256E Flash +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +// spi user mode command config + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ +void esp_rom_opiflash_pin_config(void); + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +void esp_rom_opiflash_mode_reset(int spi_num); + +#if 0 +// MX25UM25645G opi flash interface +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash id + */ +uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash status register(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash status value + */ +uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief wait opi flash status register to be idle + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of configure register + * @return value of config register2 + */ +uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); + +/** + * @brief to write the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of config register + * @param val the value to write + */ +void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); + +/** + * @brief to erase flash sector(for MX25UM25645G) + * @param spi_num spi port + * @param address the sector address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase flash block(for MX25UM25645G) + * @param spi_num spi port + * @param address the block address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase a flash area define by start address and length(for MX25UM25645G) + * @param spi_num spi port + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @param mode flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read data from opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); + +/** + * @brief to write data to opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); + +/** + * @brief to set opi flash operation mode(for MX25UM25645G) + * @param spi_num spi port + * @param cur_mode current operation mode + * @param target the target operation mode to be set + */ +void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index d65ce54d75..b801faba5a 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -64,6 +64,9 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/spiram.h" #include "esp32s2/brownout.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/spiram.h" +#include "esp32s3/brownout.h" #endif /***********************************************/ diff --git a/components/freertos/xtensa/port.c b/components/freertos/xtensa/port.c index acd99114dd..fb71db9833 100644 --- a/components/freertos/xtensa/port.c +++ b/components/freertos/xtensa/port.c @@ -127,6 +127,8 @@ #include "esp32/spiram.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/spiram.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/spiram.h" #endif #include "esp_private/startup_internal.h" // [refactor-todo] for g_spiram_ok diff --git a/components/soc/soc/esp32s3/include/soc/io_mux_reg.h b/components/soc/soc/esp32s3/include/soc/io_mux_reg.h index 37a1efa275..0e07c23cfb 100644 --- a/components/soc/soc/esp32s3/include/soc/io_mux_reg.h +++ b/components/soc/soc/esp32s3/include/soc/io_mux_reg.h @@ -139,6 +139,7 @@ #define U0RXD_GPIO_NUM 44 #define U0TXD_GPIO_NUM 43 +#define SPI_CS1_GPIO_NUM 26 #define SPI_HD_GPIO_NUM 27 #define SPI_WP_GPIO_NUM 28 #define SPI_CS0_GPIO_NUM 29 From d7e50c645721426d03a93fdc2fccdd8f548a22d2 Mon Sep 17 00:00:00 2001 From: Cao Sen Miao Date: Tue, 18 Aug 2020 17:11:46 +0800 Subject: [PATCH 03/11] spi_flash:bringup some flash supports for esp32s3 --- components/hal/CMakeLists.txt | 1 + components/hal/spi_flash_hal_iram.c | 2 + .../soc/soc/esp32s3/include/soc/spi_caps.h | 2 +- components/spi_flash/test/test_esp_flash.c | 45 ++++++++++++++++++- 4 files changed, 48 insertions(+), 2 deletions(-) diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index f62b8c6397..e47132462f 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -58,6 +58,7 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32s3") list(APPEND srcs + "spi_flash_hal_gpspi.c" "esp32s3/brownout_hal.c" "esp32s3/systimer_hal.c" "esp32s3/touch_sensor_hal.c") diff --git a/components/hal/spi_flash_hal_iram.c b/components/hal/spi_flash_hal_iram.c index cf074ca006..8660d9c9e6 100644 --- a/components/hal/spi_flash_hal_iram.c +++ b/components/hal/spi_flash_hal_iram.c @@ -68,6 +68,8 @@ bool spi_flash_hal_host_idle(spi_flash_host_inst_t *host) idle &= spi_flash_ll_host_idle(&SPI0); #elif CONFIG_IDF_TARGET_ESP32S2 idle &= spi_flash_ll_host_idle(&SPIMEM0); +#elif CONFIG_IDF_TARGET_ESP32S3 + idle &= spi_flash_ll_host_idle(&SPIMEM0); #endif } diff --git a/components/soc/soc/esp32s3/include/soc/spi_caps.h b/components/soc/soc/esp32s3/include/soc/spi_caps.h index cbcdcacb63..79c19aaf56 100644 --- a/components/soc/soc/esp32s3/include/soc/spi_caps.h +++ b/components/soc/soc/esp32s3/include/soc/spi_caps.h @@ -50,6 +50,6 @@ #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3)) // Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1) +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) (!((void*)spi_dev == (void*)&SPIMEM1)) #define SOC_MEMSPI_IS_INDEPENDENT 1 \ No newline at end of file diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index 966386185a..6fc1502298 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -61,6 +61,26 @@ static uint8_t sector_buf[4096]; #define FSPI_PIN_NUM_WP 38 #define FSPI_PIN_NUM_CS 34 +// Just use the same pins for HSPI +#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI +#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO +#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK +#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD +#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP +#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS + +#elif CONFIG_IDF_TARGET_ESP32S3 +#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs +#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd +#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp + +#define FSPI_PIN_NUM_MOSI 35 +#define FSPI_PIN_NUM_MISO 37 +#define FSPI_PIN_NUM_CLK 36 +#define FSPI_PIN_NUM_HD 33 +#define FSPI_PIN_NUM_WP 38 +#define FSPI_PIN_NUM_CS 34 + // Just use the same pins for HSPI #define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI #define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO @@ -165,6 +185,29 @@ flashtest_config_t config_list[] = { // .input_delay_ns = 20, // }, }; +#elif CONFIG_IDF_TARGET_ESP32S3 +flashtest_config_t config_list[] = { + FLASHTEST_CONFIG_COMMON, + /* No runners for esp32s2 for these config yet */ + { + .io_mode = TEST_SPI_READ_MODE, + .speed = TEST_SPI_SPEED, + .host_id = FSPI_HOST, + .cs_id = 0, + .cs_io_num = FSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, + // /* current runner doesn't have a flash on HSPI */ + // { + // .io_mode = TEST_SPI_READ_MODE, + // .speed = TEST_SPI_SPEED, + // .host_id = HSPI_HOST, + // .cs_id = 0, + // // uses GPIO matrix on esp32s2 regardles if FORCE_GPIO_MATRIX + // .cs_io_num = HSPI_PIN_NUM_CS, + // .input_delay_ns = 20, + // }, +}; #endif static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int* out_cs_id) @@ -253,7 +296,7 @@ static void setup_bus(spi_host_device_t host_id) gpio_set_level(HSPI_PIN_NUM_WP, 1); #endif } -#if !DISABLED_FOR_TARGETS(ESP32S2) +#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) else if (host_id == VSPI_HOST) { ESP_LOGI(TAG, "setup flash on SPI%d (VSPI) CS0...\n", host_id + 1); spi_bus_config_t vspi_bus_cfg = { From 61f89b97c65290c2a6fc34f611555103a083c058 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 29 Jul 2020 13:13:51 +0800 Subject: [PATCH 04/11] bringup esp32-s3 on FPGA --- components/app_trace/app_trace_util.c | 2 + components/driver/CMakeLists.txt | 8 +- components/driver/adc_common.c | 32 +- .../driver/esp32s3/include/driver/adc.h | 277 ++++++ .../driver/esp32s3/include/driver/dac.h | 80 ++ .../esp32s3/include/driver/temp_sensor.h | 105 +++ .../esp32s3/include/driver/touch_sensor.h | 582 ++++++++++++ components/driver/i2s.c | 2 +- components/driver/spi_common.c | 2 + components/driver/spi_master.c | 2 +- components/driver/spi_slave.c | 2 +- components/driver/timer.c | 15 +- components/driver/touch_sensor_common.c | 6 +- components/driver/uart.c | 2 + components/efuse/esp32s3/component.mk | 0 components/efuse/esp32s3/esp_efuse_table.c | 13 + components/efuse/esp32s3/esp_efuse_table.csv | 0 .../efuse/esp32s3/include/esp_efuse_table.h | 123 +++ components/efuse/esp32s3/sources.cmake | 1 + components/efuse/include/esp32s3/esp_efuse.h | 69 ++ components/efuse/include/esp_efuse.h | 2 + .../esp32s3/esp_efuse_utility.h | 30 + .../efuse/private_include/esp_efuse_utility.h | 2 + components/efuse/src/esp32s3/esp_efuse_api.c | 13 + .../efuse/src/esp32s3/esp_efuse_fields.c | 13 + .../efuse/src/esp32s3/esp_efuse_utility.c | 13 + components/esp32s3/CMakeLists.txt | 1 - components/esp32s3/include/esp32s3/rtc.h | 39 + components/esp32s3/ld/esp32s3.ld | 2 +- components/esp32s3/memprot.c | 2 +- components/esp32s3/sleep_modes.c | 717 --------------- .../esp_gdbstub/esp32s3/gdbstub_esp32s3.c | 51 ++ .../esp32s3/gdbstub_target_config.h | 18 + .../esp_rom/include/esp32s3/rom/opi_flash.h | 1 + .../esp_rom/include/esp32s3/rom/spi_flash.h | 1 + components/esp_system/port/cpu_start.c | 71 +- components/esp_system/port/panic_handler.c | 82 +- components/esp_system/sleep_modes.c | 19 +- components/esp_system/startup.c | 5 + components/esp_system/system_api.c | 2 + components/esp_system/system_time.c | 2 + components/esp_system/test/test_sleep.c | 3 + components/esp_timer/Kconfig | 4 +- .../esp_timer/src/esp_timer_impl_systimer.c | 10 +- components/esp_timer/src/ets_timer_legacy.c | 1 - components/esp_wifi/CMakeLists.txt | 8 + components/esp_wifi/esp32s3/esp_adapter.c | 13 + .../esp_wifi/esp32s3/include/phy_init_data.h | 13 + components/esptool_py/Kconfig.projbuild | 2 +- components/esptool_py/esptool | 2 +- .../xtensa/include/freertos/FreeRTOSConfig.h | 2 + components/freertos/xtensa/xtensa_init.c | 2 + .../hal/esp32s3/include/hal/clk_gate_ll.h | 13 + .../hal/esp32s3/include/hal/rtc_io_ll.h | 4 +- components/hal/include/hal/dac_types.h | 2 +- .../include/esp32s3/idf_performance_target.h | 17 + components/log/include/esp_log.h | 2 + components/mbedtls/port/esp32s3/aes.c | 0 components/mbedtls/port/esp32s3/bignum.c | 0 components/mbedtls/port/esp32s3/esp_sha1.c | 0 components/mbedtls/port/esp32s3/esp_sha256.c | 0 components/mbedtls/port/esp32s3/esp_sha512.c | 0 components/mbedtls/port/esp32s3/sha.c | 0 components/mbedtls/port/esp_sha.c | 2 + components/mbedtls/port/include/aes_alt.h | 2 + components/mbedtls/port/include/esp32s3/aes.h | 369 ++++++++ .../mbedtls/port/include/esp32s3/crypto_dma.h | 40 + components/mbedtls/port/include/esp32s3/gcm.h | 238 +++++ components/mbedtls/port/include/esp32s3/sha.h | 165 ++++ components/mbedtls/port/include/gcm_alt.h | 17 + components/mbedtls/port/include/sha1_alt.h | 22 + components/mbedtls/port/include/sha256_alt.h | 23 + components/mbedtls/port/include/sha512_alt.h | 36 + components/newlib/port/esp_time_impl.c | 8 +- components/newlib/syscall_table.c | 2 + components/newlib/time.c | 1 - .../soc/soc/esp32s3/include/soc/twai_caps.h | 6 +- .../soc/soc/esp32s3/include/soc/wdev_reg.h | 2 +- components/soc/src/esp32s3/rtc_clk.c | 1 + .../soc/src/esp32s3/soc_memory_layout.c | 6 +- components/spi_flash/cache_utils.c | 281 +++++- components/spi_flash/cache_utils.h | 2 +- .../spi_flash/esp32s3/flash_ops_esp32s3.c | 120 +++ components/spi_flash/esp_flash_spi_init.c | 20 +- components/spi_flash/flash_mmap.c | 48 +- components/spi_flash/flash_ops.c | 6 +- components/spi_flash/memspi_host_driver.c | 4 +- components/spi_flash/spi_flash_os_func_noos.c | 11 +- components/ulp/include/esp32s3/ulp.h | 840 ++++++++++++++++++ components/ulp/ulp.c | 3 + components/ulp/ulp_private.h | 4 +- components/unity/unity_port_esp32.c | 2 + components/vfs/vfs_uart.c | 4 +- tools/ci/config/post_check.yml | 1 + tools/tools.json | 56 ++ .../components/test_utils/ccomp_timer.c | 2 + .../components/test_utils/ccomp_timer_impl.c | 2 + 97 files changed, 4037 insertions(+), 816 deletions(-) create mode 100644 components/driver/esp32s3/include/driver/adc.h create mode 100644 components/driver/esp32s3/include/driver/dac.h create mode 100644 components/driver/esp32s3/include/driver/temp_sensor.h create mode 100644 components/driver/esp32s3/include/driver/touch_sensor.h create mode 100644 components/efuse/esp32s3/component.mk create mode 100644 components/efuse/esp32s3/esp_efuse_table.c create mode 100644 components/efuse/esp32s3/esp_efuse_table.csv create mode 100644 components/efuse/esp32s3/include/esp_efuse_table.h create mode 100644 components/efuse/esp32s3/sources.cmake create mode 100644 components/efuse/include/esp32s3/esp_efuse.h create mode 100644 components/efuse/private_include/esp32s3/esp_efuse_utility.h create mode 100644 components/efuse/src/esp32s3/esp_efuse_api.c create mode 100644 components/efuse/src/esp32s3/esp_efuse_fields.c create mode 100644 components/efuse/src/esp32s3/esp_efuse_utility.c create mode 100644 components/esp32s3/include/esp32s3/rtc.h delete mode 100644 components/esp32s3/sleep_modes.c create mode 100644 components/esp_gdbstub/esp32s3/gdbstub_esp32s3.c create mode 100644 components/esp_gdbstub/esp32s3/gdbstub_target_config.h create mode 100644 components/esp_wifi/esp32s3/esp_adapter.c create mode 100644 components/esp_wifi/esp32s3/include/phy_init_data.h create mode 100644 components/idf_test/include/esp32s3/idf_performance_target.h create mode 100644 components/mbedtls/port/esp32s3/aes.c create mode 100644 components/mbedtls/port/esp32s3/bignum.c create mode 100644 components/mbedtls/port/esp32s3/esp_sha1.c create mode 100644 components/mbedtls/port/esp32s3/esp_sha256.c create mode 100644 components/mbedtls/port/esp32s3/esp_sha512.c create mode 100644 components/mbedtls/port/esp32s3/sha.c create mode 100644 components/mbedtls/port/include/esp32s3/aes.h create mode 100644 components/mbedtls/port/include/esp32s3/crypto_dma.h create mode 100644 components/mbedtls/port/include/esp32s3/gcm.h create mode 100644 components/mbedtls/port/include/esp32s3/sha.h create mode 100644 components/spi_flash/esp32s3/flash_ops_esp32s3.c create mode 100644 components/ulp/include/esp32s3/ulp.h diff --git a/components/app_trace/app_trace_util.c b/components/app_trace/app_trace_util.c index d7ad98497b..238fd60205 100644 --- a/components/app_trace/app_trace_util.c +++ b/components/app_trace/app_trace_util.c @@ -20,6 +20,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif /////////////////////////////////////////////////////////////////////////////// diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 9f326154a1..235f87778a 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -1,3 +1,5 @@ +idf_build_get_property(target IDF_TARGET) + set(srcs "adc_common.c" "dac_common.c" @@ -23,9 +25,9 @@ set(srcs "twai.c" "uart.c") -set(includes "include") +set(includes "include" "${target}/include") -if(IDF_TARGET STREQUAL "esp32") +if(${target} STREQUAL "esp32") # SDMMC and MCPWM are in ESP32 only. list(APPEND srcs "mcpwm.c" "sdio_slave.c" @@ -37,7 +39,7 @@ if(IDF_TARGET STREQUAL "esp32") list(APPEND includes "esp32/include") endif() -if(IDF_TARGET STREQUAL "esp32s2") +if(${target} STREQUAL "esp32s2") list(APPEND srcs "esp32s2/rtc_tempsensor.c" "esp32s2/touch_sensor.c" "esp32s2/adc.c" diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c index b8cdc7b8b9..109c9cabfc 100644 --- a/components/driver/adc_common.c +++ b/components/driver/adc_common.c @@ -82,7 +82,7 @@ static _lock_t adc2_wifi_lock; #define ADC2_WIFI_LOCK_TRY_ACQUIRE() _lock_try_acquire( &adc2_wifi_lock ) #define ADC2_WIFI_LOCK_CHECK() ((uint32_t *)adc2_wifi_lock != NULL) -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) #define ADC2_WIFI_LOCK_ACQUIRE() #define ADC2_WIFI_LOCK_RELEASE() @@ -101,7 +101,7 @@ static _lock_t adc1_dma_lock; #define ADC1_DMA_LOCK_ACQUIRE() _lock_acquire( &adc1_dma_lock ) #define ADC1_DMA_LOCK_RELEASE() _lock_release( &adc1_dma_lock ) -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #ifdef CONFIG_PM_ENABLE static esp_pm_lock_handle_t s_adc2_arbiter_lock; #endif //CONFIG_PM_ENABLE @@ -209,7 +209,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits) { #ifdef CONFIG_IDF_TARGET_ESP32 ADC_CHECK(bits < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG); -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) ADC_CHECK(bits == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG); #endif @@ -231,7 +231,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits) * @return * - ESP_OK Success */ -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 esp_err_t adc_rtc_reset(void) { ADC_ENTER_CRITICAL(); @@ -284,7 +284,7 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit) { #ifdef CONFIG_IDF_TARGET_ESP32 ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG); -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG); #endif @@ -341,13 +341,17 @@ int adc1_get_raw(adc1_channel_t channel) adc_power_on(); ADC_ENTER_CRITICAL(); -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#ifdef CONFIG_IDF_TARGET_ESP32 + adc_hal_hall_disable(); //Disable other peripherals. + adc_hal_amp_disable(); //Currently the LNA is not open, close it by default. +#endif +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_set_init_code(ADC_NUM_1, channel); // calibration for adc #endif adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC); //Set controller adc_hal_convert(ADC_NUM_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid. ADC_EXIT_CRITICAL(); -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_hal_rtc_reset(); //Reset FSM of rtc controller #endif @@ -434,7 +438,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) static inline void adc2_config_width(adc_bits_width_t width_bit) { -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #ifdef CONFIG_PM_ENABLE /* Lock APB clock. */ if (s_adc2_arbiter_lock == NULL) { @@ -455,7 +459,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel) } else if ( channel == ADC2_CHANNEL_9 ) { dac_output_disable(DAC_CHANNEL_2); } -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 1 dac_output_disable(DAC_CHANNEL_1); } else if ( channel == ADC2_CHANNEL_7 ) { @@ -478,7 +482,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG); -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG); #endif @@ -494,12 +498,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc2_dac_disable(channel); //disable other peripherals #endif adc2_config_width(width_bit); // in critical section with whole rtc module. because the PWDET use the same registers, place it here. -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_set_init_code(ADC_NUM_2, channel); // calibration for adc #endif adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);// set controller -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #ifdef CONFIG_PM_ENABLE if (s_adc2_arbiter_lock) { esp_pm_lock_acquire(s_adc2_arbiter_lock); @@ -511,7 +515,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc_value = -1; } -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #ifdef CONFIG_PM_ENABLE /* Release APB clock. */ if (s_adc2_arbiter_lock) { @@ -523,7 +527,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * ADC2_WIFI_LOCK_RELEASE(); ADC2_EXIT_CRITICAL(); -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_rtc_reset(); #endif diff --git a/components/driver/esp32s3/include/driver/adc.h b/components/driver/esp32s3/include/driver/adc.h new file mode 100644 index 0000000000..423592db80 --- /dev/null +++ b/components/driver/esp32s3/include/driver/adc.h @@ -0,0 +1,277 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "driver/adc_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ + +/** + * @brief Config ADC module arbiter. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note Default priority: Wi-Fi > RTC > Digital; + * @note In normal use, there is no need to call this interface to config arbiter. + * + * @param adc_unit ADC unit. + * @param config Refer to `adc_arbiter_t`. + * + * @return + * - ESP_OK Success + * - ESP_ERR_NOT_SUPPORTED ADC unit not support arbiter. + */ +esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config); + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ +/** + * @brief ADC digital controller initialization. + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_init(void); + +/** + * @brief ADC digital controller deinitialization. + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_deinit(void); + +/** + * @brief Setting the digital controller. + * + * @param config Pointer to digital controller paramter. Refer to `adc_digi_config_t`. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_controller_config(const adc_digi_config_t *config); + +/** + * @brief Enable digital controller to trigger the measurement. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_start(void); + +/** + * @brief Disable digital controller to trigger the measurement. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_stop(void); + +/*************************************/ +/* Digital controller filter setting */ +/*************************************/ +/** + * @brief Reset adc digital controller filter. + * + * @param idx Filter index. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx); + +/** + * @brief Set adc digital controller filter configuration. + * + * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. + * + * @param idx Filter index. + * @param config See ``adc_digi_filter_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config); + +/** + * @brief Get adc digital controller filter configuration. + * + * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. + * + * @param idx Filter index. + * @param config See ``adc_digi_filter_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config); + +/** + * @brief Enable/disable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. + * + * @param idx Filter index. + * @param enable Enable/Disable filter. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable); + +/**************************************/ +/* Digital controller monitor setting */ +/**************************************/ + +/** + * @brief Config monitor of adc digital controller. + * + * @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time. + * + * @param idx Monitor index. + * @param config See ``adc_digi_monitor_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config); + +/** + * @brief Enable/disable monitor of adc digital controller. + * + * @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time. + * + * @param idx Monitor index. + * @param enable True or false enable monitor. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable); + +/**************************************/ +/* Digital controller intr setting */ +/**************************************/ + +/** + * @brief Enable interrupt of adc digital controller by bitmask. + * + * @param adc_unit ADC unit. + * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); + +/** + * @brief Disable interrupt of adc digital controller by bitmask. + * + * @param adc_unit ADC unit. + * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); + +/** + * @brief Clear interrupt of adc digital controller by bitmask. + * + * @param adc_unit ADC unit. + * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. + * + * @return + * - ESP_OK Success + */ +esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); + +/** + * @brief Get interrupt status mask of adc digital controller. + * + * @param adc_unit ADC unit. + * @return + * - intr Interrupt bitmask, See ``adc_digi_intr_t``. + */ +uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit); + +/** + * @brief Register ADC interrupt handler, the handler is an ISR. + * The handler will be attached to the same CPU core that this function is running on. + * + * @param fn Interrupt handler function. + * @param arg Parameter for handler function + * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred) + * ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. + * + * @return + * - ESP_OK Success + * - ESP_ERR_NOT_FOUND Can not find the interrupt that matches the flags. + * - ESP_ERR_INVALID_ARG Function pointer error. + */ +esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags); + +/** + * @brief Deregister ADC interrupt handler, the handler is an ISR. + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG hander error. + * - ESP_FAIL ISR not be registered. + */ +esp_err_t adc_digi_isr_deregister(void); + +/*--------------------------------------------------------------- + RTC controller setting +---------------------------------------------------------------*/ + +/*--------------------------------------------------------------- + Deprecated API +---------------------------------------------------------------*/ +/** + * @brief Set I2S data source + * + * @param src I2S DMA data source, I2S DMA can get data from digital signals or from ADC. + * + * @deprecated The ESP32S2 don't use I2S DMA. Call ``adc_digi_controller_config`` instead. + * + * @return + * - ESP_OK success + */ +esp_err_t adc_set_i2s_data_source(adc_i2s_source_t src) __attribute__((deprecated)); + +/** + * @brief Initialize I2S ADC mode + * + * @param adc_unit ADC unit index + * @param channel ADC channel index + * + * @deprecated The ESP32S2 don't use I2S DMA. Call ``adc_digi_controller_config`` instead. + * + * @return + * - ESP_OK success + * - ESP_ERR_INVALID_ARG Parameter error + */ +esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel) __attribute__((deprecated)); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/components/driver/esp32s3/include/driver/dac.h b/components/driver/esp32s3/include/driver/dac.h new file mode 100644 index 0000000000..6efcc5c2b0 --- /dev/null +++ b/components/driver/esp32s3/include/driver/dac.h @@ -0,0 +1,80 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "driver/dac_common.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ + +/** + * @brief DAC digital controller initialization. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_init(void); + +/** + * @brief DAC digital controller deinitialization. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_deinit(void); + +/** + * @brief Setting the DAC digital controller. + * + * @param cfg Pointer to digital controller paramter. See ``dac_digi_config_t``. + * + * @return + * - ESP_OK success + * - ESP_ERR_INVALID_ARG Parameter error + */ +esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg); + +/** + * @brief DAC digital controller start output voltage. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_start(void); + +/** + * @brief DAC digital controller stop output voltage. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_stop(void); + +/** + * @brief Reset DAC digital controller FIFO. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_fifo_reset(void); + +/** + * @brief Reset DAC digital controller. + * @return + * - ESP_OK success + */ +esp_err_t dac_digi_reset(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/esp32s3/include/driver/temp_sensor.h b/components/driver/esp32s3/include/driver/temp_sensor.h new file mode 100644 index 0000000000..9a6a2b5c93 --- /dev/null +++ b/components/driver/esp32s3/include/driver/temp_sensor.h @@ -0,0 +1,105 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief temperature sensor range option. + */ +typedef enum { + TSENS_DAC_L0 = 0, /*!< offset = -2, measure range: 50℃ ~ 125℃, error < 3℃. */ + TSENS_DAC_L1, /*!< offset = -1, measure range: 20℃ ~ 100℃, error < 2℃. */ + TSENS_DAC_L2, /*!< offset = 0, measure range:-10℃ ~ 80℃, error < 1℃. */ + TSENS_DAC_L3, /*!< offset = 1, measure range:-30℃ ~ 50℃, error < 2℃. */ + TSENS_DAC_L4, /*!< offset = 2, measure range:-40℃ ~ 20℃, error < 3℃. */ + TSENS_DAC_MAX, + TSENS_DAC_DEFAULT = TSENS_DAC_L2, +} temp_sensor_dac_offset_t; + +/** + * @brief Configuration for temperature sensor reading + */ +typedef struct { + temp_sensor_dac_offset_t dac_offset; /*!< The temperature measurement range is configured with a built-in temperature offset DAC. */ + uint8_t clk_div; /*!< Default: 6 */ +} temp_sensor_config_t; + +/** + * @brief temperature sensor default setting. + */ +#define TSENS_CONFIG_DEFAULT() {.dac_offset = TSENS_DAC_L2, \ + .clk_div = 6} + +/** + * @brief Set parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens); + +/** + * @brief Get parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens); + +/** + * @brief Start temperature sensor measure. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG + */ +esp_err_t temp_sensor_start(void); + +/** + * @brief Stop temperature sensor measure. + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_stop(void); + +/** + * @brief Read temperature sensor raw data. + * @param tsens_out Pointer to raw data, Range: 0 ~ 255 + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG `tsens_out` is NULL + * - ESP_ERR_INVALID_STATE temperature sensor dont start + */ +esp_err_t temp_sensor_read_raw(uint32_t *tsens_out); + +/** + * @brief Read temperature sensor data that is converted to degrees Celsius. + * @note Should not be called from interrupt. + * @param celsius The measure output value. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG ARG is NULL. + * - ESP_ERR_INVALID_STATE The ambient temperature is out of range. + */ +esp_err_t temp_sensor_read_celsius(float *celsius); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/esp32s3/include/driver/touch_sensor.h b/components/driver/esp32s3/include/driver/touch_sensor.h new file mode 100644 index 0000000000..9c7d6c6d6d --- /dev/null +++ b/components/driver/esp32s3/include/driver/touch_sensor.h @@ -0,0 +1,582 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver/touch_sensor_common.h" + +/** + * @brief Set touch sensor FSM start + * @note Start FSM after the touch sensor FSM mode is set. + * @note Call this function will reset benchmark of all touch channels. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_fsm_start(void); + +/** + * @brief Stop touch sensor FSM. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_fsm_stop(void); + +/** + * @brief Trigger a touch sensor measurement, only support in SW mode of FSM + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_sw_start(void); + +/** + * @brief Set touch sensor times of charge and discharge and sleep time. + * Excessive total time will slow down the touch response. + * Too small measurement time will not be sampled enough, resulting in inaccurate measurements. + * + * @note The greater the duty cycle of the measurement time, the more system power is consumed. + * @param sleep_cycle The touch sensor will sleep after each measurement. + * sleep_cycle decide the interval between each measurement. + * t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency). + * The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function. + * @param meas_times The times of charge and discharge in each measure process of touch channels. + * The timer frequency is 8Mhz. Range: 0 ~ 0xffff. + * Recommended typical value: Modify this value to make the measurement time around 1ms. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_times); + +/** + * @brief Get touch sensor times of charge and discharge and sleep time + * @param sleep_cycle Pointer to accept sleep cycle number + * @param meas_times Pointer to accept measurement times count. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_times); + +/** + * @brief Set connection type of touch channel in idle status. + * When a channel is in measurement mode, other initialized channels are in idle mode. + * The touch channel is generally adjacent to the trace, so the connection state of the idle channel + * affects the stability and sensitivity of the test channel. + * The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels. + * The `CONN_GND`(grounding) setting increases the stability of touch channels. + * @param type Select idle channel connect to high resistance state or ground. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_set_idle_channel_connect(touch_pad_conn_type_t type); + +/** + * @brief Set connection type of touch channel in idle status. + * When a channel is in measurement mode, other initialized channels are in idle mode. + * The touch channel is generally adjacent to the trace, so the connection state of the idle channel + * affects the stability and sensitivity of the test channel. + * The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels. + * The `CONN_GND`(grounding) setting increases the stability of touch channels. + * @param type Pointer to connection type. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type); + +/** + * @brief Set the trigger threshold of touch sensor. + * The threshold determines the sensitivity of the touch sensor. + * The threshold is the original value of the trigger state minus the benchmark value. + * @note If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered. + * @param touch_num touch pad index + * @param threshold threshold of touch sensor. Should be less than the max change value of touch. + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold); + +/** + * @brief Get touch sensor trigger threshold + * @param touch_num touch pad index + * @param threshold pointer to accept threshold + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if argument is wrong + */ +esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold); + +/** + * @brief Register touch channel into touch sensor scan group. + * The working mode of the touch sensor is cyclically scanned. + * This function will set the scan bits according to the given bitmask. + * @note If set this mask, the FSM timer should be stop firsty. + * @note The touch sensor that in scan map, should be deinit GPIO function firstly by `touch_pad_io_init`. + * @param enable_mask bitmask of touch sensor scan group. + * e.g. TOUCH_PAD_NUM14 -> BIT(14) + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_set_channel_mask(uint16_t enable_mask); + +/** + * @brief Get the touch sensor scan group bit mask. + * @param enable_mask Pointer to bitmask of touch sensor scan group. + * e.g. TOUCH_PAD_NUM14 -> BIT(14) + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_get_channel_mask(uint16_t *enable_mask); + +/** + * @brief Clear touch channel from touch sensor scan group. + * The working mode of the touch sensor is cyclically scanned. + * This function will clear the scan bits according to the given bitmask. + * @note If clear all mask, the FSM timer should be stop firsty. + * @param enable_mask bitmask of touch sensor scan group. + * e.g. TOUCH_PAD_NUM14 -> BIT(14) + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_clear_channel_mask(uint16_t enable_mask); + +/** + * @brief Configure parameter for each touch channel. + * @note Touch num 0 is denoise channel, please use `touch_pad_denoise_enable` to set denoise function + * @param touch_num touch pad index + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG if argument wrong + * - ESP_FAIL if touch pad not initialized + */ +esp_err_t touch_pad_config(touch_pad_t touch_num); + +/** + * @brief Reset the FSM of touch module. + * @note Call this function after `touch_pad_fsm_stop`. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_reset(void); + +/** + * @brief Get the current measure channel. + * @note Should be called when touch sensor measurement is in cyclic scan mode. + * @return + * - touch channel number + */ +touch_pad_t touch_pad_get_current_meas_channel(void); + +/** + * @brief Get the touch sensor interrupt status mask. + * @return + * - touch interrupt bit + */ +uint32_t touch_pad_read_intr_status_mask(void); + +/** + * @brief Enable touch sensor interrupt by bitmask. + * @param int_mask Pad mask to enable interrupts + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_intr_enable(touch_pad_intr_mask_t int_mask); + +/** + * @brief Disable touch sensor interrupt by bitmask. + * @param int_mask Pad mask to disable interrupts + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask); + +/** + * @brief Clear touch sensor interrupt by bitmask. + * @param int_mask Pad mask to clear interrupts + * @return + * - ESP_OK on success + */ +esp_err_t touch_pad_intr_clear(touch_pad_intr_mask_t int_mask); + +/** + * @brief Register touch-pad ISR. + * The handler will be attached to the same CPU core that this function is running on. + * @param fn Pointer to ISR handler + * @param arg Parameter for ISR + * @param intr_mask Enable touch sensor interrupt handler by bitmask. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Arguments error + * - ESP_ERR_NO_MEM No memory + */ +esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_mask_t intr_mask); + +/** + * @brief Enable/disable the timeout check and set timeout threshold for all touch sensor channels measurements. + * If enable: When the touch reading of a touch channel exceeds the measurement threshold, a timeout interrupt will be generated. + * If disable: the FSM does not check if the channel under measurement times out. + * + * @note The threshold compared with touch readings. + * @note In order to avoid abnormal short circuit of some touch channels. This function should be turned on. + * Ensure the normal operation of other touch channels. + * + * @param enable true(default): Enable the timeout check; false: Disable the timeout check. + * @param threshold For all channels, the maximum value that will not be exceeded during normal operation. + * +* @return + * - ESP_OK Success + */ +esp_err_t touch_pad_timeout_set(bool enable, uint32_t threshold); + +/** + * @brief Call this interface after timeout to make the touch channel resume normal work. Point on the next channel to measure. + * If this API is not called, the touch FSM will stop the measurement after timeout interrupt. + * + * @note Call this API after finishes the exception handling by user. + * + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_timeout_resume(void); + +/** + * @brief get raw data of touch sensor. + * @note After the initialization is complete, the "raw_data" is max value. You need to wait for a measurement + * cycle before you can read the correct touch value. + * @param touch_num touch pad index + * @param raw_data pointer to accept touch sensor value + * @return + * - ESP_OK Success + * - ESP_FAIL Touch channel 0 haven't this parameter. + */ + +esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data); + +/** + * @brief get benchmark of touch sensor. + * @note After initialization, the benchmark value is the maximum during the first measurement period. + * @param touch_num touch pad index + * @param benchmark pointer to accept touch sensor benchmark value + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter. + */ +esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark); + +/** + * @brief Get smoothed data that obtained by filtering the raw data. + * + * @param touch_num touch pad index + * @param smooth pointer to smoothed data + */ +esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth); + +/** + * @brief Force reset benchmark to raw data of touch sensor. + * @param touch_num touch pad index + * - TOUCH_PAD_MAX Reset basaline of all channels + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num); + +/** + * @brief set parameter of touch sensor filter and detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * @param filter_info select filter type and threshold of detection algorithm + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_filter_set_config(touch_filter_config_t *filter_info); + +/** + * @brief get parameter of touch sensor filter and detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * @param filter_info select filter type and threshold of detection algorithm + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info); + +/** + * @brief enable touch sensor filter for detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_filter_enable(void); + +/** + * @brief disable touch sensor filter for detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_filter_disable(void); + +/** + * @brief set parameter of denoise pad (TOUCH_PAD_NUM0). + * T0 is an internal channel that does not have a corresponding external GPIO. + * T0 will work simultaneously with the measured channel Tn. Finally, the actual + * measured value of Tn is the value after subtracting lower bits of T0. + * The noise reduction function filters out interference introduced simultaneously on all channels, + * such as noise introduced by power supplies and external EMI. + * @param denoise parameter of denoise + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_denoise_set_config(touch_pad_denoise_t *denoise); + +/** + * @brief get parameter of denoise pad (TOUCH_PAD_NUM0). + * @param denoise Pointer to parameter of denoise + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise); + +/** + * @brief enable denoise function. + * T0 is an internal channel that does not have a corresponding external GPIO. + * T0 will work simultaneously with the measured channel Tn. Finally, the actual + * measured value of Tn is the value after subtracting lower bits of T0. + * The noise reduction function filters out interference introduced simultaneously on all channels, + * such as noise introduced by power supplies and external EMI. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_denoise_enable(void); + +/** + * @brief disable denoise function. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_denoise_disable(void); + +/** + * @brief Get denoise measure value (TOUCH_PAD_NUM0). + * @param data Pointer to receive denoise value + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_denoise_read_data(uint32_t *data); + +/** + * @brief set parameter of waterproof function. + * + * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. + * It is generally designed as a grid and is placed around the touch buttons. + * + * @param waterproof parameter of waterproof + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_waterproof_set_config(touch_pad_waterproof_t *waterproof); + +/** + * @brief get parameter of waterproof function. + * @param waterproof parameter of waterproof + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof); + +/** + * @brief Enable parameter of waterproof function. + * Should be called after function ``touch_pad_waterproof_set_config``. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_waterproof_enable(void); + +/** + * @brief Disable parameter of waterproof function. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_waterproof_disable(void); + +/** + * @brief Enable/disable proximity function of touch channels. + * The proximity sensor measurement is the accumulation of touch channel measurements. + * + * @note Supports up to three touch channels configured as proximity sensors. + * @param touch_num touch pad index + * @param enabled true: enable the proximity function; false: disable the proximity function + * @return + * - ESP_OK: Configured correctly. + * - ESP_ERR_INVALID_ARG: Touch channel number error. + * - ESP_ERR_NOT_SUPPORTED: Don't support configured. + */ +esp_err_t touch_pad_proximity_enable(touch_pad_t touch_num, bool enabled); + +/** + * @brief Set measure count of proximity channel. + * The proximity sensor measurement is the accumulation of touch channel measurements. + * + * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`. + * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`. + * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255. + * @return + * - ESP_OK: Configured correctly. + * - ESP_ERR_INVALID_ARG: Touch channel number error. + */ +esp_err_t touch_pad_proximity_set_count(touch_pad_t touch_num, uint32_t count); + +/** + * @brief Get measure count of proximity channel. + * The proximity sensor measurement is the accumulation of touch channel measurements. + * + * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`. + * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`. + * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255. + * @return + * - ESP_OK: Configured correctly. + * - ESP_ERR_INVALID_ARG: Touch channel number error. + */ +esp_err_t touch_pad_proximity_get_count(touch_pad_t touch_num, uint32_t *count); + +/** + * @brief Get the accumulated measurement of the proximity sensor. + * The proximity sensor measurement is the accumulation of touch channel measurements. + * @param touch_num touch pad index + * @param measure_out If the accumulation process does not end, the `measure_out` is the process value. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Touch num is not proximity + */ +esp_err_t touch_pad_proximity_get_data(touch_pad_t touch_num, uint32_t *measure_out); + +/** + * @brief Get parameter of touch sensor sleep channel. + * The touch sensor can works in sleep mode to wake up sleep. + * + * @note After the sleep channel is configured, Please use special functions for sleep channel. + * e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading. + * + * @param slp_config touch sleep pad config. + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_channel_get_info(touch_pad_sleep_channel_t *slp_config); + +/** + * @brief Enable/Disable sleep channel function for touch sensor. + * The touch sensor can works in sleep mode to wake up sleep. + * + * @note ESP32S2 only support one sleep channel. + * @note After the sleep channel is configured, Please use special functions for sleep channel. + * e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading. + * + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param enable true: enable sleep pad for touch sensor; false: disable sleep pad for touch sensor; + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_channel_enable(touch_pad_t pad_num, bool enable); + +/** + * @brief Enable/Disable proximity function for sleep channel. + * The touch sensor can works in sleep mode to wake up sleep. + * + * @note ESP32S2 only support one sleep channel. + * + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param enable true: enable proximity for sleep channel; false: disable proximity for sleep channel; + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool enable); + +/** + * @brief Set the trigger threshold of touch sensor in deep sleep. + * The threshold determines the sensitivity of the touch sensor. + * + * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep. + * + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param touch_thres touch sleep pad threshold + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thres); + +/** + * @brief Get the trigger threshold of touch sensor in deep sleep. + * The threshold determines the sensitivity of the touch sensor. + * + * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep. + * + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param touch_thres touch sleep pad threshold + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres); + +/** + * @brief Read benchmark of touch sensor sleep channel. + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param benchmark pointer to accept touch sensor benchmark value + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG parameter is NULL + */ +esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark); + +/** + * @brief Read smoothed data of touch sensor sleep channel. + * Smoothed data is filtered from the raw data. + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param smooth_data pointer to accept touch sensor smoothed data + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG parameter is NULL + */ +esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smooth_data); + +/** + * @brief Read raw data of touch sensor sleep channel. + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param raw_data pointer to accept touch sensor raw data + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG parameter is NULL + */ +esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data); + +/** + * @brief Reset benchmark of touch sensor sleep channel. + * + * @return + * - ESP_OK Success + */ +esp_err_t touch_pad_sleep_channel_reset_benchmark(void); + +/** + * @brief Read proximity count of touch sensor sleep channel. + * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. + * @param proximity_cnt pointer to accept touch sensor proximity count value + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG parameter is NULL + */ +esp_err_t touch_pad_sleep_channel_read_proximity_cnt(touch_pad_t pad_num, uint32_t *proximity_cnt); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/i2s.c b/components/driver/i2s.c index 05ff802a0f..74f0fa4072 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -498,7 +498,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg) portBASE_TYPE high_priority_task_awoken = 0; - lldesc_t *finish_desc; + lldesc_t *finish_desc = NULL; if ((status & I2S_INTR_OUT_DSCR_ERR) || (status & I2S_INTR_IN_DSCR_ERR)) { ESP_EARLY_LOGE(I2S_TAG, "dma error, interrupt status: 0x%08x", status); diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index e7c93ef9aa..59280896bd 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -138,6 +138,8 @@ static inline uint32_t get_dma_periph(int dma_chan) } #elif CONFIG_IDF_TARGET_ESP32 return PERIPH_SPI_DMA_MODULE; +#else + return 0; #endif } diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c index 95a6a3f3af..09fc34dfce 100644 --- a/components/driver/spi_master.c +++ b/components/driver/spi_master.c @@ -190,7 +190,7 @@ static inline bool is_valid_host(spi_host_device_t host) { #if CONFIG_IDF_TARGET_ESP32 return host >= SPI1_HOST && host <= SPI3_HOST; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // SPI_HOST (SPI1_HOST) is not supported by the SPI Master driver on ESP32-S2 return host >= SPI2_HOST && host <= SPI3_HOST; #endif diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index 2cecf4275d..b1dad114c0 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -80,7 +80,7 @@ static inline bool is_valid_host(spi_host_device_t host) { #if CONFIG_IDF_TARGET_ESP32 return host >= SPI1_HOST && host <= SPI3_HOST; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // SPI_HOST (SPI1_HOST) is not supported by the SPI Slave driver on ESP32-S2 return host >= SPI2_HOST && host <= SPI3_HOST; #endif diff --git a/components/driver/timer.c b/components/driver/timer.c index 5df314d034..1e3ed5a56f 100644 --- a/components/driver/timer.c +++ b/components/driver/timer.c @@ -272,18 +272,25 @@ esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num, switch (group_num) { case TIMER_GROUP_0: default: - if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) { - intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer_num; - } else { + intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer_num; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) { intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer_num; } +#endif timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_0][timer_num]->hal), &status_reg, &mask); break; case TIMER_GROUP_1: + intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) { + intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer_num; + } +#endif if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) { intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num; } else { - intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer_num; + intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num; } timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_1][timer_num]->hal), &status_reg, &mask); break; diff --git a/components/driver/touch_sensor_common.c b/components/driver/touch_sensor_common.c index e5bbc74906..6063dad4bb 100644 --- a/components/driver/touch_sensor_common.c +++ b/components/driver/touch_sensor_common.c @@ -42,7 +42,7 @@ static const char *TOUCH_TAG = "TOUCH_SENSOR"; #define TOUCH_CHANNEL_CHECK(channel) do { \ TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \ } while (0); -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif defined CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define TOUCH_CHANNEL_CHECK(channel) do { \ TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \ TOUCH_CHECK(channel != SOC_TOUCH_DENOISE_CHANNEL, "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \ @@ -194,7 +194,7 @@ esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold) TOUCH_EXIT_CRITICAL(); return ESP_OK; } -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold) { TOUCH_CHANNEL_CHECK(touch_num); @@ -214,7 +214,7 @@ esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold) touch_hal_get_threshold(touch_num, threshold); return ESP_OK; } -#elif defined CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold) { TOUCH_CHANNEL_CHECK(touch_num); diff --git a/components/driver/uart.c b/components/driver/uart.c index 911d098189..81a85a263b 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -35,6 +35,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif #ifdef CONFIG_UART_ISR_IN_IRAM diff --git a/components/efuse/esp32s3/component.mk b/components/efuse/esp32s3/component.mk new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c new file mode 100644 index 0000000000..f3d9208bf8 --- /dev/null +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -0,0 +1,13 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at", +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h new file mode 100644 index 0000000000..57423323de --- /dev/null +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -0,0 +1,123 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at", +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +#ifdef __cplusplus +extern "C" { +#endif + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TINY_BASIC[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; + +#ifdef __cplusplus +} +#endif + diff --git a/components/efuse/esp32s3/sources.cmake b/components/efuse/esp32s3/sources.cmake new file mode 100644 index 0000000000..492216be21 --- /dev/null +++ b/components/efuse/esp32s3/sources.cmake @@ -0,0 +1 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c") \ No newline at end of file diff --git a/components/efuse/include/esp32s3/esp_efuse.h b/components/efuse/include/esp32s3/esp_efuse.h new file mode 100644 index 0000000000..c33eca5bbb --- /dev/null +++ b/components/efuse/include/esp32s3/esp_efuse.h @@ -0,0 +1,69 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32S3 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index ab792a49b7..84d03c5a22 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -27,6 +27,8 @@ extern "C" { #include "esp32/esp_efuse.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/esp_efuse.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/esp_efuse.h" #endif #define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */ diff --git a/components/efuse/private_include/esp32s3/esp_efuse_utility.h b/components/efuse/private_include/esp32s3/esp_efuse_utility.h new file mode 100644 index 0000000000..68c855e0ae --- /dev/null +++ b/components/efuse/private_include/esp32s3/esp_efuse_utility.h @@ -0,0 +1,30 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_BLOCKS 11 /* The number of blocks. */ +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/private_include/esp_efuse_utility.h b/components/efuse/private_include/esp_efuse_utility.h index ad45fae0aa..6999127b66 100644 --- a/components/efuse/private_include/esp_efuse_utility.h +++ b/components/efuse/private_include/esp_efuse_utility.h @@ -27,6 +27,8 @@ extern "C" { #include "esp32/esp_efuse_utility.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/esp_efuse_utility.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/esp_efuse_utility.h" #endif /** diff --git a/components/efuse/src/esp32s3/esp_efuse_api.c b/components/efuse/src/esp32s3/esp_efuse_api.c new file mode 100644 index 0000000000..dbac5ffffc --- /dev/null +++ b/components/efuse/src/esp32s3/esp_efuse_api.c @@ -0,0 +1,13 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. diff --git a/components/efuse/src/esp32s3/esp_efuse_fields.c b/components/efuse/src/esp32s3/esp_efuse_fields.c new file mode 100644 index 0000000000..aa65783146 --- /dev/null +++ b/components/efuse/src/esp32s3/esp_efuse_fields.c @@ -0,0 +1,13 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. diff --git a/components/efuse/src/esp32s3/esp_efuse_utility.c b/components/efuse/src/esp32s3/esp_efuse_utility.c new file mode 100644 index 0000000000..aa65783146 --- /dev/null +++ b/components/efuse/src/esp32s3/esp_efuse_utility.c @@ -0,0 +1,13 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. diff --git a/components/esp32s3/CMakeLists.txt b/components/esp32s3/CMakeLists.txt index 911dee42b9..5c2890a73f 100644 --- a/components/esp32s3/CMakeLists.txt +++ b/components/esp32s3/CMakeLists.txt @@ -21,7 +21,6 @@ else() "memprot.c" "pm_esp32s3.c" "pm_trace.c" - "sleep_modes.c" "spiram.c" "spiram_psram.c" "system_api_esp32s3.c") diff --git a/components/esp32s3/include/esp32s3/rtc.h b/components/esp32s3/include/esp32s3/rtc.h new file mode 100644 index 0000000000..296292e21d --- /dev/null +++ b/components/esp32s3/include/esp32s3/rtc.h @@ -0,0 +1,39 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32s2/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp32s3/ld/esp32s3.ld b/components/esp32s3/ld/esp32s3.ld index ab069788ca..33d16c902a 100644 --- a/components/esp32s3/ld/esp32s3.ld +++ b/components/esp32s3/ld/esp32s3.ld @@ -11,7 +11,7 @@ #define SRAM_IRAM_START 0x40370000 #define SRAM_DRAM_START 0x3FC80000 #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x40054000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_DRAM_END 0x403BC000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) #define SRAM_DRAM_ORG (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) diff --git a/components/esp32s3/memprot.c b/components/esp32s3/memprot.c index 00dbf2063c..b87c98ad6e 100644 --- a/components/esp32s3/memprot.c +++ b/components/esp32s3/memprot.c @@ -18,7 +18,7 @@ #include -bool esp_memprot_is_assoc_intr_any() +bool esp_memprot_is_assoc_intr_any(void) { return true; } diff --git a/components/esp32s3/sleep_modes.c b/components/esp32s3/sleep_modes.c deleted file mode 100644 index 5bdf392f19..0000000000 --- a/components/esp32s3/sleep_modes.c +++ /dev/null @@ -1,717 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include -#include -#include "esp_attr.h" -#include "esp_sleep.h" -#include "esp_private/esp_timer_private.h" -#include "esp_log.h" -#include "esp32s3/clk.h" -#include "esp_newlib.h" -#include "esp_spi_flash.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/rtc.h" -#include "esp_rom_uart.h" -#include "esp_rom_sys.h" -#include "soc/cpu.h" -#include "soc/rtc.h" -#include "soc/spi_periph.h" -#include "soc/dport_reg.h" -#include "soc/extmem_reg.h" -#include "soc/soc_memory_layout.h" -#include "soc/uart_caps.h" -#include "hal/wdt_hal.h" -#include "hal/clk_gate_ll.h" -#include "driver/rtc_io.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "sdkconfig.h" - -// If light sleep time is less than that, don't power down flash -#define FLASH_PD_MIN_SLEEP_TIME_US 2000 - -// Time from VDD_SDIO power up to first flash read in ROM code -#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700 - -// Extra time it takes to enter and exit light sleep and deep sleep -// For deep sleep, this is until the wake stub runs (not the app). -#ifdef CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS -#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ) -#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ) -#else -#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ) -#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ) -#endif // CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS - -// Minimal amount of time we can sleep for -#define LIGHT_SLEEP_MIN_TIME_US 200 - -#define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \ - (source == value)) - -/** - * Internal structure which holds all requested deep sleep parameters - */ -typedef struct { - esp_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX]; - uint64_t sleep_duration; - uint32_t wakeup_triggers : 15; - uint32_t ext1_trigger_mode : 1; - uint32_t ext1_rtc_gpio_mask : 18; - uint32_t ext0_trigger_level : 1; - uint32_t ext0_rtc_gpio_num : 5; - uint32_t sleep_time_adjustment; - uint64_t rtc_ticks_at_sleep_start; -} sleep_config_t; - -static sleep_config_t s_config = { - .pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO }, - .wakeup_triggers = 0 -}; - -/* Internal variable used to track if light sleep wakeup sources are to be - expected when determining wakeup cause. */ -static bool s_light_sleep_wakeup = false; - -/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc() - is not thread-safe. */ -static _lock_t lock_rtc_memory_crc; - -static const char *TAG = "sleep"; - -static uint32_t get_power_down_flags(void); -static void ext0_wakeup_prepare(void); -static void ext1_wakeup_prepare(void); -static void timer_wakeup_prepare(void); -static void touch_wakeup_prepare(void); - -/* Wake from deep sleep stub - See esp_deepsleep.h esp_wake_deep_sleep() comments for details. -*/ -esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void) -{ - _lock_acquire(&lock_rtc_memory_crc); - uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG); - set_rtc_memory_crc(); - uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG); - REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc); - _lock_release(&lock_rtc_memory_crc); - - if (stored_crc != calc_crc) { - return NULL; - } - esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG); - if (!esp_ptr_executable(stub_ptr)) { - return NULL; - } - return stub_ptr; -} - -void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub) -{ - _lock_acquire(&lock_rtc_memory_crc); - REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub); - set_rtc_memory_crc(); - _lock_release(&lock_rtc_memory_crc); -} - -void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) -{ - REG_SET_BIT(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_TRACE_ENA); -} - -void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void); - -void esp_deep_sleep(uint64_t time_in_us) -{ - esp_sleep_enable_timer_wakeup(time_in_us); - esp_deep_sleep_start(); -} - -static void IRAM_ATTR flush_uarts(void) -{ - for (int i = 0; i < SOC_UART_NUM; ++i) { - if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) { - esp_rom_uart_tx_wait_idle(i); - } - } -} - -static void IRAM_ATTR suspend_uarts(void) -{ - for (int i = 0; i < SOC_UART_NUM; ++i) { - if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) { - REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); - REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); - while (REG_GET_FIELD(UART_FSM_STATUS_REG(i), UART_ST_UTX_OUT) != 0) { - ; - } - } - } -} - -static void IRAM_ATTR resume_uarts(void) -{ - for (int i = 0; i < SOC_UART_NUM; ++i) { - if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) { - REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); - REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); - REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XON); - } - } -} - -static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) -{ - // Stop UART output so that output is not lost due to APB frequency change. - // For light sleep, suspend UART output — it will resume after wakeup. - // For deep sleep, wait for the contents of UART FIFO to be sent. - if (pd_flags & RTC_SLEEP_PD_DIG) { - flush_uarts(); - } else { - suspend_uarts(); - } - - // Save current frequency and switch to XTAL - // Save current frequency and switch to XTAL - rtc_cpu_freq_config_t cpu_freq_config; - rtc_clk_cpu_freq_get_config(&cpu_freq_config); - rtc_clk_cpu_freq_set_xtal(); - - // Configure pins for external wakeup - if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { - ext0_wakeup_prepare(); - } - if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) { - ext1_wakeup_prepare(); - } - // Enable ULP wakeup - if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) { - // no-op for esp32s3 - } - // Enable Touch wakeup - if (s_config.wakeup_triggers & RTC_TOUCH_TRIG_EN) { - touch_wakeup_prepare(); - } - - uint32_t reject_triggers = 0; - if ((pd_flags & RTC_SLEEP_PD_DIG) == 0) { - /* Light sleep, enable sleep reject for faster return from this function, - * in case the wakeup is already triggerred. - */ - reject_triggers = s_config.wakeup_triggers; - } - - // Enter sleep - rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); - rtc_sleep_init(config); - - // Configure timer wakeup - if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) && - s_config.sleep_duration > 0) { - timer_wakeup_prepare(); - } - - uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, reject_triggers, 1); - - // Restore CPU frequency - rtc_clk_cpu_freq_set_config(&cpu_freq_config); - - // re-enable UART output - resume_uarts(); - - return result; -} - -void IRAM_ATTR esp_deep_sleep_start(void) -{ - // record current RTC time - s_config.rtc_ticks_at_sleep_start = rtc_time_get(); - esp_sync_counters_rtc_and_frc(); - // Configure wake stub - if (esp_get_deep_sleep_wake_stub() == NULL) { - esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep); - } - - // Decide which power domains can be powered down - uint32_t pd_flags = get_power_down_flags(); - - // Correct the sleep time - s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; - - // Enter sleep - esp_sleep_start(RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | pd_flags); - - // Because RTC is in a slower clock domain than the CPU, it - // can take several CPU cycles for the sleep mode to start. - while (1) { - ; - } -} - -/** - * Helper function which handles entry to and exit from light sleep - * Placed into IRAM as flash may need some time to be powered on. - */ -static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, - uint32_t flash_enable_time_us, - rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline)); - -static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, - uint32_t flash_enable_time_us, - rtc_vddsdio_config_t vddsdio_config) -{ - // Enter sleep - esp_err_t err = esp_sleep_start(pd_flags); - - // If VDDSDIO regulator was controlled by RTC registers before sleep, - // restore the configuration. - if (vddsdio_config.force) { - rtc_vddsdio_set_config(vddsdio_config); - } - - // If SPI flash was powered down, wait for it to become ready - if (pd_flags & RTC_SLEEP_PD_VDDSDIO) { - // Wait for the flash chip to start up - esp_rom_delay_us(flash_enable_time_us); - } - return err; -} - -esp_err_t esp_light_sleep_start(void) -{ - static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED; - portENTER_CRITICAL(&light_sleep_lock); - /* We will be calling esp_timer_private_advance inside DPORT access critical - * section. Make sure the code on the other CPU is not holding esp_timer - * lock, otherwise there will be deadlock. - */ - esp_timer_private_lock(); - s_config.rtc_ticks_at_sleep_start = rtc_time_get(); - uint64_t frc_time_at_start = esp_timer_get_time(); - DPORT_STALL_OTHER_CPU_START(); - - // Decide which power domains can be powered down - uint32_t pd_flags = get_power_down_flags(); - - // Amount of time to subtract from actual sleep time. - // This is spent on entering and leaving light sleep. - s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US; - - // Decide if VDD_SDIO needs to be powered down; - // If it needs to be powered down, adjust sleep time. - const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US; - -#ifndef CONFIG_SPIRAM - const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US, - flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US); - - if (s_config.sleep_duration > vddsdio_pd_sleep_duration) { - pd_flags |= RTC_SLEEP_PD_VDDSDIO; - s_config.sleep_time_adjustment += flash_enable_time_us; - } -#endif //CONFIG_SPIRAM - - rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config(); - - // Safety net: enable WDT in case exit from light sleep fails - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here. - if (!wdt_was_enabled) { - wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); - uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_enable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - } - - // Enter sleep, then wait for flash to be ready on wakeup - esp_err_t err = esp_light_sleep_inner(pd_flags, - flash_enable_time_us, vddsdio_config); - - s_light_sleep_wakeup = true; - - // FRC1 has been clock gated for the duration of the sleep, correct for that. - uint64_t rtc_ticks_at_end = rtc_time_get(); - uint64_t frc_time_at_end = esp_timer_get_time(); - - uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, - esp_clk_slowclk_cal_get()); - uint64_t frc_time_diff = frc_time_at_end - frc_time_at_start; - - int64_t time_diff = rtc_time_diff - frc_time_diff; - /* Small negative values (up to 1 RTC_SLOW clock period) are possible, - * for very small values of sleep_duration. Ignore those to keep esp_timer - * monotonic. - */ - if (time_diff > 0) { - esp_timer_private_advance(time_diff); - } - esp_set_time_from_rtc(); - - esp_timer_private_unlock(); - DPORT_STALL_OTHER_CPU_END(); - if (!wdt_was_enabled) { - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - } - portEXIT_CRITICAL(&light_sleep_lock); - return err; -} - -esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source) -{ - // For most of sources it is enough to set trigger mask in local - // configuration structure. The actual RTC wake up options - // will be updated by esp_sleep_start(). - if (source == ESP_SLEEP_WAKEUP_ALL) { - s_config.wakeup_triggers = 0; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) { - s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN; - s_config.sleep_duration = 0; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) { - s_config.ext0_rtc_gpio_num = 0; - s_config.ext0_trigger_level = 0; - s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) { - s_config.ext1_rtc_gpio_mask = 0; - s_config.ext1_trigger_mode = 0; - s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) { - s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) { - s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN; - } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) { - s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN); - } -#ifdef CONFIG_ESP32S3_ULP_COPROC_ENABLED - else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) { - s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN; - } -#endif - else { - ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source); - return ESP_ERR_INVALID_STATE; - } - return ESP_OK; -} - -esp_err_t esp_sleep_enable_ulp_wakeup(void) -{ - s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN); - return ESP_OK; -} - -esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us) -{ - s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; - s_config.sleep_duration = time_in_us; - return ESP_OK; -} - -static void timer_wakeup_prepare(void) -{ - uint32_t period = esp_clk_slowclk_cal_get(); - int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment; - if (sleep_duration < 0) { - sleep_duration = 0; - } - int64_t rtc_count_delta = rtc_time_us_to_slowclk(sleep_duration, period); - rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta); - SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); - SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); -} - -/* In deep sleep mode, only the sleep channel is supported, and other touch channels should be turned off. */ -static void touch_wakeup_prepare(void) -{ - touch_pad_sleep_channel_t slp_config; - touch_pad_fsm_stop(); - touch_pad_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX); - touch_pad_sleep_channel_get_info(&slp_config); - touch_pad_set_channel_mask(BIT(slp_config.touch_num)); - touch_pad_fsm_start(); -} - -esp_err_t esp_sleep_enable_touchpad_wakeup(void) -{ - if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) { - ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0"); - return ESP_ERR_INVALID_STATE; - } - s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN; - return ESP_OK; -} - -touch_pad_t esp_sleep_get_touchpad_wakeup_status(void) -{ - if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) { - return TOUCH_PAD_MAX; - } - touch_pad_t pad_num; - esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b - assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero"); - return pad_num; -} - -esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level) -{ - if (level < 0 || level > 1) { - return ESP_ERR_INVALID_ARG; - } - if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { - ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); - return ESP_ERR_INVALID_STATE; - } - s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num); - s_config.ext0_trigger_level = level; - s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN; - return ESP_OK; -} - -static void ext0_wakeup_prepare(void) -{ - int rtc_gpio_num = s_config.ext0_rtc_gpio_num; - // Set GPIO to be used for wakeup - REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtc_gpio_num); - // Set level which will trigger wakeup - SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, - s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S); - // Find GPIO descriptor in the rtc_io_desc table and configure the pad - const rtc_io_desc_t *desc = &rtc_io_desc[rtc_gpio_num]; - REG_SET_BIT(desc->reg, desc->mux); - SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); - REG_SET_BIT(desc->reg, desc->ie); -} - -esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode) -{ - if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) { - return ESP_ERR_INVALID_ARG; - } - // Translate bit map of GPIO numbers into the bit map of RTC IO numbers - uint32_t rtc_gpio_mask = 0; - for (int gpio = 0; mask; ++gpio, mask >>= 1) { - if ((mask & 1) == 0) { - continue; - } - if (!RTC_GPIO_IS_VALID_GPIO(gpio)) { - ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio); - return ESP_ERR_INVALID_ARG; - } - rtc_gpio_mask |= BIT(rtc_io_number_get(gpio)); - } - s_config.ext1_rtc_gpio_mask = rtc_gpio_mask; - s_config.ext1_trigger_mode = mode; - s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN; - return ESP_OK; -} - -static void ext1_wakeup_prepare(void) -{ - // Configure all RTC IOs selected as ext1 wakeup inputs - uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask; - for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) { - int rtc_pin = rtc_io_number_get(gpio); - if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) { - continue; - } - const rtc_io_desc_t *desc = &rtc_io_desc[rtc_pin]; - // Route pad to RTC - REG_SET_BIT(desc->reg, desc->mux); - SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func); - // set input enable in sleep mode - REG_SET_BIT(desc->reg, desc->ie); - // Pad configuration depends on RTC_PERIPH state in sleep mode - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) { - // RTC_PERIPH will be powered down, so RTC_IO_ registers will - // loose their state. Lock pad configuration. - // Pullups/pulldowns also need to be disabled. - REG_CLR_BIT(desc->reg, desc->pulldown); - REG_CLR_BIT(desc->reg, desc->pullup); - REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, desc->hold_force); - } - // Keep track of pins which are processed to bail out early - rtc_gpio_mask &= ~BIT(rtc_pin); - } - // Clear state from previous wakeup - REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); - // Set pins to be used for wakeup - REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, s_config.ext1_rtc_gpio_mask); - // Set logic function (any low, all high) - SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, - s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S); -} - -uint64_t esp_sleep_get_ext1_wakeup_status(void) -{ - if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) { - return 0; - } - uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); - // Translate bit map of RTC IO numbers into the bit map of GPIO numbers - uint64_t gpio_mask = 0; - for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) { - if (!RTC_GPIO_IS_VALID_GPIO(gpio)) { - continue; - } - int rtc_pin = rtc_io_number_get(gpio); - if ((status & BIT(rtc_pin)) == 0) { - continue; - } - gpio_mask |= 1ULL << gpio; - } - return gpio_mask; -} - -esp_err_t esp_sleep_enable_gpio_wakeup(void) -{ - if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { - ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); - return ESP_ERR_INVALID_STATE; - } - s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN; - return ESP_OK; -} - -esp_err_t esp_sleep_enable_uart_wakeup(int uart_num) -{ - if (uart_num == 0) { - s_config.wakeup_triggers |= RTC_UART0_TRIG_EN; - } else if (uart_num == 1) { - s_config.wakeup_triggers |= RTC_UART1_TRIG_EN; - } else { - return ESP_ERR_INVALID_ARG; - } - - return ESP_OK; -} - -esp_err_t esp_sleep_enable_wifi_wakeup(void) -{ - s_config.wakeup_triggers |= RTC_MAC_TRIG_EN; - return ESP_OK; -} - -esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) -{ - if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) { - return ESP_SLEEP_WAKEUP_UNDEFINED; - } - - uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); - if (wakeup_cause & RTC_EXT0_TRIG_EN) { - return ESP_SLEEP_WAKEUP_EXT0; - } else if (wakeup_cause & RTC_EXT1_TRIG_EN) { - return ESP_SLEEP_WAKEUP_EXT1; - } else if (wakeup_cause & RTC_TIMER_TRIG_EN) { - return ESP_SLEEP_WAKEUP_TIMER; - } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) { - return ESP_SLEEP_WAKEUP_TOUCHPAD; - } else if (wakeup_cause & RTC_ULP_TRIG_EN) { - return ESP_SLEEP_WAKEUP_ULP; - } else if (wakeup_cause & RTC_GPIO_TRIG_EN) { - return ESP_SLEEP_WAKEUP_GPIO; - } else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) { - return ESP_SLEEP_WAKEUP_UART; - } else if (wakeup_cause & RTC_MAC_TRIG_EN) { - return ESP_SLEEP_WAKEUP_WIFI; - } else if (wakeup_cause & RTC_COCPU_TRIG_EN) { - return ESP_SLEEP_WAKEUP_ULP; - } else if (wakeup_cause & RTC_COCPU_TRAP_TRIG_EN) { - return ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG; - } else { - return ESP_SLEEP_WAKEUP_UNDEFINED; - } -} - -esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, - esp_sleep_pd_option_t option) -{ - if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) { - return ESP_ERR_INVALID_ARG; - } - s_config.pd_options[domain] = option; - return ESP_OK; -} - -static uint32_t get_power_down_flags(void) -{ - // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF. - - // RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP - // is used and RTC_SLOW_MEM is Auto. - // If there is any data placed into .rtc.data or .rtc.bss segments, and - // RTC_SLOW_MEM is Auto, keep it powered up as well. - - // Labels are defined in the linker script, see esp32s3.ld. - extern int _rtc_slow_length; - - if ((s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) && - ((size_t) &_rtc_slow_length > 0 || - (s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) { - s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON; - } - - // RTC_FAST_MEM is needed for deep sleep stub. - // If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub - // can run. - // In the new chip revision, deep sleep stub will be optional, - // and this can be changed. - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) { - s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON; - } - - // RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup. - // If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH. - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) { - if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) { - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON; - } else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { - // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH - // prevents ULP timer and touch FSMs from working correctly. - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF; - } - } - - if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) { - s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF; - } - - const char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */}; - ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s", - option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]], - option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]], - option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]); - - // Prepare flags based on the selected options - uint32_t pd_flags = 0; - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) { - pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM; - } - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) { - pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM; - } - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) { - pd_flags |= RTC_SLEEP_PD_RTC_PERIPH; - } - return pd_flags; -} diff --git a/components/esp_gdbstub/esp32s3/gdbstub_esp32s3.c b/components/esp_gdbstub/esp32s3/gdbstub_esp32s3.c new file mode 100644 index 0000000000..1f1a733d0c --- /dev/null +++ b/components/esp_gdbstub/esp32s3/gdbstub_esp32s3.c @@ -0,0 +1,51 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "sdkconfig.h" +#include "soc/uart_periph.h" +#include "soc/gpio_periph.h" +#include "esp_gdbstub_common.h" + +#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM + +void esp_gdbstub_target_init() +{ +} + +int esp_gdbstub_getchar() +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { + ; + } + return REG_READ(UART_FIFO_AHB_REG(UART_NUM)); +} + +void esp_gdbstub_putchar(int c) +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { + ; + } + REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c); +} + +int esp_gdbstub_readmem(intptr_t addr) +{ + if (addr < 0x20000000 || addr >= 0x80000000) { + /* see cpu_configure_region_protection */ + return -1; + } + uint32_t val_aligned = *(uint32_t *)(addr & (~3)); + uint32_t shift = (addr & 3) * 8; + return (val_aligned >> shift) & 0xff; +} diff --git a/components/esp_gdbstub/esp32s3/gdbstub_target_config.h b/components/esp_gdbstub/esp32s3/gdbstub_target_config.h new file mode 100644 index 0000000000..c4adad7069 --- /dev/null +++ b/components/esp_gdbstub/esp32s3/gdbstub_target_config.h @@ -0,0 +1,18 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* Number of extra TIE defined registers, not listed in the XCHAL */ +#define GDBSTUB_EXTRA_TIE_SIZE 1 diff --git a/components/esp_rom/include/esp32s3/rom/opi_flash.h b/components/esp_rom/include/esp32s3/rom/opi_flash.h index bb209f67f0..be7fcb06a9 100644 --- a/components/esp_rom/include/esp32s3/rom/opi_flash.h +++ b/components/esp_rom/include/esp32s3/rom/opi_flash.h @@ -40,6 +40,7 @@ typedef struct { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_OP_MODE_RDCMD_DOUT 0x3B #define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 diff --git a/components/esp_rom/include/esp32s3/rom/spi_flash.h b/components/esp_rom/include/esp32s3/rom/spi_flash.h index fb060c15c1..44d447e933 100644 --- a/components/esp_rom/include/esp32s3/rom/spi_flash.h +++ b/components/esp_rom/include/esp32s3/rom/spi_flash.h @@ -111,6 +111,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 92080e0004..a104b396b5 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -42,9 +42,18 @@ #include "esp32s2/rom/cache.h" #include "esp32s2/rom/rtc.h" #include "esp32s2/spiram.h" -#include "soc/periph_defs.h" #include "esp32s2/dport_access.h" #include "esp32s2/memprot.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rtc.h" +#include "esp32s3/brownout.h" +#include "esp32s3/cache_err_int.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" +#include "esp32s3/spiram.h" +#include "esp32s3/dport_access.h" +#include "esp32s3/memprot.h" +#include "soc/assist_debug_reg.h" #endif #include "bootloader_flash_config.h" @@ -53,8 +62,10 @@ #include "hal/rtc_io_hal.h" #include "hal/wdt_hal.h" +#include "soc/rtc.h" #include "soc/dport_reg.h" #include "soc/efuse_reg.h" +#include "soc/periph_defs.h" #include "soc/cpu.h" #include "soc/rtc.h" #include "soc/spinlock.h" @@ -117,15 +128,20 @@ void IRAM_ATTR call_start_cpu1(void) bootloader_init_mem(); #if CONFIG_ESP_CONSOLE_UART_NONE - ets_install_putc1(NULL); - ets_install_putc2(NULL); + esp_rom_install_channel_putc(1, NULL); + esp_rom_install_channel_putc(2, NULL); #else // CONFIG_ESP_CONSOLE_UART_NONE ets_install_uart_printf(); esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM); #endif +#if CONFIG_IDF_TARGET_ESP32 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE); DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE); +#else + REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1); + REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1); +#endif s_cpu_up[1] = true; ESP_EARLY_LOGI(TAG, "App cpu up."); @@ -153,23 +169,38 @@ static void start_other_core(void) { // If not the single core variant of ESP32 - check this since there is // no separate soc_caps.h for the single core variant. - if (!REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) { + bool is_single_core = false; +#if CONFIG_IDF_TARGET_ESP32 + is_single_core = REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); +#endif + if (!is_single_core) { ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1); +#if CONFIG_IDF_TARGET_ESP32 Cache_Flush(1); Cache_Read_Enable(1); +#endif esp_cpu_unstall(1); // Enable clock and reset APP CPU. Note that OpenOCD may have already // enabled clock and taken APP CPU out of reset. In this case don't reset // APP CPU again, as that will clear the breakpoints which may have already // been set. +#if CONFIG_IDF_TARGET_ESP32 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) { DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); } +#elif CONFIG_IDF_TARGET_ESP32S3 + if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) { + REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); + REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); + } +#endif ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1); volatile bool cpus_up = false; @@ -207,8 +238,6 @@ void IRAM_ATTR call_start_cpu0(void) RESET_REASON rst_reas[1]; #endif - bootloader_init_mem(); - // Move exception vectors to IRAM cpu_hal_set_vecbase(&_init_start); @@ -259,6 +288,20 @@ void IRAM_ATTR call_start_cpu0(void) #endif #endif +#if CONFIG_IDF_TARGET_ESP32S3 + /* Configure the mode of instruction cache : cache size, cache line size. */ + extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); + rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); + + /* If we need use SPIRAM, we should use data cache. + Configure the mode of data : cache size, cache line size.*/ + Cache_Suspend_DCache(); + extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); + rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); + Cache_Resume_DCache(0); +#endif + + bootloader_init_mem(); #if CONFIG_SPIRAM_BOOT_INIT if (esp_spiram_init() != ESP_OK) { #if CONFIG_IDF_TARGET_ESP32 @@ -282,11 +325,7 @@ void IRAM_ATTR call_start_cpu0(void) #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_cpu_up[0] = true; #endif -#ifdef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ - ESP_EARLY_LOGI(TAG, "cpu freq: %d", CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ); -#else - ESP_EARLY_LOGI(TAG, "cpu freq: %d", CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); -#endif + ESP_EARLY_LOGI(TAG, "Pro cpu up."); #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors @@ -294,7 +333,11 @@ void IRAM_ATTR call_start_cpu0(void) start_other_core(); #else ESP_EARLY_LOGI(TAG, "Single core mode"); +#if CONFIG_IDF_TARGET_ESP32 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core +#elif CONFIG_IDF_TARGET_ESP32S3 + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); +#endif #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #endif // SOC_CPU_CORES_NUM > 1 @@ -368,7 +411,11 @@ void IRAM_ATTR call_start_cpu0(void) intr_matrix_clear(); #ifdef CONFIG_ESP_CONSOLE_UART - esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, APB_CLK_FREQ, CONFIG_ESP_CONSOLE_UART_BAUDRATE); + uint32_t clock_hz = rtc_clk_apb_freq_get(); +#if CONFIG_IDF_TARGET_ESP32S3 + clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM +#endif + esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); #endif rtcio_hal_unhold_all(); diff --git a/components/esp_system/port/panic_handler.c b/components/esp_system/port/panic_handler.c index 37d334a177..61382f4651 100644 --- a/components/esp_system/port/panic_handler.c +++ b/components/esp_system/port/panic_handler.c @@ -45,6 +45,12 @@ #include "soc/extmem_reg.h" #include "soc/cache_memory.h" #include "soc/rtc_cntl_reg.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/cache_err_int.h" +#include "esp32s3/memprot.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" +#include "soc/rtc_cntl_reg.h" #endif #include "esp_private/panic_internal.h" @@ -378,6 +384,78 @@ static inline void print_memprot_err_details(const void *f) panic_print_hex( (uint32_t)fault_addr ); panic_print_str(" not permitted.\r\n"); } + +#elif CONFIG_IDF_TARGET_ESP32S3 +static inline void print_cache_err_details(const void* f) +{ + uint32_t vaddr = 0, size = 0; + uint32_t status; + status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG); + for (int i = 0; i < 32; i++) { + switch (status & BIT(i)) { + case EXTMEM_ICACHE_SYNC_OP_FAULT_ST: + //TODO, which size should fetch + //vaddr = REG_READ(EXTMEM_ICACHE_MEM_SYNC0_REG); + //size = REG_READ(EXTMEM_ICACHE_MEM_SYNC1_REG); + panic_print_str("Icache sync parameter configuration error, the error address and size is 0x"); + panic_print_hex(vaddr); + panic_print_str("(0x"); + panic_print_hex(size); + panic_print_str(")\r\n"); + break; + case EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST: + //TODO, which size should fetch + vaddr = REG_READ(EXTMEM_ICACHE_PRELOAD_ADDR_REG); + size = REG_READ(EXTMEM_ICACHE_PRELOAD_SIZE_REG); + panic_print_str("Icache preload parameter configuration error, the error address and size is 0x"); + panic_print_hex(vaddr); + panic_print_str("(0x"); + panic_print_hex(size); + panic_print_str(")\r\n"); + break; + case EXTMEM_DCACHE_SYNC_OP_FAULT_ST: + //TODO, which size should fetch + //vaddr = REG_READ(EXTMEM_DCACHE_MEM_SYNC0_REG); + //size = REG_READ(EXTMEM_DCACHE_MEM_SYNC1_REG); + panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x"); + panic_print_hex(vaddr); + panic_print_str("(0x"); + panic_print_hex(size); + panic_print_str(")\r\n"); + break; + case EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST: + //TODO, which size should fetch + vaddr = REG_READ(EXTMEM_DCACHE_PRELOAD_ADDR_REG); + size = REG_READ(EXTMEM_DCACHE_PRELOAD_SIZE_REG); + panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x"); + panic_print_hex(vaddr); + panic_print_str("(0x"); + panic_print_hex(size); + panic_print_str(")\r\n"); + break; + case EXTMEM_DCACHE_WRITE_FLASH_ST: + panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n"); + break; + case EXTMEM_MMU_ENTRY_FAULT_ST: + vaddr = REG_READ(EXTMEM_CACHE_MMU_FAULT_VADDR_REG); + panic_print_str("MMU entry fault error occurred while accessing the address 0x"); + panic_print_hex(vaddr); + + if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { + panic_print_str(" (invalid mmu entry)"); + } + panic_print_str("\r\n"); + break; + default: + break; + } + } + panic_print_str("\r\n"); +} + +static inline void print_memprot_err_details(const void *f) +{ +} #endif static void frame_to_panic_info(XtExcFrame *frame, panic_info_t *info, bool pseudo_excause) @@ -409,7 +487,7 @@ static void frame_to_panic_info(XtExcFrame *frame, panic_info_t *info, bool pseu "Interrupt wdt timeout on CPU1", #if CONFIG_IDF_TARGET_ESP32 "Cache disabled but cached memory region accessed", -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 "Cache exception", #endif }; @@ -426,7 +504,7 @@ static void frame_to_panic_info(XtExcFrame *frame, panic_info_t *info, bool pseu info->exception = PANIC_EXCEPTION_DEBUG; } -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 if (frame->exccause == PANIC_RSN_CACHEERR) { if ( esp_memprot_is_assoc_intr_any() ) { info->details = print_memprot_err_details; diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index f61c52f305..b8d7b67cd8 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -48,14 +48,16 @@ #include "esp32/rom/cache.h" #include "esp32/clk.h" #include "esp32/rom/rtc.h" -#include "esp32/rom/uart.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/rtc.h" -#include "esp32s2/rom/ets_sys.h" #include "soc/extmem_reg.h" -#include "esp32s2/rom/uart.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" +#include "soc/extmem_reg.h" #endif // If light sleep time is less than that, don't power down flash @@ -68,6 +70,8 @@ #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ #elif CONFIG_IDF_TARGET_ESP32S2 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#elif CONFIG_IDF_TARGET_ESP32S3 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ #endif #if defined(CONFIG_IDF_TARGET_ESP32) @@ -318,7 +322,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) #ifdef CONFIG_IDF_TARGET_ESP32 uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, reject_triggers); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, reject_triggers, 1); #endif @@ -524,7 +528,7 @@ esp_err_t esp_sleep_enable_ulp_wakeup(void) #else // CONFIG_ESP32_ULP_COPROC_ENABLED return ESP_ERR_INVALID_STATE; #endif // CONFIG_ESP32_ULP_COPROC_ENABLED -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN); return ESP_OK; #endif @@ -720,6 +724,9 @@ esp_err_t esp_sleep_enable_wifi_wakeup(void) #elif CONFIG_IDF_TARGET_ESP32S2 s_config.wakeup_triggers |= RTC_WIFI_TRIG_EN; return ESP_OK; +#elif CONFIG_IDF_TARGET_ESP32S3 + s_config.wakeup_triggers |= RTC_MAC_TRIG_EN; + return ESP_OK; #endif } @@ -732,7 +739,7 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) #ifdef CONFIG_IDF_TARGET_ESP32 uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); #endif diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index b801faba5a..6edb9359f9 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -59,12 +59,15 @@ // [refactor-todo] make this file completely target-independent #if CONFIG_IDF_TARGET_ESP32 +#include "esp32/clk.h" #include "esp32/spiram.h" #include "esp32/brownout.h" #elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/clk.h" #include "esp32s2/spiram.h" #include "esp32s2/brownout.h" #elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #include "esp32s3/spiram.h" #include "esp32s3/brownout.h" #endif @@ -311,6 +314,8 @@ static void start_cpu0_default(void) { ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); + int cpu_freq = esp_clk_cpu_freq(); + ESP_EARLY_LOGI(TAG, "cpu freq: %d", cpu_freq); // Display information about the current running image. if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { diff --git a/components/esp_system/system_api.c b/components/esp_system/system_api.c index 137cab621a..33541c6072 100644 --- a/components/esp_system/system_api.c +++ b/components/esp_system/system_api.c @@ -10,6 +10,8 @@ #include "esp_rom_uart.h" #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/memprot.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/memprot.h" #endif diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c index dba3fc3c53..8fae106ce8 100644 --- a/components/esp_system/system_time.c +++ b/components/esp_system/system_time.c @@ -25,6 +25,8 @@ #include "esp32/rtc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rtc.h" #endif #include "esp_private/startup_internal.h" diff --git a/components/esp_system/test/test_sleep.c b/components/esp_system/test/test_sleep.c index 716e5b1ebe..fed5dd7338 100644 --- a/components/esp_system/test/test_sleep.c +++ b/components/esp_system/test/test_sleep.c @@ -26,6 +26,9 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" #include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" +#include "esp32s3/rom/rtc.h" #endif diff --git a/components/esp_timer/Kconfig b/components/esp_timer/Kconfig index 15fd196bc2..f7dabf23fe 100644 --- a/components/esp_timer/Kconfig +++ b/components/esp_timer/Kconfig @@ -26,7 +26,7 @@ menu "High resolution timer (esp_timer)" choice ESP_TIMER_IMPL prompt "Hardware timer to use for esp_timer" default ESP_TIMER_IMPL_TG0_LAC if IDF_TARGET_ESP32 - default ESP_TIMER_IMPL_SYSTIMER if IDF_TARGET_ESP32S2 + default ESP_TIMER_IMPL_SYSTIMER help esp_timer APIs can be implemented using different hardware timers. @@ -47,7 +47,7 @@ menu "High resolution timer (esp_timer)" config ESP_TIMER_IMPL_SYSTIMER bool "SYSTIMER" - depends on IDF_TARGET_ESP32S2 + depends on !IDF_TARGET_ESP32 endchoice diff --git a/components/esp_timer/src/esp_timer_impl_systimer.c b/components/esp_timer/src/esp_timer_impl_systimer.c index fce86a5eaf..169366eebc 100644 --- a/components/esp_timer/src/esp_timer_impl_systimer.c +++ b/components/esp_timer/src/esp_timer_impl_systimer.c @@ -103,8 +103,13 @@ void esp_timer_impl_advance(int64_t time_us) esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) { s_alarm_handler = alarm_handler; +#ifdef SOC_SYSTIMER_INT_LEVEL + int int_type = 0; +#else + int int_type = ESP_INTR_FLAG_EDGE; +#endif // SOC_SYSTIMER_INT_LEVEL esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, - ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_EDGE, + ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM | int_type, &timer_alarm_isr, NULL, &s_timer_interrupt_handle); if (err != ESP_OK) { @@ -112,9 +117,10 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) goto err_intr_alloc; } - systimer_hal_enable_counter(SYSTIMER_COUNTER_0); systimer_hal_init(); + systimer_hal_enable_counter(SYSTIMER_COUNTER_0); systimer_hal_select_alarm_mode(SYSTIMER_ALARM_2, SYSTIMER_ALARM_MODE_ONESHOT); + systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_2, SYSTIMER_COUNTER_0); /* TODO: if SYSTIMER is used for anything else, access to SYSTIMER_INT_ENA_REG has to be * protected by a shared spinlock. Since this code runs as part of early startup, this diff --git a/components/esp_timer/src/ets_timer_legacy.c b/components/esp_timer/src/ets_timer_legacy.c index dc5586a240..14d5f02a7d 100644 --- a/components/esp_timer/src/ets_timer_legacy.c +++ b/components/esp_timer/src/ets_timer_legacy.c @@ -24,7 +24,6 @@ #include "esp_log.h" #include "esp_attr.h" #include "esp_intr_alloc.h" -#include "soc/frc_timer_reg.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" diff --git a/components/esp_wifi/CMakeLists.txt b/components/esp_wifi/CMakeLists.txt index ee3ce89634..c101a054d9 100644 --- a/components/esp_wifi/CMakeLists.txt +++ b/components/esp_wifi/CMakeLists.txt @@ -1,5 +1,13 @@ idf_build_get_property(idf_target IDF_TARGET) +# remove these when wifi support is ready on esp32-s3 +if(${idf_target} STREQUAL "esp32s3") + idf_component_register(INCLUDE_DIRS "include" + REQUIRES esp_event + PRIV_REQUIRES wpa_supplicant nvs_flash esp_netif) + return() +endif() + if(CONFIG_ESP32_NO_BLOBS OR CONFIG_ESP32S2_NO_BLOBS) set(link_binary_libs 0) set(ldfragments) diff --git a/components/esp_wifi/esp32s3/esp_adapter.c b/components/esp_wifi/esp32s3/esp_adapter.c new file mode 100644 index 0000000000..e989f005e8 --- /dev/null +++ b/components/esp_wifi/esp32s3/esp_adapter.c @@ -0,0 +1,13 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. diff --git a/components/esp_wifi/esp32s3/include/phy_init_data.h b/components/esp_wifi/esp32s3/include/phy_init_data.h new file mode 100644 index 0000000000..b09acb8e4b --- /dev/null +++ b/components/esp_wifi/esp32s3/include/phy_init_data.h @@ -0,0 +1,13 @@ +// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index 3069be8a69..f078cb6159 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -57,7 +57,7 @@ menu "Serial flasher config" config ESPTOOLPY_WITH_STUB # Only real reason to disable this is when ESP32-S2 Secure Download Mode is set bool - default "y" + default "y" if !IDF_ENV_FPGA depends on !SECURE_ENABLE_SECURE_ROM_DL_MODE choice ESPTOOLPY_FLASHMODE diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index 10225816df..09549c0311 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit 10225816df4c9c1b078e677e8a75a87778786ad1 +Subproject commit 09549c03111a2b330371d361d56227a457af66c5 diff --git a/components/freertos/xtensa/include/freertos/FreeRTOSConfig.h b/components/freertos/xtensa/include/freertos/FreeRTOSConfig.h index 6e589c673e..95dd00df6f 100644 --- a/components/freertos/xtensa/include/freertos/FreeRTOSConfig.h +++ b/components/freertos/xtensa/include/freertos/FreeRTOSConfig.h @@ -125,6 +125,8 @@ int xt_clock_freq(void) __attribute__((deprecated)); #include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif #if defined(CONFIG_FREERTOS_ASSERT_DISABLE) diff --git a/components/freertos/xtensa/xtensa_init.c b/components/freertos/xtensa/xtensa_init.c index 8581c5bbbb..4bb8b61210 100644 --- a/components/freertos/xtensa/xtensa_init.c +++ b/components/freertos/xtensa/xtensa_init.c @@ -39,6 +39,8 @@ that are implemented in C. #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif #ifdef XT_RTOS_TIMER_INT diff --git a/components/hal/esp32s3/include/hal/clk_gate_ll.h b/components/hal/esp32s3/include/hal/clk_gate_ll.h index bc897ac305..c8fc693b61 100644 --- a/components/hal/esp32s3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s3/include/hal/clk_gate_ll.h @@ -214,6 +214,18 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +{ + DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +{ + DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + static inline void periph_ll_reset(periph_module_t periph) { DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); @@ -228,3 +240,4 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) #ifdef __cplusplus } +#endif diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index 5f6eb3c423..d1051d2c04 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -55,14 +55,14 @@ typedef enum { static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) { if (func == RTCIO_FUNC_RTC) { - SENS.sar_io_mux_conf.iomux_clk_gate_en = 1; + // SENS.sar_io_mux_conf.iomux_clk_gate_en = 1; // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); //0:RTC FUNCTION 1,2,3:Reserved SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func); } else if (func == RTCIO_FUNC_DIGITAL) { CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); - SENS.sar_io_mux_conf.iomux_clk_gate_en = 0; + // SENS.sar_io_mux_conf.iomux_clk_gate_en = 0; } } diff --git a/components/hal/include/hal/dac_types.h b/components/hal/include/hal/dac_types.h index b1f4b6fe65..1adc511a6c 100644 --- a/components/hal/include/hal/dac_types.h +++ b/components/hal/include/hal/dac_types.h @@ -40,7 +40,7 @@ typedef struct { Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */ } dac_cw_config_t; -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 /** * @brief DAC digital controller (DMA mode) work mode. diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h new file mode 100644 index 0000000000..75bbce7015 --- /dev/null +++ b/components/idf_test/include/esp32s3/idf_performance_target.h @@ -0,0 +1,17 @@ +#pragma once + +#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 14.4 + +// SHA256 hardware throughput at 240MHz, threshold set lower than worst case +#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 19.8 +// esp_sha() time to process 32KB of input data from RAM +#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000 +#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 + +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 14000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 100000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 60000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 600000 + +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h index 1abc70c13b..a6ac60ea79 100644 --- a/components/log/include/esp_log.h +++ b/components/log/include/esp_log.h @@ -23,6 +23,8 @@ #include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif #ifdef __cplusplus diff --git a/components/mbedtls/port/esp32s3/aes.c b/components/mbedtls/port/esp32s3/aes.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp32s3/bignum.c b/components/mbedtls/port/esp32s3/bignum.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp32s3/esp_sha1.c b/components/mbedtls/port/esp32s3/esp_sha1.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp32s3/esp_sha256.c b/components/mbedtls/port/esp32s3/esp_sha256.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp32s3/esp_sha512.c b/components/mbedtls/port/esp32s3/esp_sha512.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp32s3/sha.c b/components/mbedtls/port/esp32s3/sha.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/port/esp_sha.c b/components/mbedtls/port/esp_sha.c index 9265033c5f..1791cbf3ca 100644 --- a/components/mbedtls/port/esp_sha.c +++ b/components/mbedtls/port/esp_sha.c @@ -19,6 +19,8 @@ #include "esp32/sha.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/sha.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/sha.h" #endif #include diff --git a/components/mbedtls/port/include/aes_alt.h b/components/mbedtls/port/include/aes_alt.h index ee6cfed6b0..f313d508bd 100644 --- a/components/mbedtls/port/include/aes_alt.h +++ b/components/mbedtls/port/include/aes_alt.h @@ -32,6 +32,8 @@ extern "C" { #include "esp32/aes.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/aes.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/aes.h" #endif typedef esp_aes_context mbedtls_aes_context; diff --git a/components/mbedtls/port/include/esp32s3/aes.h b/components/mbedtls/port/include/esp32s3/aes.h new file mode 100644 index 0000000000..904a0ecdf5 --- /dev/null +++ b/components/mbedtls/port/include/esp32s3/aes.h @@ -0,0 +1,369 @@ +/** + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_AES_H +#define ESP_AES_H + +#include "esp_types.h" +#include "esp32s3/rom/aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* padlock.c and aesni.c rely on these values! */ +#define ESP_AES_ENCRYPT 1 +#define ESP_AES_DECRYPT 0 + +#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + + +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct { + uint8_t key_bytes; + volatile uint8_t key_in_hardware; /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + uint8_t key[32]; +} esp_aes_context; + + +/** + * \brief The AES XTS context-type definition. + */ +typedef struct { + esp_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + esp_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} esp_aes_xts_context; + +/** + * \brief Lock access to AES hardware unit + * + * AES hardware unit can only be used by one + * consumer at a time. + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_acquire_hardware( void ); + +/** + * \brief Unlock access to AES hardware unit + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_release_hardware( void ); + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void esp_aes_init( esp_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void esp_aes_free( esp_aes_context *ctx ); + +/* + * \brief This function initializes the specified AES XTS context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES XTS context to initialize. + */ +void esp_aes_xts_init( esp_aes_xts_context *ctx ); + +/** + * \brief This function releases and clears the specified AES XTS context. + * + * \param ctx The AES XTS context to clear. + */ +void esp_aes_xts_free( esp_aes_xts_context *ctx ); + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); + +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH + */ +int esp_aes_crypt_cbc( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb8( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int esp_aes_crypt_ctr( esp_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an AES-OFB (Output Feedback Mode) + * encryption or decryption operation. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int esp_aes_crypt_ofb( esp_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function prepares an XTS context for encryption and + * sets the encryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * \param key The encryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int esp_aes_xts_setkey_enc( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_aes_xts_setkey_dec( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_encrypt */ +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_decrypt */ +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** AES-XTS buffer encryption/decryption */ +int esp_aes_crypt_xts( esp_aes_xts_context *ctx, int mode, size_t length, const unsigned char data_unit[16], const unsigned char *input, unsigned char *output ); + + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/components/mbedtls/port/include/esp32s3/crypto_dma.h b/components/mbedtls/port/include/esp32s3/crypto_dma.h new file mode 100644 index 0000000000..ce7d67efad --- /dev/null +++ b/components/mbedtls/port/include/esp32s3/crypto_dma.h @@ -0,0 +1,40 @@ +/** + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_CRYPTO_DMA_H +#define ESP_CRYPTO_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Since crypto DMA is shared between DMA-AES and SHA blocks + * Needs to be taken by respective blocks before using Crypto DMA + */ +extern _lock_t crypto_dma_lock; + +#ifdef __cplusplus +} +#endif + +#endif /* crypto_dma.h */ diff --git a/components/mbedtls/port/include/esp32s3/gcm.h b/components/mbedtls/port/include/esp32s3/gcm.h new file mode 100644 index 0000000000..07c80ad5e6 --- /dev/null +++ b/components/mbedtls/port/include/esp32s3/gcm.h @@ -0,0 +1,238 @@ +/** + * \brief AES block cipher, ESP32C hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2019-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_GCM_H +#define ESP_GCM_H + +#include "aes.h" +#include "mbedtls/cipher.h" +#ifdef __cplusplus +extern "C" { +#endif + + +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */ +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function.*/ + +typedef enum { + ESP_AES_GCM_STATE_INIT, + ESP_AES_GCM_STATE_UPDATE, + ESP_AES_GCM_STATE_FINISH +} esp_aes_gcm_state; +/** + * \brief The GCM context structure. + */ +typedef struct { + uint8_t H[16]; /*!< Initial hash value */ + uint8_t ghash[16]; /*!< GHASH value. */ + uint8_t J0[16]; + uint64_t HL[16]; /*!< Precalculated HTable low. */ + uint64_t HH[16]; /*!< Precalculated HTable high. */ + uint8_t ori_j0[16]; /*!< J0 from first iteration. */ + const uint8_t *iv; + size_t iv_len; /*!< The length of IV. */ + uint64_t aad_len; /*!< The total length of the additional data. */ + size_t data_len; + int mode; + const unsigned char *aad; /*!< The additional data. */ + esp_aes_context aes_ctx; + esp_aes_gcm_state gcm_state; +} esp_gcm_context; + +/** + * \brief This function initializes the specified GCM context + * + * \param ctx The GCM context to initialize. + */ +void esp_aes_gcm_init( esp_gcm_context *ctx); + +/** + * \brief This function associates a GCM context with a + * key. + * + * \param ctx The GCM context to initialize. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int esp_aes_gcm_setkey( esp_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data, or NULL + * if \p add_len is 0. + * \param add_len The length of the additional data. If 0, + * \p add is NULL. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_starts( esp_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *aad, + size_t aad_len ); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * ` The function expects input to be a multiple of 16 + * Bytes. Only the last call before calling + * mbedtls_gcm_finish() can be less than 16 Bytes. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_update( esp_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. + * \param tag The buffer for holding the tag. + * \param tag_len The length of the tag to generate. Must be at least four. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_finish( esp_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ); + +/** + * \brief This function clears a GCM context + * + * \param ctx The GCM context to clear. + */ +void esp_aes_gcm_free( esp_gcm_context *ctx); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context to use for encryption or decryption. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_crypt_and_tag( esp_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ); + + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple + * of 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag. + * \param tag_len The length of the tag. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + */ +int esp_aes_gcm_auth_decrypt( esp_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ); + +#ifdef __cplusplus +} +#endif + +#endif /* gcm.h */ diff --git a/components/mbedtls/port/include/esp32s3/sha.h b/components/mbedtls/port/include/esp32s3/sha.h new file mode 100644 index 0000000000..960d63b770 --- /dev/null +++ b/components/mbedtls/port/include/esp32s3/sha.h @@ -0,0 +1,165 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_SHA_H_ +#define _ESP_SHA_H_ + +#include "esp32s3/rom/sha.h" + +/** @brief Low-level support functions for the hardware SHA engine using DMA + * + * @note If you're looking for a SHA API to use, try mbedtls component + * mbedtls/shaXX.h. That API supports hardware acceleration. + * + * The API in this header provides some building blocks for implementing a + * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). + * + * Some technical details about the hardware SHA engine: + * + * - The crypto DMA is shared between the SHA and AES engine, it is not + * possible for them to run calcalutions in parallel. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined in rom/sha.h */ +typedef SHA_TYPE esp_sha_type; + +/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine + * + * @note For more versatile SHA calculations, where data doesn't need + * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. + * + * @note It is not necessary to lock any SHA hardware before calling + * this function, thread safety is managed internally. + * + * @param sha_type SHA algorithm to use. + * + * @param input Input data buffer. + * + * @param ilen Length of input data in bytes. + * + * @param output Buffer for output SHA digest. Output is 20 bytes for + * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for + * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. + */ +void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); + +/** @brief Execute SHA block operation using DMA + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * @param sha_type SHA algorithm to use. + * + * @param input Pointer to the input data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param ilen length of input data should be multiple of block length. + * + * @param buf Pointer to blocks of data that will be prepended + * to data_block before hashing. Useful when there is two sources of + * data that need to be efficiently calculated in a single SHA DMA + * operation. + * + * @param buf_len length of buf data should be multiple of block length. + * Should not be longer than the maximum amount of bytes in a single block + * (128 bytes) + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + * @param t The number of bits for the SHA512/t hash function, with + * output truncated to t bits. Used for calculating the inital hash. + * t is any positive integer between 1 and 512, except 384. + * + * @return 0 if successful + */ +int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block); + +/** + * @brief Read out the current state of the SHA digest + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * If the SHA suffix padding block has been executed already, the + * value that is read is the SHA digest. + * Otherwise, the value that is read is an interim SHA state. + * + * @param sha_type SHA algorithm in use. + * @param digest_state Pointer to a memory buffer to hold the SHA state. Size + * is 20 bytes (SHA1), 32 bytes (SHA2_256), or 64 bytes (SHA2_384, SHA2_512). + */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); + +/** + * @brief Set the current state of the SHA digest + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * When resuming a + * + * @param sha_type SHA algorithm in use. + * @param digest_state + */ +void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state); + + +/** + * @brief Enables the SHA and crypto DMA peripheral and takes the + * locks for both of them. + */ +void esp_sha_acquire_hardware(void); + +/** + * @brief Disables the SHA and crypto DMA peripheral and releases the + * locks. + */ +void esp_sha_release_hardware(void); + +/** + * @brief Sets the initial hash value for SHA512/t. + * + * @note Is generated according to the algorithm described in the TRM, + * chapter SHA-Accelerator + * + * @note The engine must be locked until the value is used for an operation + * or read out. Else you risk another operation overwriting it. + * + * @param t + * + * @return 0 if successful + */ +int esp_sha_512_t_init_hash(uint16_t t); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/components/mbedtls/port/include/gcm_alt.h b/components/mbedtls/port/include/gcm_alt.h index c3d886a7c9..9a79850c02 100644 --- a/components/mbedtls/port/include/gcm_alt.h +++ b/components/mbedtls/port/include/gcm_alt.h @@ -29,6 +29,23 @@ extern "C" { #if defined(MBEDTLS_GCM_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/gcm.h" + + +typedef esp_gcm_context mbedtls_gcm_context; + +#define mbedtls_gcm_init esp_aes_gcm_init +#define mbedtls_gcm_free esp_aes_gcm_free +#define mbedtls_gcm_setkey esp_aes_gcm_setkey +#define mbedtls_gcm_starts esp_aes_gcm_starts +#define mbedtls_gcm_update esp_aes_gcm_update +#define mbedtls_gcm_finish esp_aes_gcm_finish +#define mbedtls_gcm_auth_decrypt esp_aes_gcm_auth_decrypt +#define mbedtls_gcm_crypt_and_tag esp_aes_gcm_crypt_and_tag + +#endif // CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/gcm.h" diff --git a/components/mbedtls/port/include/sha1_alt.h b/components/mbedtls/port/include/sha1_alt.h index a3f05a84c4..628607518e 100644 --- a/components/mbedtls/port/include/sha1_alt.h +++ b/components/mbedtls/port/include/sha1_alt.h @@ -29,6 +29,28 @@ extern "C" { #if defined(MBEDTLS_SHA1_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 + +#include "esp32s3/sha.h" +typedef enum { + ESP_SHA1_STATE_INIT, + ESP_SHA1_STATE_IN_PROCESS +} esp_sha1_state; + +/** + * \brief SHA-1 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + int first_block; /*!< if first then true else false */ + esp_sha_type mode; + esp_sha1_state sha_state; +} mbedtls_sha1_context; + +#endif //CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/sha.h" diff --git a/components/mbedtls/port/include/sha256_alt.h b/components/mbedtls/port/include/sha256_alt.h index db82fb6453..fabb22f9ad 100644 --- a/components/mbedtls/port/include/sha256_alt.h +++ b/components/mbedtls/port/include/sha256_alt.h @@ -29,6 +29,29 @@ extern "C" { #if defined(MBEDTLS_SHA256_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 + +#include "esp32s3/sha.h" + +typedef enum { + ESP_SHA256_STATE_INIT, + ESP_SHA256_STATE_IN_PROCESS +} esp_sha256_state; + +/** + * \brief SHA-256 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + int first_block; /*!< if first then true, else false */ + esp_sha_type mode; + esp_sha256_state sha_state; +} +mbedtls_sha256_context; + +#endif //CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index da58e8a71c..d5c5f6981d 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -30,6 +30,42 @@ extern "C" { #if defined(MBEDTLS_SHA512_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/sha.h" + +typedef enum { + ESP_SHA512_STATE_INIT, + ESP_SHA512_STATE_IN_PROCESS +} esp_sha512_state; + +/** + * \brief SHA-512 context structure + */ +typedef struct { + uint64_t total[2]; /*!< number of bytes processed */ + uint64_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[128]; /*!< data block being processed */ + int first_block; + esp_sha_type mode; + uint32_t t_val; /*!< t_val for 512/t mode */ + esp_sha512_state sha_state; +} mbedtls_sha512_context; + +/** + * @brief Sets the specfic algorithm for SHA512 + * + * @param ctx The mbedtls sha512 context + * + * @param type The mode, used for setting SHA2_512224 and SHA2_512256: + * + */ +void esp_sha512_set_mode(mbedtls_sha512_context *ctx, esp_sha_type type); + +/* For SHA512/t mode the intial hash value will depend on t */ +void esp_sha512_set_t( mbedtls_sha512_context *ctx, uint16_t t_val); + +#endif //CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/sha.h" diff --git a/components/newlib/port/esp_time_impl.c b/components/newlib/port/esp_time_impl.c index f719f228f0..450c71ceea 100644 --- a/components/newlib/port/esp_time_impl.c +++ b/components/newlib/port/esp_time_impl.c @@ -35,12 +35,18 @@ #include "esp32s2/rom/rtc.h" #include "esp32s2/clk.h" #include "esp32s2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" +#include "esp32s3/clk.h" +#include "esp32s3/rtc.h" #endif #if defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC ) \ || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 ) \ || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC ) \ - || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 ) + || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 ) \ + || defined( CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC ) \ + || defined( CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1 ) #define WITH_RTC 1 #endif diff --git a/components/newlib/syscall_table.c b/components/newlib/syscall_table.c index 40ad8bb9af..5f8fea2d0a 100644 --- a/components/newlib/syscall_table.c +++ b/components/newlib/syscall_table.c @@ -31,6 +31,8 @@ #include "esp32/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/libc_stubs.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/libc_stubs.h" #endif static struct _reent s_reent; diff --git a/components/newlib/time.c b/components/newlib/time.c index 5ec5957c14..e4f0eda085 100644 --- a/components/newlib/time.c +++ b/components/newlib/time.c @@ -25,7 +25,6 @@ #include "esp_system.h" #include "esp_attr.h" - #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/soc/soc/esp32s3/include/soc/twai_caps.h b/components/soc/soc/esp32s3/include/soc/twai_caps.h index 88968ba90a..4ad5fbd829 100644 --- a/components/soc/soc/esp32s3/include/soc/twai_caps.h +++ b/components/soc/soc/esp32s3/include/soc/twai_caps.h @@ -18,10 +18,8 @@ extern "C" { #endif -//Chip specific TWAI related macros -//Any even number from 2 to 32768 -#define TWAI_BRP_IS_VALID(brp) ((brp) >= 2 && (brp) <= 32768 && ((brp) & 0x1) == 0) -#define TWAI_BRP_MAX 32768 +#define TWAI_BRP_MIN 2 +#define TWAI_BRP_MAX 32768 #ifdef __cplusplus } diff --git a/components/soc/soc/esp32s3/include/soc/wdev_reg.h b/components/soc/soc/esp32s3/include/soc/wdev_reg.h index 3427eb1077..9d4981c8d7 100644 --- a/components/soc/soc/esp32s3/include/soc/wdev_reg.h +++ b/components/soc/soc/esp32s3/include/soc/wdev_reg.h @@ -17,4 +17,4 @@ #include "soc.h" /* Hardware random number generator register */ -#define WDEV_RND_REG 0x60035110 +#define WDEV_RND_REG 0x6003507C diff --git a/components/soc/src/esp32s3/rtc_clk.c b/components/soc/src/esp32s3/rtc_clk.c index 152cbc6461..ebe6ed27cc 100644 --- a/components/soc/src/esp32s3/rtc_clk.c +++ b/components/soc/src/esp32s3/rtc_clk.c @@ -334,6 +334,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); I2C_WRITEREG_MASK_RTC(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); + rtc_clk_apb_freq_update(80 * MHZ); ets_update_cpu_frequency(cpu_freq_mhz); } diff --git a/components/soc/src/esp32s3/soc_memory_layout.c b/components/soc/src/esp32s3/soc_memory_layout.c index b9a4784b15..de5f26d9cf 100644 --- a/components/soc/src/esp32s3/soc_memory_layout.c +++ b/components/soc/src/esp32s3/soc_memory_layout.c @@ -57,7 +57,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor */ const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM - { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available + { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available #endif #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB { 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM @@ -101,7 +101,9 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_ #endif #ifdef CONFIG_SPIRAM -SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); //SPI RAM gets added later if needed, in spiram.c; reserve it for now +/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this + * memory to heap depending on the actual SPIRAM chip size. */ +SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); #endif #if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0 diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 0c27c81d8c..def10c00ae 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -28,6 +28,11 @@ #include "esp32s2/rom/cache.h" #include "soc/extmem_reg.h" #include "soc/cache_memory.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #endif #include #include @@ -304,6 +309,11 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st *saved_state = ret; #elif CONFIG_IDF_TARGET_ESP32S2 *saved_state = Cache_Suspend_ICache(); +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t icache_state, dcache_state; + icache_state = Cache_Suspend_ICache() << 16; + dcache_state = Cache_Suspend_DCache(); + *saved_state = icache_state | dcache_state; #endif } @@ -323,6 +333,9 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta #endif #elif CONFIG_IDF_TARGET_ESP32S2 Cache_Resume_ICache(saved_state); +#elif CONFIG_IDF_TARGET_ESP32S3 + Cache_Resume_DCache(saved_state & 0xffff); + Cache_Resume_ICache(saved_state >> 16); #endif } @@ -335,6 +348,8 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) #endif #elif CONFIG_IDF_TARGET_ESP32S2 bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); +#elif CONFIG_IDF_TARGET_ESP32S3 + bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0); #endif return result; } @@ -448,16 +463,19 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; uint32_t drom0_in_icache = 1;//always 1 in esp32s2 +#if CONFIG_IDF_TARGET_ESP32S3 + drom0_in_icache = 0; +#endif if (icache_wrap_enable) { -#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B +#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B icache_wrap_size = 16; #else icache_wrap_size = 32; #endif } if (dcache_wrap_enable) { -#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B +#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B dcache_wrap_size = 16; #else dcache_wrap_size = 32; @@ -549,13 +567,13 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable #ifdef CONFIG_FLASHMODE_QIO flash_support_wrap = true; -extern bool spi_flash_support_wrap_size(uint32_t wrap_size); + extern bool spi_flash_support_wrap_size(uint32_t wrap_size); if (!spi_flash_support_wrap_size(flash_wrap_size)) { flash_support_wrap = false; ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size); } #else - ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap."); + ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap."); #endif #ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT @@ -588,6 +606,261 @@ extern bool spi_flash_support_wrap_size(uint32_t wrap_size); return ESP_OK; +} +#endif +#if CONFIG_IDF_TARGET_ESP32S3 +IRAM_ATTR void esp_config_instruction_cache_mode(void) +{ + cache_size_t cache_size; + cache_ways_t cache_ways; + cache_line_size_t cache_line_size; + +#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB + Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_HALF; +#else + Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1); + cache_size = CACHE_SIZE_FULL; +#endif +#if CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS + cache_ways = CACHE_4WAYS_ASSOC; +#else + cache_ways = CACHE_8WAYS_ASSOC; +#endif +#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B + cache_line_size = CACHE_LINE_SIZE_16B; +#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B + cache_line_size = CACHE_LINE_SIZE_32B; +#else + cache_line_size = CACHE_LINE_SIZE_64B; +#endif + ESP_EARLY_LOGI(TAG, "Instruction cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_HALF ? 16 : 32, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size); + Cache_Invalidate_ICache_All(); + extern void Cache_Enable_ICache(uint32_t autoload); + Cache_Enable_ICache(0); +} + +IRAM_ATTR void esp_config_data_cache_mode(void) +{ + cache_size_t cache_size; + cache_ways_t cache_ways; + cache_line_size_t cache_line_size; + +#if CONFIG_ESP32S3_DATA_CACHE_32KB + Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK1, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_HALF; +#else + Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1); + cache_size = CACHE_SIZE_FULL; +#endif +#if CONFIG_ESP32S3_DATA_CACHE_4WAYS + cache_ways = CACHE_4WAYS_ASSOC; +#else + cache_ways = CACHE_8WAYS_ASSOC; +#endif +#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B + cache_line_size = CACHE_LINE_SIZE_16B; +#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B + cache_line_size = CACHE_LINE_SIZE_32B; +#else + cache_line_size = CACHE_LINE_SIZE_64B; +#endif + // ESP_EARLY_LOGI(TAG, "Data cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_HALF ? 32 : 64, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size); + Cache_Invalidate_DCache_All(); +} + +static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) +{ + uint32_t i_autoload, d_autoload; + if (icache) { + i_autoload = Cache_Suspend_ICache(); + } + if (dcache) { + d_autoload = Cache_Suspend_DCache(); + } + REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_FLASH_WRAP_AROUND); + if (icache) { + Cache_Resume_ICache(i_autoload); + } + if (dcache) { + Cache_Resume_DCache(d_autoload); + } +} + +#if CONFIG_ESP32S3_SPIRAM_SUPPORT +static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) +{ + uint32_t i_autoload, d_autoload; + if (icache) { + i_autoload = Cache_Suspend_ICache(); + } + if (dcache) { + d_autoload = Cache_Suspend_DCache(); + } + REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_SRAM_RD_WRAP_AROUND); + if (icache) { + Cache_Resume_ICache(i_autoload); + } + if (dcache) { + Cache_Resume_DCache(d_autoload); + } +} +#endif + +esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable) +{ + int icache_wrap_size = 0, dcache_wrap_size = 0; + int flash_wrap_sizes[2] = {-1, -1}, spiram_wrap_sizes[2] = {-1, -1}; + int flash_wrap_size = 0, spiram_wrap_size = 0; + int flash_count = 0, spiram_count = 0; + int i; + bool flash_spiram_wrap_together, flash_support_wrap = false, spiram_support_wrap = true; + uint32_t drom0_in_icache = 0;//always 0 in chip7.2.4 + + if (icache_wrap_enable) { +#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B + icache_wrap_size = 16; +#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B + icache_wrap_size = 32; +#else + icache_wrap_size = 64; +#endif + } + if (dcache_wrap_enable) { +#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B + dcache_wrap_size = 16; +#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B + dcache_wrap_size = 32; +#else + dcache_wrap_size = 64; +#endif + } + + uint32_t instruction_use_spiram = 0; + uint32_t rodata_use_spiram = 0; +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + extern uint32_t esp_spiram_instruction_access_enabled(); + instruction_use_spiram = esp_spiram_instruction_access_enabled(); +#endif +#if CONFIG_SPIRAM_RODATA + extern uint32_t esp_spiram_rodata_access_enabled(); + rodata_use_spiram = esp_spiram_rodata_access_enabled(); +#endif + + if (instruction_use_spiram) { + spiram_wrap_sizes[0] = icache_wrap_size; + } else { + flash_wrap_sizes[0] = icache_wrap_size; + } + if (rodata_use_spiram) { + if (drom0_in_icache) { + spiram_wrap_sizes[0] = icache_wrap_size; + } else { + spiram_wrap_sizes[1] = dcache_wrap_size; + } +#ifdef CONFIG_EXT_RODATA_SUPPORT + spiram_wrap_sizes[1] = dcache_wrap_size; +#endif + } else { + if (drom0_in_icache) { + flash_wrap_sizes[0] = icache_wrap_size; + } else { + flash_wrap_sizes[1] = dcache_wrap_size; + } +#ifdef CONFIG_EXT_RODATA_SUPPORT + flash_wrap_sizes[1] = dcache_wrap_size; +#endif + } +#ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT + spiram_wrap_sizes[1] = dcache_wrap_size; +#endif + for (i = 0; i < 2; i++) { + if (flash_wrap_sizes[i] != -1) { + flash_count++; + flash_wrap_size = flash_wrap_sizes[i]; + } + } + for (i = 0; i < 2; i++) { + if (spiram_wrap_sizes[i] != -1) { + spiram_count++; + spiram_wrap_size = spiram_wrap_sizes[i]; + } + } + if (flash_count + spiram_count <= 2) { + flash_spiram_wrap_together = false; + } else { + flash_spiram_wrap_together = true; + } + if (flash_count > 1 && flash_wrap_sizes[0] != flash_wrap_sizes[1]) { + ESP_EARLY_LOGW(TAG, "Flash wrap with different length %d and %d, abort wrap.", flash_wrap_sizes[0], flash_wrap_sizes[1]); + if (spiram_wrap_size == 0) { + return ESP_FAIL; + } + if (flash_spiram_wrap_together) { + ESP_EARLY_LOGE(TAG, "Abort spiram wrap because flash wrap length not fixed."); + return ESP_FAIL; + } + } + if (spiram_count > 1 && spiram_wrap_sizes[0] != spiram_wrap_sizes[1]) { + ESP_EARLY_LOGW(TAG, "SPIRAM wrap with different length %d and %d, abort wrap.", spiram_wrap_sizes[0], spiram_wrap_sizes[1]); + if (flash_wrap_size == 0) { + return ESP_FAIL; + } + if (flash_spiram_wrap_together) { + ESP_EARLY_LOGW(TAG, "Abort flash wrap because spiram wrap length not fixed."); + return ESP_FAIL; + } + } + + if (flash_spiram_wrap_together && flash_wrap_size != spiram_wrap_size) { + ESP_EARLY_LOGW(TAG, "SPIRAM has different wrap length with flash, %d and %d, abort wrap.", spiram_wrap_size, flash_wrap_size); + return ESP_FAIL; + } + +#ifdef CONFIG_FLASHMODE_QIO + flash_support_wrap = true; + extern bool spi_flash_support_wrap_size(uint32_t wrap_size); + if (!spi_flash_support_wrap_size(flash_wrap_size)) { + flash_support_wrap = false; + ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size); + } +#else + ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap."); +#endif + + +#ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT + extern bool psram_support_wrap_size(uint32_t wrap_size); + if (!psram_support_wrap_size(spiram_wrap_size)) { + spiram_support_wrap = false; + ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size); + } +#endif + + if (flash_spiram_wrap_together && !(flash_support_wrap && spiram_support_wrap)) { + ESP_EARLY_LOGW(TAG, "Flash and SPIRAM should support wrap together."); + return ESP_FAIL; + } + + extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size); + if (flash_support_wrap && flash_wrap_size > 0) { + ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size); + spi_flash_enable_wrap(flash_wrap_size); + esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0)); + } +#if CONFIG_ESP32S3_SPIRAM_SUPPORT + extern esp_err_t psram_enable_wrap(uint32_t wrap_size); + if (spiram_support_wrap && spiram_wrap_size > 0) { + ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size); + psram_enable_wrap(spiram_wrap_size); + esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0)); + } +#endif + + return ESP_OK; + } #endif diff --git a/components/spi_flash/cache_utils.h b/components/spi_flash/cache_utils.h index bc3de9f964..e12f2f8442 100644 --- a/components/spi_flash/cache_utils.h +++ b/components/spi_flash/cache_utils.h @@ -60,7 +60,7 @@ void spi_flash_enable_interrupts_caches_no_os(void); bool spi_flash_check_and_flush_cache(uint32_t start_addr, uint32_t length); //config cache mode -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 //config instrcutin cache size and cache block size by menuconfig void esp_config_instruction_cache_mode(void); //config data cache size and cache block size by menuconfig diff --git a/components/spi_flash/esp32s3/flash_ops_esp32s3.c b/components/spi_flash/esp32s3/flash_ops_esp32s3.c new file mode 100644 index 0000000000..4014c8ba1e --- /dev/null +++ b/components/spi_flash/esp32s3/flash_ops_esp32s3.c @@ -0,0 +1,120 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#include "esp_spi_flash.h" +#include "soc/system_reg.h" +#include "soc/soc_memory_layout.h" +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "bootloader_flash.h" +#include "hal/spi_flash_hal.h" +#include "esp_flash.h" +#include "esp_log.h" + +static const char *TAG = "spiflash_s3"; + +#define SPICACHE SPIMEM0 +#define SPIFLASH SPIMEM1 + +esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size) +{ + const spi_flash_guard_funcs_t *ops = spi_flash_guard_get(); + esp_rom_spiflash_result_t rc; + + assert((dest_addr % 16) == 0); + assert((size % 16) == 0); + + if (!esp_ptr_internal(src)) { + uint8_t block[128]; // Need to buffer in RAM as we write + while (size > 0) { + size_t next_block = MIN(size, sizeof(block)); + memcpy(block, src, next_block); + + esp_rom_spiflash_result_t r = spi_flash_write_encrypted_chip(dest_addr, block, next_block); + if (r != ESP_ROM_SPIFLASH_RESULT_OK) { + return r; + } + + size -= next_block; + dest_addr += next_block; + src = ((uint8_t *)src) + next_block; + } + bzero(block, sizeof(block)); + + return ESP_ROM_SPIFLASH_RESULT_OK; + } else { // Already in internal memory + ESP_LOGV(TAG, "calling SPI_Encrypt_Write addr 0x%x src %p size 0x%x", dest_addr, src, size); + +#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL + /* The ROM function SPI_Encrypt_Write assumes ADDR_BITLEN is already set but new + implementation doesn't automatically set this to a usable value */ + SPIFLASH.user1.usr_addr_bitlen = 23; +#endif + + if (ops && ops->start) { + ops->start(); + } + rc = SPI_Encrypt_Write(dest_addr, src, size); + if (ops && ops->end) { + ops->end(); + } + return rc; + } +} + +esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode) +{ + return bootloader_flash_wrap_set(mode); +} + +esp_err_t spi_flash_enable_wrap(uint32_t wrap_size) +{ + switch (wrap_size) { + case 8: + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_8B); + case 16: + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_16B); + case 32: + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_32B); + case 64: + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_64B); + default: + return ESP_FAIL; + } +} + +void spi_flash_disable_wrap(void) +{ + bootloader_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); +} + +bool spi_flash_support_wrap_size(uint32_t wrap_size) +{ + if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FASTRD_MODE)) { + return ESP_FAIL; + } + switch (wrap_size) { + case 0: + case 8: + case 16: + case 32: + case 64: + return true; + default: + return false; + } +} diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index eefe8a9779..f0d48a62d9 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -17,7 +17,6 @@ #include "memspi_host_driver.h" #include "esp_flash_spi_init.h" #include "driver/gpio.h" -#include "esp32/rom/spi_flash.h" #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp_log.h" @@ -25,6 +24,14 @@ #include "hal/spi_types.h" #include "driver/spi_common_internal.h" #include "esp_flash_internal.h" +#include "esp_rom_gpio.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/spi_flash.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/spi_flash.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#endif __attribute__((unused)) static const char TAG[] = "spi_flash"; @@ -68,6 +75,15 @@ __attribute__((unused)) static const char TAG[] = "spi_flash"; .iomux = true, \ .input_delay_ns = 0,\ } +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/efuse.h" +#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ + .host_id = SPI_HOST,\ + .speed = DEFAULT_FLASH_SPEED, \ + .cs_num = 0, \ + .iomux = true, \ + .input_delay_ns = 0,\ +} #endif @@ -207,7 +223,7 @@ esp_err_t esp_flash_init_default_chip(void) { memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT(); - #ifdef CONFIG_IDF_TARGET_ESP32S2 + #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // For esp32s2 spi IOs are configured as from IO MUX by default cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false; #endif diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 6789d4211a..6020157e15 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -39,6 +39,12 @@ #include "esp32s2/spiram.h" #include "soc/extmem_reg.h" #include "soc/cache_memory.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/spiram.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #endif #ifndef NDEBUG @@ -48,6 +54,7 @@ #include "sys/queue.h" #ifdef CONFIG_IDF_TARGET_ESP32 +#define PAGES_PER_REGION 64 #define REGIONS_COUNT 4 #define IROM0_PAGES_START 64 #define IROM0_PAGES_END 256 @@ -56,7 +63,10 @@ #define PAGE_IN_FLASH(page) (page) #define INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL #define MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK +#define VADDR1_START_ADDR 0x40000000 +#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) #elif CONFIG_IDF_TARGET_ESP32S2 +#define PAGES_PER_REGION 64 #define REGIONS_COUNT 6 #define IROM0_PAGES_START (PRO_CACHE_IBUS0_MMU_START / sizeof(uint32_t)) #define IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t)) @@ -66,16 +76,28 @@ #define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL #define MMU_ADDR_MASK MMU_ADDRESS_MASK #define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) +#elif CONFIG_IDF_TARGET_ESP32S3 +#define REGIONS_COUNT 2 +#define PAGES_PER_REGION 256 +#define IROM0_PAGES_START (CACHE_IBUS_MMU_START / sizeof(uint32_t)) +#define IROM0_PAGES_END (CACHE_IBUS_MMU_END / sizeof(uint32_t)) +#define DROM0_PAGES_START (CACHE_DBUS_MMU_START / sizeof(uint32_t)) +#define DROM0_PAGES_END (CACHE_DBUS_MMU_END / sizeof(uint32_t)) +#define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define MMU_ADDR_MASK MMU_ADDRESS_MASK +#define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define PRO_IRAM0_FIRST_USABLE_PAGE (IROM0_PAGES_START) #endif -#define PAGES_PER_REGION 64 #define IROM0_PAGES_NUM (IROM0_PAGES_END - IROM0_PAGES_START) #define DROM0_PAGES_NUM (DROM0_PAGES_END - DROM0_PAGES_START) #define PAGES_LIMIT (IROM0_PAGES_END > DROM0_PAGES_END ? IROM0_PAGES_END:DROM0_PAGES_END) #define VADDR0_START_ADDR SOC_DROM_LOW -#define VADDR1_START_ADDR 0x40000000 #define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW -#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) typedef struct mmap_entry_{ uint32_t handle; @@ -99,7 +121,7 @@ static void IRAM_ATTR spi_flash_mmap_init(void) DPORT_INTERRUPT_DISABLE(); for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) { uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]); if (entry_pro != entry_app) { @@ -112,7 +134,7 @@ static void IRAM_ATTR spi_flash_mmap_init(void) s_mmap_page_refcnt[i] = 1; } else { DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; #endif } @@ -229,27 +251,27 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp for (int i = start; i != start + page_count; ++i, ++pageno) { // sanity check: we won't reconfigure entries with non-zero reference count uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]); #endif assert(s_mmap_page_refcnt[i] == 0 || (entry_pro == PAGE_IN_FLASH(pages[pageno]) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 && entry_app == PAGE_IN_FLASH(pages[pageno]) #endif )); if (s_mmap_page_refcnt[i] == 0) { if (entry_pro != PAGE_IN_FLASH(pages[pageno]) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 || entry_app != PAGE_IN_FLASH(pages[pageno]) #endif ) { DPORT_PRO_FLASH_MMU_TABLE[i] = PAGE_IN_FLASH(pages[pageno]); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 DPORT_APP_FLASH_MMU_TABLE[i] = pages[pageno]; #endif -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 Cache_Invalidate_Addr(region_addr + (i - region_begin) * SPI_FLASH_MMU_PAGE_SIZE, SPI_FLASH_MMU_PAGE_SIZE); #endif need_flush = true; @@ -306,7 +328,7 @@ void IRAM_ATTR spi_flash_munmap(spi_flash_mmap_handle_t handle) assert(s_mmap_page_refcnt[i] > 0); if (--s_mmap_page_refcnt[i] == 0) { DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; #endif } @@ -481,7 +503,7 @@ static bool IRAM_ATTR is_page_mapped_in_cache(uint32_t phys_page, const void **o for (int j = 0; j < 2; j++) { for (int i = start[j]; i < end[j]; i++) { if (DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == PAGE_IN_FLASH(phys_page)) { -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 if (j == 0) { /* SPI_FLASH_MMAP_DATA */ *out_ptr = (const void *)(VADDR0_START_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[0])); } else { /* SPI_FLASH_MMAP_INST */ @@ -522,7 +544,7 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length) Cache_Flush(1); #endif return true; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 if (vaddr != NULL) { Cache_Invalidate_Addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE); ret = true; diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index eb331b06bf..0068f4cd69 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -36,6 +36,10 @@ #include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/cache.h" #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/clk.h" #endif #include "esp_flash_partitions.h" #include "cache_utils.h" @@ -776,7 +780,7 @@ void spi_flash_dump_counters(void) #endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS -#if defined(CONFIG_SPI_FLASH_USE_LEGACY_IMPL) && defined(CONFIG_IDF_TARGET_ESP32S2) +#if defined(CONFIG_SPI_FLASH_USE_LEGACY_IMPL) && (defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)) // TODO esp32s2: Remove once ESP32S2 has new SPI Flash API support esp_flash_t *esp_flash_default_chip = NULL; #endif diff --git a/components/spi_flash/memspi_host_driver.c b/components/spi_flash/memspi_host_driver.c index 5f2002d638..9286b10fb1 100644 --- a/components/spi_flash/memspi_host_driver.c +++ b/components/spi_flash/memspi_host_driver.c @@ -25,7 +25,7 @@ static const char TAG[] = "memspi"; DRAM_ATTR static const spi_flash_host_driver_t esp_flash_default_host = ESP_FLASH_DEFAULT_HOST_DRIVER(); -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 extern void spi_flash_hal_gpspi_poll_cmd_done(spi_flash_host_inst_t *host); extern esp_err_t spi_flash_hal_gpspi_device_config(spi_flash_host_inst_t *host); esp_err_t spi_flash_hal_gpspi_configure_host_io_mode( @@ -67,7 +67,7 @@ esp_err_t memspi_host_init_pointers(memspi_host_inst_t *host, const memspi_host_ { #ifdef CONFIG_IDF_TARGET_ESP32 host->inst.driver = &esp_flash_default_host; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 if (cfg->host_id == SPI_HOST) host->inst.driver = &esp_flash_default_host; else { diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index b36ff345f1..493aad0aa4 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -22,11 +22,14 @@ #include "esp32/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" +#include "esp32s3/rom/cache.h" #endif #include "esp_attr.h" -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 typedef struct { uint32_t icache_autoload; uint32_t dcache_autoload; @@ -40,7 +43,7 @@ static IRAM_ATTR esp_err_t start(void *arg) #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Read_Disable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); spi_arg->dcache_autoload = Cache_Suspend_DCache(); @@ -55,7 +58,7 @@ static IRAM_ATTR esp_err_t end(void *arg) Cache_Flush(1); Cache_Read_Enable(0); Cache_Read_Enable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi_noos_arg_t *spi_arg = arg; Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); @@ -85,7 +88,7 @@ esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip) { chip->os_func = &esp_flash_noos_functions; -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 chip->os_func_data = &spi_arg; #endif diff --git a/components/ulp/include/esp32s3/ulp.h b/components/ulp/include/esp32s3/ulp.h new file mode 100644 index 0000000000..9207a00ead --- /dev/null +++ b/components/ulp/include/esp32s3/ulp.h @@ -0,0 +1,840 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */ +#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */ + +/** + * @defgroup ulp_registers ULP coprocessor registers + * @{ + */ + + +#define R0 0 /*!< general purpose register 0 */ +#define R1 1 /*!< general purpose register 1 */ +#define R2 2 /*!< general purpose register 2 */ +#define R3 3 /*!< general purpose register 3 */ +/**@}*/ + +/** @defgroup ulp_opcodes ULP coprocessor opcodes, sub opcodes, and various modifiers/flags + * + * These definitions are not intended to be used directly. + * They are used in definitions of instructions later on. + * + * @{ + */ + +#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */ + +#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ + +#define OPCODE_DELAY 4 /*!< Instruction: delay (nop) for a given number of cycles */ + +#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */ + +#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +#define OPCODE_ALU 7 /*!< Arithmetic instructions */ +#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */ +#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */ +#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/ +#define ALU_SEL_ADD 0 /*!< Addition */ +#define ALU_SEL_SUB 1 /*!< Subtraction */ +#define ALU_SEL_AND 2 /*!< Logical AND */ +#define ALU_SEL_OR 3 /*!< Logical OR */ +#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */ +#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */ +#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */ + +#define OPCODE_BRANCH 8 /*!< Branch instructions */ +#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */ +#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */ +#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */ +#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */ +#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */ +#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */ +#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */ + +#define OPCODE_END 9 /*!< Stop executing the program */ +#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */ +#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */ + +#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */ + +#define OPCODE_HALT 11 /*!< Halt the coprocessor */ + +#define OPCODE_LD 13 /*!< Indirect load lower 16 bits from RTC memory */ + +#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */ +#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */ +#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */ +/**@}*/ + +/** + * @brief Instruction format structure + * + * All ULP instructions are 32 bit long. + * This union contains field layouts used by all of the supported instructions. + * This union also includes a special "macro" instruction layout. + * This is not a real instruction which can be executed by the CPU. It acts + * as a token which is removed from the program by the + * ulp_process_macros_and_load function. + * + * These structures are not intended to be used directly. + * Preprocessor definitions provided below fill the fields of these structure with + * the right arguments. + */ +union ulp_insn { + + struct { + uint32_t cycles : 16; /*!< Number of cycles to sleep */ + uint32_t unused : 12; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */ + } delay; /*!< Format of DELAY instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains data to store */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ST) */ + } st; /*!< Format of ST instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where the data should be loaded to */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 7; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */ + } ld; /*!< Format of LD instruction */ + + struct { + uint32_t unused : 28; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_HALT) */ + } halt; /*!< Format of HALT instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */ + uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */ + uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } bx; /*!< Format of BRANCH instruction (absolute address) */ + + struct { + uint32_t imm : 16; /*!< Immediate value to compare against */ + uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */ + uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */ + uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } b; /*!< Format of BRANCH instruction (relative address) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t treg : 2; /*!< Register with operand B */ + uint32_t unused : 15; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t imm : 16; /*!< Immediate value of operand B */ + uint32_t unused : 1; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_imm; /*!< Format of ALU instruction (one source is an immediate) */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t data : 8; /*!< 8 bits of data to write */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } wr_reg; /*!< Format of WR_REG instruction */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } rd_reg; /*!< Format of RD_REG instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store ADC result */ + uint32_t mux : 4; /*!< Select SARADC pad (mux + 1) */ + uint32_t sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */ + uint32_t unused1 : 1; /*!< Unused */ + uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_ADC) */ + } adc; /*!< Format of ADC instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store temperature measurement result */ + uint32_t wait_delay: 14; /*!< Cycles to wait after measurement is done */ + uint32_t reserved: 12; /*!< Reserved, set to 0 */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_TSENS) */ + } tsens; /*!< Format of TSENS instruction */ + + struct { + uint32_t i2c_addr : 8; /*!< I2C slave address */ + uint32_t data : 8; /*!< Data to read or write */ + uint32_t low_bits : 3; /*!< TBD */ + uint32_t high_bits : 3; /*!< TBD */ + uint32_t i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */ + uint32_t unused : 1; /*!< Unused */ + uint32_t rw : 1; /*!< Write (1) or read (0) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_I2C) */ + } i2c; /*!< Format of I2C instruction */ + + struct { + uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */ + uint32_t unused : 24; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } end; /*!< Format of END instruction with wakeup */ + + struct { + uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */ + uint32_t unused : 21; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } sleep; /*!< Format of END instruction with sleep */ + + struct { + uint32_t label : 16; /*!< Label number */ + uint32_t unused : 8; /*!< Unused */ + uint32_t sub_opcode : 4; /*!< SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_MACRO) */ + } macro; /*!< Format of tokens used by LABEL and BRANCH macros */ + +}; + +typedef union ulp_insn ulp_insn_t; + +_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes"); + +/** + * Delay (nop) for a given number of cycles + */ +#define I_DELAY(cycles_) { .delay = {\ + .cycles = cycles_, \ + .unused = 0, \ + .opcode = OPCODE_DELAY } } + +/** + * Halt the coprocessor. + * + * This instruction halts the coprocessor, but keeps ULP timer active. + * As such, ULP program will be restarted again by timer. + * To stop the program and prevent the timer from restarting the program, + * use I_END(0) instruction. + */ +#define I_HALT() { .halt = {\ + .unused = 0, \ + .opcode = OPCODE_HALT } } + +/** + * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG + * instructions. + * + * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. + * @return periph_sel value for the peripheral to which this register belongs. + */ +static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) +{ + uint32_t ret = 3; + if (reg < DR_REG_RTCCNTL_BASE) { + assert(0 && "invalid register base"); + } else if (reg < DR_REG_RTCIO_BASE) { + ret = RD_REG_PERIPH_RTC_CNTL; + } else if (reg < DR_REG_SENS_BASE) { + ret = RD_REG_PERIPH_RTC_IO; + } else if (reg < DR_REG_RTC_I2C_BASE) { + ret = RD_REG_PERIPH_SENS; + } else if (reg < DR_REG_IO_MUX_BASE) { + ret = RD_REG_PERIPH_RTC_I2C; + } else { + assert(0 && "invalid register base"); + } + return ret; +} + +/** + * Write literal value to a peripheral register + * + * reg[high_bit : low_bit] = val + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .data = val, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_WR_REG } } + +/** + * Read from peripheral register into R0 + * + * R0 = reg[high_bit : low_bit] + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .unused = 0, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_RD_REG } } + +/** + * Set or clear a bit in the peripheral register. + * + * Sets bit (1 << shift) of register reg to value val. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) + +/** + * Wake the SoC from deep sleep. + * + * This instruction initiates wake up from deep sleep. + * Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup + * triggered by the ULP before going into deep sleep. + * Note that ULP program will still keep running until the I_HALT + * instruction, and it will still be restarted by timer at regular + * intervals, even when the SoC is woken up. + * + * To stop the ULP program, use I_HALT instruction. + * + * To disable the timer which start ULP program, use I_END() + * instruction. I_END instruction clears the + * RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG + * register, which controls the ULP timer. + */ +#define I_WAKE() { .end = { \ + .wakeup = 1, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_END, \ + .opcode = OPCODE_END } } + +/** + * Stop ULP program timer. + * + * This is a convenience macro which disables the ULP program timer. + * Once this instruction is used, ULP program will not be restarted + * anymore until ulp_run function is called. + * + * ULP program will continue running after this instruction. To stop + * the currently running program, use I_HALT(). + */ +#define I_END() \ + I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0) +/** + * Select the time interval used to run ULP program. + * + * This instructions selects which of the SENS_SLEEP_CYCLES_Sx + * registers' value is used by the ULP program timer. + * When the ULP program stops at I_HALT instruction, ULP program + * timer start counting. When the counter reaches the value of + * the selected SENS_SLEEP_CYCLES_Sx register, ULP program + * start running again from the start address (passed to the ulp_run + * function). + * There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5. + * + * By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP + * program timer. + */ +#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \ + .cycle_sel = timer_idx, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_SLEEP, \ + .opcode = OPCODE_END } } + +/** + * Perform temperature sensor measurement and store it into reg_dest. + * + * Delay can be set between 1 and ((1 << 14) - 1). Higher values give + * higher measurement resolution. + */ +#define I_TSENS(reg_dest, delay) { .tsens = { \ + .dreg = reg_dest, \ + .wait_delay = delay, \ + .reserved = 0, \ + .opcode = OPCODE_TSENS } } + +/** + * Perform ADC measurement and store result in reg_dest. + * + * adc_idx selects ADC (0 or 1). + * pad_idx selects ADC pad (0 - 7). + */ +#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ + .dreg = reg_dest, \ + .mux = pad_idx + 1, \ + .sar_sel = adc_idx, \ + .unused1 = 0, \ + .cycles = 0, \ + .unused2 = 0, \ + .opcode = OPCODE_ADC } } + +/** + * Store value from register reg_val into RTC memory. + * + * The value is written to an offset calculated by adding value of + * reg_addr register and offset_ field (this offset is expressed in 32-bit words). + * 32 bits written to RTC memory are built as follows: + * - bits [31:21] hold the PC of current instruction, expressed in 32-bit words + * - bits [20:16] = 5'b1 + * - bits [15:0] are assigned the contents of reg_val + * + * RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] } + */ +#define I_ST(reg_val, reg_addr, offset_) { .st = { \ + .dreg = reg_val, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .sub_opcode = SUB_OPCODE_ST, \ + .opcode = OPCODE_ST } } + + +/** + * Load value from RTC memory into reg_dest register. + * + * Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and + * value of offset_. + */ +#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ + .dreg = reg_dest, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .opcode = OPCODE_LD } } + + +/** + * Branch relative if R0 less than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BL(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_L, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch relative if R0 greater or equal than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BGE(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_GE, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXZR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXZI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, address in register + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXFR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, immediate address + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXFI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + + +/** + * Addition: dest = src1 + src2 + */ +#define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Subtraction: dest = src1 - src2 + */ +#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND: dest = src1 & src2 + */ +#define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR: dest = src1 | src2 + */ +#define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Copy: dest = src + */ +#define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = 0, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left: dest = src << shift + */ +#define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right: dest = src >> shift + */ +#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Add register and an immediate value: dest = src1 + imm + */ +#define I_ADDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Subtract register and an immediate value: dest = src - imm + */ +#define I_SUBI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND register and an immediate value: dest = src & imm + */ +#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR register and an immediate value: dest = src | imm + */ +#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Copy an immediate value into register: dest = imm + */ +#define I_MOVI(reg_dest, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = 0, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left register value by an immediate: dest = src << imm + */ +#define I_LSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right register value by an immediate: dest = val >> imm + */ +#define I_RSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Define a label with number label_num. + * + * This is a macro which doesn't generate a real instruction. + * The token generated by this macro is removed by ulp_process_macros_and_load + * function. Label defined using this macro can be used in branch macros defined + * below. + */ +#define M_LABEL(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_LABEL, \ + .opcode = OPCODE_MACRO } } + +/** + * Token macro used by M_B and M_BX macros. Not to be used directly. + */ +#define M_BRANCH(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_BRANCH, \ + .opcode = OPCODE_MACRO } } + +/** + * Macro: branch to label label_num if R0 is less than immediate value. + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BL(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BL(0, imm_value) + +/** + * Macro: branch to label label_num if R0 is greater or equal than immediate value + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BGE(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BGE(0, imm_value) + +/** + * Macro: unconditional branch to label + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BX(label_num) \ + M_BRANCH(label_num), \ + I_BXI(0) + +/** + * Macro: branch to label if ALU result is zero + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXZ(label_num) \ + M_BRANCH(label_num), \ + I_BXZI(0) + +/** + * Macro: branch to label if ALU overflow + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXF(label_num) \ + M_BRANCH(label_num), \ + I_BXFI(0) + + + +#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */ + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp.c b/components/ulp/ulp.c index f01e5b9826..8bce618d8d 100644 --- a/components/ulp/ulp.c +++ b/components/ulp/ulp.c @@ -25,6 +25,9 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" #include "esp32s2/ulp.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" +#include "esp32s3/ulp.h" #endif #include "soc/soc.h" diff --git a/components/ulp/ulp_private.h b/components/ulp/ulp_private.h index 3d5b281493..df3fcf6cd1 100644 --- a/components/ulp/ulp_private.h +++ b/components/ulp/ulp_private.h @@ -16,6 +16,8 @@ #ifdef CONFIG_ESP32_ULP_COPROC_RESERVE_MEM #define ULP_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM -#else +#elif defined(CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM) #define ULP_RESERVE_MEM CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM +#elif defined(CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM) +#define ULP_RESERVE_MEM CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM #endif diff --git a/components/unity/unity_port_esp32.c b/components/unity/unity_port_esp32.c index 1500f57ce2..f85aa503ab 100644 --- a/components/unity/unity_port_esp32.c +++ b/components/unity/unity_port_esp32.c @@ -20,6 +20,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif static uint32_t s_test_start, s_test_stop; diff --git a/components/vfs/vfs_uart.c b/components/vfs/vfs_uart.c index 93b9e14cae..5ef09d7040 100644 --- a/components/vfs/vfs_uart.c +++ b/components/vfs/vfs_uart.c @@ -162,7 +162,7 @@ static void uart_tx_char(int fd, int c) } #if CONFIG_IDF_TARGET_ESP32 uart->fifo.rw_byte = c; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uart->ahb_fifo.rw_byte = c; #endif } @@ -181,7 +181,7 @@ static int uart_rx_char(int fd) } #if CONFIG_IDF_TARGET_ESP32 return uart->fifo.rw_byte; -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 return READ_PERI_REG(UART_FIFO_AHB_REG(fd)); #endif } diff --git a/tools/ci/config/post_check.yml b/tools/ci/config/post_check.yml index 3ee5903f6d..27b095fb3a 100644 --- a/tools/ci/config/post_check.yml +++ b/tools/ci/config/post_check.yml @@ -23,6 +23,7 @@ check_submodule_sync: - *show_submodule_urls - git submodule update --recursive - echo "IDF was cloned from ${PUBLIC_IDF_URL} completely" + allow_failure: true # remove this line when esp32s3 support in esptool got merged into master check_ut_cmake_make: extends: .check_job_template_with_filter diff --git a/tools/tools.json b/tools/tools.json index d659599bbc..64063885e9 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -112,6 +112,62 @@ } ] }, + { + "description": "Toolchain for Xtensa (ESP32-S3) based on GCC", + "export_paths": [ + [ + "xtensa-esp32s3-elf", + "bin" + ] + ], + "export_vars": {}, + "info_url": "https://github.com/espressif/crosstool-NG", + "install": "always", + "license": "GPL-3.0-with-GCC-exception", + "name": "xtensa-esp32s3-elf", + "version_cmd": [ + "xtensa-esp32s3-elf-gcc", + "--version" + ], + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-]+)\\)\\s*([0-9\\.]+)", + "version_regex_replace": "\\1-\\2", + "versions": [ + { + "linux-amd64": { + "sha256": "22bf5e63baf3f3f5103ae21bcc35d80cd888d8032095e7b9e8f9631074ac462a", + "size": 86029457, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-linux-amd64.tar.gz" + }, + "linux-armel": { + "sha256": "27f423af3cfb9d8ed7a02173ccd8dc3b0fd3b3e76a92e9ba507121e73bfa5df3", + "size": 84120606, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-linux-armel.tar.gz" + }, + "linux-i686": { + "sha256": "479a71cfb4b0c0b36371a1aaed2e6095dfc3241937a54f60a1ba115da73ddec5", + "size": 88015798, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-linux-i686.tar.gz" + }, + "macos": { + "sha256": "c09b8fcbb840540a3f59429b1bbfbe5abfcacccf7a8a955e4e01e3f50b53a079", + "size": 93013216, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-macos.tar.gz" + }, + "name": "esp-2020r3-8.4.0", + "status": "recommended", + "win32": { + "sha256": "9591fc32896b13d7fe77310afbbff197cbbc20437d316e0e2460c5c50a10d7b5", + "size": 104536285, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-win32.zip" + }, + "win64": { + "sha256": "1caf56e9588214d8f1bc17734680ebab2906da3b5f31095e60407dad170f1221", + "size": 107245907, + "url": "https://dl.espressif.com/dl/xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-win64.zip" + } + } + ] + }, { "description": "Toolchain for RISC-V", "export_paths": [ diff --git a/tools/unit-test-app/components/test_utils/ccomp_timer.c b/tools/unit-test-app/components/test_utils/ccomp_timer.c index c218b22f65..104d8f8a50 100644 --- a/tools/unit-test-app/components/test_utils/ccomp_timer.c +++ b/tools/unit-test-app/components/test_utils/ccomp_timer.c @@ -27,6 +27,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif diff --git a/tools/unit-test-app/components/test_utils/ccomp_timer_impl.c b/tools/unit-test-app/components/test_utils/ccomp_timer_impl.c index 2caddf2481..e56b743e53 100644 --- a/tools/unit-test-app/components/test_utils/ccomp_timer_impl.c +++ b/tools/unit-test-app/components/test_utils/ccomp_timer_impl.c @@ -31,6 +31,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif #define D_STALL_COUNTER_ID 0 From 28145e0894f147712948c78c9fcb7465e1c2cefe Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Fri, 28 Aug 2020 11:53:28 +0800 Subject: [PATCH 05/11] support flash instr and rodata copy to SPIRAM --- components/esp32s3/include/esp32s3/spiram.h | 47 +++++++ components/esp32s3/ld/esp32s3.project.ld.in | 4 + components/esp32s3/spiram.c | 148 ++++++++++---------- components/esp_system/port/cpu_start.c | 12 +- components/spi_flash/flash_mmap.c | 14 +- components/spi_flash/test/test_mmap.c | 5 +- 6 files changed, 147 insertions(+), 83 deletions(-) diff --git a/components/esp32s3/include/esp32s3/spiram.h b/components/esp32s3/include/esp32s3/spiram.h index fdfc7b8c5c..abe2d05ecd 100644 --- a/components/esp32s3/include/esp32s3/spiram.h +++ b/components/esp32s3/include/esp32s3/spiram.h @@ -87,5 +87,52 @@ void esp_spiram_writeback_cache(void); */ esp_err_t esp_spiram_reserve_dma_pool(size_t size); +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + +extern int _instruction_reserved_start, _instruction_reserved_end; + +/** + * @brief Get the start page number of the instruction in SPI flash + * + * @return start page number + */ +uint32_t instruction_flash_start_page_get(void); +/** + * @brief Get the end page number of the instruction in SPI flash + * + * @return end page number + */ +uint32_t instruction_flash_end_page_get(void); +/** + * @brief Get the offset of instruction from SPI flash to SPI RAM + * + * @return instruction offset + */ +int instruction_flash2spiram_offset(void); +#endif + +#if CONFIG_SPIRAM_RODATA + +extern int _rodata_reserved_start, _rodata_reserved_end; + +/** + * @brief Get the start page number of the rodata in SPI flash + * + * @return start page number + */ +uint32_t rodata_flash_start_page_get(void); +/** + * @brief Get the end page number of the rodata in SPI flash + * + * @return end page number + */ +uint32_t rodata_flash_end_page_get(void); +/** + * @brief Get the offset number of rodata from SPI flash to SPI RAM + * + * @return rodata offset + */ +int rodata_flash2spiram_offset(void); +#endif #endif diff --git a/components/esp32s3/ld/esp32s3.project.ld.in b/components/esp32s3/ld/esp32s3.project.ld.in index b85c127ea0..aa241f6d04 100644 --- a/components/esp32s3/ld/esp32s3.project.ld.in +++ b/components/esp32s3/ld/esp32s3.project.ld.in @@ -284,6 +284,7 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); mapping[flash_text] @@ -294,6 +295,7 @@ SECTIONS *(.fini) *(.gnu.version) _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); _etext = .; /** @@ -308,6 +310,7 @@ SECTIONS { . = SIZEOF(.flash.text); . = ALIGN(0x10000) + 0x20; + _rodata_reserved_start = .; } > drom0_0_seg /* When modifying the alignment, don't forget to update tls_section_alignment in pxPortInitialiseStack */ @@ -367,6 +370,7 @@ SECTIONS *(.tbss) *(.tbss.*) _thread_local_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); } > default_rodata_seg diff --git a/components/esp32s3/spiram.c b/components/esp32s3/spiram.c index f1711a5bff..c8a5609b1c 100644 --- a/components/esp32s3/spiram.c +++ b/components/esp32s3/spiram.c @@ -40,7 +40,7 @@ we add more types of external RAM memory, this can be made into a more intellige #if CONFIG_SPIRAM -static const char* TAG = "spiram"; +static const char *TAG = "spiram"; #if CONFIG_SPIRAM_SPEED_40M #define PSRAM_SPEED PSRAM_CACHE_S40M @@ -50,9 +50,7 @@ static const char* TAG = "spiram"; #define PSRAM_SPEED PSRAM_CACHE_S20M #endif -#define SPIRAM_SIZE esp_spiram_get_size() - -static bool spiram_inited=false; +static bool spiram_inited = false; /* @@ -62,31 +60,34 @@ static bool spiram_inited=false; */ bool esp_spiram_test(void) { - volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE); + size_t spiram_size = esp_spiram_get_size(); + volatile int *spiram = (volatile int *)(SOC_EXTRAM_DATA_HIGH - spiram_size); size_t p; - size_t s=SPIRAM_SIZE; - int errct=0; - int initial_err=-1; + size_t s = spiram_size; + int errct = 0; + int initial_err = -1; - if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < SPIRAM_SIZE) { + if (SOC_EXTRAM_DATA_SIZE < spiram_size) { ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH); - spiram=(volatile int*)SOC_EXTRAM_DATA_LOW; + spiram = (volatile int *)SOC_EXTRAM_DATA_LOW; s = SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW; } - for (p=0; p<(s/sizeof(int)); p+=8) { - spiram[p]=p^0xAAAAAAAA; + for (p = 0; p < (s / sizeof(int)); p += 8) { + spiram[p] = p ^ 0xAAAAAAAA; } - for (p=0; p<(s/sizeof(int)); p+=8) { - if (spiram[p]!=(p^0xAAAAAAAA)) { + for (p = 0; p < (s / sizeof(int)); p += 8) { + if (spiram[p] != (p ^ 0xAAAAAAAA)) { errct++; - if (errct==1) initial_err=p*4; + if (errct == 1) { + initial_err = p * 4; + } if (errct < 4) { - ESP_EARLY_LOGE(TAG, "SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], p^0xAAAAAAAA); + ESP_EARLY_LOGE(TAG, "SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], p ^ 0xAAAAAAAA); } } } if (errct) { - ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW); + ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s / 32, initial_err + SOC_EXTRAM_DATA_LOW); return false; } else { ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK"); @@ -96,11 +97,12 @@ bool esp_spiram_test(void) void IRAM_ATTR esp_spiram_init_cache(void) { + size_t spiram_size = esp_spiram_get_size(); Cache_Suspend_DCache(); - if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >= SPIRAM_SIZE) { - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE, 0, 64, SPIRAM_SIZE >> 16, 0); + if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >= spiram_size) { + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - spiram_size, 0, 64, spiram_size >> 16, 0); } else { - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE, 0, 64, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >> 16, 0); + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - spiram_size, 0, 64, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >> 16, 0); } REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS); #if !CONFIG_FREERTOS_UNICORE @@ -110,8 +112,6 @@ void IRAM_ATTR esp_spiram_init_cache(void) } static uint32_t pages_for_flash = 0; -static uint32_t page0_mapped = 0; -static uint32_t page0_page = INVALID_PHY_PAGE; static uint32_t instrcution_in_spiram = 0; static uint32_t rodata_in_spiram = 0; @@ -127,6 +127,11 @@ static uint32_t rodata_start_page = 0; static uint32_t rodata_end_page = 0; #endif +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA +static uint32_t page0_mapped = 0; +static uint32_t page0_page = INVALID_PHY_PAGE; +#endif + uint32_t esp_spiram_instruction_access_enabled(void) { return instrcution_in_spiram; @@ -140,21 +145,18 @@ uint32_t esp_spiram_rodata_access_enabled(void) #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS esp_err_t esp_spiram_enable_instruction_access(void) { + size_t spiram_size = esp_spiram_get_size(); uint32_t pages_in_flash = 0; - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped); - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped); - if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { - ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (SPIRAM_SIZE >> 16), (pages_in_flash + pages_for_flash)); + pages_in_flash += Cache_Count_Flash_Pages(CACHE_IBUS, &page0_mapped); + if ((pages_in_flash + pages_for_flash) > (spiram_size >> 16)) { + ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (spiram_size >> 16), (pages_in_flash + pages_for_flash)); return ESP_FAIL; } ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM"); - uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; - uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START + instr_mmu_offset*sizeof(uint32_t)); - mmu_value &= MMU_ADDRESS_MASK; + uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START); instr_flash2spiram_offs = mmu_value - pages_for_flash; ESP_EARLY_LOGV(TAG, "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, instr_flash2spiram_offs); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, IRAM0_CACHE_ADDRESS_LOW, pages_for_flash, &page0_page); instrcution_in_spiram = 1; return ESP_OK; } @@ -163,27 +165,19 @@ esp_err_t esp_spiram_enable_instruction_access(void) #if CONFIG_SPIRAM_RODATA esp_err_t esp_spiram_enable_rodata_access(void) { + size_t spiram_size = esp_spiram_get_size(); uint32_t pages_in_flash = 0; - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped); - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS0, &page0_mapped); - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped); - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped); + pages_in_flash += Cache_Count_Flash_Pages(CACHE_DBUS, &page0_mapped); - if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { + if ((pages_in_flash + pages_for_flash) > (spiram_size >> 16)) { ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data."); return ESP_FAIL; } - ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM"); - uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; - uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START + rodata_mmu_offset*sizeof(uint32_t)); - mmu_value &= MMU_ADDRESS_MASK; + uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); rodata_flash2spiram_offs = mmu_value - pages_for_flash; ESP_EARLY_LOGV(TAG, "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, rodata_flash2spiram_offs); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, pages_for_flash, &page0_page); + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, DRAM0_CACHE_ADDRESS_LOW, pages_for_flash, &page0_page); rodata_in_spiram = 1; return ESP_OK; } @@ -192,10 +186,9 @@ esp_err_t esp_spiram_enable_rodata_access(void) #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS void instruction_flash_page_info_init(void) { - uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE; - uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START + instr_mmu_offset*sizeof(uint32_t)); + instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START); instr_start_page &= MMU_ADDRESS_MASK; instr_end_page = instr_start_page + instr_page_cnt - 1; } @@ -219,10 +212,9 @@ int IRAM_ATTR instruction_flash2spiram_offset(void) #if CONFIG_SPIRAM_RODATA void rodata_flash_page_info_init(void) { - uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - SOC_DROM_LOW + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE; - uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & 0xFFFFFF)/MMU_PAGE_SIZE; + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START + rodata_mmu_offset*sizeof(uint32_t)); + rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); rodata_start_page &= MMU_ADDRESS_MASK; rodata_end_page = rodata_start_page + rodata_page_cnt - 1; } @@ -254,46 +246,52 @@ esp_err_t esp_spiram_init(void) return r; } - spiram_inited=true; + spiram_inited = true; #if (CONFIG_SPIRAM_SIZE != -1) - if (esp_spiram_get_size()!=CONFIG_SPIRAM_SIZE) { - ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE/1024, esp_spiram_get_size()/1024); + if (esp_spiram_get_size() != CONFIG_SPIRAM_SIZE) { + ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE / 1024, esp_spiram_get_size() / 1024); return ESP_ERR_INVALID_SIZE; } #endif ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device", - (esp_spiram_get_size()*8)/(1024*1024)); + (esp_spiram_get_size() * 8) / (1024 * 1024)); ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : \ - PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m"); + PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m"); ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \ - (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \ - (PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \ - (PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR"); + (PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ? "even/odd (2-core)" : \ + (PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ? "low/high (2-core)" : \ + (PSRAM_MODE == PSRAM_VADDR_MODE_NORMAL) ? "normal (1-core)" : "ERROR"); return ESP_OK; } esp_err_t esp_spiram_add_to_heapalloc(void) { + size_t spiram_size = esp_spiram_get_size(); uint32_t size_for_flash = (pages_for_flash << 16); - ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (SPIRAM_SIZE - (pages_for_flash << 16))/1024); + ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (spiram_size - (pages_for_flash << 16)) / 1024); //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's //no need to explicitly specify them. - return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE + size_for_flash, (intptr_t)SOC_EXTRAM_DATA_HIGH -1); + return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_HIGH - spiram_size + size_for_flash, (intptr_t)SOC_EXTRAM_DATA_HIGH - 1); } static uint8_t *dma_heap; -esp_err_t esp_spiram_reserve_dma_pool(size_t size) { - if (size==0) return ESP_OK; //no-op - ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024); - dma_heap=heap_caps_malloc(size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL); - if (!dma_heap) return ESP_ERR_NO_MEM; - uint32_t caps[]={MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}; - return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1); +esp_err_t esp_spiram_reserve_dma_pool(size_t size) +{ + if (size == 0) { + return ESP_OK; //no-op + } + ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size / 1024); + dma_heap = heap_caps_malloc(size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + if (!dma_heap) { + return ESP_ERR_NO_MEM; + } + uint32_t caps[] = {MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}; + return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap + size - 1); } size_t esp_spiram_get_size(void) @@ -303,11 +301,17 @@ size_t esp_spiram_get_size(void) abort(); } - psram_size_t size=psram_get_size(); - if (size==PSRAM_SIZE_16MBITS) return 2*1024*1024; - if (size==PSRAM_SIZE_32MBITS) return 4*1024*1024; - if (size==PSRAM_SIZE_64MBITS) return 8*1024*1024; - return SPIRAM_SIZE; + psram_size_t size = psram_get_size(); + if (size == PSRAM_SIZE_16MBITS) { + return 2 * 1024 * 1024; + } + if (size == PSRAM_SIZE_32MBITS) { + return 4 * 1024 * 1024; + } + if (size == PSRAM_SIZE_64MBITS) { + return 8 * 1024 * 1024; + } + return CONFIG_SPIRAM_SIZE; } /* diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index a104b396b5..d2de4bcf55 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -54,6 +54,7 @@ #include "esp32s3/dport_access.h" #include "esp32s3/memprot.h" #include "soc/assist_debug_reg.h" +#include "soc/cache_memory.h" #endif #include "bootloader_flash_config.h" @@ -299,6 +300,13 @@ void IRAM_ATTR call_start_cpu0(void) extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); Cache_Resume_DCache(0); + + /* Configure the Cache MMU size for instruction and rodata in flash. */ + extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + extern int _rodata_reserved_start; + uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); + uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t); + Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); #endif bootloader_init_mem(); @@ -351,7 +359,7 @@ void IRAM_ATTR call_start_cpu0(void) } #endif -#if CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void instruction_flash_page_info_init(void); instruction_flash_page_info_init(); @@ -381,7 +389,7 @@ void IRAM_ATTR call_start_cpu0(void) extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable); esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable); #endif -#endif // CONFIG_IDF_TARGET_ESP32S2 +#endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 6020157e15..a6a24b4a23 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -65,6 +65,7 @@ #define MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK #define VADDR1_START_ADDR 0x40000000 #define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) +#define VADDR0_START_ADDR SOC_DROM_LOW #elif CONFIG_IDF_TARGET_ESP32S2 #define PAGES_PER_REGION 64 #define REGIONS_COUNT 6 @@ -76,27 +77,28 @@ #define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL #define MMU_ADDR_MASK MMU_ADDRESS_MASK #define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) -#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define VADDR1_START_ADDR 0x40000000 #define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) +#define VADDR0_START_ADDR SOC_DROM_LOW #elif CONFIG_IDF_TARGET_ESP32S3 #define REGIONS_COUNT 2 #define PAGES_PER_REGION 256 -#define IROM0_PAGES_START (CACHE_IBUS_MMU_START / sizeof(uint32_t)) -#define IROM0_PAGES_END (CACHE_IBUS_MMU_END / sizeof(uint32_t)) -#define DROM0_PAGES_START (CACHE_DBUS_MMU_START / sizeof(uint32_t)) -#define DROM0_PAGES_END (CACHE_DBUS_MMU_END / sizeof(uint32_t)) +#define IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) #define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE #define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL #define MMU_ADDR_MASK MMU_ADDRESS_MASK #define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) #define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW #define PRO_IRAM0_FIRST_USABLE_PAGE (IROM0_PAGES_START) +#define VADDR0_START_ADDR (SOC_DROM_LOW + (DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) #endif #define IROM0_PAGES_NUM (IROM0_PAGES_END - IROM0_PAGES_START) #define DROM0_PAGES_NUM (DROM0_PAGES_END - DROM0_PAGES_START) #define PAGES_LIMIT (IROM0_PAGES_END > DROM0_PAGES_END ? IROM0_PAGES_END:DROM0_PAGES_END) -#define VADDR0_START_ADDR SOC_DROM_LOW #define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW typedef struct mmap_entry_{ diff --git a/components/spi_flash/test/test_mmap.c b/components/spi_flash/test/test_mmap.c index 4c38511f57..ab0772eceb 100644 --- a/components/spi_flash/test/test_mmap.c +++ b/components/spi_flash/test/test_mmap.c @@ -324,9 +324,8 @@ TEST_CASE("flash_mmap can mmap after get enough free MMU pages", "[spi_flash][mm } } uint32_t free_pages = spi_flash_mmap_get_free_pages(SPI_FLASH_MMAP_DATA); - if (spi_flash_get_chip_size() <= 0x200000) { - free_pages -= 0x200000/0x10000; - } + uint32_t flash_pages = spi_flash_get_chip_size() / SPI_FLASH_MMU_PAGE_SIZE; + free_pages = (free_pages > flash_pages) ? flash_pages : free_pages; printf("Mapping %x (+%x)\n", 0, free_pages * SPI_FLASH_MMU_PAGE_SIZE); const void *ptr2; From e90dbe29cb107fb6e2b376218172092c227267c9 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 6 Aug 2020 21:03:04 +0800 Subject: [PATCH 06/11] esp32s3: run on chip --- Kconfig | 1 - components/esptool_py/Kconfig.projbuild | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Kconfig b/Kconfig index 8bda616ea6..02a9380814 100644 --- a/Kconfig +++ b/Kconfig @@ -33,7 +33,6 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_TARGET_ESP32S3 bool default "y" if IDF_TARGET="esp32s3" - select IDF_ENV_FPGA config IDF_FIRMWARE_CHIP_ID hex diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index f078cb6159..16eca6e003 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -57,7 +57,7 @@ menu "Serial flasher config" config ESPTOOLPY_WITH_STUB # Only real reason to disable this is when ESP32-S2 Secure Download Mode is set bool - default "y" if !IDF_ENV_FPGA + default "y" if !IDF_TARGET_ESP32S3 depends on !SECURE_ENABLE_SECURE_ROM_DL_MODE choice ESPTOOLPY_FLASHMODE From 75a372a9f038b51b63639a9719b5553fc0377846 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 13 Aug 2020 11:56:52 +0800 Subject: [PATCH 07/11] unit_test: support reference clock, test delay function --- components/esp_timer/test/test_esp_timer.c | 7 +- components/hal/esp32s3/include/hal/rmt_ll.h | 55 +- components/hal/include/hal/rmt_hal.h | 1 + .../include/esp32s3/idf_performance_target.h | 16 + .../soc/soc/esp32s3/include/soc/rmt_reg.h | 4810 ++++++++++------- .../soc/soc/esp32s3/include/soc/rmt_struct.h | 472 +- .../test_utils/include/test_utils.h | 3 +- .../components/test_utils/ref_clock.c | 2 +- 8 files changed, 3058 insertions(+), 2308 deletions(-) diff --git a/components/esp_timer/test/test_esp_timer.c b/components/esp_timer/test/test_esp_timer.c index 44113e59ee..3ef7b3a879 100644 --- a/components/esp_timer/test/test_esp_timer.c +++ b/components/esp_timer/test/test_esp_timer.c @@ -6,7 +6,6 @@ #include "esp_timer.h" #include "esp_timer_impl.h" #include "unity.h" -#include "soc/frc_timer_reg.h" #include "soc/timer_group_reg.h" #include "esp_heap_caps.h" #include "freertos/FreeRTOS.h" @@ -16,6 +15,10 @@ #include "esp_freertos_hooks.h" #include "esp_rom_sys.h" +#if CONFIG_ESP_TIMER_IMPL_FRC2 +#include "soc/frc_timer_reg.h" +#endif + #ifdef CONFIG_ESP_TIMER_PROFILING #define WITH_PROFILING 1 #endif @@ -855,6 +858,7 @@ TEST_CASE("Test case when esp_timer_impl_set_alarm needs set timer < now_time", TEST_ASSERT(alarm_reg <= (count_reg + offset)); } +#ifdef CONFIG_ESP_TIMER_IMPL_FRC2 TEST_CASE("Test esp_timer_impl_set_alarm when the counter is near an overflow value", "[esp_timer]") { for (int i = 0; i < 1024; ++i) { @@ -864,3 +868,4 @@ TEST_CASE("Test esp_timer_impl_set_alarm when the counter is near an overflow va esp_timer_impl_set_alarm(1); // timestamp is expired } } +#endif diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index fe4dbdd0b8..779279e360 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -17,6 +17,7 @@ extern "C" { #endif +#include #include #include "soc/rmt_struct.h" #include "soc/rmt_caps.h" @@ -24,6 +25,16 @@ extern "C" { #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) +static inline void rmt_ll_set_sclk(rmt_dev_t *dev, uint32_t source, uint32_t div_num, uint32_t div_frac_a, uint32_t div_frac_b) +{ + dev->sys_conf.sclk_active = 0; + dev->sys_conf.sclk_sel = source; + dev->sys_conf.sclk_div_num = div_num; + dev->sys_conf.sclk_div_a = div_frac_a; + dev->sys_conf.sclk_div_b = div_frac_b; + dev->sys_conf.sclk_active = 1; +} + static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->sys_conf.clk_en = enable; // register clock gating @@ -38,14 +49,20 @@ static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t chann static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel) { + dev->tx_conf[channel].apb_mem_rst = 1; + dev->tx_conf[channel].mem_rd_rst = 1; } static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel) { + dev->rx_conf[channel].conf1.apb_mem_rst = 1; + dev->rx_conf[channel].conf1.mem_wr_rst = 1; } static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel) { + dev->tx_conf[channel].conf_update = 1; + dev->tx_conf[channel].tx_start = 1; } static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel) @@ -72,6 +89,7 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { + dev->tx_conf[channel].mem_size = block_num; } static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) @@ -81,11 +99,12 @@ static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { + dev->tx_conf[channel].div_cnt = div; } static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) { - return 256; + return dev->tx_conf[channel].div_cnt; } static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable) @@ -117,6 +136,7 @@ static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { + dev->tx_conf[channel].tx_conti_mode = enable; } static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) @@ -126,23 +146,23 @@ static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { - dev->tx_lim_ch[channel].tx_loop_num = count; + dev->tx_lim[channel].tx_loop_num = count; } static inline void rmt_ll_reset_tx_loop(rmt_dev_t *dev, uint32_t channel) { - dev->tx_lim_ch[channel].loop_count_reset = 1; - dev->tx_lim_ch[channel].loop_count_reset = 0; + dev->tx_lim[channel].loop_count_reset = 1; + dev->tx_lim[channel].loop_count_reset = 0; } static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_lim_ch[channel].tx_loop_cnt_en = enable; + dev->tx_lim[channel].tx_loop_cnt_en = enable; } static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable) { - dev->tx_sim.en = enable; + dev->tx_sim.tx_sim_en = enable; } static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel) @@ -175,30 +195,32 @@ static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t cha static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { + dev->tx_conf[channel].idle_out_en = enable; } static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { - return false; + return dev->tx_conf[channel].idle_out_en; } static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { + dev->tx_conf[channel].idle_out_lv = level; } static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel) { - return 0; + return dev->tx_conf[channel].idle_out_lv; } static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel) { - return dev->status_ch[channel].val; + return 0; } static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { - dev->tx_lim_ch[channel].limit = limit; + dev->tx_lim[channel].limit = limit; } static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) @@ -316,34 +338,39 @@ static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) // We take care of the "read-modify-write" procedure by ourselves. - typeof(dev->carrier_duty_ch[0]) reg; + typeof(dev->tx_carrier[0]) reg; reg.high = high_ticks; reg.low = low_ticks; - dev->carrier_duty_ch[channel].val = reg.val; + dev->tx_carrier[channel].val = reg.val; } static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { + typeof(dev->rx_carrier[0]) reg; + reg.high_thres = high_ticks; + reg.low_thres = low_ticks; + dev->rx_carrier[channel].val = reg.val; } static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { - *high_ticks = dev->carrier_duty_ch[channel].high; - *low_ticks = dev->carrier_duty_ch[channel].low; } static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable) { + dev->tx_conf[channel].carrier_en = enable; } static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { + dev->tx_conf[channel].carrier_out_lv = level; } // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { + dev->tx_conf[channel].carrier_eff_en = !enable; } static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) diff --git a/components/hal/include/hal/rmt_hal.h b/components/hal/include/hal/rmt_hal.h index ba1cac070f..6d44acf940 100644 --- a/components/hal/include/hal/rmt_hal.h +++ b/components/hal/include/hal/rmt_hal.h @@ -17,6 +17,7 @@ extern "C" { #endif +#include #include "soc/rmt_struct.h" #include "soc/rmt_caps.h" diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h index 75bbce7015..52e376e6cb 100644 --- a/components/idf_test/include/esp32s3/idf_performance_target.h +++ b/components/idf_test/include/esp32s3/idf_performance_target.h @@ -15,3 +15,19 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600 +#endif + +// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) +#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 +#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/soc/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/soc/esp32s3/include/soc/rmt_reg.h index bddf00227c..c330ad17a7 100644 --- a/components/soc/soc/esp32s3/include/soc/rmt_reg.h +++ b/components/soc/soc/esp32s3/include/soc/rmt_reg.h @@ -1,2119 +1,2811 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFF +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFF +#define RMT_CH0DATA_S 0 -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFF +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFF +#define RMT_CH1DATA_S 0 -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFF +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFF +#define RMT_CH2DATA_S 0 -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFF +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFF +#define RMT_CH3DATA_S 0 -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) +/** RMT_CH4DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_CH4DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH4DATA 0xFFFFFFFF +#define RMT_CH4DATA_M (RMT_CH4DATA_V << RMT_CH4DATA_S) +#define RMT_CH4DATA_V 0xFFFFFFFF +#define RMT_CH4DATA_S 0 -#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) +/** RMT_CH5DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_CH5DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH5DATA 0xFFFFFFFF +#define RMT_CH5DATA_M (RMT_CH5DATA_V << RMT_CH5DATA_S) +#define RMT_CH5DATA_V 0xFFFFFFFF +#define RMT_CH5DATA_S 0 -#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) +/** RMT_CH6DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_CH6DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH6DATA 0xFFFFFFFF +#define RMT_CH6DATA_M (RMT_CH6DATA_V << RMT_CH6DATA_S) +#define RMT_CH6DATA_V 0xFFFFFFFF +#define RMT_CH6DATA_S 0 -#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) +/** RMT_CH7DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_CH7DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH7DATA 0xFFFFFFFF +#define RMT_CH7DATA_M (RMT_CH7DATA_V << RMT_CH7DATA_S) +#define RMT_CH7DATA_V 0xFFFFFFFF +#define RMT_CH7DATA_S 0 -#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_TX_START_0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_0 (BIT(0)) +#define RMT_TX_START_0_M (RMT_TX_START_0_V << RMT_TX_START_0_S) +#define RMT_TX_START_0_V 0x00000001 +#define RMT_TX_START_0_S 0 +/** RMT_MEM_RD_RST_0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_0 (BIT(1)) +#define RMT_MEM_RD_RST_0_M (RMT_MEM_RD_RST_0_V << RMT_MEM_RD_RST_0_S) +#define RMT_MEM_RD_RST_0_V 0x00000001 +#define RMT_MEM_RD_RST_0_S 1 +/** RMT_APB_MEM_RST_0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_0 (BIT(2)) +#define RMT_APB_MEM_RST_0_M (RMT_APB_MEM_RST_0_V << RMT_APB_MEM_RST_0_S) +#define RMT_APB_MEM_RST_0_V 0x00000001 +#define RMT_APB_MEM_RST_0_S 2 +/** RMT_TX_CONTI_MODE_0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_0 (BIT(3)) +#define RMT_TX_CONTI_MODE_0_M (RMT_TX_CONTI_MODE_0_V << RMT_TX_CONTI_MODE_0_S) +#define RMT_TX_CONTI_MODE_0_V 0x00000001 +#define RMT_TX_CONTI_MODE_0_S 3 +/** RMT_MEM_TX_WRAP_EN_0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_0_M (RMT_MEM_TX_WRAP_EN_0_V << RMT_MEM_TX_WRAP_EN_0_S) +#define RMT_MEM_TX_WRAP_EN_0_V 0x00000001 +#define RMT_MEM_TX_WRAP_EN_0_S 4 +/** RMT_IDLE_OUT_LV_0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_0 (BIT(5)) +#define RMT_IDLE_OUT_LV_0_M (RMT_IDLE_OUT_LV_0_V << RMT_IDLE_OUT_LV_0_S) +#define RMT_IDLE_OUT_LV_0_V 0x00000001 +#define RMT_IDLE_OUT_LV_0_S 5 +/** RMT_IDLE_OUT_EN_0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_0 (BIT(6)) +#define RMT_IDLE_OUT_EN_0_M (RMT_IDLE_OUT_EN_0_V << RMT_IDLE_OUT_EN_0_S) +#define RMT_IDLE_OUT_EN_0_V 0x00000001 +#define RMT_IDLE_OUT_EN_0_S 6 +/** RMT_TX_STOP_0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_0 (BIT(7)) +#define RMT_TX_STOP_0_M (RMT_TX_STOP_0_V << RMT_TX_STOP_0_S) +#define RMT_TX_STOP_0_V 0x00000001 +#define RMT_TX_STOP_0_S 7 +/** RMT_DIV_CNT_0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_0 0x000000FF +#define RMT_DIV_CNT_0_M (RMT_DIV_CNT_0_V << RMT_DIV_CNT_0_S) +#define RMT_DIV_CNT_0_V 0x000000FF +#define RMT_DIV_CNT_0_S 8 +/** RMT_MEM_SIZE_0 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_0 0x0000000F +#define RMT_MEM_SIZE_0_M (RMT_MEM_SIZE_0_V << RMT_MEM_SIZE_0_S) +#define RMT_MEM_SIZE_0_V 0x0000000F +#define RMT_MEM_SIZE_0_S 16 +/** RMT_CARRIER_EFF_EN_0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_0_M (RMT_CARRIER_EFF_EN_0_V << RMT_CARRIER_EFF_EN_0_S) +#define RMT_CARRIER_EFF_EN_0_V 0x00000001 +#define RMT_CARRIER_EFF_EN_0_S 20 +/** RMT_CARRIER_EN_0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_0 (BIT(21)) +#define RMT_CARRIER_EN_0_M (RMT_CARRIER_EN_0_V << RMT_CARRIER_EN_0_S) +#define RMT_CARRIER_EN_0_V 0x00000001 +#define RMT_CARRIER_EN_0_S 21 +/** RMT_CARRIER_OUT_LV_0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_0_M (RMT_CARRIER_OUT_LV_0_V << RMT_CARRIER_OUT_LV_0_S) +#define RMT_CARRIER_OUT_LV_0_V 0x00000001 +#define RMT_CARRIER_OUT_LV_0_S 22 +/** RMT_AFIFO_RST_0 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_0 (BIT(23)) +#define RMT_AFIFO_RST_0_M (RMT_AFIFO_RST_0_V << RMT_AFIFO_RST_0_S) +#define RMT_AFIFO_RST_0_V 0x00000001 +#define RMT_AFIFO_RST_0_S 23 +/** RMT_CONF_UPDATE_0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_0 (BIT(24)) +#define RMT_CONF_UPDATE_0_M (RMT_CONF_UPDATE_0_V << RMT_CONF_UPDATE_0_S) +#define RMT_CONF_UPDATE_0_V 0x00000001 +#define RMT_CONF_UPDATE_0_S 24 -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) -/* RMT_CONF_UPDATE_CH0 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH0 (BIT(24)) -#define RMT_CONF_UPDATE_CH0_M (BIT(24)) -#define RMT_CONF_UPDATE_CH0_V 0x1 -#define RMT_CONF_UPDATE_CH0_S 24 -/* RMT_AFIFO_RST_CH0 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH0 (BIT(23)) -#define RMT_AFIFO_RST_CH0_M (BIT(23)) -#define RMT_AFIFO_RST_CH0_V 0x1 -#define RMT_AFIFO_RST_CH0_S 23 -/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 22 -/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH0 (BIT(21)) -#define RMT_CARRIER_EN_CH0_M (BIT(21)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 21 -/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_V 0x1 -#define RMT_CARRIER_EFF_EN_CH0_S 20 -/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH0 0x0000000F -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V) << (RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0xF -#define RMT_MEM_SIZE_CH0_S 16 -/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V) << (RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 8 -/* RMT_TX_STOP_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH0 (BIT(7)) -#define RMT_TX_STOP_CH0_M (BIT(7)) -#define RMT_TX_STOP_CH0_V 0x1 -#define RMT_TX_STOP_CH0_S 7 -/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 6 -/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 5 -/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH0_S 4 -/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 3 -/* RMT_APB_MEM_RST_CH0 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH0 (BIT(2)) -#define RMT_APB_MEM_RST_CH0_M (BIT(2)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 2 -/* RMT_MEM_RD_RST_CH0 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH0 (BIT(1)) -#define RMT_MEM_RD_RST_CH0_M (BIT(1)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 1 -/* RMT_TX_START_CH0 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_TX_START_1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_1 (BIT(0)) +#define RMT_TX_START_1_M (RMT_TX_START_1_V << RMT_TX_START_1_S) +#define RMT_TX_START_1_V 0x00000001 +#define RMT_TX_START_1_S 0 +/** RMT_MEM_RD_RST_1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_1 (BIT(1)) +#define RMT_MEM_RD_RST_1_M (RMT_MEM_RD_RST_1_V << RMT_MEM_RD_RST_1_S) +#define RMT_MEM_RD_RST_1_V 0x00000001 +#define RMT_MEM_RD_RST_1_S 1 +/** RMT_APB_MEM_RST_1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_1 (BIT(2)) +#define RMT_APB_MEM_RST_1_M (RMT_APB_MEM_RST_1_V << RMT_APB_MEM_RST_1_S) +#define RMT_APB_MEM_RST_1_V 0x00000001 +#define RMT_APB_MEM_RST_1_S 2 +/** RMT_TX_CONTI_MODE_1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_1 (BIT(3)) +#define RMT_TX_CONTI_MODE_1_M (RMT_TX_CONTI_MODE_1_V << RMT_TX_CONTI_MODE_1_S) +#define RMT_TX_CONTI_MODE_1_V 0x00000001 +#define RMT_TX_CONTI_MODE_1_S 3 +/** RMT_MEM_TX_WRAP_EN_1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_1_M (RMT_MEM_TX_WRAP_EN_1_V << RMT_MEM_TX_WRAP_EN_1_S) +#define RMT_MEM_TX_WRAP_EN_1_V 0x00000001 +#define RMT_MEM_TX_WRAP_EN_1_S 4 +/** RMT_IDLE_OUT_LV_1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_1 (BIT(5)) +#define RMT_IDLE_OUT_LV_1_M (RMT_IDLE_OUT_LV_1_V << RMT_IDLE_OUT_LV_1_S) +#define RMT_IDLE_OUT_LV_1_V 0x00000001 +#define RMT_IDLE_OUT_LV_1_S 5 +/** RMT_IDLE_OUT_EN_1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_1 (BIT(6)) +#define RMT_IDLE_OUT_EN_1_M (RMT_IDLE_OUT_EN_1_V << RMT_IDLE_OUT_EN_1_S) +#define RMT_IDLE_OUT_EN_1_V 0x00000001 +#define RMT_IDLE_OUT_EN_1_S 6 +/** RMT_TX_STOP_1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_1 (BIT(7)) +#define RMT_TX_STOP_1_M (RMT_TX_STOP_1_V << RMT_TX_STOP_1_S) +#define RMT_TX_STOP_1_V 0x00000001 +#define RMT_TX_STOP_1_S 7 +/** RMT_DIV_CNT_1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_1 0x000000FF +#define RMT_DIV_CNT_1_M (RMT_DIV_CNT_1_V << RMT_DIV_CNT_1_S) +#define RMT_DIV_CNT_1_V 0x000000FF +#define RMT_DIV_CNT_1_S 8 +/** RMT_MEM_SIZE_1 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_1 0x0000000F +#define RMT_MEM_SIZE_1_M (RMT_MEM_SIZE_1_V << RMT_MEM_SIZE_1_S) +#define RMT_MEM_SIZE_1_V 0x0000000F +#define RMT_MEM_SIZE_1_S 16 +/** RMT_CARRIER_EFF_EN_1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_1_M (RMT_CARRIER_EFF_EN_1_V << RMT_CARRIER_EFF_EN_1_S) +#define RMT_CARRIER_EFF_EN_1_V 0x00000001 +#define RMT_CARRIER_EFF_EN_1_S 20 +/** RMT_CARRIER_EN_1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_1 (BIT(21)) +#define RMT_CARRIER_EN_1_M (RMT_CARRIER_EN_1_V << RMT_CARRIER_EN_1_S) +#define RMT_CARRIER_EN_1_V 0x00000001 +#define RMT_CARRIER_EN_1_S 21 +/** RMT_CARRIER_OUT_LV_1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_1_M (RMT_CARRIER_OUT_LV_1_V << RMT_CARRIER_OUT_LV_1_S) +#define RMT_CARRIER_OUT_LV_1_V 0x00000001 +#define RMT_CARRIER_OUT_LV_1_S 22 +/** RMT_AFIFO_RST_1 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_1 (BIT(23)) +#define RMT_AFIFO_RST_1_M (RMT_AFIFO_RST_1_V << RMT_AFIFO_RST_1_S) +#define RMT_AFIFO_RST_1_V 0x00000001 +#define RMT_AFIFO_RST_1_S 23 +/** RMT_CONF_UPDATE_1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_1 (BIT(24)) +#define RMT_CONF_UPDATE_1_M (RMT_CONF_UPDATE_1_V << RMT_CONF_UPDATE_1_S) +#define RMT_CONF_UPDATE_1_V 0x00000001 +#define RMT_CONF_UPDATE_1_S 24 -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0024) -/* RMT_CONF_UPDATE_CH1 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH1 (BIT(24)) -#define RMT_CONF_UPDATE_CH1_M (BIT(24)) -#define RMT_CONF_UPDATE_CH1_V 0x1 -#define RMT_CONF_UPDATE_CH1_S 24 -/* RMT_AFIFO_RST_CH1 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH1 (BIT(23)) -#define RMT_AFIFO_RST_CH1_M (BIT(23)) -#define RMT_AFIFO_RST_CH1_V 0x1 -#define RMT_AFIFO_RST_CH1_S 23 -/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 22 -/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH1 (BIT(21)) -#define RMT_CARRIER_EN_CH1_M (BIT(21)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 21 -/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_V 0x1 -#define RMT_CARRIER_EFF_EN_CH1_S 20 -/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH1 0x0000000F -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V) << (RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0xF -#define RMT_MEM_SIZE_CH1_S 16 -/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V) << (RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 8 -/* RMT_TX_STOP_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH1 (BIT(7)) -#define RMT_TX_STOP_CH1_M (BIT(7)) -#define RMT_TX_STOP_CH1_V 0x1 -#define RMT_TX_STOP_CH1_S 7 -/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 6 -/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 5 -/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH1_S 4 -/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 3 -/* RMT_APB_MEM_RST_CH1 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH1 (BIT(2)) -#define RMT_APB_MEM_RST_CH1_M (BIT(2)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 2 -/* RMT_MEM_RD_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH1 (BIT(1)) -#define RMT_MEM_RD_RST_CH1_M (BIT(1)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 1 -/* RMT_TX_START_CH1 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_TX_START_2 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL2. + */ +#define RMT_TX_START_2 (BIT(0)) +#define RMT_TX_START_2_M (RMT_TX_START_2_V << RMT_TX_START_2_S) +#define RMT_TX_START_2_V 0x00000001 +#define RMT_TX_START_2_S 0 +/** RMT_MEM_RD_RST_2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL2 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_2 (BIT(1)) +#define RMT_MEM_RD_RST_2_M (RMT_MEM_RD_RST_2_V << RMT_MEM_RD_RST_2_S) +#define RMT_MEM_RD_RST_2_V 0x00000001 +#define RMT_MEM_RD_RST_2_S 1 +/** RMT_APB_MEM_RST_2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_2 (BIT(2)) +#define RMT_APB_MEM_RST_2_M (RMT_APB_MEM_RST_2_V << RMT_APB_MEM_RST_2_S) +#define RMT_APB_MEM_RST_2_V 0x00000001 +#define RMT_APB_MEM_RST_2_S 2 +/** RMT_TX_CONTI_MODE_2 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL2. + */ +#define RMT_TX_CONTI_MODE_2 (BIT(3)) +#define RMT_TX_CONTI_MODE_2_M (RMT_TX_CONTI_MODE_2_V << RMT_TX_CONTI_MODE_2_S) +#define RMT_TX_CONTI_MODE_2_V 0x00000001 +#define RMT_TX_CONTI_MODE_2_S 3 +/** RMT_MEM_TX_WRAP_EN_2 : R/W; bitpos: [4]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_2_M (RMT_MEM_TX_WRAP_EN_2_V << RMT_MEM_TX_WRAP_EN_2_S) +#define RMT_MEM_TX_WRAP_EN_2_V 0x00000001 +#define RMT_MEM_TX_WRAP_EN_2_S 4 +/** RMT_IDLE_OUT_LV_2 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL2 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_2 (BIT(5)) +#define RMT_IDLE_OUT_LV_2_M (RMT_IDLE_OUT_LV_2_V << RMT_IDLE_OUT_LV_2_S) +#define RMT_IDLE_OUT_LV_2_V 0x00000001 +#define RMT_IDLE_OUT_LV_2_S 5 +/** RMT_IDLE_OUT_EN_2 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL2 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_2 (BIT(6)) +#define RMT_IDLE_OUT_EN_2_M (RMT_IDLE_OUT_EN_2_V << RMT_IDLE_OUT_EN_2_S) +#define RMT_IDLE_OUT_EN_2_V 0x00000001 +#define RMT_IDLE_OUT_EN_2_S 6 +/** RMT_TX_STOP_2 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL2 sending data out. + */ +#define RMT_TX_STOP_2 (BIT(7)) +#define RMT_TX_STOP_2_M (RMT_TX_STOP_2_V << RMT_TX_STOP_2_S) +#define RMT_TX_STOP_2_V 0x00000001 +#define RMT_TX_STOP_2_S 7 +/** RMT_DIV_CNT_2 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_2 0x000000FF +#define RMT_DIV_CNT_2_M (RMT_DIV_CNT_2_V << RMT_DIV_CNT_2_S) +#define RMT_DIV_CNT_2_V 0x000000FF +#define RMT_DIV_CNT_2_S 8 +/** RMT_MEM_SIZE_2 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_2 0x0000000F +#define RMT_MEM_SIZE_2_M (RMT_MEM_SIZE_2_V << RMT_MEM_SIZE_2_S) +#define RMT_MEM_SIZE_2_V 0x0000000F +#define RMT_MEM_SIZE_2_S 16 +/** RMT_CARRIER_EFF_EN_2 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL2. 0: Add carrier modulation on the output signal at all state for CHANNEL2. + * Only valid when RMT_CARRIER_EN_CH2 is 1. + */ +#define RMT_CARRIER_EFF_EN_2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_2_M (RMT_CARRIER_EFF_EN_2_V << RMT_CARRIER_EFF_EN_2_S) +#define RMT_CARRIER_EFF_EN_2_V 0x00000001 +#define RMT_CARRIER_EFF_EN_2_S 20 +/** RMT_CARRIER_EN_2 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_2 (BIT(21)) +#define RMT_CARRIER_EN_2_M (RMT_CARRIER_EN_2_V << RMT_CARRIER_EN_2_S) +#define RMT_CARRIER_EN_2_V 0x00000001 +#define RMT_CARRIER_EN_2_S 21 +/** RMT_CARRIER_OUT_LV_2 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_2_M (RMT_CARRIER_OUT_LV_2_V << RMT_CARRIER_OUT_LV_2_S) +#define RMT_CARRIER_OUT_LV_2_V 0x00000001 +#define RMT_CARRIER_OUT_LV_2_S 22 +/** RMT_AFIFO_RST_2 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_2 (BIT(23)) +#define RMT_AFIFO_RST_2_M (RMT_AFIFO_RST_2_V << RMT_AFIFO_RST_2_S) +#define RMT_AFIFO_RST_2_V 0x00000001 +#define RMT_AFIFO_RST_2_S 23 +/** RMT_CONF_UPDATE_2 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_2 (BIT(24)) +#define RMT_CONF_UPDATE_2_M (RMT_CONF_UPDATE_2_V << RMT_CONF_UPDATE_2_S) +#define RMT_CONF_UPDATE_2_V 0x00000001 +#define RMT_CONF_UPDATE_2_S 24 -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0028) -/* RMT_CONF_UPDATE_CH2 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH2 (BIT(24)) -#define RMT_CONF_UPDATE_CH2_M (BIT(24)) -#define RMT_CONF_UPDATE_CH2_V 0x1 -#define RMT_CONF_UPDATE_CH2_S 24 -/* RMT_AFIFO_RST_CH2 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH2 (BIT(23)) -#define RMT_AFIFO_RST_CH2_M (BIT(23)) -#define RMT_AFIFO_RST_CH2_V 0x1 -#define RMT_AFIFO_RST_CH2_S 23 -/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 22 -/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH2 (BIT(21)) -#define RMT_CARRIER_EN_CH2_M (BIT(21)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 21 -/* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_V 0x1 -#define RMT_CARRIER_EFF_EN_CH2_S 20 -/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH2 0x0000000F -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V) << (RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0xF -#define RMT_MEM_SIZE_CH2_S 16 -/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V) << (RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 8 -/* RMT_TX_STOP_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH2 (BIT(7)) -#define RMT_TX_STOP_CH2_M (BIT(7)) -#define RMT_TX_STOP_CH2_V 0x1 -#define RMT_TX_STOP_CH2_S 7 -/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_V 0x1 -#define RMT_IDLE_OUT_EN_CH2_S 6 -/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_V 0x1 -#define RMT_IDLE_OUT_LV_CH2_S 5 -/* RMT_MEM_TX_WRAP_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH2_S 4 -/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_V 0x1 -#define RMT_TX_CONTI_MODE_CH2_S 3 -/* RMT_APB_MEM_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH2 (BIT(2)) -#define RMT_APB_MEM_RST_CH2_M (BIT(2)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 2 -/* RMT_MEM_RD_RST_CH2 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH2 (BIT(1)) -#define RMT_MEM_RD_RST_CH2_M (BIT(1)) -#define RMT_MEM_RD_RST_CH2_V 0x1 -#define RMT_MEM_RD_RST_CH2_S 1 -/* RMT_TX_START_CH2 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH2 (BIT(0)) -#define RMT_TX_START_CH2_M (BIT(0)) -#define RMT_TX_START_CH2_V 0x1 -#define RMT_TX_START_CH2_S 0 +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_TX_START_3 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL3. + */ +#define RMT_TX_START_3 (BIT(0)) +#define RMT_TX_START_3_M (RMT_TX_START_3_V << RMT_TX_START_3_S) +#define RMT_TX_START_3_V 0x00000001 +#define RMT_TX_START_3_S 0 +/** RMT_MEM_RD_RST_3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL3 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_3 (BIT(1)) +#define RMT_MEM_RD_RST_3_M (RMT_MEM_RD_RST_3_V << RMT_MEM_RD_RST_3_S) +#define RMT_MEM_RD_RST_3_V 0x00000001 +#define RMT_MEM_RD_RST_3_S 1 +/** RMT_APB_MEM_RST_3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_3 (BIT(2)) +#define RMT_APB_MEM_RST_3_M (RMT_APB_MEM_RST_3_V << RMT_APB_MEM_RST_3_S) +#define RMT_APB_MEM_RST_3_V 0x00000001 +#define RMT_APB_MEM_RST_3_S 2 +/** RMT_TX_CONTI_MODE_3 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL3. + */ +#define RMT_TX_CONTI_MODE_3 (BIT(3)) +#define RMT_TX_CONTI_MODE_3_M (RMT_TX_CONTI_MODE_3_V << RMT_TX_CONTI_MODE_3_S) +#define RMT_TX_CONTI_MODE_3_V 0x00000001 +#define RMT_TX_CONTI_MODE_3_S 3 +/** RMT_MEM_TX_WRAP_EN_3 : R/W; bitpos: [4]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_3_M (RMT_MEM_TX_WRAP_EN_3_V << RMT_MEM_TX_WRAP_EN_3_S) +#define RMT_MEM_TX_WRAP_EN_3_V 0x00000001 +#define RMT_MEM_TX_WRAP_EN_3_S 4 +/** RMT_IDLE_OUT_LV_3 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL3 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_3 (BIT(5)) +#define RMT_IDLE_OUT_LV_3_M (RMT_IDLE_OUT_LV_3_V << RMT_IDLE_OUT_LV_3_S) +#define RMT_IDLE_OUT_LV_3_V 0x00000001 +#define RMT_IDLE_OUT_LV_3_S 5 +/** RMT_IDLE_OUT_EN_3 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL3 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_3 (BIT(6)) +#define RMT_IDLE_OUT_EN_3_M (RMT_IDLE_OUT_EN_3_V << RMT_IDLE_OUT_EN_3_S) +#define RMT_IDLE_OUT_EN_3_V 0x00000001 +#define RMT_IDLE_OUT_EN_3_S 6 +/** RMT_TX_STOP_3 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL3 sending data out. + */ +#define RMT_TX_STOP_3 (BIT(7)) +#define RMT_TX_STOP_3_M (RMT_TX_STOP_3_V << RMT_TX_STOP_3_S) +#define RMT_TX_STOP_3_V 0x00000001 +#define RMT_TX_STOP_3_S 7 +/** RMT_DIV_CNT_3 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_3 0x000000FF +#define RMT_DIV_CNT_3_M (RMT_DIV_CNT_3_V << RMT_DIV_CNT_3_S) +#define RMT_DIV_CNT_3_V 0x000000FF +#define RMT_DIV_CNT_3_S 8 +/** RMT_MEM_SIZE_3 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_3 0x0000000F +#define RMT_MEM_SIZE_3_M (RMT_MEM_SIZE_3_V << RMT_MEM_SIZE_3_S) +#define RMT_MEM_SIZE_3_V 0x0000000F +#define RMT_MEM_SIZE_3_S 16 +/** RMT_CARRIER_EFF_EN_3 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL3. 0: Add carrier modulation on the output signal at all state for CHANNEL3. + * Only valid when RMT_CARRIER_EN_CH3 is 1. + */ +#define RMT_CARRIER_EFF_EN_3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_3_M (RMT_CARRIER_EFF_EN_3_V << RMT_CARRIER_EFF_EN_3_S) +#define RMT_CARRIER_EFF_EN_3_V 0x00000001 +#define RMT_CARRIER_EFF_EN_3_S 20 +/** RMT_CARRIER_EN_3 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_3 (BIT(21)) +#define RMT_CARRIER_EN_3_M (RMT_CARRIER_EN_3_V << RMT_CARRIER_EN_3_S) +#define RMT_CARRIER_EN_3_V 0x00000001 +#define RMT_CARRIER_EN_3_S 21 +/** RMT_CARRIER_OUT_LV_3 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_3_M (RMT_CARRIER_OUT_LV_3_V << RMT_CARRIER_OUT_LV_3_S) +#define RMT_CARRIER_OUT_LV_3_V 0x00000001 +#define RMT_CARRIER_OUT_LV_3_S 22 +/** RMT_AFIFO_RST_3 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_3 (BIT(23)) +#define RMT_AFIFO_RST_3_M (RMT_AFIFO_RST_3_V << RMT_AFIFO_RST_3_S) +#define RMT_AFIFO_RST_3_V 0x00000001 +#define RMT_AFIFO_RST_3_S 23 +/** RMT_CONF_UPDATE_3 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_3 (BIT(24)) +#define RMT_CONF_UPDATE_3_M (RMT_CONF_UPDATE_3_V << RMT_CONF_UPDATE_3_S) +#define RMT_CONF_UPDATE_3_V 0x00000001 +#define RMT_CONF_UPDATE_3_S 24 -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x002c) -/* RMT_CONF_UPDATE_CH3 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH3 (BIT(24)) -#define RMT_CONF_UPDATE_CH3_M (BIT(24)) -#define RMT_CONF_UPDATE_CH3_V 0x1 -#define RMT_CONF_UPDATE_CH3_S 24 -/* RMT_AFIFO_RST_CH3 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH3 (BIT(23)) -#define RMT_AFIFO_RST_CH3_M (BIT(23)) -#define RMT_AFIFO_RST_CH3_V 0x1 -#define RMT_AFIFO_RST_CH3_S 23 -/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 22 -/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH3 (BIT(21)) -#define RMT_CARRIER_EN_CH3_M (BIT(21)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 21 -/* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_V 0x1 -#define RMT_CARRIER_EFF_EN_CH3_S 20 -/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH3 0x0000000F -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V) << (RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0xF -#define RMT_MEM_SIZE_CH3_S 16 -/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V) << (RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 8 -/* RMT_TX_STOP_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH3 (BIT(7)) -#define RMT_TX_STOP_CH3_M (BIT(7)) -#define RMT_TX_STOP_CH3_V 0x1 -#define RMT_TX_STOP_CH3_S 7 -/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_V 0x1 -#define RMT_IDLE_OUT_EN_CH3_S 6 -/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_V 0x1 -#define RMT_IDLE_OUT_LV_CH3_S 5 -/* RMT_MEM_TX_WRAP_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH3_S 4 -/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_V 0x1 -#define RMT_TX_CONTI_MODE_CH3_S 3 -/* RMT_APB_MEM_RST_CH3 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH3 (BIT(2)) -#define RMT_APB_MEM_RST_CH3_M (BIT(2)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 2 -/* RMT_MEM_RD_RST_CH3 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH3 (BIT(1)) -#define RMT_MEM_RD_RST_CH3_M (BIT(1)) -#define RMT_MEM_RD_RST_CH3_V 0x1 -#define RMT_MEM_RD_RST_CH3_S 1 -/* RMT_TX_START_CH3 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH3 (BIT(0)) -#define RMT_TX_START_CH3_M (BIT(0)) -#define RMT_TX_START_CH3_V 0x1 -#define RMT_TX_START_CH3_S 0 +/** RMT_CH4CONF0_REG register + * Channel 4 configure register 0 + */ +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_DIV_CNT_4 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL4. + */ +#define RMT_DIV_CNT_4 0x000000FF +#define RMT_DIV_CNT_4_M (RMT_DIV_CNT_4_V << RMT_DIV_CNT_4_S) +#define RMT_DIV_CNT_4_V 0x000000FF +#define RMT_DIV_CNT_4_S 0 +/** RMT_IDLE_THRES_4 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_4 0x00007FFF +#define RMT_IDLE_THRES_4_M (RMT_IDLE_THRES_4_V << RMT_IDLE_THRES_4_S) +#define RMT_IDLE_THRES_4_V 0x00007FFF +#define RMT_IDLE_THRES_4_S 8 +/** RMT_MEM_SIZE_4 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL4. + */ +#define RMT_MEM_SIZE_4 0x0000000F +#define RMT_MEM_SIZE_4_M (RMT_MEM_SIZE_4_V << RMT_MEM_SIZE_4_S) +#define RMT_MEM_SIZE_4_V 0x0000000F +#define RMT_MEM_SIZE_4_S 24 +/** RMT_CARRIER_EN_4 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL4. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_4 (BIT(28)) +#define RMT_CARRIER_EN_4_M (RMT_CARRIER_EN_4_V << RMT_CARRIER_EN_4_S) +#define RMT_CARRIER_EN_4_V 0x00000001 +#define RMT_CARRIER_EN_4_S 28 +/** RMT_CARRIER_OUT_LV_4 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL4. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_4_M (RMT_CARRIER_OUT_LV_4_V << RMT_CARRIER_OUT_LV_4_S) +#define RMT_CARRIER_OUT_LV_4_V 0x00000001 +#define RMT_CARRIER_OUT_LV_4_S 29 -#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0030) -/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_V 0x1 -#define RMT_CARRIER_OUT_LV_CH4_S 29 -/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH4 (BIT(28)) -#define RMT_CARRIER_EN_CH4_M (BIT(28)) -#define RMT_CARRIER_EN_CH4_V 0x1 -#define RMT_CARRIER_EN_CH4_S 28 -/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH4 0x0000000F -#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V) << (RMT_MEM_SIZE_CH4_S)) -#define RMT_MEM_SIZE_CH4_V 0xF -#define RMT_MEM_SIZE_CH4_S 24 -/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH4 0x00007FFF -#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V) << (RMT_IDLE_THRES_CH4_S)) -#define RMT_IDLE_THRES_CH4_V 0x7FFF -#define RMT_IDLE_THRES_CH4_S 8 -/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH4 0x000000FF -#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V) << (RMT_DIV_CNT_CH4_S)) -#define RMT_DIV_CNT_CH4_V 0xFF -#define RMT_DIV_CNT_CH4_S 0 +/** RMT_CH4CONF1_REG register + * Channel 4 configure register 1 + */ +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_RX_EN_4 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL4. + */ +#define RMT_RX_EN_4 (BIT(0)) +#define RMT_RX_EN_4_M (RMT_RX_EN_4_V << RMT_RX_EN_4_S) +#define RMT_RX_EN_4_V 0x00000001 +#define RMT_RX_EN_4_S 0 +/** RMT_MEM_WR_RST_4 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL4 by accessing receiver. + */ +#define RMT_MEM_WR_RST_4 (BIT(1)) +#define RMT_MEM_WR_RST_4_M (RMT_MEM_WR_RST_4_V << RMT_MEM_WR_RST_4_S) +#define RMT_MEM_WR_RST_4_V 0x00000001 +#define RMT_MEM_WR_RST_4_S 1 +/** RMT_APB_MEM_RST_4 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL4 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_4 (BIT(2)) +#define RMT_APB_MEM_RST_4_M (RMT_APB_MEM_RST_4_V << RMT_APB_MEM_RST_4_S) +#define RMT_APB_MEM_RST_4_V 0x00000001 +#define RMT_APB_MEM_RST_4_S 2 +/** RMT_MEM_OWNER_4 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL4's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_4 (BIT(3)) +#define RMT_MEM_OWNER_4_M (RMT_MEM_OWNER_4_V << RMT_MEM_OWNER_4_S) +#define RMT_MEM_OWNER_4_V 0x00000001 +#define RMT_MEM_OWNER_4_S 3 +/** RMT_RX_FILTER_EN_4 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL4. + */ +#define RMT_RX_FILTER_EN_4 (BIT(4)) +#define RMT_RX_FILTER_EN_4_M (RMT_RX_FILTER_EN_4_V << RMT_RX_FILTER_EN_4_S) +#define RMT_RX_FILTER_EN_4_V 0x00000001 +#define RMT_RX_FILTER_EN_4_S 4 +/** RMT_RX_FILTER_THRES_4 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_4 0x000000FF +#define RMT_RX_FILTER_THRES_4_M (RMT_RX_FILTER_THRES_4_V << RMT_RX_FILTER_THRES_4_S) +#define RMT_RX_FILTER_THRES_4_V 0x000000FF +#define RMT_RX_FILTER_THRES_4_S 5 +/** RMT_MEM_RX_WRAP_EN_4 : R/W; bitpos: [13]; default: 0; + * This is the channel 4 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_4_M (RMT_MEM_RX_WRAP_EN_4_V << RMT_MEM_RX_WRAP_EN_4_S) +#define RMT_MEM_RX_WRAP_EN_4_V 0x00000001 +#define RMT_MEM_RX_WRAP_EN_4_S 13 +/** RMT_AFIFO_RST_4 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_4 (BIT(14)) +#define RMT_AFIFO_RST_4_M (RMT_AFIFO_RST_4_V << RMT_AFIFO_RST_4_S) +#define RMT_AFIFO_RST_4_V 0x00000001 +#define RMT_AFIFO_RST_4_S 14 +/** RMT_CONF_UPDATE_4 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL4 + */ +#define RMT_CONF_UPDATE_4 (BIT(15)) +#define RMT_CONF_UPDATE_4_M (RMT_CONF_UPDATE_4_V << RMT_CONF_UPDATE_4_S) +#define RMT_CONF_UPDATE_4_V 0x00000001 +#define RMT_CONF_UPDATE_4_S 15 -#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0034) -/* RMT_CONF_UPDATE_CH4 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH4 (BIT(15)) -#define RMT_CONF_UPDATE_CH4_M (BIT(15)) -#define RMT_CONF_UPDATE_CH4_V 0x1 -#define RMT_CONF_UPDATE_CH4_S 15 -/* RMT_AFIFO_RST_CH4 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH4 (BIT(14)) -#define RMT_AFIFO_RST_CH4_M (BIT(14)) -#define RMT_AFIFO_RST_CH4_V 0x1 -#define RMT_AFIFO_RST_CH4_S 14 -/* RMT_MEM_RX_WRAP_EN_CH4 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH4_S 13 -/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH4 0x000000FF -#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V) << (RMT_RX_FILTER_THRES_CH4_S)) -#define RMT_RX_FILTER_THRES_CH4_V 0xFF -#define RMT_RX_FILTER_THRES_CH4_S 5 -/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH4 (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_V 0x1 -#define RMT_RX_FILTER_EN_CH4_S 4 -/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH4 (BIT(3)) -#define RMT_MEM_OWNER_CH4_M (BIT(3)) -#define RMT_MEM_OWNER_CH4_V 0x1 -#define RMT_MEM_OWNER_CH4_S 3 -/* RMT_APB_MEM_RST_CH4 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH4 (BIT(2)) -#define RMT_APB_MEM_RST_CH4_M (BIT(2)) -#define RMT_APB_MEM_RST_CH4_V 0x1 -#define RMT_APB_MEM_RST_CH4_S 2 -/* RMT_MEM_WR_RST_CH4 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH4 (BIT(1)) -#define RMT_MEM_WR_RST_CH4_M (BIT(1)) -#define RMT_MEM_WR_RST_CH4_V 0x1 -#define RMT_MEM_WR_RST_CH4_S 1 -/* RMT_RX_EN_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH4 (BIT(0)) -#define RMT_RX_EN_CH4_M (BIT(0)) -#define RMT_RX_EN_CH4_V 0x1 -#define RMT_RX_EN_CH4_S 0 +/** RMT_CH5CONF0_REG register + * Channel 5 configure register 0 + */ +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_DIV_CNT_5 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL5. + */ +#define RMT_DIV_CNT_5 0x000000FF +#define RMT_DIV_CNT_5_M (RMT_DIV_CNT_5_V << RMT_DIV_CNT_5_S) +#define RMT_DIV_CNT_5_V 0x000000FF +#define RMT_DIV_CNT_5_S 0 +/** RMT_IDLE_THRES_5 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_5 0x00007FFF +#define RMT_IDLE_THRES_5_M (RMT_IDLE_THRES_5_V << RMT_IDLE_THRES_5_S) +#define RMT_IDLE_THRES_5_V 0x00007FFF +#define RMT_IDLE_THRES_5_S 8 +/** RMT_MEM_SIZE_5 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL5. + */ +#define RMT_MEM_SIZE_5 0x0000000F +#define RMT_MEM_SIZE_5_M (RMT_MEM_SIZE_5_V << RMT_MEM_SIZE_5_S) +#define RMT_MEM_SIZE_5_V 0x0000000F +#define RMT_MEM_SIZE_5_S 24 +/** RMT_CARRIER_EN_5 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL5. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_5 (BIT(28)) +#define RMT_CARRIER_EN_5_M (RMT_CARRIER_EN_5_V << RMT_CARRIER_EN_5_S) +#define RMT_CARRIER_EN_5_V 0x00000001 +#define RMT_CARRIER_EN_5_S 28 +/** RMT_CARRIER_OUT_LV_5 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL5. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_5_M (RMT_CARRIER_OUT_LV_5_V << RMT_CARRIER_OUT_LV_5_S) +#define RMT_CARRIER_OUT_LV_5_V 0x00000001 +#define RMT_CARRIER_OUT_LV_5_S 29 -#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0038) -/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_V 0x1 -#define RMT_CARRIER_OUT_LV_CH5_S 29 -/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH5 (BIT(28)) -#define RMT_CARRIER_EN_CH5_M (BIT(28)) -#define RMT_CARRIER_EN_CH5_V 0x1 -#define RMT_CARRIER_EN_CH5_S 28 -/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH5 0x0000000F -#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V) << (RMT_MEM_SIZE_CH5_S)) -#define RMT_MEM_SIZE_CH5_V 0xF -#define RMT_MEM_SIZE_CH5_S 24 -/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH5 0x00007FFF -#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V) << (RMT_IDLE_THRES_CH5_S)) -#define RMT_IDLE_THRES_CH5_V 0x7FFF -#define RMT_IDLE_THRES_CH5_S 8 -/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH5 0x000000FF -#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V) << (RMT_DIV_CNT_CH5_S)) -#define RMT_DIV_CNT_CH5_V 0xFF -#define RMT_DIV_CNT_CH5_S 0 +/** RMT_CH5CONF1_REG register + * Channel 5 configure register 1 + */ +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_RX_EN_5 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL5. + */ +#define RMT_RX_EN_5 (BIT(0)) +#define RMT_RX_EN_5_M (RMT_RX_EN_5_V << RMT_RX_EN_5_S) +#define RMT_RX_EN_5_V 0x00000001 +#define RMT_RX_EN_5_S 0 +/** RMT_MEM_WR_RST_5 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL5 by accessing receiver. + */ +#define RMT_MEM_WR_RST_5 (BIT(1)) +#define RMT_MEM_WR_RST_5_M (RMT_MEM_WR_RST_5_V << RMT_MEM_WR_RST_5_S) +#define RMT_MEM_WR_RST_5_V 0x00000001 +#define RMT_MEM_WR_RST_5_S 1 +/** RMT_APB_MEM_RST_5 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL5 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_5 (BIT(2)) +#define RMT_APB_MEM_RST_5_M (RMT_APB_MEM_RST_5_V << RMT_APB_MEM_RST_5_S) +#define RMT_APB_MEM_RST_5_V 0x00000001 +#define RMT_APB_MEM_RST_5_S 2 +/** RMT_MEM_OWNER_5 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL5's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_5 (BIT(3)) +#define RMT_MEM_OWNER_5_M (RMT_MEM_OWNER_5_V << RMT_MEM_OWNER_5_S) +#define RMT_MEM_OWNER_5_V 0x00000001 +#define RMT_MEM_OWNER_5_S 3 +/** RMT_RX_FILTER_EN_5 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL5. + */ +#define RMT_RX_FILTER_EN_5 (BIT(4)) +#define RMT_RX_FILTER_EN_5_M (RMT_RX_FILTER_EN_5_V << RMT_RX_FILTER_EN_5_S) +#define RMT_RX_FILTER_EN_5_V 0x00000001 +#define RMT_RX_FILTER_EN_5_S 4 +/** RMT_RX_FILTER_THRES_5 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_5 0x000000FF +#define RMT_RX_FILTER_THRES_5_M (RMT_RX_FILTER_THRES_5_V << RMT_RX_FILTER_THRES_5_S) +#define RMT_RX_FILTER_THRES_5_V 0x000000FF +#define RMT_RX_FILTER_THRES_5_S 5 +/** RMT_MEM_RX_WRAP_EN_5 : R/W; bitpos: [13]; default: 0; + * This is the channel 5 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_5_M (RMT_MEM_RX_WRAP_EN_5_V << RMT_MEM_RX_WRAP_EN_5_S) +#define RMT_MEM_RX_WRAP_EN_5_V 0x00000001 +#define RMT_MEM_RX_WRAP_EN_5_S 13 +/** RMT_AFIFO_RST_5 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_5 (BIT(14)) +#define RMT_AFIFO_RST_5_M (RMT_AFIFO_RST_5_V << RMT_AFIFO_RST_5_S) +#define RMT_AFIFO_RST_5_V 0x00000001 +#define RMT_AFIFO_RST_5_S 14 +/** RMT_CONF_UPDATE_5 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL5 + */ +#define RMT_CONF_UPDATE_5 (BIT(15)) +#define RMT_CONF_UPDATE_5_M (RMT_CONF_UPDATE_5_V << RMT_CONF_UPDATE_5_S) +#define RMT_CONF_UPDATE_5_V 0x00000001 +#define RMT_CONF_UPDATE_5_S 15 -#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x003c) -/* RMT_CONF_UPDATE_CH5 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH5 (BIT(15)) -#define RMT_CONF_UPDATE_CH5_M (BIT(15)) -#define RMT_CONF_UPDATE_CH5_V 0x1 -#define RMT_CONF_UPDATE_CH5_S 15 -/* RMT_AFIFO_RST_CH5 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH5 (BIT(14)) -#define RMT_AFIFO_RST_CH5_M (BIT(14)) -#define RMT_AFIFO_RST_CH5_V 0x1 -#define RMT_AFIFO_RST_CH5_S 14 -/* RMT_MEM_RX_WRAP_EN_CH5 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH5_S 13 -/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH5 0x000000FF -#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V) << (RMT_RX_FILTER_THRES_CH5_S)) -#define RMT_RX_FILTER_THRES_CH5_V 0xFF -#define RMT_RX_FILTER_THRES_CH5_S 5 -/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH5 (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_V 0x1 -#define RMT_RX_FILTER_EN_CH5_S 4 -/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH5 (BIT(3)) -#define RMT_MEM_OWNER_CH5_M (BIT(3)) -#define RMT_MEM_OWNER_CH5_V 0x1 -#define RMT_MEM_OWNER_CH5_S 3 -/* RMT_APB_MEM_RST_CH5 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH5 (BIT(2)) -#define RMT_APB_MEM_RST_CH5_M (BIT(2)) -#define RMT_APB_MEM_RST_CH5_V 0x1 -#define RMT_APB_MEM_RST_CH5_S 2 -/* RMT_MEM_WR_RST_CH5 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH5 (BIT(1)) -#define RMT_MEM_WR_RST_CH5_M (BIT(1)) -#define RMT_MEM_WR_RST_CH5_V 0x1 -#define RMT_MEM_WR_RST_CH5_S 1 -/* RMT_RX_EN_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH5 (BIT(0)) -#define RMT_RX_EN_CH5_M (BIT(0)) -#define RMT_RX_EN_CH5_V 0x1 -#define RMT_RX_EN_CH5_S 0 +/** RMT_CH6CONF0_REG register + * Channel 6 configure register 0 + */ +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_DIV_CNT_6 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL6. + */ +#define RMT_DIV_CNT_6 0x000000FF +#define RMT_DIV_CNT_6_M (RMT_DIV_CNT_6_V << RMT_DIV_CNT_6_S) +#define RMT_DIV_CNT_6_V 0x000000FF +#define RMT_DIV_CNT_6_S 0 +/** RMT_IDLE_THRES_6 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_6 0x00007FFF +#define RMT_IDLE_THRES_6_M (RMT_IDLE_THRES_6_V << RMT_IDLE_THRES_6_S) +#define RMT_IDLE_THRES_6_V 0x00007FFF +#define RMT_IDLE_THRES_6_S 8 +/** RMT_MEM_SIZE_6 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL6. + */ +#define RMT_MEM_SIZE_6 0x0000000F +#define RMT_MEM_SIZE_6_M (RMT_MEM_SIZE_6_V << RMT_MEM_SIZE_6_S) +#define RMT_MEM_SIZE_6_V 0x0000000F +#define RMT_MEM_SIZE_6_S 24 +/** RMT_CARRIER_EN_6 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL6. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_6 (BIT(28)) +#define RMT_CARRIER_EN_6_M (RMT_CARRIER_EN_6_V << RMT_CARRIER_EN_6_S) +#define RMT_CARRIER_EN_6_V 0x00000001 +#define RMT_CARRIER_EN_6_S 28 +/** RMT_CARRIER_OUT_LV_6 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL6. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_6_M (RMT_CARRIER_OUT_LV_6_V << RMT_CARRIER_OUT_LV_6_S) +#define RMT_CARRIER_OUT_LV_6_V 0x00000001 +#define RMT_CARRIER_OUT_LV_6_S 29 -#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0040) -/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_V 0x1 -#define RMT_CARRIER_OUT_LV_CH6_S 29 -/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH6 (BIT(28)) -#define RMT_CARRIER_EN_CH6_M (BIT(28)) -#define RMT_CARRIER_EN_CH6_V 0x1 -#define RMT_CARRIER_EN_CH6_S 28 -/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH6 0x0000000F -#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V) << (RMT_MEM_SIZE_CH6_S)) -#define RMT_MEM_SIZE_CH6_V 0xF -#define RMT_MEM_SIZE_CH6_S 24 -/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH6 0x00007FFF -#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V) << (RMT_IDLE_THRES_CH6_S)) -#define RMT_IDLE_THRES_CH6_V 0x7FFF -#define RMT_IDLE_THRES_CH6_S 8 -/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH6 0x000000FF -#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V) << (RMT_DIV_CNT_CH6_S)) -#define RMT_DIV_CNT_CH6_V 0xFF -#define RMT_DIV_CNT_CH6_S 0 +/** RMT_CH6CONF1_REG register + * Channel 6 configure register 1 + */ +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_RX_EN_6 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL6. + */ +#define RMT_RX_EN_6 (BIT(0)) +#define RMT_RX_EN_6_M (RMT_RX_EN_6_V << RMT_RX_EN_6_S) +#define RMT_RX_EN_6_V 0x00000001 +#define RMT_RX_EN_6_S 0 +/** RMT_MEM_WR_RST_6 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL6 by accessing receiver. + */ +#define RMT_MEM_WR_RST_6 (BIT(1)) +#define RMT_MEM_WR_RST_6_M (RMT_MEM_WR_RST_6_V << RMT_MEM_WR_RST_6_S) +#define RMT_MEM_WR_RST_6_V 0x00000001 +#define RMT_MEM_WR_RST_6_S 1 +/** RMT_APB_MEM_RST_6 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL6 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_6 (BIT(2)) +#define RMT_APB_MEM_RST_6_M (RMT_APB_MEM_RST_6_V << RMT_APB_MEM_RST_6_S) +#define RMT_APB_MEM_RST_6_V 0x00000001 +#define RMT_APB_MEM_RST_6_S 2 +/** RMT_MEM_OWNER_6 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL6's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_6 (BIT(3)) +#define RMT_MEM_OWNER_6_M (RMT_MEM_OWNER_6_V << RMT_MEM_OWNER_6_S) +#define RMT_MEM_OWNER_6_V 0x00000001 +#define RMT_MEM_OWNER_6_S 3 +/** RMT_RX_FILTER_EN_6 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL6. + */ +#define RMT_RX_FILTER_EN_6 (BIT(4)) +#define RMT_RX_FILTER_EN_6_M (RMT_RX_FILTER_EN_6_V << RMT_RX_FILTER_EN_6_S) +#define RMT_RX_FILTER_EN_6_V 0x00000001 +#define RMT_RX_FILTER_EN_6_S 4 +/** RMT_RX_FILTER_THRES_6 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_6 0x000000FF +#define RMT_RX_FILTER_THRES_6_M (RMT_RX_FILTER_THRES_6_V << RMT_RX_FILTER_THRES_6_S) +#define RMT_RX_FILTER_THRES_6_V 0x000000FF +#define RMT_RX_FILTER_THRES_6_S 5 +/** RMT_MEM_RX_WRAP_EN_6 : R/W; bitpos: [13]; default: 0; + * This is the channel 6 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_6_M (RMT_MEM_RX_WRAP_EN_6_V << RMT_MEM_RX_WRAP_EN_6_S) +#define RMT_MEM_RX_WRAP_EN_6_V 0x00000001 +#define RMT_MEM_RX_WRAP_EN_6_S 13 +/** RMT_AFIFO_RST_6 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_6 (BIT(14)) +#define RMT_AFIFO_RST_6_M (RMT_AFIFO_RST_6_V << RMT_AFIFO_RST_6_S) +#define RMT_AFIFO_RST_6_V 0x00000001 +#define RMT_AFIFO_RST_6_S 14 +/** RMT_CONF_UPDATE_6 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL6 + */ +#define RMT_CONF_UPDATE_6 (BIT(15)) +#define RMT_CONF_UPDATE_6_M (RMT_CONF_UPDATE_6_V << RMT_CONF_UPDATE_6_S) +#define RMT_CONF_UPDATE_6_V 0x00000001 +#define RMT_CONF_UPDATE_6_S 15 -#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0044) -/* RMT_CONF_UPDATE_CH6 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH6 (BIT(15)) -#define RMT_CONF_UPDATE_CH6_M (BIT(15)) -#define RMT_CONF_UPDATE_CH6_V 0x1 -#define RMT_CONF_UPDATE_CH6_S 15 -/* RMT_AFIFO_RST_CH6 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH6 (BIT(14)) -#define RMT_AFIFO_RST_CH6_M (BIT(14)) -#define RMT_AFIFO_RST_CH6_V 0x1 -#define RMT_AFIFO_RST_CH6_S 14 -/* RMT_MEM_RX_WRAP_EN_CH6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH6_S 13 -/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH6 0x000000FF -#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V) << (RMT_RX_FILTER_THRES_CH6_S)) -#define RMT_RX_FILTER_THRES_CH6_V 0xFF -#define RMT_RX_FILTER_THRES_CH6_S 5 -/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH6 (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_V 0x1 -#define RMT_RX_FILTER_EN_CH6_S 4 -/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH6 (BIT(3)) -#define RMT_MEM_OWNER_CH6_M (BIT(3)) -#define RMT_MEM_OWNER_CH6_V 0x1 -#define RMT_MEM_OWNER_CH6_S 3 -/* RMT_APB_MEM_RST_CH6 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH6 (BIT(2)) -#define RMT_APB_MEM_RST_CH6_M (BIT(2)) -#define RMT_APB_MEM_RST_CH6_V 0x1 -#define RMT_APB_MEM_RST_CH6_S 2 -/* RMT_MEM_WR_RST_CH6 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH6 (BIT(1)) -#define RMT_MEM_WR_RST_CH6_M (BIT(1)) -#define RMT_MEM_WR_RST_CH6_V 0x1 -#define RMT_MEM_WR_RST_CH6_S 1 -/* RMT_RX_EN_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH6 (BIT(0)) -#define RMT_RX_EN_CH6_M (BIT(0)) -#define RMT_RX_EN_CH6_V 0x1 -#define RMT_RX_EN_CH6_S 0 +/** RMT_CH7CONF0_REG register + * Channel 7 configure register 0 + */ +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_DIV_CNT_7 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL7. + */ +#define RMT_DIV_CNT_7 0x000000FF +#define RMT_DIV_CNT_7_M (RMT_DIV_CNT_7_V << RMT_DIV_CNT_7_S) +#define RMT_DIV_CNT_7_V 0x000000FF +#define RMT_DIV_CNT_7_S 0 +/** RMT_IDLE_THRES_7 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_7 0x00007FFF +#define RMT_IDLE_THRES_7_M (RMT_IDLE_THRES_7_V << RMT_IDLE_THRES_7_S) +#define RMT_IDLE_THRES_7_V 0x00007FFF +#define RMT_IDLE_THRES_7_S 8 +/** RMT_MEM_SIZE_7 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL7. + */ +#define RMT_MEM_SIZE_7 0x0000000F +#define RMT_MEM_SIZE_7_M (RMT_MEM_SIZE_7_V << RMT_MEM_SIZE_7_S) +#define RMT_MEM_SIZE_7_V 0x0000000F +#define RMT_MEM_SIZE_7_S 24 +/** RMT_CARRIER_EN_7 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL7. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_7 (BIT(28)) +#define RMT_CARRIER_EN_7_M (RMT_CARRIER_EN_7_V << RMT_CARRIER_EN_7_S) +#define RMT_CARRIER_EN_7_V 0x00000001 +#define RMT_CARRIER_EN_7_S 28 +/** RMT_CARRIER_OUT_LV_7 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL7. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_7_M (RMT_CARRIER_OUT_LV_7_V << RMT_CARRIER_OUT_LV_7_S) +#define RMT_CARRIER_OUT_LV_7_V 0x00000001 +#define RMT_CARRIER_OUT_LV_7_S 29 -#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0048) -/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_V 0x1 -#define RMT_CARRIER_OUT_LV_CH7_S 29 -/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH7 (BIT(28)) -#define RMT_CARRIER_EN_CH7_M (BIT(28)) -#define RMT_CARRIER_EN_CH7_V 0x1 -#define RMT_CARRIER_EN_CH7_S 28 -/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH7 0x0000000F -#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V) << (RMT_MEM_SIZE_CH7_S)) -#define RMT_MEM_SIZE_CH7_V 0xF -#define RMT_MEM_SIZE_CH7_S 24 -/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH7 0x00007FFF -#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V) << (RMT_IDLE_THRES_CH7_S)) -#define RMT_IDLE_THRES_CH7_V 0x7FFF -#define RMT_IDLE_THRES_CH7_S 8 -/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH7 0x000000FF -#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V) << (RMT_DIV_CNT_CH7_S)) -#define RMT_DIV_CNT_CH7_V 0xFF -#define RMT_DIV_CNT_CH7_S 0 +/** RMT_CH7CONF1_REG register + * Channel 7 configure register 1 + */ +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_RX_EN_7 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL7. + */ +#define RMT_RX_EN_7 (BIT(0)) +#define RMT_RX_EN_7_M (RMT_RX_EN_7_V << RMT_RX_EN_7_S) +#define RMT_RX_EN_7_V 0x00000001 +#define RMT_RX_EN_7_S 0 +/** RMT_MEM_WR_RST_7 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL7 by accessing receiver. + */ +#define RMT_MEM_WR_RST_7 (BIT(1)) +#define RMT_MEM_WR_RST_7_M (RMT_MEM_WR_RST_7_V << RMT_MEM_WR_RST_7_S) +#define RMT_MEM_WR_RST_7_V 0x00000001 +#define RMT_MEM_WR_RST_7_S 1 +/** RMT_APB_MEM_RST_7 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL7 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_7 (BIT(2)) +#define RMT_APB_MEM_RST_7_M (RMT_APB_MEM_RST_7_V << RMT_APB_MEM_RST_7_S) +#define RMT_APB_MEM_RST_7_V 0x00000001 +#define RMT_APB_MEM_RST_7_S 2 +/** RMT_MEM_OWNER_7 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL7's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_7 (BIT(3)) +#define RMT_MEM_OWNER_7_M (RMT_MEM_OWNER_7_V << RMT_MEM_OWNER_7_S) +#define RMT_MEM_OWNER_7_V 0x00000001 +#define RMT_MEM_OWNER_7_S 3 +/** RMT_RX_FILTER_EN_7 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL7. + */ +#define RMT_RX_FILTER_EN_7 (BIT(4)) +#define RMT_RX_FILTER_EN_7_M (RMT_RX_FILTER_EN_7_V << RMT_RX_FILTER_EN_7_S) +#define RMT_RX_FILTER_EN_7_V 0x00000001 +#define RMT_RX_FILTER_EN_7_S 4 +/** RMT_RX_FILTER_THRES_7 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_7 0x000000FF +#define RMT_RX_FILTER_THRES_7_M (RMT_RX_FILTER_THRES_7_V << RMT_RX_FILTER_THRES_7_S) +#define RMT_RX_FILTER_THRES_7_V 0x000000FF +#define RMT_RX_FILTER_THRES_7_S 5 +/** RMT_MEM_RX_WRAP_EN_7 : R/W; bitpos: [13]; default: 0; + * This is the channel 7 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_7_M (RMT_MEM_RX_WRAP_EN_7_V << RMT_MEM_RX_WRAP_EN_7_S) +#define RMT_MEM_RX_WRAP_EN_7_V 0x00000001 +#define RMT_MEM_RX_WRAP_EN_7_S 13 +/** RMT_AFIFO_RST_7 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_7 (BIT(14)) +#define RMT_AFIFO_RST_7_M (RMT_AFIFO_RST_7_V << RMT_AFIFO_RST_7_S) +#define RMT_AFIFO_RST_7_V 0x00000001 +#define RMT_AFIFO_RST_7_S 14 +/** RMT_CONF_UPDATE_7 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL7 + */ +#define RMT_CONF_UPDATE_7 (BIT(15)) +#define RMT_CONF_UPDATE_7_M (RMT_CONF_UPDATE_7_V << RMT_CONF_UPDATE_7_S) +#define RMT_CONF_UPDATE_7_V 0x00000001 +#define RMT_CONF_UPDATE_7_S 15 -#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x004c) -/* RMT_CONF_UPDATE_CH7 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH7 (BIT(15)) -#define RMT_CONF_UPDATE_CH7_M (BIT(15)) -#define RMT_CONF_UPDATE_CH7_V 0x1 -#define RMT_CONF_UPDATE_CH7_S 15 -/* RMT_AFIFO_RST_CH7 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH7 (BIT(14)) -#define RMT_AFIFO_RST_CH7_M (BIT(14)) -#define RMT_AFIFO_RST_CH7_V 0x1 -#define RMT_AFIFO_RST_CH7_S 14 -/* RMT_MEM_RX_WRAP_EN_CH7 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH7_S 13 -/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH7 0x000000FF -#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V) << (RMT_RX_FILTER_THRES_CH7_S)) -#define RMT_RX_FILTER_THRES_CH7_V 0xFF -#define RMT_RX_FILTER_THRES_CH7_S 5 -/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH7 (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_V 0x1 -#define RMT_RX_FILTER_EN_CH7_S 4 -/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH7 (BIT(3)) -#define RMT_MEM_OWNER_CH7_M (BIT(3)) -#define RMT_MEM_OWNER_CH7_V 0x1 -#define RMT_MEM_OWNER_CH7_S 3 -/* RMT_APB_MEM_RST_CH7 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH7 (BIT(2)) -#define RMT_APB_MEM_RST_CH7_M (BIT(2)) -#define RMT_APB_MEM_RST_CH7_V 0x1 -#define RMT_APB_MEM_RST_CH7_S 2 -/* RMT_MEM_WR_RST_CH7 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH7 (BIT(1)) -#define RMT_MEM_WR_RST_CH7_M (BIT(1)) -#define RMT_MEM_WR_RST_CH7_V 0x1 -#define RMT_MEM_WR_RST_CH7_S 1 -/* RMT_RX_EN_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH7 (BIT(0)) -#define RMT_RX_EN_CH7_M (BIT(0)) -#define RMT_RX_EN_CH7_V 0x1 -#define RMT_RX_EN_CH7_S 0 +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_MEM_RADDR_EX_0 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_0 0x000003FF +#define RMT_MEM_RADDR_EX_0_M (RMT_MEM_RADDR_EX_0_V << RMT_MEM_RADDR_EX_0_S) +#define RMT_MEM_RADDR_EX_0_V 0x000003FF +#define RMT_MEM_RADDR_EX_0_S 0 +/** RMT_APB_MEM_WADDR_0 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_0 0x000003FF +#define RMT_APB_MEM_WADDR_0_M (RMT_APB_MEM_WADDR_0_V << RMT_APB_MEM_WADDR_0_S) +#define RMT_APB_MEM_WADDR_0_V 0x000003FF +#define RMT_APB_MEM_WADDR_0_S 11 +/** RMT_STATE_0 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_0 0x00000007 +#define RMT_STATE_0_M (RMT_STATE_0_V << RMT_STATE_0_S) +#define RMT_STATE_0_V 0x00000007 +#define RMT_STATE_0_S 22 +/** RMT_MEM_EMPTY_0 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_0 (BIT(25)) +#define RMT_MEM_EMPTY_0_M (RMT_MEM_EMPTY_0_V << RMT_MEM_EMPTY_0_S) +#define RMT_MEM_EMPTY_0_V 0x00000001 +#define RMT_MEM_EMPTY_0_S 25 +/** RMT_APB_MEM_WR_ERR_0 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_0_M (RMT_APB_MEM_WR_ERR_0_V << RMT_APB_MEM_WR_ERR_0_S) +#define RMT_APB_MEM_WR_ERR_0_V 0x00000001 +#define RMT_APB_MEM_WR_ERR_0_S 26 -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0050) -/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH0_S 26 -/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (BIT(25)) -#define RMT_MEM_EMPTY_CH0_V 0x1 -#define RMT_MEM_EMPTY_CH0_S 25 -/* RMT_STATE_CH0 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH0 0x00000007 -#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V) << (RMT_STATE_CH0_S)) -#define RMT_STATE_CH0_V 0x7 -#define RMT_STATE_CH0_S 22 -/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:11] ;default: 10'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH0 0x000003FF -#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V) << (RMT_APB_MEM_WADDR_CH0_S)) -#define RMT_APB_MEM_WADDR_CH0_V 0x3FF -#define RMT_APB_MEM_WADDR_CH0_S 11 -/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH0 0x000003FF -#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V) << (RMT_MEM_RADDR_EX_CH0_S)) -#define RMT_MEM_RADDR_EX_CH0_V 0x3FF -#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_MEM_RADDR_EX_1 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_1 0x000003FF +#define RMT_MEM_RADDR_EX_1_M (RMT_MEM_RADDR_EX_1_V << RMT_MEM_RADDR_EX_1_S) +#define RMT_MEM_RADDR_EX_1_V 0x000003FF +#define RMT_MEM_RADDR_EX_1_S 0 +/** RMT_APB_MEM_WADDR_1 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_1 0x000003FF +#define RMT_APB_MEM_WADDR_1_M (RMT_APB_MEM_WADDR_1_V << RMT_APB_MEM_WADDR_1_S) +#define RMT_APB_MEM_WADDR_1_V 0x000003FF +#define RMT_APB_MEM_WADDR_1_S 11 +/** RMT_STATE_1 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_1 0x00000007 +#define RMT_STATE_1_M (RMT_STATE_1_V << RMT_STATE_1_S) +#define RMT_STATE_1_V 0x00000007 +#define RMT_STATE_1_S 22 +/** RMT_MEM_EMPTY_1 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_1 (BIT(25)) +#define RMT_MEM_EMPTY_1_M (RMT_MEM_EMPTY_1_V << RMT_MEM_EMPTY_1_S) +#define RMT_MEM_EMPTY_1_V 0x00000001 +#define RMT_MEM_EMPTY_1_S 25 +/** RMT_APB_MEM_WR_ERR_1 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_1_M (RMT_APB_MEM_WR_ERR_1_V << RMT_APB_MEM_WR_ERR_1_S) +#define RMT_APB_MEM_WR_ERR_1_V 0x00000001 +#define RMT_APB_MEM_WR_ERR_1_S 26 -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0054) -/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH1_S 26 -/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH1 (BIT(25)) -#define RMT_MEM_EMPTY_CH1_M (BIT(25)) -#define RMT_MEM_EMPTY_CH1_V 0x1 -#define RMT_MEM_EMPTY_CH1_S 25 -/* RMT_STATE_CH1 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH1 0x00000007 -#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V) << (RMT_STATE_CH1_S)) -#define RMT_STATE_CH1_V 0x7 -#define RMT_STATE_CH1_S 22 -/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:11] ;default: 10'h30 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH1 0x000003FF -#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V) << (RMT_APB_MEM_WADDR_CH1_S)) -#define RMT_APB_MEM_WADDR_CH1_V 0x3FF -#define RMT_APB_MEM_WADDR_CH1_S 11 -/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h30 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH1 0x000003FF -#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V) << (RMT_MEM_RADDR_EX_CH1_S)) -#define RMT_MEM_RADDR_EX_CH1_V 0x3FF -#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_MEM_RADDR_EX_2 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL2 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_2 0x000003FF +#define RMT_MEM_RADDR_EX_2_M (RMT_MEM_RADDR_EX_2_V << RMT_MEM_RADDR_EX_2_S) +#define RMT_MEM_RADDR_EX_2_V 0x000003FF +#define RMT_MEM_RADDR_EX_2_S 0 +/** RMT_APB_MEM_WADDR_2 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_2 0x000003FF +#define RMT_APB_MEM_WADDR_2_M (RMT_APB_MEM_WADDR_2_V << RMT_APB_MEM_WADDR_2_S) +#define RMT_APB_MEM_WADDR_2_V 0x000003FF +#define RMT_APB_MEM_WADDR_2_S 11 +/** RMT_STATE_2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_2 0x00000007 +#define RMT_STATE_2_M (RMT_STATE_2_V << RMT_STATE_2_S) +#define RMT_STATE_2_V 0x00000007 +#define RMT_STATE_2_S 22 +/** RMT_MEM_EMPTY_2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_2 (BIT(25)) +#define RMT_MEM_EMPTY_2_M (RMT_MEM_EMPTY_2_V << RMT_MEM_EMPTY_2_S) +#define RMT_MEM_EMPTY_2_V 0x00000001 +#define RMT_MEM_EMPTY_2_S 25 +/** RMT_APB_MEM_WR_ERR_2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_2_M (RMT_APB_MEM_WR_ERR_2_V << RMT_APB_MEM_WR_ERR_2_S) +#define RMT_APB_MEM_WR_ERR_2_V 0x00000001 +#define RMT_APB_MEM_WR_ERR_2_S 26 -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0058) -/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH2_S 26 -/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH2 (BIT(25)) -#define RMT_MEM_EMPTY_CH2_M (BIT(25)) -#define RMT_MEM_EMPTY_CH2_V 0x1 -#define RMT_MEM_EMPTY_CH2_S 25 -/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH2 0x00000007 -#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V) << (RMT_STATE_CH2_S)) -#define RMT_STATE_CH2_V 0x7 -#define RMT_STATE_CH2_S 22 -/* RMT_APB_MEM_WADDR_CH2 : RO ;bitpos:[20:11] ;default: 10'h60 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH2 0x000003FF -#define RMT_APB_MEM_WADDR_CH2_M ((RMT_APB_MEM_WADDR_CH2_V) << (RMT_APB_MEM_WADDR_CH2_S)) -#define RMT_APB_MEM_WADDR_CH2_V 0x3FF -#define RMT_APB_MEM_WADDR_CH2_S 11 -/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h60 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH2 0x000003FF -#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V) << (RMT_MEM_RADDR_EX_CH2_S)) -#define RMT_MEM_RADDR_EX_CH2_V 0x3FF -#define RMT_MEM_RADDR_EX_CH2_S 0 +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_MEM_RADDR_EX_3 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL3 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_3 0x000003FF +#define RMT_MEM_RADDR_EX_3_M (RMT_MEM_RADDR_EX_3_V << RMT_MEM_RADDR_EX_3_S) +#define RMT_MEM_RADDR_EX_3_V 0x000003FF +#define RMT_MEM_RADDR_EX_3_S 0 +/** RMT_APB_MEM_WADDR_3 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_3 0x000003FF +#define RMT_APB_MEM_WADDR_3_M (RMT_APB_MEM_WADDR_3_V << RMT_APB_MEM_WADDR_3_S) +#define RMT_APB_MEM_WADDR_3_V 0x000003FF +#define RMT_APB_MEM_WADDR_3_S 11 +/** RMT_STATE_3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_3 0x00000007 +#define RMT_STATE_3_M (RMT_STATE_3_V << RMT_STATE_3_S) +#define RMT_STATE_3_V 0x00000007 +#define RMT_STATE_3_S 22 +/** RMT_MEM_EMPTY_3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_3 (BIT(25)) +#define RMT_MEM_EMPTY_3_M (RMT_MEM_EMPTY_3_V << RMT_MEM_EMPTY_3_S) +#define RMT_MEM_EMPTY_3_V 0x00000001 +#define RMT_MEM_EMPTY_3_S 25 +/** RMT_APB_MEM_WR_ERR_3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_3_M (RMT_APB_MEM_WR_ERR_3_V << RMT_APB_MEM_WR_ERR_3_S) +#define RMT_APB_MEM_WR_ERR_3_V 0x00000001 +#define RMT_APB_MEM_WR_ERR_3_S 26 -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x005c) -/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH3_S 26 -/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH3 (BIT(25)) -#define RMT_MEM_EMPTY_CH3_M (BIT(25)) -#define RMT_MEM_EMPTY_CH3_V 0x1 -#define RMT_MEM_EMPTY_CH3_S 25 -/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH3 0x00000007 -#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V) << (RMT_STATE_CH3_S)) -#define RMT_STATE_CH3_V 0x7 -#define RMT_STATE_CH3_S 22 -/* RMT_APB_MEM_WADDR_CH3 : RO ;bitpos:[20:11] ;default: 10'h90 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH3 0x000003FF -#define RMT_APB_MEM_WADDR_CH3_M ((RMT_APB_MEM_WADDR_CH3_V) << (RMT_APB_MEM_WADDR_CH3_S)) -#define RMT_APB_MEM_WADDR_CH3_V 0x3FF -#define RMT_APB_MEM_WADDR_CH3_S 11 -/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h90 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH3 0x000003FF -#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V) << (RMT_MEM_RADDR_EX_CH3_S)) -#define RMT_MEM_RADDR_EX_CH3_V 0x3FF -#define RMT_MEM_RADDR_EX_CH3_S 0 +/** RMT_CH4STATUS_REG register + * Channel 4 status register + */ +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_MEM_WADDR_EX_4 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL4 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_4 0x000003FF +#define RMT_MEM_WADDR_EX_4_M (RMT_MEM_WADDR_EX_4_V << RMT_MEM_WADDR_EX_4_S) +#define RMT_MEM_WADDR_EX_4_V 0x000003FF +#define RMT_MEM_WADDR_EX_4_S 0 +/** RMT_APB_MEM_RADDR_4 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_4 0x000003FF +#define RMT_APB_MEM_RADDR_4_M (RMT_APB_MEM_RADDR_4_V << RMT_APB_MEM_RADDR_4_S) +#define RMT_APB_MEM_RADDR_4_V 0x000003FF +#define RMT_APB_MEM_RADDR_4_S 11 +/** RMT_STATE_4 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL4. + */ +#define RMT_STATE_4 0x00000007 +#define RMT_STATE_4_M (RMT_STATE_4_V << RMT_STATE_4_S) +#define RMT_STATE_4_V 0x00000007 +#define RMT_STATE_4_S 22 +/** RMT_MEM_OWNER_ERR_4 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_4_M (RMT_MEM_OWNER_ERR_4_V << RMT_MEM_OWNER_ERR_4_S) +#define RMT_MEM_OWNER_ERR_4_V 0x00000001 +#define RMT_MEM_OWNER_ERR_4_S 25 +/** RMT_MEM_FULL_4 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_4 (BIT(26)) +#define RMT_MEM_FULL_4_M (RMT_MEM_FULL_4_V << RMT_MEM_FULL_4_S) +#define RMT_MEM_FULL_4_V 0x00000001 +#define RMT_MEM_FULL_4_S 26 +/** RMT_APB_MEM_RD_ERR_4 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_4_M (RMT_APB_MEM_RD_ERR_4_V << RMT_APB_MEM_RD_ERR_4_S) +#define RMT_APB_MEM_RD_ERR_4_V 0x00000001 +#define RMT_APB_MEM_RD_ERR_4_S 27 -#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0060) -/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH4_S 27 -/* RMT_MEM_FULL_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH4 (BIT(26)) -#define RMT_MEM_FULL_CH4_M (BIT(26)) -#define RMT_MEM_FULL_CH4_V 0x1 -#define RMT_MEM_FULL_CH4_S 26 -/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_V 0x1 -#define RMT_MEM_OWNER_ERR_CH4_S 25 -/* RMT_STATE_CH4 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH4 0x00000007 -#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V) << (RMT_STATE_CH4_S)) -#define RMT_STATE_CH4_V 0x7 -#define RMT_STATE_CH4_S 22 -/* RMT_APB_MEM_RADDR_CH4 : RO ;bitpos:[20:11] ;default: 10'hc0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH4 0x000003FF -#define RMT_APB_MEM_RADDR_CH4_M ((RMT_APB_MEM_RADDR_CH4_V) << (RMT_APB_MEM_RADDR_CH4_S)) -#define RMT_APB_MEM_RADDR_CH4_V 0x3FF -#define RMT_APB_MEM_RADDR_CH4_S 11 -/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'hc0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH4 0x000003FF -#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V) << (RMT_MEM_WADDR_EX_CH4_S)) -#define RMT_MEM_WADDR_EX_CH4_V 0x3FF -#define RMT_MEM_WADDR_EX_CH4_S 0 +/** RMT_CH5STATUS_REG register + * Channel 5 status register + */ +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_MEM_WADDR_EX_5 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL5 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_5 0x000003FF +#define RMT_MEM_WADDR_EX_5_M (RMT_MEM_WADDR_EX_5_V << RMT_MEM_WADDR_EX_5_S) +#define RMT_MEM_WADDR_EX_5_V 0x000003FF +#define RMT_MEM_WADDR_EX_5_S 0 +/** RMT_APB_MEM_RADDR_5 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_5 0x000003FF +#define RMT_APB_MEM_RADDR_5_M (RMT_APB_MEM_RADDR_5_V << RMT_APB_MEM_RADDR_5_S) +#define RMT_APB_MEM_RADDR_5_V 0x000003FF +#define RMT_APB_MEM_RADDR_5_S 11 +/** RMT_STATE_5 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL5. + */ +#define RMT_STATE_5 0x00000007 +#define RMT_STATE_5_M (RMT_STATE_5_V << RMT_STATE_5_S) +#define RMT_STATE_5_V 0x00000007 +#define RMT_STATE_5_S 22 +/** RMT_MEM_OWNER_ERR_5 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_5_M (RMT_MEM_OWNER_ERR_5_V << RMT_MEM_OWNER_ERR_5_S) +#define RMT_MEM_OWNER_ERR_5_V 0x00000001 +#define RMT_MEM_OWNER_ERR_5_S 25 +/** RMT_MEM_FULL_5 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_5 (BIT(26)) +#define RMT_MEM_FULL_5_M (RMT_MEM_FULL_5_V << RMT_MEM_FULL_5_S) +#define RMT_MEM_FULL_5_V 0x00000001 +#define RMT_MEM_FULL_5_S 26 +/** RMT_APB_MEM_RD_ERR_5 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_5_M (RMT_APB_MEM_RD_ERR_5_V << RMT_APB_MEM_RD_ERR_5_S) +#define RMT_APB_MEM_RD_ERR_5_V 0x00000001 +#define RMT_APB_MEM_RD_ERR_5_S 27 -#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0064) -/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH5_S 27 -/* RMT_MEM_FULL_CH5 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH5 (BIT(26)) -#define RMT_MEM_FULL_CH5_M (BIT(26)) -#define RMT_MEM_FULL_CH5_V 0x1 -#define RMT_MEM_FULL_CH5_S 26 -/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_V 0x1 -#define RMT_MEM_OWNER_ERR_CH5_S 25 -/* RMT_STATE_CH5 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH5 0x00000007 -#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V) << (RMT_STATE_CH5_S)) -#define RMT_STATE_CH5_V 0x7 -#define RMT_STATE_CH5_S 22 -/* RMT_APB_MEM_RADDR_CH5 : RO ;bitpos:[20:11] ;default: 10'hf0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH5 0x000003FF -#define RMT_APB_MEM_RADDR_CH5_M ((RMT_APB_MEM_RADDR_CH5_V) << (RMT_APB_MEM_RADDR_CH5_S)) -#define RMT_APB_MEM_RADDR_CH5_V 0x3FF -#define RMT_APB_MEM_RADDR_CH5_S 11 -/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH5 0x000003FF -#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V) << (RMT_MEM_WADDR_EX_CH5_S)) -#define RMT_MEM_WADDR_EX_CH5_V 0x3FF -#define RMT_MEM_WADDR_EX_CH5_S 0 +/** RMT_CH6STATUS_REG register + * Channel 6 status register + */ +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_MEM_WADDR_EX_6 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL6 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_6 0x000003FF +#define RMT_MEM_WADDR_EX_6_M (RMT_MEM_WADDR_EX_6_V << RMT_MEM_WADDR_EX_6_S) +#define RMT_MEM_WADDR_EX_6_V 0x000003FF +#define RMT_MEM_WADDR_EX_6_S 0 +/** RMT_APB_MEM_RADDR_6 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_6 0x000003FF +#define RMT_APB_MEM_RADDR_6_M (RMT_APB_MEM_RADDR_6_V << RMT_APB_MEM_RADDR_6_S) +#define RMT_APB_MEM_RADDR_6_V 0x000003FF +#define RMT_APB_MEM_RADDR_6_S 11 +/** RMT_STATE_6 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL6. + */ +#define RMT_STATE_6 0x00000007 +#define RMT_STATE_6_M (RMT_STATE_6_V << RMT_STATE_6_S) +#define RMT_STATE_6_V 0x00000007 +#define RMT_STATE_6_S 22 +/** RMT_MEM_OWNER_ERR_6 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_6_M (RMT_MEM_OWNER_ERR_6_V << RMT_MEM_OWNER_ERR_6_S) +#define RMT_MEM_OWNER_ERR_6_V 0x00000001 +#define RMT_MEM_OWNER_ERR_6_S 25 +/** RMT_MEM_FULL_6 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_6 (BIT(26)) +#define RMT_MEM_FULL_6_M (RMT_MEM_FULL_6_V << RMT_MEM_FULL_6_S) +#define RMT_MEM_FULL_6_V 0x00000001 +#define RMT_MEM_FULL_6_S 26 +/** RMT_APB_MEM_RD_ERR_6 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_6_M (RMT_APB_MEM_RD_ERR_6_V << RMT_APB_MEM_RD_ERR_6_S) +#define RMT_APB_MEM_RD_ERR_6_V 0x00000001 +#define RMT_APB_MEM_RD_ERR_6_S 27 -#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0068) -/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH6_S 27 -/* RMT_MEM_FULL_CH6 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH6 (BIT(26)) -#define RMT_MEM_FULL_CH6_M (BIT(26)) -#define RMT_MEM_FULL_CH6_V 0x1 -#define RMT_MEM_FULL_CH6_S 26 -/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_V 0x1 -#define RMT_MEM_OWNER_ERR_CH6_S 25 -/* RMT_STATE_CH6 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH6 0x00000007 -#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V) << (RMT_STATE_CH6_S)) -#define RMT_STATE_CH6_V 0x7 -#define RMT_STATE_CH6_S 22 -/* RMT_APB_MEM_RADDR_CH6 : RO ;bitpos:[20:11] ;default: 10'h120 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH6 0x000003FF -#define RMT_APB_MEM_RADDR_CH6_M ((RMT_APB_MEM_RADDR_CH6_V) << (RMT_APB_MEM_RADDR_CH6_S)) -#define RMT_APB_MEM_RADDR_CH6_V 0x3FF -#define RMT_APB_MEM_RADDR_CH6_S 11 -/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h120 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH6 0x000003FF -#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V) << (RMT_MEM_WADDR_EX_CH6_S)) -#define RMT_MEM_WADDR_EX_CH6_V 0x3FF -#define RMT_MEM_WADDR_EX_CH6_S 0 +/** RMT_CH7STATUS_REG register + * Channel 7 status register + */ +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_MEM_WADDR_EX_7 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL7 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_7 0x000003FF +#define RMT_MEM_WADDR_EX_7_M (RMT_MEM_WADDR_EX_7_V << RMT_MEM_WADDR_EX_7_S) +#define RMT_MEM_WADDR_EX_7_V 0x000003FF +#define RMT_MEM_WADDR_EX_7_S 0 +/** RMT_APB_MEM_RADDR_7 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_7 0x000003FF +#define RMT_APB_MEM_RADDR_7_M (RMT_APB_MEM_RADDR_7_V << RMT_APB_MEM_RADDR_7_S) +#define RMT_APB_MEM_RADDR_7_V 0x000003FF +#define RMT_APB_MEM_RADDR_7_S 11 +/** RMT_STATE_7 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL7. + */ +#define RMT_STATE_7 0x00000007 +#define RMT_STATE_7_M (RMT_STATE_7_V << RMT_STATE_7_S) +#define RMT_STATE_7_V 0x00000007 +#define RMT_STATE_7_S 22 +/** RMT_MEM_OWNER_ERR_7 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_7_M (RMT_MEM_OWNER_ERR_7_V << RMT_MEM_OWNER_ERR_7_S) +#define RMT_MEM_OWNER_ERR_7_V 0x00000001 +#define RMT_MEM_OWNER_ERR_7_S 25 +/** RMT_MEM_FULL_7 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_7 (BIT(26)) +#define RMT_MEM_FULL_7_M (RMT_MEM_FULL_7_V << RMT_MEM_FULL_7_S) +#define RMT_MEM_FULL_7_V 0x00000001 +#define RMT_MEM_FULL_7_S 26 +/** RMT_APB_MEM_RD_ERR_7 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_7_M (RMT_APB_MEM_RD_ERR_7_V << RMT_APB_MEM_RD_ERR_7_S) +#define RMT_APB_MEM_RD_ERR_7_V 0x00000001 +#define RMT_APB_MEM_RD_ERR_7_S 27 -#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x006c) -/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH7_S 27 -/* RMT_MEM_FULL_CH7 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH7 (BIT(26)) -#define RMT_MEM_FULL_CH7_M (BIT(26)) -#define RMT_MEM_FULL_CH7_V 0x1 -#define RMT_MEM_FULL_CH7_S 26 -/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_V 0x1 -#define RMT_MEM_OWNER_ERR_CH7_S 25 -/* RMT_STATE_CH7 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH7 0x00000007 -#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V) << (RMT_STATE_CH7_S)) -#define RMT_STATE_CH7_V 0x7 -#define RMT_STATE_CH7_S 22 -/* RMT_APB_MEM_RADDR_CH7 : RO ;bitpos:[20:11] ;default: 10'h150 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH7 0x000003FF -#define RMT_APB_MEM_RADDR_CH7_M ((RMT_APB_MEM_RADDR_CH7_V) << (RMT_APB_MEM_RADDR_CH7_S)) -#define RMT_APB_MEM_RADDR_CH7_V 0x3FF -#define RMT_APB_MEM_RADDR_CH7_S 11 -/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h150 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH7 0x000003FF -#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V) << (RMT_MEM_WADDR_EX_CH7_S)) -#define RMT_MEM_WADDR_EX_CH7_V 0x3FF -#define RMT_MEM_WADDR_EX_CH7_S 0 +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001 +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001 +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_TX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ +#define RMT_CH2_TX_END_INT_RAW (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_M (RMT_CH2_TX_END_INT_RAW_V << RMT_CH2_TX_END_INT_RAW_S) +#define RMT_CH2_TX_END_INT_RAW_V 0x00000001 +#define RMT_CH2_TX_END_INT_RAW_S 2 +/** RMT_CH3_TX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ +#define RMT_CH3_TX_END_INT_RAW (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_M (RMT_CH3_TX_END_INT_RAW_V << RMT_CH3_TX_END_INT_RAW_S) +#define RMT_CH3_TX_END_INT_RAW_V 0x00000001 +#define RMT_CH3_TX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001 +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001 +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001 +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001 +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (RMT_CH2_TX_THR_EVENT_INT_RAW_V << RMT_CH2_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (RMT_CH3_TX_THR_EVENT_INT_RAW_V << RMT_CH3_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001 +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001 +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/** RMT_CH2_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_M (RMT_CH2_TX_LOOP_INT_RAW_V << RMT_CH2_TX_LOOP_INT_RAW_S) +#define RMT_CH2_TX_LOOP_INT_RAW_V 0x00000001 +#define RMT_CH2_TX_LOOP_INT_RAW_S 14 +/** RMT_CH3_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_M (RMT_CH3_TX_LOOP_INT_RAW_V << RMT_CH3_TX_LOOP_INT_RAW_S) +#define RMT_CH3_TX_LOOP_INT_RAW_V 0x00000001 +#define RMT_CH3_TX_LOOP_INT_RAW_S 15 +/** RMT_CH4_RX_END_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ +#define RMT_CH4_RX_END_INT_RAW (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_M (RMT_CH4_RX_END_INT_RAW_V << RMT_CH4_RX_END_INT_RAW_S) +#define RMT_CH4_RX_END_INT_RAW_V 0x00000001 +#define RMT_CH4_RX_END_INT_RAW_S 16 +/** RMT_CH5_RX_END_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ +#define RMT_CH5_RX_END_INT_RAW (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_M (RMT_CH5_RX_END_INT_RAW_V << RMT_CH5_RX_END_INT_RAW_S) +#define RMT_CH5_RX_END_INT_RAW_V 0x00000001 +#define RMT_CH5_RX_END_INT_RAW_S 17 +/** RMT_CH6_RX_END_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ +#define RMT_CH6_RX_END_INT_RAW (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_M (RMT_CH6_RX_END_INT_RAW_V << RMT_CH6_RX_END_INT_RAW_S) +#define RMT_CH6_RX_END_INT_RAW_V 0x00000001 +#define RMT_CH6_RX_END_INT_RAW_S 18 +/** RMT_CH7_RX_END_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ +#define RMT_CH7_RX_END_INT_RAW (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_M (RMT_CH7_RX_END_INT_RAW_V << RMT_CH7_RX_END_INT_RAW_S) +#define RMT_CH7_RX_END_INT_RAW_V 0x00000001 +#define RMT_CH7_RX_END_INT_RAW_S 19 +/** RMT_CH4_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ +#define RMT_CH4_ERR_INT_RAW (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_M (RMT_CH4_ERR_INT_RAW_V << RMT_CH4_ERR_INT_RAW_S) +#define RMT_CH4_ERR_INT_RAW_V 0x00000001 +#define RMT_CH4_ERR_INT_RAW_S 20 +/** RMT_CH5_ERR_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ +#define RMT_CH5_ERR_INT_RAW (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_M (RMT_CH5_ERR_INT_RAW_V << RMT_CH5_ERR_INT_RAW_S) +#define RMT_CH5_ERR_INT_RAW_V 0x00000001 +#define RMT_CH5_ERR_INT_RAW_S 21 +/** RMT_CH6_ERR_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ +#define RMT_CH6_ERR_INT_RAW (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_M (RMT_CH6_ERR_INT_RAW_V << RMT_CH6_ERR_INT_RAW_S) +#define RMT_CH6_ERR_INT_RAW_V 0x00000001 +#define RMT_CH6_ERR_INT_RAW_S 22 +/** RMT_CH7_ERR_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (RMT_CH7_ERR_INT_RAW_V << RMT_CH7_ERR_INT_RAW_S) +#define RMT_CH7_ERR_INT_RAW_V 0x00000001 +#define RMT_CH7_ERR_INT_RAW_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (RMT_CH4_RX_THR_EVENT_INT_RAW_V << RMT_CH4_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (RMT_CH5_RX_THR_EVENT_INT_RAW_V << RMT_CH5_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (RMT_CH6_RX_THR_EVENT_INT_RAW_V << RMT_CH6_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (RMT_CH7_RX_THR_EVENT_INT_RAW_V << RMT_CH7_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x00000001 +#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0070) -/* RMT_CH7_RX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 -/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_RAW (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_V 0x1 -#define RMT_CH7_ERR_INT_RAW_S 23 -/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_RAW (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_M (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_V 0x1 -#define RMT_CH6_ERR_INT_RAW_S 22 -/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_RAW (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_M (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_V 0x1 -#define RMT_CH5_ERR_INT_RAW_S 21 -/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_RAW (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_M (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_V 0x1 -#define RMT_CH4_ERR_INT_RAW_S 20 -/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_RAW (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_M (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_V 0x1 -#define RMT_CH7_RX_END_INT_RAW_S 19 -/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_RAW (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_M (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_V 0x1 -#define RMT_CH6_RX_END_INT_RAW_S 18 -/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_RAW (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_M (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_V 0x1 -#define RMT_CH5_RX_END_INT_RAW_S 17 -/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_RAW (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_M (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_V 0x1 -#define RMT_CH4_RX_END_INT_RAW_S 16 -/* RMT_CH3_TX_LOOP_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH3_TX_LOOP_INT_RAW_S 15 -/* RMT_CH2_TX_LOOP_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH2_TX_LOOP_INT_RAW_S 14 -/* RMT_CH1_TX_LOOP_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH1_TX_LOOP_INT_RAW_S 13 -/* RMT_CH0_TX_LOOP_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH0_TX_LOOP_INT_RAW_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 -/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_RAW (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 7 -/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_RAW (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 6 -/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 -/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_RAW (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 4 -/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_RAW (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_M (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_V 0x1 -#define RMT_CH3_TX_END_INT_RAW_S 3 -/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_RAW (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_M (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_V 0x1 -#define RMT_CH2_TX_END_INT_RAW_S 2 -/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_RAW (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 1 -/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 -#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001 +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001 +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_TX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ST (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_M (RMT_CH2_TX_END_INT_ST_V << RMT_CH2_TX_END_INT_ST_S) +#define RMT_CH2_TX_END_INT_ST_V 0x00000001 +#define RMT_CH2_TX_END_INT_ST_S 2 +/** RMT_CH3_TX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ST (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_M (RMT_CH3_TX_END_INT_ST_V << RMT_CH3_TX_END_INT_ST_S) +#define RMT_CH3_TX_END_INT_ST_V 0x00000001 +#define RMT_CH3_TX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001 +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001 +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001 +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001 +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (RMT_CH2_TX_THR_EVENT_INT_ST_V << RMT_CH2_TX_THR_EVENT_INT_ST_S) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (RMT_CH3_TX_THR_EVENT_INT_ST_V << RMT_CH3_TX_THR_EVENT_INT_ST_S) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001 +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001 +#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/** RMT_CH2_TX_LOOP_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_M (RMT_CH2_TX_LOOP_INT_ST_V << RMT_CH2_TX_LOOP_INT_ST_S) +#define RMT_CH2_TX_LOOP_INT_ST_V 0x00000001 +#define RMT_CH2_TX_LOOP_INT_ST_S 14 +/** RMT_CH3_TX_LOOP_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_M (RMT_CH3_TX_LOOP_INT_ST_V << RMT_CH3_TX_LOOP_INT_ST_S) +#define RMT_CH3_TX_LOOP_INT_ST_V 0x00000001 +#define RMT_CH3_TX_LOOP_INT_ST_S 15 +/** RMT_CH4_RX_END_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ST (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_M (RMT_CH4_RX_END_INT_ST_V << RMT_CH4_RX_END_INT_ST_S) +#define RMT_CH4_RX_END_INT_ST_V 0x00000001 +#define RMT_CH4_RX_END_INT_ST_S 16 +/** RMT_CH5_RX_END_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ST (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_M (RMT_CH5_RX_END_INT_ST_V << RMT_CH5_RX_END_INT_ST_S) +#define RMT_CH5_RX_END_INT_ST_V 0x00000001 +#define RMT_CH5_RX_END_INT_ST_S 17 +/** RMT_CH6_RX_END_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ST (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_M (RMT_CH6_RX_END_INT_ST_V << RMT_CH6_RX_END_INT_ST_S) +#define RMT_CH6_RX_END_INT_ST_V 0x00000001 +#define RMT_CH6_RX_END_INT_ST_S 18 +/** RMT_CH7_RX_END_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ST (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_M (RMT_CH7_RX_END_INT_ST_V << RMT_CH7_RX_END_INT_ST_S) +#define RMT_CH7_RX_END_INT_ST_V 0x00000001 +#define RMT_CH7_RX_END_INT_ST_S 19 +/** RMT_CH4_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ST (BIT(20)) +#define RMT_CH4_ERR_INT_ST_M (RMT_CH4_ERR_INT_ST_V << RMT_CH4_ERR_INT_ST_S) +#define RMT_CH4_ERR_INT_ST_V 0x00000001 +#define RMT_CH4_ERR_INT_ST_S 20 +/** RMT_CH5_ERR_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ST (BIT(21)) +#define RMT_CH5_ERR_INT_ST_M (RMT_CH5_ERR_INT_ST_V << RMT_CH5_ERR_INT_ST_S) +#define RMT_CH5_ERR_INT_ST_V 0x00000001 +#define RMT_CH5_ERR_INT_ST_S 21 +/** RMT_CH6_ERR_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ST (BIT(22)) +#define RMT_CH6_ERR_INT_ST_M (RMT_CH6_ERR_INT_ST_V << RMT_CH6_ERR_INT_ST_S) +#define RMT_CH6_ERR_INT_ST_V 0x00000001 +#define RMT_CH6_ERR_INT_ST_S 22 +/** RMT_CH7_ERR_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (RMT_CH7_ERR_INT_ST_V << RMT_CH7_ERR_INT_ST_S) +#define RMT_CH7_ERR_INT_ST_V 0x00000001 +#define RMT_CH7_ERR_INT_ST_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_M (RMT_CH4_RX_THR_EVENT_INT_ST_V << RMT_CH4_RX_THR_EVENT_INT_ST_S) +#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_M (RMT_CH5_RX_THR_EVENT_INT_ST_V << RMT_CH5_RX_THR_EVENT_INT_ST_S) +#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_M (RMT_CH6_RX_THR_EVENT_INT_ST_V << RMT_CH6_RX_THR_EVENT_INT_ST_S) +#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_M (RMT_CH7_RX_THR_EVENT_INT_ST_V << RMT_CH7_RX_THR_EVENT_INT_ST_S) +#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x00000001 +#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x0074) -/* RMT_CH7_RX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 -/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_ST (BIT(23)) -#define RMT_CH7_ERR_INT_ST_M (BIT(23)) -#define RMT_CH7_ERR_INT_ST_V 0x1 -#define RMT_CH7_ERR_INT_ST_S 23 -/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_ST (BIT(22)) -#define RMT_CH6_ERR_INT_ST_M (BIT(22)) -#define RMT_CH6_ERR_INT_ST_V 0x1 -#define RMT_CH6_ERR_INT_ST_S 22 -/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_ST (BIT(21)) -#define RMT_CH5_ERR_INT_ST_M (BIT(21)) -#define RMT_CH5_ERR_INT_ST_V 0x1 -#define RMT_CH5_ERR_INT_ST_S 21 -/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_ST (BIT(20)) -#define RMT_CH4_ERR_INT_ST_M (BIT(20)) -#define RMT_CH4_ERR_INT_ST_V 0x1 -#define RMT_CH4_ERR_INT_ST_S 20 -/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_ST (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_V 0x1 -#define RMT_CH7_RX_END_INT_ST_S 19 -/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_ST (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_V 0x1 -#define RMT_CH6_RX_END_INT_ST_S 18 -/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_ST (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_V 0x1 -#define RMT_CH5_RX_END_INT_ST_S 17 -/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_ST (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_V 0x1 -#define RMT_CH4_RX_END_INT_ST_S 16 -/* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ST_S 15 -/* RMT_CH2_TX_LOOP_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ST_S 14 -/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ST_S 13 -/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ST_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 -/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ST (BIT(7)) -#define RMT_CH3_ERR_INT_ST_M (BIT(7)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 7 -/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ST (BIT(6)) -#define RMT_CH2_ERR_INT_ST_M (BIT(6)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 6 -/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 -/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ST (BIT(4)) -#define RMT_CH0_ERR_INT_ST_M (BIT(4)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 4 -/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_ST (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_V 0x1 -#define RMT_CH3_TX_END_INT_ST_S 3 -/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_ST (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_V 0x1 -#define RMT_CH2_TX_END_INT_ST_S 2 -/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ST (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 1 -/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 -#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001 +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001 +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_TX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ENA (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_M (RMT_CH2_TX_END_INT_ENA_V << RMT_CH2_TX_END_INT_ENA_S) +#define RMT_CH2_TX_END_INT_ENA_V 0x00000001 +#define RMT_CH2_TX_END_INT_ENA_S 2 +/** RMT_CH3_TX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ENA (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_M (RMT_CH3_TX_END_INT_ENA_V << RMT_CH3_TX_END_INT_ENA_S) +#define RMT_CH3_TX_END_INT_ENA_V 0x00000001 +#define RMT_CH3_TX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001 +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001 +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001 +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001 +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (RMT_CH2_TX_THR_EVENT_INT_ENA_V << RMT_CH2_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (RMT_CH3_TX_THR_EVENT_INT_ENA_V << RMT_CH3_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001 +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001 +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/** RMT_CH2_TX_LOOP_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_M (RMT_CH2_TX_LOOP_INT_ENA_V << RMT_CH2_TX_LOOP_INT_ENA_S) +#define RMT_CH2_TX_LOOP_INT_ENA_V 0x00000001 +#define RMT_CH2_TX_LOOP_INT_ENA_S 14 +/** RMT_CH3_TX_LOOP_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_M (RMT_CH3_TX_LOOP_INT_ENA_V << RMT_CH3_TX_LOOP_INT_ENA_S) +#define RMT_CH3_TX_LOOP_INT_ENA_V 0x00000001 +#define RMT_CH3_TX_LOOP_INT_ENA_S 15 +/** RMT_CH4_RX_END_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ENA (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_M (RMT_CH4_RX_END_INT_ENA_V << RMT_CH4_RX_END_INT_ENA_S) +#define RMT_CH4_RX_END_INT_ENA_V 0x00000001 +#define RMT_CH4_RX_END_INT_ENA_S 16 +/** RMT_CH5_RX_END_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ENA (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_M (RMT_CH5_RX_END_INT_ENA_V << RMT_CH5_RX_END_INT_ENA_S) +#define RMT_CH5_RX_END_INT_ENA_V 0x00000001 +#define RMT_CH5_RX_END_INT_ENA_S 17 +/** RMT_CH6_RX_END_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ENA (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_M (RMT_CH6_RX_END_INT_ENA_V << RMT_CH6_RX_END_INT_ENA_S) +#define RMT_CH6_RX_END_INT_ENA_V 0x00000001 +#define RMT_CH6_RX_END_INT_ENA_S 18 +/** RMT_CH7_RX_END_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ENA (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_M (RMT_CH7_RX_END_INT_ENA_V << RMT_CH7_RX_END_INT_ENA_S) +#define RMT_CH7_RX_END_INT_ENA_V 0x00000001 +#define RMT_CH7_RX_END_INT_ENA_S 19 +/** RMT_CH4_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ENA (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_M (RMT_CH4_ERR_INT_ENA_V << RMT_CH4_ERR_INT_ENA_S) +#define RMT_CH4_ERR_INT_ENA_V 0x00000001 +#define RMT_CH4_ERR_INT_ENA_S 20 +/** RMT_CH5_ERR_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ENA (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_M (RMT_CH5_ERR_INT_ENA_V << RMT_CH5_ERR_INT_ENA_S) +#define RMT_CH5_ERR_INT_ENA_V 0x00000001 +#define RMT_CH5_ERR_INT_ENA_S 21 +/** RMT_CH6_ERR_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ENA (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_M (RMT_CH6_ERR_INT_ENA_V << RMT_CH6_ERR_INT_ENA_S) +#define RMT_CH6_ERR_INT_ENA_V 0x00000001 +#define RMT_CH6_ERR_INT_ENA_S 22 +/** RMT_CH7_ERR_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (RMT_CH7_ERR_INT_ENA_V << RMT_CH7_ERR_INT_ENA_S) +#define RMT_CH7_ERR_INT_ENA_V 0x00000001 +#define RMT_CH7_ERR_INT_ENA_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (RMT_CH4_RX_THR_EVENT_INT_ENA_V << RMT_CH4_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (RMT_CH5_RX_THR_EVENT_INT_ENA_V << RMT_CH5_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (RMT_CH6_RX_THR_EVENT_INT_ENA_V << RMT_CH6_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (RMT_CH7_RX_THR_EVENT_INT_ENA_V << RMT_CH7_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x00000001 +#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0078) -/* RMT_CH7_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 -/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_ENA (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_V 0x1 -#define RMT_CH7_ERR_INT_ENA_S 23 -/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_ENA (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_M (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_V 0x1 -#define RMT_CH6_ERR_INT_ENA_S 22 -/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_ENA (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_M (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_V 0x1 -#define RMT_CH5_ERR_INT_ENA_S 21 -/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_ENA (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_M (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_V 0x1 -#define RMT_CH4_ERR_INT_ENA_S 20 -/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_ENA (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_V 0x1 -#define RMT_CH7_RX_END_INT_ENA_S 19 -/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_ENA (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_V 0x1 -#define RMT_CH6_RX_END_INT_ENA_S 18 -/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_ENA (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_V 0x1 -#define RMT_CH5_RX_END_INT_ENA_S 17 -/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_ENA (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_V 0x1 -#define RMT_CH4_RX_END_INT_ENA_S 16 -/* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ENA_S 15 -/* RMT_CH2_TX_LOOP_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ENA_S 14 -/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ENA_S 13 -/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ENA_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 -/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ENA (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 7 -/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ENA (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 6 -/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 -/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ENA (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 4 -/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_ENA (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_V 0x1 -#define RMT_CH3_TX_END_INT_ENA_S 3 -/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_ENA (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_V 0x1 -#define RMT_CH2_TX_END_INT_ENA_S 2 -/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ENA (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 1 -/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 -#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7c) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001 +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001 +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_TX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ +#define RMT_CH2_TX_END_INT_CLR (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_M (RMT_CH2_TX_END_INT_CLR_V << RMT_CH2_TX_END_INT_CLR_S) +#define RMT_CH2_TX_END_INT_CLR_V 0x00000001 +#define RMT_CH2_TX_END_INT_CLR_S 2 +/** RMT_CH3_TX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ +#define RMT_CH3_TX_END_INT_CLR (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_M (RMT_CH3_TX_END_INT_CLR_V << RMT_CH3_TX_END_INT_CLR_S) +#define RMT_CH3_TX_END_INT_CLR_V 0x00000001 +#define RMT_CH3_TX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001 +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001 +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001 +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001 +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (RMT_CH2_TX_THR_EVENT_INT_CLR_V << RMT_CH2_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (RMT_CH3_TX_THR_EVENT_INT_CLR_V << RMT_CH3_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001 +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001 +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/** RMT_CH2_TX_LOOP_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ +#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_M (RMT_CH2_TX_LOOP_INT_CLR_V << RMT_CH2_TX_LOOP_INT_CLR_S) +#define RMT_CH2_TX_LOOP_INT_CLR_V 0x00000001 +#define RMT_CH2_TX_LOOP_INT_CLR_S 14 +/** RMT_CH3_TX_LOOP_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ +#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_M (RMT_CH3_TX_LOOP_INT_CLR_V << RMT_CH3_TX_LOOP_INT_CLR_S) +#define RMT_CH3_TX_LOOP_INT_CLR_V 0x00000001 +#define RMT_CH3_TX_LOOP_INT_CLR_S 15 +/** RMT_CH4_RX_END_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ +#define RMT_CH4_RX_END_INT_CLR (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_M (RMT_CH4_RX_END_INT_CLR_V << RMT_CH4_RX_END_INT_CLR_S) +#define RMT_CH4_RX_END_INT_CLR_V 0x00000001 +#define RMT_CH4_RX_END_INT_CLR_S 16 +/** RMT_CH5_RX_END_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ +#define RMT_CH5_RX_END_INT_CLR (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_M (RMT_CH5_RX_END_INT_CLR_V << RMT_CH5_RX_END_INT_CLR_S) +#define RMT_CH5_RX_END_INT_CLR_V 0x00000001 +#define RMT_CH5_RX_END_INT_CLR_S 17 +/** RMT_CH6_RX_END_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ +#define RMT_CH6_RX_END_INT_CLR (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_M (RMT_CH6_RX_END_INT_CLR_V << RMT_CH6_RX_END_INT_CLR_S) +#define RMT_CH6_RX_END_INT_CLR_V 0x00000001 +#define RMT_CH6_RX_END_INT_CLR_S 18 +/** RMT_CH7_RX_END_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ +#define RMT_CH7_RX_END_INT_CLR (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_M (RMT_CH7_RX_END_INT_CLR_V << RMT_CH7_RX_END_INT_CLR_S) +#define RMT_CH7_RX_END_INT_CLR_V 0x00000001 +#define RMT_CH7_RX_END_INT_CLR_S 19 +/** RMT_CH4_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ +#define RMT_CH4_ERR_INT_CLR (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_M (RMT_CH4_ERR_INT_CLR_V << RMT_CH4_ERR_INT_CLR_S) +#define RMT_CH4_ERR_INT_CLR_V 0x00000001 +#define RMT_CH4_ERR_INT_CLR_S 20 +/** RMT_CH5_ERR_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ +#define RMT_CH5_ERR_INT_CLR (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_M (RMT_CH5_ERR_INT_CLR_V << RMT_CH5_ERR_INT_CLR_S) +#define RMT_CH5_ERR_INT_CLR_V 0x00000001 +#define RMT_CH5_ERR_INT_CLR_S 21 +/** RMT_CH6_ERR_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ +#define RMT_CH6_ERR_INT_CLR (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_M (RMT_CH6_ERR_INT_CLR_V << RMT_CH6_ERR_INT_CLR_S) +#define RMT_CH6_ERR_INT_CLR_V 0x00000001 +#define RMT_CH6_ERR_INT_CLR_S 22 +/** RMT_CH7_ERR_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (RMT_CH7_ERR_INT_CLR_V << RMT_CH7_ERR_INT_CLR_S) +#define RMT_CH7_ERR_INT_CLR_V 0x00000001 +#define RMT_CH7_ERR_INT_CLR_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (RMT_CH4_RX_THR_EVENT_INT_CLR_V << RMT_CH4_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (RMT_CH5_RX_THR_EVENT_INT_CLR_V << RMT_CH5_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (RMT_CH6_RX_THR_EVENT_INT_CLR_V << RMT_CH6_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (RMT_CH7_RX_THR_EVENT_INT_CLR_V << RMT_CH7_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x00000001 +#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x007c) -/* RMT_CH7_RX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 -/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_CLR (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_V 0x1 -#define RMT_CH7_ERR_INT_CLR_S 23 -/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_CLR (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_M (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_V 0x1 -#define RMT_CH6_ERR_INT_CLR_S 22 -/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_CLR (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_M (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_V 0x1 -#define RMT_CH5_ERR_INT_CLR_S 21 -/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_CLR (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_M (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_V 0x1 -#define RMT_CH4_ERR_INT_CLR_S 20 -/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_CLR (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_M (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_V 0x1 -#define RMT_CH7_RX_END_INT_CLR_S 19 -/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_CLR (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_M (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_V 0x1 -#define RMT_CH6_RX_END_INT_CLR_S 18 -/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_CLR (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_M (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_V 0x1 -#define RMT_CH5_RX_END_INT_CLR_S 17 -/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_CLR (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_M (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_V 0x1 -#define RMT_CH4_RX_END_INT_CLR_S 16 -/* RMT_CH3_TX_LOOP_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH3_TX_LOOP_INT_CLR_S 15 -/* RMT_CH2_TX_LOOP_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH2_TX_LOOP_INT_CLR_S 14 -/* RMT_CH1_TX_LOOP_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH1_TX_LOOP_INT_CLR_S 13 -/* RMT_CH0_TX_LOOP_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH0_TX_LOOP_INT_CLR_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 -/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_CLR (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 7 -/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_CLR (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 6 -/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 -/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_CLR (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 4 -/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_CLR (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_M (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_V 0x1 -#define RMT_CH3_TX_END_INT_CLR_S 3 -/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_CLR (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_M (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_V 0x1 -#define RMT_CH2_TX_END_INT_CLR_S 2 -/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_CLR (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 1 -/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 -#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_S 16 -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0080) -/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V) << (RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 -/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V) << (RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF -#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_S 16 -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0084) -/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V) << (RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 -/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V) << (RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF -#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CH2CARRIER_DUTY_REG register + * Channel 2 duty cycle configuration register + */ +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88) +/** RMT_CARRIER_LOW_CH2 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M (RMT_CARRIER_LOW_CH2_V << RMT_CARRIER_LOW_CH2_S) +#define RMT_CARRIER_LOW_CH2_V 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_S 0 +/** RMT_CARRIER_HIGH_CH2 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M (RMT_CARRIER_HIGH_CH2_V << RMT_CARRIER_HIGH_CH2_S) +#define RMT_CARRIER_HIGH_CH2_V 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_S 16 -#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0088) -/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V) << (RMT_CARRIER_HIGH_CH2_S)) -#define RMT_CARRIER_HIGH_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_CH2_S 16 -/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V) << (RMT_CARRIER_LOW_CH2_S)) -#define RMT_CARRIER_LOW_CH2_V 0xFFFF -#define RMT_CARRIER_LOW_CH2_S 0 +/** RMT_CH3CARRIER_DUTY_REG register + * Channel 3 duty cycle configuration register + */ +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8c) +/** RMT_CARRIER_LOW_CH3 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M (RMT_CARRIER_LOW_CH3_V << RMT_CARRIER_LOW_CH3_S) +#define RMT_CARRIER_LOW_CH3_V 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_S 0 +/** RMT_CARRIER_HIGH_CH3 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M (RMT_CARRIER_HIGH_CH3_V << RMT_CARRIER_HIGH_CH3_S) +#define RMT_CARRIER_HIGH_CH3_V 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_S 16 -#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x008c) -/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V) << (RMT_CARRIER_HIGH_CH3_S)) -#define RMT_CARRIER_HIGH_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_CH3_S 16 -/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V) << (RMT_CARRIER_LOW_CH3_S)) -#define RMT_CARRIER_LOW_CH3_V 0xFFFF -#define RMT_CARRIER_LOW_CH3_S 0 +/** RMT_CH4_RX_CARRIER_RM_REG register + * Channel 4 carrier remove register + */ +#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) +/** RMT_CARRIER_LOW_THRES_CH4 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH4_M (RMT_CARRIER_LOW_THRES_CH4_V << RMT_CARRIER_LOW_THRES_CH4_S) +#define RMT_CARRIER_LOW_THRES_CH4_V 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH4_S 0 +/** RMT_CARRIER_HIGH_THRES_CH4 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH4_M (RMT_CARRIER_HIGH_THRES_CH4_V << RMT_CARRIER_HIGH_THRES_CH4_S) +#define RMT_CARRIER_HIGH_THRES_CH4_V 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH4_S 16 -#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0090) -/* RMT_CARRIER_HIGH_THRES_CH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH4_M ((RMT_CARRIER_HIGH_THRES_CH4_V) << (RMT_CARRIER_HIGH_THRES_CH4_S)) -#define RMT_CARRIER_HIGH_THRES_CH4_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH4_S 16 -/* RMT_CARRIER_LOW_THRES_CH4 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH4_M ((RMT_CARRIER_LOW_THRES_CH4_V) << (RMT_CARRIER_LOW_THRES_CH4_S)) -#define RMT_CARRIER_LOW_THRES_CH4_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH4_S 0 +/** RMT_CH5_RX_CARRIER_RM_REG register + * Channel 5 carrier remove register + */ +#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) +/** RMT_CARRIER_LOW_THRES_CH5 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH5_M (RMT_CARRIER_LOW_THRES_CH5_V << RMT_CARRIER_LOW_THRES_CH5_S) +#define RMT_CARRIER_LOW_THRES_CH5_V 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH5_S 0 +/** RMT_CARRIER_HIGH_THRES_CH5 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH5_M (RMT_CARRIER_HIGH_THRES_CH5_V << RMT_CARRIER_HIGH_THRES_CH5_S) +#define RMT_CARRIER_HIGH_THRES_CH5_V 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH5_S 16 -#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0094) -/* RMT_CARRIER_HIGH_THRES_CH5 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH5_M ((RMT_CARRIER_HIGH_THRES_CH5_V) << (RMT_CARRIER_HIGH_THRES_CH5_S)) -#define RMT_CARRIER_HIGH_THRES_CH5_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH5_S 16 -/* RMT_CARRIER_LOW_THRES_CH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH5_M ((RMT_CARRIER_LOW_THRES_CH5_V) << (RMT_CARRIER_LOW_THRES_CH5_S)) -#define RMT_CARRIER_LOW_THRES_CH5_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH5_S 0 +/** RMT_CH6_RX_CARRIER_RM_REG register + * Channel 6 carrier remove register + */ +#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) +/** RMT_CARRIER_LOW_THRES_CH6 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH6_M (RMT_CARRIER_LOW_THRES_CH6_V << RMT_CARRIER_LOW_THRES_CH6_S) +#define RMT_CARRIER_LOW_THRES_CH6_V 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH6_S 0 +/** RMT_CARRIER_HIGH_THRES_CH6 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH6_M (RMT_CARRIER_HIGH_THRES_CH6_V << RMT_CARRIER_HIGH_THRES_CH6_S) +#define RMT_CARRIER_HIGH_THRES_CH6_V 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH6_S 16 -#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0098) -/* RMT_CARRIER_HIGH_THRES_CH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH6_M ((RMT_CARRIER_HIGH_THRES_CH6_V) << (RMT_CARRIER_HIGH_THRES_CH6_S)) -#define RMT_CARRIER_HIGH_THRES_CH6_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH6_S 16 -/* RMT_CARRIER_LOW_THRES_CH6 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH6_M ((RMT_CARRIER_LOW_THRES_CH6_V) << (RMT_CARRIER_LOW_THRES_CH6_S)) -#define RMT_CARRIER_LOW_THRES_CH6_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH6_S 0 +/** RMT_CH7_RX_CARRIER_RM_REG register + * Channel 7 carrier remove register + */ +#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9c) +/** RMT_CARRIER_LOW_THRES_CH7 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH7_M (RMT_CARRIER_LOW_THRES_CH7_V << RMT_CARRIER_LOW_THRES_CH7_S) +#define RMT_CARRIER_LOW_THRES_CH7_V 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH7_S 0 +/** RMT_CARRIER_HIGH_THRES_CH7 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH7_M (RMT_CARRIER_HIGH_THRES_CH7_V << RMT_CARRIER_HIGH_THRES_CH7_S) +#define RMT_CARRIER_HIGH_THRES_CH7_V 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH7_S 16 -#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x009c) -/* RMT_CARRIER_HIGH_THRES_CH7 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH7_M ((RMT_CARRIER_HIGH_THRES_CH7_V) << (RMT_CARRIER_HIGH_THRES_CH7_S)) -#define RMT_CARRIER_HIGH_THRES_CH7_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH7_S 16 -/* RMT_CARRIER_LOW_THRES_CH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH7_M ((RMT_CARRIER_LOW_THRES_CH7_V) << (RMT_CARRIER_LOW_THRES_CH7_S)) -#define RMT_CARRIER_LOW_THRES_CH7_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH7_S 0 +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xa0) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FF +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FF +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FF +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001 +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001 +#define RMT_LOOP_COUNT_RESET_CH0_S 20 -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a0) -/* RMT_LOOP_COUNT_RESET_CH0 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH0_S 20 -/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FF -#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V) << (RMT_TX_LOOP_NUM_CH0_S)) -#define RMT_TX_LOOP_NUM_CH0_V 0x3FF -#define RMT_TX_LOOP_NUM_CH0_S 9 -/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V) << (RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF -#define RMT_TX_LIM_CH0_S 0 +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xa4) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FF +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FF +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FF +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001 +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001 +#define RMT_LOOP_COUNT_RESET_CH1_S 20 -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a4) -/* RMT_LOOP_COUNT_RESET_CH1 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH1_S 20 -/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH1_S 19 -/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH1 0x000003FF -#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V) << (RMT_TX_LOOP_NUM_CH1_S)) -#define RMT_TX_LOOP_NUM_CH1_V 0x3FF -#define RMT_TX_LOOP_NUM_CH1_S 9 -/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V) << (RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF -#define RMT_TX_LIM_CH1_S 0 +/** RMT_CH2_TX_LIM_REG register + * Channel 2 Tx event configuration register + */ +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xa8) +/** RMT_TX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can send out. + */ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M (RMT_TX_LIM_CH2_V << RMT_TX_LIM_CH2_S) +#define RMT_TX_LIM_CH2_V 0x000001FF +#define RMT_TX_LIM_CH2_S 0 +/** RMT_TX_LOOP_NUM_CH2 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH2 0x000003FF +#define RMT_TX_LOOP_NUM_CH2_M (RMT_TX_LOOP_NUM_CH2_V << RMT_TX_LOOP_NUM_CH2_S) +#define RMT_TX_LOOP_NUM_CH2_V 0x000003FF +#define RMT_TX_LOOP_NUM_CH2_S 9 +/** RMT_TX_LOOP_CNT_EN_CH2 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (RMT_TX_LOOP_CNT_EN_CH2_V << RMT_TX_LOOP_CNT_EN_CH2_S) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x00000001 +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/** RMT_LOOP_COUNT_RESET_CH2 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (RMT_LOOP_COUNT_RESET_CH2_V << RMT_LOOP_COUNT_RESET_CH2_S) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x00000001 +#define RMT_LOOP_COUNT_RESET_CH2_S 20 -#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a8) -/* RMT_LOOP_COUNT_RESET_CH2 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH2_S 20 -/* RMT_TX_LOOP_CNT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH2_S 19 -/* RMT_TX_LOOP_NUM_CH2 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH2 0x000003FF -#define RMT_TX_LOOP_NUM_CH2_M ((RMT_TX_LOOP_NUM_CH2_V) << (RMT_TX_LOOP_NUM_CH2_S)) -#define RMT_TX_LOOP_NUM_CH2_V 0x3FF -#define RMT_TX_LOOP_NUM_CH2_S 9 -/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH2 0x000001FF -#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V) << (RMT_TX_LIM_CH2_S)) -#define RMT_TX_LIM_CH2_V 0x1FF -#define RMT_TX_LIM_CH2_S 0 +/** RMT_CH3_TX_LIM_REG register + * Channel 3 Tx event configuration register + */ +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xac) +/** RMT_TX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can send out. + */ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M (RMT_TX_LIM_CH3_V << RMT_TX_LIM_CH3_S) +#define RMT_TX_LIM_CH3_V 0x000001FF +#define RMT_TX_LIM_CH3_S 0 +/** RMT_TX_LOOP_NUM_CH3 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH3 0x000003FF +#define RMT_TX_LOOP_NUM_CH3_M (RMT_TX_LOOP_NUM_CH3_V << RMT_TX_LOOP_NUM_CH3_S) +#define RMT_TX_LOOP_NUM_CH3_V 0x000003FF +#define RMT_TX_LOOP_NUM_CH3_S 9 +/** RMT_TX_LOOP_CNT_EN_CH3 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (RMT_TX_LOOP_CNT_EN_CH3_V << RMT_TX_LOOP_CNT_EN_CH3_S) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x00000001 +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/** RMT_LOOP_COUNT_RESET_CH3 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (RMT_LOOP_COUNT_RESET_CH3_V << RMT_LOOP_COUNT_RESET_CH3_S) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x00000001 +#define RMT_LOOP_COUNT_RESET_CH3_S 20 -#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ac) -/* RMT_LOOP_COUNT_RESET_CH3 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH3_S 20 -/* RMT_TX_LOOP_CNT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH3_S 19 -/* RMT_TX_LOOP_NUM_CH3 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH3 0x000003FF -#define RMT_TX_LOOP_NUM_CH3_M ((RMT_TX_LOOP_NUM_CH3_V) << (RMT_TX_LOOP_NUM_CH3_S)) -#define RMT_TX_LOOP_NUM_CH3_V 0x3FF -#define RMT_TX_LOOP_NUM_CH3_S 9 -/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH3 0x000001FF -#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V) << (RMT_TX_LIM_CH3_S)) -#define RMT_TX_LIM_CH3_V 0x1FF -#define RMT_TX_LIM_CH3_S 0 +/** RMT_CH4_RX_LIM_REG register + * Channel 4 Rx event configuration register + */ +#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xb0) +/** RMT_CH4_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL4 can receive. + */ +#define RMT_CH4_RX_LIM_REG 0x000001FF +#define RMT_CH4_RX_LIM_REG_M (RMT_CH4_RX_LIM_REG_V << RMT_CH4_RX_LIM_REG_S) +#define RMT_CH4_RX_LIM_REG_V 0x000001FF +#define RMT_CH4_RX_LIM_REG_S 0 -#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b0) -/* RMT_RX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH4 0x000001FF -#define RMT_RX_LIM_CH4_M ((RMT_RX_LIM_CH4_V) << (RMT_RX_LIM_CH4_S)) -#define RMT_RX_LIM_CH4_V 0x1FF -#define RMT_RX_LIM_CH4_S 0 +/** RMT_CH5_RX_LIM_REG register + * Channel 5 Rx event configuration register + */ +#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xb4) +/** RMT_CH5_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL5 can receive. + */ +#define RMT_CH5_RX_LIM_REG 0x000001FF +#define RMT_CH5_RX_LIM_REG_M (RMT_CH5_RX_LIM_REG_V << RMT_CH5_RX_LIM_REG_S) +#define RMT_CH5_RX_LIM_REG_V 0x000001FF +#define RMT_CH5_RX_LIM_REG_S 0 -#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b4) -/* RMT_RX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH5 0x000001FF -#define RMT_RX_LIM_CH5_M ((RMT_RX_LIM_CH5_V) << (RMT_RX_LIM_CH5_S)) -#define RMT_RX_LIM_CH5_V 0x1FF -#define RMT_RX_LIM_CH5_S 0 +/** RMT_CH6_RX_LIM_REG register + * Channel 6 Rx event configuration register + */ +#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xb8) +/** RMT_CH6_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL6 can receive. + */ +#define RMT_CH6_RX_LIM_REG 0x000001FF +#define RMT_CH6_RX_LIM_REG_M (RMT_CH6_RX_LIM_REG_V << RMT_CH6_RX_LIM_REG_S) +#define RMT_CH6_RX_LIM_REG_V 0x000001FF +#define RMT_CH6_RX_LIM_REG_S 0 -#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b8) -/* RMT_RX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH6 0x000001FF -#define RMT_RX_LIM_CH6_M ((RMT_RX_LIM_CH6_V) << (RMT_RX_LIM_CH6_S)) -#define RMT_RX_LIM_CH6_V 0x1FF -#define RMT_RX_LIM_CH6_S 0 +/** RMT_CH7_RX_LIM_REG register + * Channel 7 Rx event configuration register + */ +#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xbc) +/** RMT_CH7_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL7 can receive. + */ +#define RMT_CH7_RX_LIM_REG 0x000001FF +#define RMT_CH7_RX_LIM_REG_M (RMT_CH7_RX_LIM_REG_V << RMT_CH7_RX_LIM_REG_S) +#define RMT_CH7_RX_LIM_REG_V 0x000001FF +#define RMT_CH7_RX_LIM_REG_S 0 -#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0x00bc) -/* RMT_RX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH7 0x000001FF -#define RMT_RX_LIM_CH7_M ((RMT_RX_LIM_CH7_V) << (RMT_RX_LIM_CH7_S)) -#define RMT_RX_LIM_CH7_V 0x1FF -#define RMT_RX_LIM_CH7_S 0 +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xc0) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001 +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001 +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) +#define RMT_MEM_FORCE_PD_V 0x00000001 +#define RMT_MEM_FORCE_PD_S 2 +/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) +#define RMT_MEM_FORCE_PU_V 0x00000001 +#define RMT_MEM_FORCE_PU_S 3 +/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_SCLK_DIV_NUM 0x000000FF +#define RMT_SCLK_DIV_NUM_M (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S) +#define RMT_SCLK_DIV_NUM_V 0x000000FF +#define RMT_SCLK_DIV_NUM_S 4 +/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_A 0x0000003F +#define RMT_SCLK_DIV_A_M (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S) +#define RMT_SCLK_DIV_A_V 0x0000003F +#define RMT_SCLK_DIV_A_S 12 +/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_B 0x0000003F +#define RMT_SCLK_DIV_B_M (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S) +#define RMT_SCLK_DIV_B_V 0x0000003F +#define RMT_SCLK_DIV_B_S 18 +/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + */ +#define RMT_SCLK_SEL 0x00000003 +#define RMT_SCLK_SEL_M (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S) +#define RMT_SCLK_SEL_V 0x00000003 +#define RMT_SCLK_SEL_S 24 +/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S) +#define RMT_SCLK_ACTIVE_V 0x00000001 +#define RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001 +#define RMT_CLK_EN_S 31 -#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x00c0) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ -/*description: */ -#define RMT_SCLK_ACTIVE (BIT(26)) -#define RMT_SCLK_ACTIVE_M (BIT(26)) -#define RMT_SCLK_ACTIVE_V 0x1 -#define RMT_SCLK_ACTIVE_S 26 -/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ -/*description: */ -#define RMT_SCLK_SEL 0x00000003 -#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V) << (RMT_SCLK_SEL_S)) -#define RMT_SCLK_SEL_V 0x3 -#define RMT_SCLK_SEL_S 24 -/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_B 0x0000003F -#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V) << (RMT_SCLK_DIV_B_S)) -#define RMT_SCLK_DIV_B_V 0x3F -#define RMT_SCLK_DIV_B_S 18 -/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_A 0x0000003F -#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V) << (RMT_SCLK_DIV_A_S)) -#define RMT_SCLK_DIV_A_V 0x3F -#define RMT_SCLK_DIV_A_S 12 -/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ -/*description: */ -#define RMT_SCLK_DIV_NUM 0x000000FF -#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V) << (RMT_SCLK_DIV_NUM_S)) -#define RMT_SCLK_DIV_NUM_V 0xFF -#define RMT_SCLK_DIV_NUM_S 4 -/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PU (BIT(3)) -#define RMT_MEM_FORCE_PU_M (BIT(3)) -#define RMT_MEM_FORCE_PU_V 0x1 -#define RMT_MEM_FORCE_PU_S 3 -/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PD (BIT(2)) -#define RMT_MEM_FORCE_PD_M (BIT(2)) -#define RMT_MEM_FORCE_PD_V 0x1 -#define RMT_MEM_FORCE_PD_S 2 -/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_CLK_FORCE_ON (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_V 0x1 -#define RMT_MEM_CLK_FORCE_ON_S 1 -/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 -#define RMT_APB_FIFO_MASK_S 0 +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xc4) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001 +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001 +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH2 (BIT(2)) +#define RMT_TX_SIM_CH2_M (RMT_TX_SIM_CH2_V << RMT_TX_SIM_CH2_S) +#define RMT_TX_SIM_CH2_V 0x00000001 +#define RMT_TX_SIM_CH2_S 2 +/** RMT_TX_SIM_CH3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH3 (BIT(3)) +#define RMT_TX_SIM_CH3_M (RMT_TX_SIM_CH3_V << RMT_TX_SIM_CH3_S) +#define RMT_TX_SIM_CH3_V 0x00000001 +#define RMT_TX_SIM_CH3_S 3 +/** RMT_TX_SIM_EN : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(4)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001 +#define RMT_TX_SIM_EN_S 4 -#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x00c4) -/* RMT_TX_SIM_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_EN (BIT(4)) -#define RMT_TX_SIM_EN_M (BIT(4)) -#define RMT_TX_SIM_EN_V 0x1 -#define RMT_TX_SIM_EN_S 4 -/* RMT_TX_SIM_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH3 (BIT(3)) -#define RMT_TX_SIM_CH3_M (BIT(3)) -#define RMT_TX_SIM_CH3_V 0x1 -#define RMT_TX_SIM_CH3_S 3 -/* RMT_TX_SIM_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH2 (BIT(2)) -#define RMT_TX_SIM_CH2_M (BIT(2)) -#define RMT_TX_SIM_CH2_V 0x1 -#define RMT_TX_SIM_CH2_S 2 -/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH1 (BIT(1)) -#define RMT_TX_SIM_CH1_M (BIT(1)) -#define RMT_TX_SIM_CH1_V 0x1 -#define RMT_TX_SIM_CH1_S 1 -/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH0 (BIT(0)) -#define RMT_TX_SIM_CH0_M (BIT(0)) -#define RMT_TX_SIM_CH0_V 0x1 -#define RMT_TX_SIM_CH0_S 0 +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xc8) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001 +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001 +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001 +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001 +#define RMT_REF_CNT_RST_CH3_S 3 +/** RMT_REF_CNT_RST_CH4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ +#define RMT_REF_CNT_RST_CH4 (BIT(4)) +#define RMT_REF_CNT_RST_CH4_M (RMT_REF_CNT_RST_CH4_V << RMT_REF_CNT_RST_CH4_S) +#define RMT_REF_CNT_RST_CH4_V 0x00000001 +#define RMT_REF_CNT_RST_CH4_S 4 +/** RMT_REF_CNT_RST_CH5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ +#define RMT_REF_CNT_RST_CH5 (BIT(5)) +#define RMT_REF_CNT_RST_CH5_M (RMT_REF_CNT_RST_CH5_V << RMT_REF_CNT_RST_CH5_S) +#define RMT_REF_CNT_RST_CH5_V 0x00000001 +#define RMT_REF_CNT_RST_CH5_S 5 +/** RMT_REF_CNT_RST_CH6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ +#define RMT_REF_CNT_RST_CH6 (BIT(6)) +#define RMT_REF_CNT_RST_CH6_M (RMT_REF_CNT_RST_CH6_V << RMT_REF_CNT_RST_CH6_S) +#define RMT_REF_CNT_RST_CH6_V 0x00000001 +#define RMT_REF_CNT_RST_CH6_S 6 +/** RMT_REF_CNT_RST_CH7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ +#define RMT_REF_CNT_RST_CH7 (BIT(7)) +#define RMT_REF_CNT_RST_CH7_M (RMT_REF_CNT_RST_CH7_V << RMT_REF_CNT_RST_CH7_S) +#define RMT_REF_CNT_RST_CH7_V 0x00000001 +#define RMT_REF_CNT_RST_CH7_S 7 -#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x00c8) -/* RMT_REF_CNT_RST_CH7 : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH7 (BIT(7)) -#define RMT_REF_CNT_RST_CH7_M (BIT(7)) -#define RMT_REF_CNT_RST_CH7_V 0x1 -#define RMT_REF_CNT_RST_CH7_S 7 -/* RMT_REF_CNT_RST_CH6 : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH6 (BIT(6)) -#define RMT_REF_CNT_RST_CH6_M (BIT(6)) -#define RMT_REF_CNT_RST_CH6_V 0x1 -#define RMT_REF_CNT_RST_CH6_S 6 -/* RMT_REF_CNT_RST_CH5 : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH5 (BIT(5)) -#define RMT_REF_CNT_RST_CH5_M (BIT(5)) -#define RMT_REF_CNT_RST_CH5_V 0x1 -#define RMT_REF_CNT_RST_CH5_S 5 -/* RMT_REF_CNT_RST_CH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH4 (BIT(4)) -#define RMT_REF_CNT_RST_CH4_M (BIT(4)) -#define RMT_REF_CNT_RST_CH4_V 0x1 -#define RMT_REF_CNT_RST_CH4_S 4 -/* RMT_REF_CNT_RST_CH3 : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH3 (BIT(3)) -#define RMT_REF_CNT_RST_CH3_M (BIT(3)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 3 -/* RMT_REF_CNT_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH2 (BIT(2)) -#define RMT_REF_CNT_RST_CH2_M (BIT(2)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 2 -/* RMT_REF_CNT_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH1 (BIT(1)) -#define RMT_REF_CNT_RST_CH1_M (BIT(1)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 1 -/* RMT_REF_CNT_RST_CH0 : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH0 (BIT(0)) -#define RMT_REF_CNT_RST_CH0_M (BIT(0)) -#define RMT_REF_CNT_RST_CH0_V 0x1 -#define RMT_REF_CNT_RST_CH0_S 0 - -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00cc) -/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003041 ; */ -/*description: */ -#define RMT_DATE 0x0FFFFFFF -#define RMT_DATE_M ((RMT_DATE_V) << (RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFF -#define RMT_DATE_S 0 +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_DATE : R/W; bitpos: [27:0]; default: 33566785; + * This is the version register. + */ +#define RMT_DATE 0x0FFFFFFF +#define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) +#define RMT_DATE_V 0x0FFFFFFF +#define RMT_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/soc/esp32s3/include/soc/rmt_struct.h index 75ce375d5f..6d00bdcade 100644 --- a/components/soc/soc/esp32s3/include/soc/rmt_struct.h +++ b/components/soc/soc/esp32s3/include/soc/rmt_struct.h @@ -17,314 +17,322 @@ extern "C" { #endif -#include - typedef volatile struct { - uint32_t data_ch[8]; /**/ + uint32_t data_ch[8]; union { struct { - uint32_t mem_raddr_ex: 10; - uint32_t reserved10: 1; - uint32_t waddr: 10; - uint32_t reserved21: 1; - uint32_t state: 3; - uint32_t mem_empty: 1; - uint32_t apb_mem_wr_err: 1; - uint32_t reserved27: 5; + uint32_t tx_start : 1; + uint32_t mem_rd_rst : 1; + uint32_t apb_mem_rst : 1; + uint32_t tx_conti_mode : 1; + uint32_t mem_tx_wrap_en : 1; + uint32_t idle_out_lv : 1; + uint32_t idle_out_en : 1; + uint32_t tx_stop : 1; + uint32_t div_cnt : 8; + uint32_t mem_size : 4; + uint32_t carrier_eff_en : 1; + uint32_t carrier_en : 1; + uint32_t carrier_out_lv : 1; + uint32_t afifo_rst : 1; + uint32_t conf_update : 1; + uint32_t reserved25 : 7; }; uint32_t val; - } status_ch[8]; + } tx_conf[4]; + struct { + union { + struct { + uint32_t div_cnt : 8; + uint32_t idle_thres : 15; + uint32_t reserved23 : 1; + uint32_t mem_size : 4; + uint32_t carrier_en : 1; + uint32_t carrier_out_lv : 1; + uint32_t reserved30 : 2; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_en : 1; + uint32_t mem_wr_rst : 1; + uint32_t apb_mem_rst : 1; + uint32_t mem_owner : 1; + uint32_t rx_filter_en : 1; + uint32_t rx_filter_thres : 8; + uint32_t mem_rx_wrap_en : 1; + uint32_t afifo_rst : 1; + uint32_t conf_update : 1; + uint32_t reserved16 : 16; + }; + uint32_t val; + } conf1; + } rx_conf[4]; union { struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_tx_end: 1; - uint32_t ch3_tx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_tx_thr_event: 1; - uint32_t ch3_tx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t ch2_tx_loop: 1; - uint32_t ch3_tx_loop: 1; - uint32_t ch4_rx_end: 1; - uint32_t ch5_rx_end: 1; - uint32_t ch6_rx_end: 1; - uint32_t ch7_rx_end: 1; - uint32_t ch4_err: 1; - uint32_t ch5_err: 1; - uint32_t ch6_err: 1; - uint32_t ch7_err: 1; - uint32_t ch4_rx_thr_event: 1; - uint32_t ch5_rx_thr_event: 1; - uint32_t ch6_rx_thr_event: 1; - uint32_t ch7_rx_thr_event: 1; - uint32_t reserved28: 4; + uint32_t mem_raddr_ex : 10; + uint32_t reserved10 : 1; + uint32_t apb_mem_waddr : 10; + uint32_t reserved21 : 1; + uint32_t state : 3; + uint32_t mem_empty : 1; + uint32_t apb_mem_wr_err : 1; + uint32_t reserved27 : 5; + }; + uint32_t val; + } tx_status[4]; + union { + struct { + uint32_t mem_waddr_ex : 10; + uint32_t reserved10 : 1; + uint32_t apb_mem_raddr : 10; + uint32_t reserved21 : 1; + uint32_t state : 3; + uint32_t mem_owner_err : 1; + uint32_t mem_full : 1; + uint32_t apb_mem_rd_err : 1; + uint32_t reserved27 : 4; + }; + uint32_t val; + } rx_status[4]; + union { + struct { + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t reserved28 : 4; }; uint32_t val; } int_raw; union { struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_tx_end: 1; - uint32_t ch3_tx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_tx_thr_event: 1; - uint32_t ch3_tx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t ch2_tx_loop: 1; - uint32_t ch3_tx_loop: 1; - uint32_t ch4_rx_end: 1; - uint32_t ch5_rx_end: 1; - uint32_t ch6_rx_end: 1; - uint32_t ch7_rx_end: 1; - uint32_t ch4_err: 1; - uint32_t ch5_err: 1; - uint32_t ch6_err: 1; - uint32_t ch7_err: 1; - uint32_t ch4_rx_thr_event: 1; - uint32_t ch5_rx_thr_event: 1; - uint32_t ch6_rx_thr_event: 1; - uint32_t ch7_rx_thr_event: 1; - uint32_t reserved28: 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t reserved28 : 4; }; uint32_t val; } int_st; union { struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_tx_end: 1; - uint32_t ch3_tx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_tx_thr_event: 1; - uint32_t ch3_tx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t ch2_tx_loop: 1; - uint32_t ch3_tx_loop: 1; - uint32_t ch4_rx_end: 1; - uint32_t ch5_rx_end: 1; - uint32_t ch6_rx_end: 1; - uint32_t ch7_rx_end: 1; - uint32_t ch4_err: 1; - uint32_t ch5_err: 1; - uint32_t ch6_err: 1; - uint32_t ch7_err: 1; - uint32_t ch4_rx_thr_event: 1; - uint32_t ch5_rx_thr_event: 1; - uint32_t ch6_rx_thr_event: 1; - uint32_t ch7_rx_thr_event: 1; - uint32_t reserved28: 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t reserved28 : 4; }; uint32_t val; } int_ena; union { struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_tx_end: 1; - uint32_t ch3_tx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_tx_thr_event: 1; - uint32_t ch3_tx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t ch2_tx_loop: 1; - uint32_t ch3_tx_loop: 1; - uint32_t ch4_rx_end: 1; - uint32_t ch5_rx_end: 1; - uint32_t ch6_rx_end: 1; - uint32_t ch7_rx_end: 1; - uint32_t ch4_err: 1; - uint32_t ch5_err: 1; - uint32_t ch6_err: 1; - uint32_t ch7_err: 1; - uint32_t ch4_rx_thr_event: 1; - uint32_t ch5_rx_thr_event: 1; - uint32_t ch6_rx_thr_event: 1; - uint32_t ch7_rx_thr_event: 1; - uint32_t reserved28: 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t reserved28 : 4; }; uint32_t val; } int_clr; union { struct { - uint32_t low: 16; - uint32_t high: 16; + uint32_t low : 16; + uint32_t high : 16; }; uint32_t val; - } carrier_duty_ch[8]; + } tx_carrier[4]; union { struct { - uint32_t carrier_low_thres_ch4: 16; - uint32_t carrier_high_thres_ch4: 16; + uint32_t low_thres : 16; + uint32_t high_thres : 16; }; uint32_t val; - } ch4_rx_carrier_rm; + } rx_carrier[4]; union { struct { - uint32_t carrier_low_thres_ch5: 16; - uint32_t carrier_high_thres_ch5: 16; + uint32_t limit : 9; + uint32_t tx_loop_num : 10; + uint32_t tx_loop_cnt_en : 1; + uint32_t loop_count_reset : 1; + uint32_t reserved21 : 11; }; uint32_t val; - } ch5_rx_carrier_rm; + } tx_lim[4]; union { struct { - uint32_t carrier_low_thres_ch6: 16; - uint32_t carrier_high_thres_ch6: 16; + uint32_t rx_lim : 9; + uint32_t reserved9 : 23; }; uint32_t val; - } ch6_rx_carrier_rm; + } rx_lim[4]; union { struct { - uint32_t carrier_low_thres_ch7: 16; - uint32_t carrier_high_thres_ch7: 16; - }; - uint32_t val; - } ch7_rx_carrier_rm; - union { - struct { - uint32_t limit: 9; - uint32_t tx_loop_num: 10; - uint32_t tx_loop_cnt_en: 1; - uint32_t loop_count_reset: 1; - uint32_t reserved21: 11; - }; - uint32_t val; - } tx_lim_ch[8]; - union { - struct { - uint32_t rx_lim_ch4: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } ch4_rx_lim; - union { - struct { - uint32_t rx_lim_ch5: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } ch5_rx_lim; - union { - struct { - uint32_t rx_lim_ch6: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } ch6_rx_lim; - union { - struct { - uint32_t rx_lim_ch7: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } ch7_rx_lim; - union { - struct { - uint32_t fifo_mask: 1; - uint32_t mem_clk_force_on: 1; - uint32_t mem_force_pd: 1; - uint32_t mem_force_pu: 1; - uint32_t sclk_div_num: 8; - uint32_t sclk_div_a: 6; - uint32_t sclk_div_b: 6; - uint32_t sclk_sel: 2; - uint32_t sclk_active: 1; - uint32_t reserved27: 4; - uint32_t clk_en: 1; + uint32_t fifo_mask : 1; + uint32_t mem_clk_force_on : 1; + uint32_t mem_force_pd : 1; + uint32_t mem_force_pu : 1; + uint32_t sclk_div_num : 8; + uint32_t sclk_div_a : 6; + uint32_t sclk_div_b : 6; + uint32_t sclk_sel : 2; + uint32_t sclk_active : 1; + uint32_t reserved27 : 4; + uint32_t clk_en : 1; }; uint32_t val; } sys_conf; union { struct { - uint32_t ch0: 1; - uint32_t ch1: 1; - uint32_t ch2: 1; - uint32_t ch3: 1; - uint32_t en: 1; - uint32_t reserved5: 27; + uint32_t tx_sim_ch0 : 1; + uint32_t tx_sim_ch1 : 1; + uint32_t tx_sim_ch2 : 1; + uint32_t tx_sim_ch3 : 1; + uint32_t tx_sim_en : 1; + uint32_t reserved5 : 27; }; uint32_t val; } tx_sim; union { struct { - uint32_t ch0: 1; - uint32_t ch1: 1; - uint32_t ch2: 1; - uint32_t ch3: 1; - uint32_t ch4: 1; - uint32_t ch5: 1; - uint32_t ch6: 1; - uint32_t ch7: 1; - uint32_t reserved8: 24; + uint32_t ref_cnt_rst_ch0 : 1; + uint32_t ref_cnt_rst_ch1 : 1; + uint32_t ref_cnt_rst_ch2 : 1; + uint32_t ref_cnt_rst_ch3 : 1; + uint32_t ref_cnt_rst_ch4 : 1; + uint32_t ref_cnt_rst_ch5 : 1; + uint32_t ref_cnt_rst_ch6 : 1; + uint32_t ref_cnt_rst_ch7 : 1; + uint32_t reserved8 : 24; }; uint32_t val; } ref_cnt_rst; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; } rmt_dev_t; -extern rmt_dev_t RMT; - typedef struct { union { struct { - uint32_t duration0 :15; - uint32_t level0 :1; - uint32_t duration1 :15; - uint32_t level1 :1; + uint32_t duration0 : 15; + uint32_t level0 : 1; + uint32_t duration1 : 15; + uint32_t level1 : 1; }; uint32_t val; }; } rmt_item32_t; -typedef struct { - union { - struct { - uint16_t duration :15; - uint16_t level :1; - }; - uint16_t val; - }; -} rmt_item16_t; +extern rmt_dev_t RMT; -//Allow access to RMT memory using RMTMEM.chan[0].data32[8] typedef volatile struct { struct { union { - rmt_item32_t data32[64]; - rmt_item16_t data16[128]; + rmt_item32_t data32[48]; }; - } chan[4]; + } chan[8]; } rmt_mem_t; extern rmt_mem_t RMTMEM; diff --git a/tools/unit-test-app/components/test_utils/include/test_utils.h b/tools/unit-test-app/components/test_utils/include/test_utils.h index f69b18fe45..2cfb2a5ea2 100644 --- a/tools/unit-test-app/components/test_utils/include/test_utils.h +++ b/tools/unit-test-app/components/test_utils/include/test_utils.h @@ -20,9 +20,10 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" - +#include "unity.h" /* include performance pass standards header file */ #include "idf_performance.h" +#include "idf_performance_target.h" #ifdef __cplusplus extern "C" { diff --git a/tools/unit-test-app/components/test_utils/ref_clock.c b/tools/unit-test-app/components/test_utils/ref_clock.c index bad79a5b84..d97244ec65 100644 --- a/tools/unit-test-app/components/test_utils/ref_clock.c +++ b/tools/unit-test-app/components/test_utils/ref_clock.c @@ -77,7 +77,7 @@ void ref_clock_init(void) #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 0); // select REF_TICK (1MHz) #else - // TODO: configure RMT module clock source to fixed 1MHz + rmt_ll_set_sclk(s_rmt_hal.regs, 3, 39, 0, 0); // XTAL(40MHz), rmt_sclk => 1MHz (40/(1+39)) #endif rmt_hal_set_counter_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz rmt_ll_enable_tx_idle(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); // enable idle output From cc66334014785d811c95f28dc90b35d502d6c8dd Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 14 Aug 2020 11:36:58 +0800 Subject: [PATCH 08/11] esp_timer: initial support on esp32-s3 --- components/esp32s3/ld/esp32s3.peripherals.ld | 1 + components/esp_timer/src/ets_timer_legacy.c | 2 + components/esp_timer/test/test_ets_timer.c | 2 + .../hal/esp32s3/include/hal/systimer_ll.h | 73 +++++++++++-------- components/hal/esp32s3/systimer_hal.c | 7 +- 5 files changed, 53 insertions(+), 32 deletions(-) diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index 7d56b730e1..68815bb27f 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -21,6 +21,7 @@ PROVIDE ( LEDC = 0x60019000 ); PROVIDE ( MCP = 0x600c3000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); +PROVIDE ( SYS_TIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); diff --git a/components/esp_timer/src/ets_timer_legacy.c b/components/esp_timer/src/ets_timer_legacy.c index 14d5f02a7d..cec5525337 100644 --- a/components/esp_timer/src/ets_timer_legacy.c +++ b/components/esp_timer/src/ets_timer_legacy.c @@ -34,6 +34,8 @@ #include "esp32/rom/ets_sys.h" // for ETSTimer type #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif /* We abuse 'timer_arg' field of ETSTimer structure to hold a pointer to esp_timer */ diff --git a/components/esp_timer/test/test_ets_timer.c b/components/esp_timer/test/test_ets_timer.c index 5d7bf34d57..75f92e830d 100644 --- a/components/esp_timer/test/test_ets_timer.c +++ b/components/esp_timer/test/test_ets_timer.c @@ -11,6 +11,8 @@ #include "esp32/rom/ets_sys.h" // for ETSTimer type #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif TEST_CASE("ets_timer produces correct delay", "[ets_timer]") diff --git a/components/hal/esp32s3/include/hal/systimer_ll.h b/components/hal/esp32s3/include/hal/systimer_ll.h index 21ee0dabcc..0da3a4a16e 100644 --- a/components/hal/esp32s3/include/hal/systimer_ll.h +++ b/components/hal/esp32s3/include/hal/systimer_ll.h @@ -37,15 +37,13 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_counter(uin REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (30 - counter_id)); } -__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 31); -} - -__attribute__((always_inline)) static inline void systimer_ll_load_counter_value(uint32_t counter_id, uint64_t value) -{ - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG + 8 * counter_id, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG, value >> 32); + if (can) { + REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + } else { + REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + } } __attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(uint32_t counter_id) @@ -58,6 +56,12 @@ __attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_v return REG_GET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 29); } +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(uint32_t counter_id, uint64_t value) +{ + REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG + 8 * counter_id, value & 0xFFFFFFFF); + REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG, (value >> 32) & 0xFFFFF); +} + __attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(uint32_t counter_id) { return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG + 8 * counter_id); @@ -68,13 +72,17 @@ __attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_va return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG + 8 * counter_id); } +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(uint32_t counter_id) +{ + REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG + 4 * counter_id, SYS_TIMER_TIMER_UNIT0_LOAD); +} + /*******************alarm*************************/ __attribute__((always_inline)) static inline void systimer_ll_set_alarm_value(uint32_t alarm_id, uint64_t value) { REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, value >> 32); - REG_WRITE(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG + alarm_id * 4, SYS_TIMER_TIMER_COMP0_LOAD); + REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value >> 32) & 0xFFFFF); } __attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_value(uint32_t alarm_id) @@ -83,6 +91,31 @@ __attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_valu | REG_READ(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8); } +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(uint32_t alarm_id, uint32_t counter_id) +{ + REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + 4 * alarm_id, SYS_TIMER_TARGET0_TIMER_UNIT_SEL, counter_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) +{ + REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) +{ + REG_SET_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); +} + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) +{ + REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD, period); +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(uint32_t alarm_id) +{ + REG_SET_BIT(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG + alarm_id * 4, SYS_TIMER_TIMER_COMP0_LOAD); +} + __attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id) { REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); @@ -93,26 +126,6 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint3 REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) -{ - REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE_M); -} - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) -{ - REG_SET_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE_M); -} - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) -{ - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD, period); -} - -__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(uint32_t alarm_id, uint32_t counter_id) -{ - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + 4 * alarm_id, SYS_TIMER_TARGET0_TIMER_UNIT_SEL, counter_id); -} - /*******************interrupt*************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id) diff --git a/components/hal/esp32s3/systimer_hal.c b/components/hal/esp32s3/systimer_hal.c index fef0e4d939..1f615f8e4f 100644 --- a/components/hal/esp32s3/systimer_hal.c +++ b/components/hal/esp32s3/systimer_hal.c @@ -17,8 +17,9 @@ #include "hal/systimer_ll.h" #include "hal/systimer_types.h" #include "soc/systimer_caps.h" +#include "hal/clk_gate_ll.h" -#define SYSTIMER_TICKS_PER_US (16) // Number of timer ticks per microsecond +#define SYSTIMER_TICKS_PER_US (16) // Systimer clock source is fixed to 16MHz uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id) { @@ -56,6 +57,7 @@ void systimer_hal_set_alarm_value(systimer_alarm_id_t alarm_id, uint64_t timesta systimer_counter_value_t alarm = { .val = timestamp * SYSTIMER_TICKS_PER_US}; systimer_ll_disable_alarm(alarm_id); systimer_ll_set_alarm_value(alarm_id, alarm.val); + systimer_ll_apply_alarm_value(alarm_id); systimer_ll_enable_alarm(alarm_id); } @@ -78,7 +80,7 @@ void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us) void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us) { systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(counter_id) + time_us * SYSTIMER_TICKS_PER_US }; - systimer_ll_load_counter_value(counter_id, new_count.val); + systimer_ll_set_counter_value(counter_id, new_count.val); systimer_ll_apply_counter_value(counter_id); } @@ -89,6 +91,7 @@ void systimer_hal_enable_counter(systimer_counter_id_t counter_id) void systimer_hal_init(void) { + periph_ll_enable_clk_clear_rst(PERIPH_SYSTIMER_MODULE); systimer_ll_enable_clock(); } From bff0016eb85d4abd7df372040ab08336ea093d0d Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 19 Aug 2020 14:39:12 +0800 Subject: [PATCH 09/11] crypto accelerator support on esp32s3 SHA: passing unit tests RSA: pass tests AES: tests passing --- components/esp32s3/ld/esp32s3.peripherals.ld | 1 + .../hal/esp32s3/include/hal/clk_gate_ll.h | 35 + .../include/esp32s3/idf_performance_target.h | 8 +- components/mbedtls/port/esp32s3/aes.c | 1059 +++++++++++++++++ components/mbedtls/port/esp32s3/bignum.c | 223 ++++ components/mbedtls/port/esp32s3/esp_sha1.c | 255 ++++ components/mbedtls/port/esp32s3/esp_sha256.c | 267 +++++ components/mbedtls/port/esp32s3/esp_sha512.c | 317 +++++ components/mbedtls/port/esp32s3/sha.c | 384 ++++++ components/mbedtls/port/esp_aes_xts.c | 8 +- components/mbedtls/test/test_aes.c | 280 ++++- 11 files changed, 2831 insertions(+), 6 deletions(-) diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index 68815bb27f..8f31656ca4 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -29,5 +29,6 @@ PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( UART2 = 0x60010000 ); +PROVIDE ( DMA = 0x6003F000 ); PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( LCD_CAM = 0x60041000 ); diff --git a/components/hal/esp32s3/include/hal/clk_gate_ll.h b/components/hal/esp32s3/include/hal/clk_gate_ll.h index c8fc693b61..94cca9f93f 100644 --- a/components/hal/esp32s3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s3/include/hal/clk_gate_ll.h @@ -94,6 +94,12 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return SYSTEM_SYSTIMER_CLK_EN; case PERIPH_GDMA_MODULE: return SYSTEM_DMA_CLK_EN; + case PERIPH_AES_MODULE: + return SYSTEM_CRYPTO_AES_CLK_EN; + case PERIPH_SHA_MODULE: + return SYSTEM_CRYPTO_SHA_CLK_EN; + case PERIPH_RSA_MODULE: + return SYSTEM_CRYPTO_RSA_CLK_EN; default: return 0; } @@ -159,6 +165,30 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en return SYSTEM_SYSTIMER_RST; case PERIPH_GDMA_MODULE: return SYSTEM_DMA_RST; + case PERIPH_AES_MODULE: + if (enable == true) { + // Clear reset on digital signature, otherwise AES unit is held in reset also. + return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST); + } else { + //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. + return SYSTEM_CRYPTO_AES_RST; + } + case PERIPH_SHA_MODULE: + if (enable == true) { + // Clear reset on digital signature and HMAC, otherwise SHA is held in reset + return (SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_DS_RST | SYSTEM_CRYPTO_HMAC_RST | SYSTEM_DMA_RST) ; + } else { + // Don't assert reset on secure boot, otherwise AES is held in reset + return SYSTEM_CRYPTO_SHA_RST | SYSTEM_DMA_RST; + } + case PERIPH_RSA_MODULE: + if (enable == true) { + /* also clear reset on digital signature, otherwise RSA is held in reset */ + return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST); + } else { + /* don't reset digital signature unit, as this resets AES also */ + return SYSTEM_CRYPTO_RSA_RST; + } default: return 0; } @@ -177,6 +207,9 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) case PERIPH_UART2_MODULE: case PERIPH_SDMMC_MODULE: case PERIPH_GDMA_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_SHA_MODULE: + case PERIPH_RSA_MODULE: return SYSTEM_PERIP_CLK_EN1_REG; default: return SYSTEM_PERIP_CLK_EN0_REG; @@ -196,6 +229,8 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) case PERIPH_UART2_MODULE: case PERIPH_SDMMC_MODULE: case PERIPH_GDMA_MODULE: + case PERIPH_AES_MODULE: + case PERIPH_RSA_MODULE: return SYSTEM_PERIP_RST_EN1_REG; default: return SYSTEM_PERIP_RST_EN0_REG; diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h index 52e376e6cb..269a3c9103 100644 --- a/components/idf_test/include/esp32s3/idf_performance_target.h +++ b/components/idf_test/include/esp32s3/idf_performance_target.h @@ -8,10 +8,10 @@ #define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000 #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 14000 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 100000 -#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 60000 -#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 600000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1500000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 diff --git a/components/mbedtls/port/esp32s3/aes.c b/components/mbedtls/port/esp32s3/aes.c index e69de29bb2..f092b6a3df 100644 --- a/components/mbedtls/port/esp32s3/aes.c +++ b/components/mbedtls/port/esp32s3/aes.c @@ -0,0 +1,1059 @@ +/** + * \brief AES block cipher, ESP32-S2 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include +#include +#include +#include "mbedtls/aes.h" +#include "esp32s3/aes.h" +#include "soc/cpu.h" +#include "soc/dport_reg.h" +#include "soc/hwcrypto_reg.h" +#include "soc/periph_defs.h" +#include "esp32s3/rom/lldesc.h" +#include "esp32s3/rom/cache.h" +#include "esp_intr_alloc.h" +#include "driver/periph_ctrl.h" +#include "esp_log.h" +#include "soc/lldesc.h" +#include "esp_heap_caps.h" +#include "sys/param.h" +#include "esp_pm.h" +#include "soc/soc_memory_layout.h" +#include "soc/gdma_reg.h" +#include "soc/gdma_struct.h" +#include "soc/extmem_reg.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +#define AES_BLOCK_BYTES 16 +#define IV_WORDS 4 + +#define DMA_PERIPH_AES 6 /* DMA peripheral indexes */ +#define DMA_PERIPH_SHA 7 +/* Max size of each chunk to process when output buffer is in unaligned external ram + must be a multiple of block size +*/ +#define AES_MAX_CHUNK_WRITE_SIZE 1600 + +/* Input over this length will yield and wait for interrupt instead of + busy-waiting, 30000 bytes is approx 0.5 ms */ +#define AES_DMA_INTR_TRIG_LEN 2000 + +#define ESP_PUT_BE64(a, val) \ + do { \ + *(uint64_t*)(a) = __builtin_bswap64( (uint64_t)(val) ); \ + } while (0) + + +/* DMA AES working modes*/ +typedef enum { + ESP_AES_BLOCK_MODE_ECB = 0, + ESP_AES_BLOCK_MODE_CBC, + ESP_AES_BLOCK_MODE_OFB, + ESP_AES_BLOCK_MODE_CTR, + ESP_AES_BLOCK_MODE_CFB8, + ESP_AES_BLOCK_MODE_CFB128, +} esp_aes_mode_t; + + +#if defined(CONFIG_MBEDTLS_AES_USE_INTERRUPT) +static SemaphoreHandle_t op_complete_sem; +#if defined(CONFIG_PM_ENABLE) +static esp_pm_lock_handle_t s_pm_cpu_lock; +static esp_pm_lock_handle_t s_pm_sleep_lock; +#endif +#endif + +static const char *TAG = "esp-aes"; + +static _lock_t s_aes_lock; + +static inline bool valid_key_length(const esp_aes_context *ctx) +{ + return ctx->key_bytes == 128 / 8 || ctx->key_bytes == 256 / 8; +} + + +void esp_aes_acquire_hardware( void ) +{ + _lock_acquire(&s_aes_lock); + + /* Enable AES hardware */ + //periph_module_enable(PERIPH_AES_DMA_MODULE); + /* Enable AES hardware */ + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_CRYPTO_AES_CLK_EN | SYSTEM_DMA_CLK_EN); + /* Clear reset on digital signature unit, + otherwise AES unit is held in reset also. */ + REG_CLR_BIT(SYSTEM_PERIP_RST_EN1_REG, + SYSTEM_CRYPTO_AES_RST | SYSTEM_DMA_RST | SYSTEM_CRYPTO_DS_RST); +} + +/* Function to disable AES and Crypto DMA clocks and release locks */ +void esp_aes_release_hardware( void ) +{ + /* Disable AES hardware */ + //periph_module_disable(PERIPH_AES_DMA_MODULE); + /* Disable AES hardware */ + REG_SET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_AES_RST | SYSTEM_DMA_RST); + /* Don't return other units to reset, as this pulls + reset on RSA & SHA units, respectively. */ + REG_CLR_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_CRYPTO_AES_CLK_EN | SYSTEM_DMA_CLK_EN); + + _lock_release(&s_aes_lock); +} + + +/* Function to init AES context to zero */ +void esp_aes_init( esp_aes_context *ctx ) +{ + if ( ctx == NULL ) { + return; + } + + bzero( ctx, sizeof( esp_aes_context ) ); +} + +/* Function to clear AES context */ +void esp_aes_free( esp_aes_context *ctx ) +{ + if ( ctx == NULL ) { + return; + } + + bzero( ctx, sizeof( esp_aes_context ) ); +} + +/* + * AES key schedule (same for encryption or decryption, as hardware handles schedule) + * + */ +int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + if (keybits == 192) { + return MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE; + } + if (keybits != 128 && keybits != 256) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + ctx->key_bytes = keybits / 8; + memcpy(ctx->key, key, ctx->key_bytes); + ctx->key_in_hardware = 0; + return 0; +} + +/* + * Helper function to copy key from esp_aes_context buffer + * to hardware key registers. + * + * Call only while holding esp_aes_acquire_hardware(). + */ +static void esp_aes_setkey_hardware( esp_aes_context *ctx, int crypt_mode) +{ + const uint32_t MODE_DECRYPT_BIT = 4; + unsigned mode_reg_base = (crypt_mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; + + ctx->key_in_hardware = 0; + + for (int i = 0; i < ctx->key_bytes / 4; ++i) { + REG_WRITE(AES_KEY_BASE + i * 4, *(((uint32_t *)ctx->key) + i)); + ctx->key_in_hardware += 4; + } + + REG_WRITE(AES_MODE_REG, mode_reg_base + ((ctx->key_bytes / 8) - 2)); + + /* Fault injection check: all words of key data should have been written to hardware */ + if (ctx->key_in_hardware < 16 + || ctx->key_in_hardware != ctx->key_bytes) { + abort(); + } +} + +/* + * Sets the AES DMA block mode (ECB, CBC, CFB, OFB, GCM, CTR) + * and intializes the required registers for that working mode + */ +static inline void esp_aes_mode_init(esp_aes_mode_t mode) +{ + /* Set the algorithm mode CBC, CFB ... */ + REG_WRITE(AES_BLOCK_MODE_REG, mode); + + /* Presently hard-coding the INC function to 32 bit */ + if (mode == ESP_AES_BLOCK_MODE_CTR) { + REG_WRITE(AES_INC_SEL_REG, 0); + } +} + +/* + * Write IV to hardware iv registers + */ +static inline void esp_aes_set_iv(uint8_t *iv) +{ + uint32_t *iv_words = (uint32_t *)iv; + uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE); + + for (int i = 0; i < IV_WORDS; i++ ) { + REG_WRITE(®_addr_buf[i], iv_words[i]); + } +} + +/* + * Read IV from hardware iv registers + */ +static inline void esp_aes_get_iv(uint8_t *iv) +{ + esp_dport_access_read_buffer((uint32_t *)iv, AES_IV_BASE, IV_WORDS); +} + + +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) +static IRAM_ATTR void esp_aes_complete_isr(void *arg) +{ + BaseType_t higher_woken; + REG_WRITE(AES_INT_CLR_REG, 1); + xSemaphoreGiveFromISR(op_complete_sem, &higher_woken); + if (higher_woken) { + portYIELD_FROM_ISR(); + } +} + +static esp_err_t esp_aes_isr_initialise( void ) +{ + REG_WRITE(AES_INT_CLR_REG, 1); + REG_WRITE(AES_INT_ENA_REG, 1); + if (op_complete_sem == NULL) { + op_complete_sem = xSemaphoreCreateBinary(); + + if (op_complete_sem == NULL) { + ESP_LOGE(TAG, "Failed to create intr semaphore"); + return ESP_FAIL; + } + + esp_intr_alloc(ETS_AES_INTR_SOURCE, 0, esp_aes_complete_isr, NULL, NULL); + } + + /* AES is clocked proportionally to CPU clock, take power management lock */ +#ifdef CONFIG_PM_ENABLE + if (s_pm_cpu_lock == NULL) { + if (esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "aes_sleep", &s_pm_sleep_lock) != ESP_OK) { + ESP_LOGE(TAG, "Failed to create PM sleep lock"); + return ESP_FAIL; + } + if (esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "aes_cpu", &s_pm_cpu_lock) != ESP_OK) { + ESP_LOGE(TAG, "Failed to create PM CPU lock"); + return ESP_FAIL; + } + } + esp_pm_lock_acquire(s_pm_cpu_lock); + esp_pm_lock_acquire(s_pm_sleep_lock); +#endif + + return ESP_OK; +} +#endif // CONFIG_MBEDTLS_AES_USE_INTERRUPT + +/* Wait for AES hardware block operation to complete */ +static void esp_aes_dma_wait_complete(bool use_intr, lldesc_t *output_desc) +{ + __attribute__((unused)) volatile uint32_t dma_done; + +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) + if (use_intr) { + if (!xSemaphoreTake(op_complete_sem, 2000 / portTICK_PERIOD_MS)) { + /* indicates a fundamental problem with driver */ + ESP_LOGE("AES", "Timed out waiting for completion of AES Interrupt"); + abort(); + } +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_release(s_pm_cpu_lock); + esp_pm_lock_release(s_pm_sleep_lock); +#endif // CONFIG_PM_ENABLE + } +#endif + + /* Checking this if interrupt is used also, to avoid + issues with AES fault injection + */ + while (REG_READ(AES_STATE_REG) != AES_STATE_DONE) { + } + + + /* Wait for DMA write operation to complete */ + while (1) { + dma_done = REG_READ(CRYPTO_DMA_INT_RAW_REG); + // Wait for ownership of buffer to be transferred back to CPU + if ( (output_desc->owner == 0) ) { + break; + } + } +} + +/* Init DMA related registers for AES operation */ +static void esp_aes_dma_init(lldesc_t *input, lldesc_t *output) +{ + /* Enable DMA mode */ + REG_WRITE(AES_DMA_ENABLE_REG, 1); + REG_CLR_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN); + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN); + REG_SET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_CLR_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + + /* Initialize DMA registers - this is probably mostly one off initialization + + Note: hardcoded to DMA channel 0 + */ + /* Note: burst mode has alignment requirements that we have not checked here */ + GDMA.conf0[0].outdscr_burst_en = 0; + GDMA.conf0[0].indscr_burst_en = 0; + GDMA.conf0[0].out_data_burst_en = 0; + GDMA.conf0[0].in_data_burst_en = 0; + + GDMA.peri_sel[0].peri_out_sel = DMA_PERIPH_AES; + GDMA.peri_sel[0].peri_in_sel = DMA_PERIPH_AES; + + /* Set descriptor addresses: NOTE BACKWARDS AS DMA IN/OUT is reverse of AES in/out */ + GDMA.out_link[0].addr = (uint32_t)input; + GDMA.in_link[0].addr = (uint32_t)output; + + GDMA.sram_size[0].in_size = 3; /* 40 bytes, also minimum size for EDMA */ + GDMA.sram_size[0].out_size = 3; + GDMA.conf1[0].in_ext_mem_bk_size = 0; // 16 bytes + GDMA.conf1[0].out_ext_mem_bk_size = 0; // 16 bytes + + /* + printf("DESC HEAD pointers IN/outlink %p OUT/inlink / %p\n", in_desc_head, out_desc_head); + + printf("before starting in_desc_head owner %d out_desc_head owner %d INT_RAW 0x%08x\n", + in_desc_head->owner, + out_desc_head->owner, + DMA.int_raw.val); + + */ + + //REG_SET_BIT(EXTMEM_CACHE_MMU_OWNER_REG, 1<<23); //mark PSRAM DCache as belonging to DMA + + GDMA.conf0[0].in_rst = 1; + GDMA.conf0[0].in_rst = 0; + GDMA.conf0[0].out_rst = 1; + GDMA.conf0[0].out_rst = 0; + + /* Start transfer */ + GDMA.out_link[0].start = 1; + GDMA.in_link[0].start = 1; +} + +static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsigned char *output, size_t len, uint8_t *stream_out); + + +/* Output buffers in external ram needs to be 16-byte aligned and DMA cant access input in the iCache mem range, + reallocate them into internal memory and encrypt in chunks to avoid + having to malloc too big of a buffer +*/ + +static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char *input, unsigned char *output, size_t len, uint8_t *stream_out, bool realloc_input, bool realloc_output) +{ + size_t chunk_len; + int ret = 0; + int offset = 0; + unsigned char *input_buf = NULL; + unsigned char *output_buf = NULL; + const unsigned char *dma_input; + chunk_len = MIN(AES_MAX_CHUNK_WRITE_SIZE, len); + + if (realloc_input) { + input_buf = heap_caps_malloc(chunk_len, MALLOC_CAP_DMA); + + if (input_buf == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory"); + ret = -1; + goto cleanup; + } + } + + if (realloc_output) { + output_buf = heap_caps_malloc(chunk_len, MALLOC_CAP_DMA); + + if (output_buf == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory"); + ret = -1; + goto cleanup; + } + } else { + output_buf = output; + } + + while (len) { + chunk_len = MIN(AES_MAX_CHUNK_WRITE_SIZE, len); + + /* If input needs realloc then copy it, else use the input with offset*/ + if (realloc_input) { + memcpy(input_buf, input + offset, chunk_len); + dma_input = input_buf; + } else { + dma_input = input + offset; + } + + if (esp_aes_process_dma(ctx, dma_input, output_buf, chunk_len, stream_out) != 0) { + ret = -1; + goto cleanup; + } + + if (realloc_output) { + memcpy(output + offset, output_buf, chunk_len); + } else { + output_buf = output + offset + chunk_len; + } + + len -= chunk_len; + offset += chunk_len; + } + +cleanup: + + if (realloc_input) { + free(input_buf); + } + if (realloc_output) { + free(output_buf); + } + + return ret; +} + +/* Encrypt/decrypt the input using DMA */ +static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsigned char *output, size_t len, uint8_t *stream_out) +{ + lldesc_t stream_in_desc, stream_out_desc; + lldesc_t *in_desc_head, *out_desc_head; + lldesc_t *block_desc = NULL, *block_in_desc, *block_out_desc; + size_t lldesc_num; + uint8_t stream_in[16] = {}; + unsigned stream_bytes = len % AES_BLOCK_BYTES; // bytes which aren't in a full block + unsigned block_bytes = len - stream_bytes; // bytes which are in a full block + unsigned char *non_icache_input = NULL; + unsigned blocks = (block_bytes / AES_BLOCK_BYTES) + ((stream_bytes > 0) ? 1 : 0); + bool use_intr = false; + bool input_needs_realloc = false; + bool output_needs_realloc = false; + int ret = 0; + + assert(len > 0); // caller shouldn't ever have len set to zero + assert(stream_bytes == 0 || stream_out != NULL); // stream_out can be NULL if we're processing full block(s) + + /* If no key is written to hardware yet, either the user hasn't called + mbedtls_aes_setkey_enc/mbedtls_aes_setkey_dec - meaning we also don't + know which mode to use - or a fault skipped the + key write to hardware. Treat this as a fatal error and zero the output block. + */ + if (ctx->key_in_hardware != ctx->key_bytes) { + bzero(output, len); + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + if (block_bytes > 0) { + /* Flush cache if input in external ram */ +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if (esp_ptr_external_ram(input)) { + Cache_WriteBack_All(); + } + if (esp_ptr_external_ram(output)) { + if (((intptr_t)(output) & 0xF) != 0) { + // Non aligned ext-mem buffer + output_needs_realloc = true; + } + } +#endif + /* DMA cannot access memory in the iCache range, copy input to internal ram */ + if (!esp_ptr_dma_ext_capable(input) && !esp_ptr_dma_capable(input)) { + input_needs_realloc = true; + } + + if (!esp_ptr_dma_ext_capable(output) && !esp_ptr_dma_capable(output)) { + output_needs_realloc = true; + } + + /* If either input or output is unaccessible to the DMA then they need to be reallocated */ + if (input_needs_realloc || output_needs_realloc) { + return esp_aes_process_dma_ext_ram(ctx, input, output, len, stream_out, input_needs_realloc, output_needs_realloc); + } + + + /* Set up dma descriptors for input and output */ + lldesc_num = lldesc_get_required_num(block_bytes); + + /* Allocate both in and out descriptors to save a malloc/free per function call */ + block_desc = heap_caps_malloc(sizeof(lldesc_t) * lldesc_num * 2, MALLOC_CAP_DMA); + if (block_desc == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory"); + ret = -1; + goto cleanup; + } + + block_in_desc = block_desc; + block_out_desc = block_desc + lldesc_num; + + lldesc_setup_link(block_desc, input, block_bytes, 0); + lldesc_setup_link(block_desc + lldesc_num, output, block_bytes, 0); + } + + /* Any leftover bytes which are appended as an additional DMA list */ + if (stream_bytes > 0) { + memcpy(stream_in, input + block_bytes, stream_bytes); + + lldesc_setup_link(&stream_in_desc, stream_in, AES_BLOCK_BYTES, 0); + lldesc_setup_link(&stream_out_desc, stream_out, AES_BLOCK_BYTES, 0); + + if (block_bytes > 0) { + /* Link with block descriptors*/ + block_in_desc[lldesc_num - 1].empty = (uint32_t)&stream_in_desc; + block_out_desc[lldesc_num - 1].empty = (uint32_t)&stream_out_desc; + } + } + + // block buffers are sent to DMA first, unless there aren't any + in_desc_head = (block_bytes > 0) ? block_in_desc : &stream_in_desc; + out_desc_head = (block_bytes > 0) ? block_out_desc : &stream_out_desc; + + esp_aes_dma_init(in_desc_head, out_desc_head); + + /* Write the number of blocks */ + REG_WRITE(AES_BLOCK_NUM_REG, blocks); + + +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) + /* Only use interrupt for long AES operations */ + if (len > AES_DMA_INTR_TRIG_LEN) { + use_intr = true; + if (esp_aes_isr_initialise() == ESP_FAIL) { + ret = -1; + goto cleanup; + } + } else +#endif + { + REG_WRITE(AES_INT_ENA_REG, 0); + } + + /* Start AES operation */ + REG_WRITE(AES_TRIGGER_REG, 1); + esp_aes_dma_wait_complete(use_intr, out_desc_head); + + + +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if (block_bytes > 0) { + if (esp_ptr_external_ram(output)) { + Cache_Invalidate_DCache_All(); + } + } +#endif + + REG_WRITE(AES_DMA_EXIT_REG, 0); + /* Disable DMA mode */ + REG_WRITE(AES_DMA_ENABLE_REG, 0); + + if (stream_bytes > 0) { + memcpy(output + block_bytes, stream_out, stream_bytes); + } + +cleanup: + free(non_icache_input); + free(block_desc); + return ret; +} + + +static int esp_aes_validate_input(esp_aes_context *ctx, const unsigned char *input, + unsigned char *output ) +{ + if (!ctx) { + ESP_LOGE(TAG, "No AES context supplied"); + return -1; + } + if (!input) { + ESP_LOGE(TAG, "No input supplied"); + return -1; + } + if (!output) { + ESP_LOGE(TAG, "No output supplied"); + return -1; + } + + return 0; +} + + +/* + * AES-ECB single block encryption + */ +int esp_internal_aes_encrypt( esp_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int r; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); + esp_aes_release_hardware(); + + return r; +} + +void esp_aes_encrypt( esp_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + esp_internal_aes_encrypt(ctx, input, output); +} + +/* + * AES-ECB single block decryption + */ +int esp_internal_aes_decrypt( esp_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int r; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); + esp_aes_release_hardware(); + + return r; +} + +void esp_aes_decrypt( esp_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + esp_internal_aes_decrypt(ctx, input, output); +} + + +/* + * AES-ECB block encryption/decryption + */ +int esp_aes_crypt_ecb( esp_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + int r; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, mode); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); + esp_aes_release_hardware(); + + return r; +} + +/* + * AES-CBC buffer encryption/decryption + */ +int esp_aes_crypt_cbc( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int r = 0; + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!iv) { + ESP_LOGE(TAG, "No IV supplied"); + return -1; + } + + /* For CBC input length should be multiple of + * AES BLOCK BYTES + * */ + if ( (length % AES_BLOCK_BYTES) || (length == 0) ) { + return ERR_ESP_AES_INVALID_INPUT_LENGTH; + } + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, mode); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_CBC); + esp_aes_set_iv(iv); + + r = esp_aes_process_dma(ctx, input, output, length, NULL); + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + esp_aes_get_iv(iv); + esp_aes_release_hardware(); + + return r; +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int esp_aes_crypt_cfb8( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + int r = 0; + size_t block_bytes = length - (length % AES_BLOCK_BYTES); + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!iv) { + ESP_LOGE(TAG, "No IV supplied"); + return -1; + } + + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + /* The DMA engine will only output correct IV if it runs + full blocks of input in CFB8 mode + */ + esp_aes_acquire_hardware(); + + if (block_bytes > 0) { + + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, mode); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_CFB8); + esp_aes_set_iv(iv); + r = esp_aes_process_dma(ctx, input, output, block_bytes, NULL); + esp_aes_get_iv(iv); + + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + length -= block_bytes; + input += block_bytes; + output += block_bytes; + } + + // Process remaining bytes block-at-a-time in ECB mode + if (length > 0) { + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, MBEDTLS_AES_ENCRYPT); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_ECB); + + while ( length-- ) { + memcpy( ov, iv, 16 ); + + r = esp_aes_process_dma(ctx, iv, iv, AES_BLOCK_BYTES, NULL); + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + if ( mode == MBEDTLS_AES_DECRYPT ) { + ov[16] = *input; + } + + c = *output++ = ( iv[0] ^ *input++ ); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + ov[16] = c; + } + memcpy( iv, ov + 1, 16 ); + } + + } + esp_aes_release_hardware(); + + return r; +} + +/* + * AES-CFB128 buffer encryption/decryption + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) + +{ + uint8_t c; + int r = 0; + size_t stream_bytes = 0; + size_t n; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!iv) { + ESP_LOGE(TAG, "No IV supplied"); + return -1; + } + + if (!iv_off) { + ESP_LOGE(TAG, "No IV offset supplied"); + return -1; + } + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + n = *iv_off; + + /* First process the *iv_off bytes + * which are pending from the previous call to this API + */ + while (n > 0 && length > 0) { + if (mode == MBEDTLS_AES_ENCRYPT) { + iv[n] = *output++ = *input++ ^ iv[n]; + } else { + c = *input++; + *output++ = c ^ iv[n]; + iv[n] = c; + } + n = (n + 1) % AES_BLOCK_BYTES; + length--; + } + + + if (length > 0) { + stream_bytes = length % AES_BLOCK_BYTES; + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, mode); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_CFB128); + esp_aes_set_iv(iv); + + r = esp_aes_process_dma(ctx, input, output, length, iv); + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + if (stream_bytes == 0) { + // if we didn't need the partial 'stream block' then the new IV is in the IV register + esp_aes_get_iv(iv); + } else { + // if we did process a final partial block the new IV is already processed via DMA (and has some bytes of output in it), + // In decrypt mode any partial bytes are output plaintext (iv ^ c) and need to be swapped back to ciphertext (as the next + // block uses ciphertext as its IV input) + // + // Note: It may be more efficient to not process the partial block via DMA in this case. + if (mode == MBEDTLS_AES_DECRYPT) { + memcpy(iv, input + length - stream_bytes, stream_bytes); + } + } + esp_aes_release_hardware(); + } + + *iv_off = n + stream_bytes; + return r; +} + +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ + +int esp_aes_crypt_ofb( esp_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int r = 0; + size_t n; + size_t stream_bytes = 0; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!iv) { + ESP_LOGE(TAG, "No IV supplied"); + return -1; + } + + if (!iv_off) { + ESP_LOGE(TAG, "No IV offset supplied"); + return -1; + } + + n = *iv_off; + + /* If there is an offset then use the output of the previous AES block + (the updated IV) to calculate the new output */ + while (n > 0 && length > 0) { + *output++ = (*input++ ^ iv[n]); + n = (n + 1) & 0xF; + length--; + } + if (length > 0) { + stream_bytes = (length % AES_BLOCK_BYTES); + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT); + esp_aes_mode_init(ESP_AES_BLOCK_MODE_OFB); + esp_aes_set_iv(iv); + + r = esp_aes_process_dma(ctx, input, output, length, iv); + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + esp_aes_get_iv(iv); + esp_aes_release_hardware(); + } + + *iv_off = n + stream_bytes; + + return r; +} + +/* + * AES-CTR buffer encryption/decryption + */ +int esp_aes_crypt_ctr( esp_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int r = 0; + size_t n; + + if (esp_aes_validate_input(ctx, input, output)) { + return -1; + } + + if (!nonce_counter) { + ESP_LOGE(TAG, "No nonce supplied"); + return -1; + } + + if (!nc_off) { + ESP_LOGE(TAG, "No nonce offset supplied"); + return -1; + } + + n = *nc_off; + + if (!valid_key_length(ctx)) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + /* Process any unprocessed bytes left in stream block from + last operation */ + while (n > 0 && length > 0) { + *output++ = (unsigned char)(*input++ ^ stream_block[n]); + n = (n + 1) & 0xF; + length--; + } + + if (length > 0) { + + esp_aes_acquire_hardware(); + ctx->key_in_hardware = 0; + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT); + + esp_aes_mode_init(ESP_AES_BLOCK_MODE_CTR); + esp_aes_set_iv(nonce_counter); + + r = esp_aes_process_dma(ctx, input, output, length, stream_block); + + if (r != 0) { + esp_aes_release_hardware(); + return r; + } + + esp_aes_get_iv(nonce_counter); + + esp_aes_release_hardware(); + + } + *nc_off = n + (length % AES_BLOCK_BYTES); + + return r; +} diff --git a/components/mbedtls/port/esp32s3/bignum.c b/components/mbedtls/port/esp32s3/bignum.c index e69de29bb2..96e20de6b0 100644 --- a/components/mbedtls/port/esp32s3/bignum.c +++ b/components/mbedtls/port/esp32s3/bignum.c @@ -0,0 +1,223 @@ +/** + * \brief Multi-precision integer library, ESP32 S3 hardware accelerated parts + * + * based on mbedTLS implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#include "soc/hwcrypto_periph.h" +#include "driver/periph_ctrl.h" +#include +#include "bignum_impl.h" +#include "soc/dport_reg.h" +#include "soc/system_reg.h" +#include "soc/periph_defs.h" +#include + +size_t esp_mpi_hardware_words(size_t words) +{ + return words; +} + +void esp_mpi_enable_hardware_hw_op( void ) +{ + /* Enable RSA hardware */ + periph_module_enable(PERIPH_RSA_MODULE); + + REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); + + while (DPORT_REG_READ(RSA_QUERY_CLEAN_REG) != 1) { + } + // Note: from enabling RSA clock to here takes about 1.3us + + +} + +void esp_mpi_disable_hardware_hw_op( void ) +{ + REG_SET_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); + + /* Disable RSA hardware */ + periph_module_disable(PERIPH_RSA_MODULE); +} + + +/* Copy mbedTLS MPI bignum 'mpi' to hardware memory block at 'mem_base'. + + If num_words is higher than the number of words in the bignum then + these additional words will be zeroed in the memory buffer. +*/ +static inline void mpi_to_mem_block(uint32_t mem_base, const mbedtls_mpi *mpi, size_t num_words) +{ + uint32_t *pbase = (uint32_t *)mem_base; + uint32_t copy_words = MIN(num_words, mpi->n); + + /* Copy MPI data to memory block registers */ + for (int i = 0; i < copy_words; i++) { + pbase[i] = mpi->p[i]; + } + + /* Zero any remaining memory block data */ + for (int i = copy_words; i < num_words; i++) { + pbase[i] = 0; + } +} + +/* Read mbedTLS MPI bignum back from hardware memory block. + + Reads num_words words from block. +*/ +static inline void mem_block_to_mpi(mbedtls_mpi *x, uint32_t mem_base, int num_words) +{ + + /* Copy data from memory block registers */ + esp_dport_access_read_buffer(x->p, mem_base, num_words); + /* Zero any remaining limbs in the bignum, if the buffer is bigger + than num_words */ + for (size_t i = num_words; i < x->n; i++) { + x->p[i] = 0; + } +} + + + +/* Begin an RSA operation. op_reg specifies which 'START' register + to write to. +*/ +static inline void start_op(uint32_t op_reg) +{ + /* Clear interrupt status */ + DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); + + /* Note: above REG_WRITE includes a memw, so we know any writes + to the memory blocks are also complete. */ + + DPORT_REG_WRITE(op_reg, 1); +} + +/* Wait for an RSA operation to complete. +*/ +static inline void wait_op_complete(void) +{ + while (DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) != 1) + { } + + /* clear the interrupt */ + DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); +} + + +/* Read result from last MPI operation */ +void esp_mpi_read_result_hw_op(mbedtls_mpi *Z, size_t z_words) +{ + wait_op_complete(); + mem_block_to_mpi(Z, RSA_MEM_Z_BLOCK_BASE, z_words); +} + + +/* Z = (X * Y) mod M + + Not an mbedTLS function +*/ +void esp_mpi_mul_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) +{ + DPORT_REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); + + /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ + mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); + mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); + mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); + mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); + DPORT_REG_WRITE(RSA_M_DASH_REG, Mprime); + + start_op(RSA_MOD_MULT_START_REG); +} + +/* Z = (X ^ Y) mod M +*/ +void esp_mpi_exp_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) +{ + size_t y_bits = mbedtls_mpi_bitlen(Y); + + DPORT_REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); + + /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ + mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); + mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); + mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); + mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); + DPORT_REG_WRITE(RSA_M_DASH_REG, Mprime); + + /* Enable acceleration options */ + DPORT_REG_WRITE(RSA_CONSTANT_TIME_REG, 0); + DPORT_REG_WRITE(RSA_SEARCH_OPEN_REG, 1); + DPORT_REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1); + + /* Execute first stage montgomery multiplication */ + start_op(RSA_MODEXP_START_REG); + + DPORT_REG_WRITE(RSA_SEARCH_OPEN_REG, 0); +} + + +/* Z = X * Y */ +void esp_mpi_mul_mpi_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) +{ + /* Copy X (right-extended) & Y (left-extended) to memory block */ + mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); + mpi_to_mem_block(RSA_MEM_Z_BLOCK_BASE + num_words * 4, Y, num_words); + /* NB: as Y is left-extended, we don't zero the bottom words_mult words of Y block. + This is OK for now because zeroing is done by hardware when we do esp_mpi_acquire_hardware(). + */ + DPORT_REG_WRITE(RSA_LENGTH_REG, (num_words * 2 - 1)); + start_op(RSA_MULT_START_REG); +} + + + +/** + * @brief Special-case of (X * Y), where we use hardware montgomery mod + multiplication to calculate result where either A or B are >2048 bits so + can't use the standard multiplication method. + * + */ +void esp_mpi_mult_mpi_failover_mod_mult_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) +{ + /* M = 2^num_words - 1, so block is entirely FF */ + for (int i = 0; i < num_words; i++) { + DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); + } + + /* Mprime = 1 */ + DPORT_REG_WRITE(RSA_M_DASH_REG, 1); + DPORT_REG_WRITE(RSA_LENGTH_REG, num_words - 1); + + /* Load X & Y */ + mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); + mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); + + /* Rinv = 1, write first word */ + DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); + + /* Zero out rest of the Rinv words */ + for (int i = 1; i < num_words; i++) { + DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); + } + + start_op(RSA_MOD_MULT_START_REG); +} diff --git a/components/mbedtls/port/esp32s3/esp_sha1.c b/components/mbedtls/port/esp32s3/esp_sha1.c index e69de29bb2..1890fc7369 100644 --- a/components/mbedtls/port/esp32s3/esp_sha1.c +++ b/components/mbedtls/port/esp32s3/esp_sha1.c @@ -0,0 +1,255 @@ +/* + * SHA-1 implementation with hardware ESP32 support added. + * Uses mbedTLS software implementation for failover when concurrent + * SHA operations are in use. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE LTD + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA1_C) && defined(MBEDTLS_SHA1_ALT) + +#include "mbedtls/sha1.h" + +#include + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#include "esp32s3/sha.h" + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char *)v; while ( n-- ) *p++ = 0; +} + +/* + * 32-bit integer manipulation macros (big endian) + */ + +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} +#endif + +void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_sha1_context ) ); +} + +void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_context ) ); +} + +void mbedtls_sha1_clone( mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src ) +{ + memcpy(dst, src, sizeof(mbedtls_sha1_context)); +} + +/* + * SHA-1 context setup + */ +int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ) +{ + ctx->total[0] = 0; + ctx->total[1] = 0; + + memset( ctx, 0, sizeof( mbedtls_sha1_context ) ); + ctx->mode = SHA1; + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ) +{ + mbedtls_sha1_starts_ret( ctx ); +} +#endif + +static int esp_internal_sha1_dma_process(mbedtls_sha1_context *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + return esp_sha_dma(SHA1, data, len, buf, buf_len, ctx->first_block); +} + +int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ) +{ + int ret; + esp_sha_acquire_hardware(); + ret = esp_sha_dma(ctx->mode, data, 64, 0, 0, ctx->first_block); + esp_sha_release_hardware(); + return ret; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha1_process( mbedtls_sha1_context *ctx, + const unsigned char data[64] ) +{ + mbedtls_internal_sha1_process( ctx, data ); +} +#endif + +int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ) +{ + int ret; + size_t fill; + uint32_t left, len, local_len = 0; + + if ( !ilen || (input == NULL)) { + return 0; + } + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += (uint32_t) ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if ( ctx->total[0] < (uint32_t) ilen ) { + ctx->total[1]++; + } + + if ( left && ilen >= fill ) { + memcpy( (void *) (ctx->buffer + left), input, fill ); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + if ( len || local_len) { + + esp_sha_acquire_hardware(); + + if (ctx->sha_state == ESP_SHA1_STATE_INIT) { + ctx->first_block = true; + ctx->sha_state = ESP_SHA1_STATE_IN_PROCESS; + } else if (ctx->sha_state == ESP_SHA1_STATE_IN_PROCESS) { + ctx->first_block = false; + esp_sha_write_digest_state(SHA1, ctx->state); + } + + ret = esp_internal_sha1_dma_process(ctx, input, len, ctx->buffer, local_len); + + esp_sha_read_digest_state(SHA1, ctx->state); + + esp_sha_release_hardware(); + + if (ret != 0) { + return ret; + } + + } + + if ( ilen > 0 ) { + memcpy( (void *) (ctx->buffer + left), input + len, ilen - len ); + } + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha1_update( mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + mbedtls_sha1_update_ret( ctx, input, ilen ); +} +#endif + +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* +* SHA-1 final digest + */ +int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ) +{ + int ret; + uint32_t last, padn; + uint32_t high, low; + unsigned char msglen[8]; + + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, msglen, 0 ); + PUT_UINT32_BE( low, msglen, 4 ); + + last = ctx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + + if ( ( ret = mbedtls_sha1_update_ret( ctx, sha1_padding, padn ) ) != 0 ) { + return ret; + } + if ( ( ret = mbedtls_sha1_update_ret( ctx, msglen, 8 ) ) != 0 ) { + return ret; + } + + memcpy(output, ctx->state, 20); + + return ret; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, + unsigned char output[20] ) +{ + mbedtls_sha1_finish_ret( ctx, output ); +} +#endif + +#endif /* MBEDTLS_SHA1_C && MBEDTLS_SHA1_ALT */ diff --git a/components/mbedtls/port/esp32s3/esp_sha256.c b/components/mbedtls/port/esp32s3/esp_sha256.c index e69de29bb2..ba1e60753a 100644 --- a/components/mbedtls/port/esp32s3/esp_sha256.c +++ b/components/mbedtls/port/esp32s3/esp_sha256.c @@ -0,0 +1,267 @@ +/* + * SHA-256 implementation with hardware ESP32 support added. + * Uses mbedTLS software implementation for failover when concurrent + * SHA operations are in use. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE LTD + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * The SHA-256 Secure Hash Standard was published by NIST in 2002. + * + * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA256_C) && defined(MBEDTLS_SHA256_ALT) + +#include "mbedtls/sha256.h" + +#include + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#include "esp32s3/sha.h" + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; while ( n-- ) *p++ = 0; +} + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n,b,i) \ +do { \ + (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ + | ( (uint32_t) (b)[(i) + 1] << 16 ) \ + | ( (uint32_t) (b)[(i) + 2] << 8 ) \ + | ( (uint32_t) (b)[(i) + 3] ); \ +} while( 0 ) +#endif + +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +do { \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} while( 0 ) +#endif + +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ) +{ + *dst = *src; +} + +/* + * SHA-256 context setup + */ +int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ) +{ + memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); + + if ( is224 ) { + ctx->mode = SHA2_224; + } else { + ctx->mode = SHA2_256; + } + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, + int is224 ) +{ + mbedtls_sha256_starts_ret( ctx, is224 ); +} +#endif + + +int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ) +{ + int ret; + esp_sha_acquire_hardware(); + ret = esp_sha_dma(ctx->mode, data, 64, 0, 0, ctx->first_block); + esp_sha_release_hardware(); + + return ret; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ) +{ + mbedtls_internal_sha256_process( ctx, data ); +} +#endif + +/* + * SHA-256 process buffer + */ +int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, + size_t ilen ) +{ + int ret = 0; + size_t fill; + uint32_t left, len, local_len = 0; + + if ( ilen == 0 ) { + return 0; + } + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += (uint32_t) ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if ( ctx->total[0] < (uint32_t) ilen ) { + ctx->total[1]++; + } + + /* Check if any data pending from previous call to this API */ + if ( left && ilen >= fill ) { + memcpy( (void *) (ctx->buffer + left), input, fill ); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + + if ( len || local_len) { + esp_sha_acquire_hardware(); + + if (ctx->sha_state == ESP_SHA256_STATE_INIT) { + ctx->first_block = true; + ctx->sha_state = ESP_SHA256_STATE_IN_PROCESS; + } else if (ctx->sha_state == ESP_SHA256_STATE_IN_PROCESS) { + ctx->first_block = false; + esp_sha_write_digest_state(ctx->mode, ctx->state); + } + + ret = esp_sha_dma(ctx->mode, input, len, ctx->buffer, local_len, ctx->first_block); + + esp_sha_read_digest_state(ctx->mode, ctx->state); + + esp_sha_release_hardware(); + + if (ret != 0) { + return ret; + } + } + + if ( ilen > 0 ) { + memcpy( (void *) (ctx->buffer + left), input + len, ilen - len ); + } + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_update( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + mbedtls_sha256_update_ret( ctx, input, ilen ); +} +#endif + +static const unsigned char sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* + * SHA-256 final digest + */ +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ) +{ + int ret; + uint32_t last, padn; + uint32_t high, low; + unsigned char msglen[8]; + + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, msglen, 0 ); + PUT_UINT32_BE( low, msglen, 4 ); + + last = ctx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + if ( ( ret = mbedtls_sha256_update_ret( ctx, sha256_padding, padn ) ) != 0 ) { + return ret; + } + + if ( ( ret = mbedtls_sha256_update_ret( ctx, msglen, 8 ) ) != 0 ) { + return ret; + } + + memcpy(output, ctx->state, 32); + + return ret; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, + unsigned char output[32] ) +{ + mbedtls_sha256_finish_ret( ctx, output ); +} +#endif + +#endif /* MBEDTLS_SHA256_C && MBEDTLS_SHA256_ALT */ diff --git a/components/mbedtls/port/esp32s3/esp_sha512.c b/components/mbedtls/port/esp32s3/esp_sha512.c index e69de29bb2..20a43ad03c 100644 --- a/components/mbedtls/port/esp32s3/esp_sha512.c +++ b/components/mbedtls/port/esp32s3/esp_sha512.c @@ -0,0 +1,317 @@ +/* + * SHA-512 implementation with hardware ESP32 support added. + * Uses mbedTLS software implementation for failover when concurrent + * SHA operations are in use. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE LTD + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * The SHA-512 Secure Hash Standard was published by NIST in 2002. + * + * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA512_C) && defined(MBEDTLS_SHA512_ALT) + +#include "mbedtls/sha512.h" + +#if defined(_MSC_VER) || defined(__WATCOMC__) +#define UL64(x) x##ui64 +#else +#define UL64(x) x##ULL +#endif + +#include + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#include "esp32s3/sha.h" + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; while ( n-- ) *p++ = 0; +} + +/* + * 64-bit integer manipulation macros (big endian) + */ +#ifndef PUT_UINT64_BE +#define PUT_UINT64_BE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( (n) >> 56 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 48 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 40 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 32 ); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 7] = (unsigned char) ( (n) ); \ +} +#endif /* PUT_UINT64_BE */ + +void esp_sha512_set_mode(mbedtls_sha512_context *ctx, esp_sha_type type) +{ + switch (type) { + case SHA2_384: + case SHA2_512224: + case SHA2_512256: + case SHA2_512T: + ctx->mode = type; + break; + default: + ctx->mode = SHA2_512; + break; + } +} + + +/* For SHA512/t mode the intial hash value will depend on t */ +void esp_sha512_set_t( mbedtls_sha512_context *ctx, uint16_t t_val) +{ + ctx->t_val = t_val; +} + +void mbedtls_sha512_init( mbedtls_sha512_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_sha512_context ) ); +} + +void mbedtls_sha512_free( mbedtls_sha512_context *ctx ) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_zeroize( ctx, sizeof( mbedtls_sha512_context ) ); +} + +void mbedtls_sha512_clone( mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src ) +{ + memcpy(dst, src, sizeof(mbedtls_sha512_context)); +} + +/* + * SHA-512 context setup + */ +int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ) +{ + mbedtls_zeroize( ctx, sizeof( mbedtls_sha512_context ) ); + + if ( is384 ) { + ctx->mode = SHA2_384; + } else { + ctx->mode = SHA2_512; + } + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, + int is384 ) +{ + mbedtls_sha512_starts_ret( ctx, is384 ); +} +#endif + +static int esp_internal_sha512_dma_process(mbedtls_sha512_context *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + + + return esp_sha_dma(ctx->mode, data, len, buf, buf_len, ctx->first_block); + + +} + +int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ) +{ + int ret; + esp_sha_acquire_hardware(); + ret = esp_internal_sha512_dma_process(ctx, data, 128, 0, 0); + esp_sha_release_hardware(); + + return ret; + +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_process( mbedtls_sha512_context *ctx, + const unsigned char data[128] ) +{ + mbedtls_internal_sha512_process( ctx, data ); +} +#endif + +/* + * SHA-512 process buffer + */ +int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char *input, + size_t ilen ) +{ + int ret; + size_t fill; + unsigned int left, len, local_len = 0; + + if ( ilen == 0 ) { + return 0; + } + + left = (unsigned int) (ctx->total[0] & 0x7F); + fill = 128 - left; + + ctx->total[0] += (uint64_t) ilen; + + if ( ctx->total[0] < (uint64_t) ilen ) { + ctx->total[1]++; + } + + if ( left && ilen >= fill ) { + memcpy( (void *) (ctx->buffer + left), input, fill ); + + input += fill; + ilen -= fill; + left = 0; + local_len = 128; + } + + len = (ilen / 128) * 128; + + if ( len || local_len) { + + esp_sha_acquire_hardware(); + + if (ctx->sha_state == ESP_SHA512_STATE_INIT) { + + if (ctx->mode == SHA2_512T) { + esp_sha_512_t_init_hash(ctx->t_val); + ctx->first_block = false; + } else { + ctx->first_block = true; + } + ctx->sha_state = ESP_SHA512_STATE_IN_PROCESS; + + } else if (ctx->sha_state == ESP_SHA512_STATE_IN_PROCESS) { + ctx->first_block = false; + esp_sha_write_digest_state(ctx->mode, ctx->state); + } + + ret = esp_internal_sha512_dma_process(ctx, input, len, ctx->buffer, local_len); + + esp_sha_read_digest_state(ctx->mode, ctx->state); + + esp_sha_release_hardware(); + + if (ret != 0) { + return ret; + } + + } + + + if ( ilen > 0 ) { + memcpy( (void *) (ctx->buffer + left), input + len, ilen - len ); + } + + return 0; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_update( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + mbedtls_sha512_update_ret( ctx, input, ilen ); +} +#endif + + +static const unsigned char sha512_padding[128] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* + * SHA-512 final digest + */ +int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, unsigned char output[64] ) +{ + int ret; + size_t last, padn; + uint64_t high, low; + unsigned char msglen[16]; + + high = ( ctx->total[0] >> 61 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT64_BE( high, msglen, 0 ); + PUT_UINT64_BE( low, msglen, 8 ); + + last = (size_t)( ctx->total[0] & 0x7F ); + padn = ( last < 112 ) ? ( 112 - last ) : ( 240 - last ); + + if ( ( ret = mbedtls_sha512_update_ret( ctx, sha512_padding, padn ) ) != 0 ) { + return ret; + } + + if ( ( ret = mbedtls_sha512_update_ret( ctx, msglen, 16 ) ) != 0 ) { + return ret; + } + + if (ctx->mode == SHA2_384) { + memcpy(output, ctx->state, 48); + } else { + memcpy(output, ctx->state, 64); + } + + return ret; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, + unsigned char output[64] ) +{ + mbedtls_sha512_finish_ret( ctx, output ); +} +#endif + +#endif /* MBEDTLS_SHA512_C && MBEDTLS_SHA512_ALT */ diff --git a/components/mbedtls/port/esp32s3/sha.c b/components/mbedtls/port/esp32s3/sha.c index e69de29bb2..e2dc8ff20a 100644 --- a/components/mbedtls/port/esp32s3/sha.c +++ b/components/mbedtls/port/esp32s3/sha.c @@ -0,0 +1,384 @@ +/* + * ESP32 hardware accelerated SHA1/256/512 implementation + * based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ + +typedef int _lock_t; + +#include +#include +#include +#include "esp_err.h" +#include "esp_log.h" +#include "esp32s3/rom/ets_sys.h" +#include "soc/dport_reg.h" +#include "soc/hwcrypto_reg.h" +#include "soc/soc_memory_layout.h" + +#include "esp32s3/rom/cache.h" + +#include "soc/cache_memory.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +#include "esp32s3/sha.h" +#include "esp32s3/rom/lldesc.h" +#include "soc/periph_defs.h" +#include "driver/periph_ctrl.h" +#include "sys/param.h" +#include "soc/gdma_struct.h" +#include "soc/extmem_reg.h" + +#define DMA_PERIPH_AES 6 /* DMA peripheral indexes */ +#define DMA_PERIPH_SHA 7 +#define DMA_CHANNEL 1 /* note: hard-coded */ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SHA_DMA_MAX_BYTES 3968 + +/* Lock for SHA engine */ +static _lock_t s_sha_lock; + +const static char *TAG = "esp-sha"; + +inline static size_t block_length(esp_sha_type type) +{ + switch (type) { + case SHA1: + case SHA2_224: + case SHA2_256: + return 64; + case SHA2_384: + case SHA2_512: + case SHA2_512224: + case SHA2_512256: + case SHA2_512T: + return 128; + default: + return 0; + } +} + +/* Return state size (in bytes) for a given SHA type */ +inline static size_t state_length(esp_sha_type type) +{ + switch (type) { + case SHA1: + return 160 / 8; + case SHA2_224: + case SHA2_256: + return 256 / 8; + case SHA2_384: + case SHA2_512: + case SHA2_512224: + case SHA2_512256: + case SHA2_512T: + return 512 / 8; + default: + return 0; + } +} + +/* Enable SHA peripheral and then lock it */ +void esp_sha_acquire_hardware() +{ + _lock_acquire(&s_sha_lock); + + /* Enable SHA and DMA hardware */ + //periph_module_enable(PERIPH_SHA_DMA_MODULE); + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_CRYPTO_SHA_CLK_EN | SYSTEM_DMA_CLK_EN); + REG_CLR_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_HMAC_RST | + SYSTEM_DMA_RST | SYSTEM_CRYPTO_DS_RST); + + +} + +/* Disable SHA peripheral block and then release it */ +void esp_sha_release_hardware() +{ + /* Disable SHA and DMA hardware */ + //periph_module_disable(PERIPH_SHA_MODULE); + REG_SET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_SHA_RST | SYSTEM_DMA_RST | + SYSTEM_CRYPTO_DS_RST); + REG_CLR_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_CRYPTO_SHA_CLK_EN | SYSTEM_DMA_CLK_EN); + + _lock_release(&s_sha_lock); + +} + + +/* Busy wait until SHA is idle */ +static void esp_sha_wait_idle(void) +{ + while (DPORT_REG_READ(SHA_BUSY_REG) != 0) { + } +} + + +void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE); + + for (int i = 0; i < state_length(sha_type) / 4; i++) { + REG_WRITE(®_addr_buf[i], digest_state_words[i]); + } +} + +/* Read the SHA digest from hardware */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + int word_len = state_length(sha_type) / 4; + + esp_dport_access_read_buffer(digest_state_words, SHA_H_BASE, word_len); + + /* Fault injection check: verify SHA engine actually ran, + state is not all zeroes. + */ + for (int i = 0; i < word_len; i++) { + if (digest_state_words[i] != 0) { + return; + } + } + abort(); // SHA peripheral returned all zero state, probably due to fault injection +} + + +static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block); + +/* Performs SHA on multiple blocks at a time using DMA + splits up into smaller operations for inputs that exceed a single DMA list + */ +int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block) +{ + int ret = 0; + const void *dma_input; + unsigned char *non_icache_input = NULL; + unsigned char *non_icache_buf = NULL; + int dma_op_num = ( ilen / (SHA_DMA_MAX_BYTES + 1) ) + 1; + + if (buf_len > 128) { + ESP_LOGE(TAG, "SHA DMA buf_len cannot exceed max size for a single block"); + return -1; + } + + /* DMA cannot access memory in the iCache range, copy data to temporary buffers before transfer */ + if (!esp_ptr_dma_capable(input) && ilen) { + non_icache_input = malloc(sizeof(unsigned char) * MIN(ilen, SHA_DMA_MAX_BYTES)); + if (non_icache_input == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory"); + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + } + + if (!esp_ptr_dma_capable(buf) && buf_len) { + non_icache_buf = malloc(sizeof(unsigned char) * buf_len); + if (non_icache_buf == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory"); + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + memcpy(non_icache_buf, buf, buf_len); + buf = non_icache_buf; + } + + /* The max amount of blocks in a single hardware operation is 2^6 - 1 = 63 + Thus we only do a single DMA input list + dma buf list, + which is max 3968/64 + 64/64 = 63 blocks */ + for (int i = 0; i < dma_op_num; i++) { + int dma_chunk_len = MIN(ilen, SHA_DMA_MAX_BYTES); + + + /* Input depends on if it's a temp alloc buffer or supplied by user */ + if (non_icache_input != NULL) { + memcpy(non_icache_input, input, dma_chunk_len); + dma_input = non_icache_input; + } else { + dma_input = input; + } + + ret = esp_sha_dma_process(sha_type, dma_input, dma_chunk_len, buf, buf_len, is_first_block); + + + if (ret != 0) { + return ret; + } + + is_first_block = false; + + + ilen -= dma_chunk_len; + input += dma_chunk_len; + + // Only append buf to the first operation + buf_len = 0; + } + +cleanup: + free(non_icache_input); + free(non_icache_buf); + return ret; +} + +static void esp_sha_dma_init(lldesc_t *input) +{ + /* Reset DMA */ + REG_CLR_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN); + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN); + REG_SET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_CLR_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + + /* NOTE: all hardcoded to DMA channel 1 */ + /* Note: burst mode has alignment requirements that we have not checked here */ + GDMA.conf0[0].outdscr_burst_en = 0; /* was 1*/ + GDMA.conf0[0].out_data_burst_en = 0; /* was 1*/ + GDMA.conf0[0].out_auto_wrback = 0; + + GDMA.peri_sel[0].peri_out_sel = DMA_PERIPH_SHA; + + GDMA.sram_size[0].in_size = 3; /* 40 bytes, also minimum size for EDMA */ + GDMA.sram_size[0].out_size = 3; + GDMA.conf1[0].in_ext_mem_bk_size = 0; // 16 bytes + GDMA.conf1[0].out_ext_mem_bk_size = 0; // 16 bytes + + /* Set descriptors */ + GDMA.out_link[0].addr = (uint32_t)input; + + GDMA.conf0[0].in_rst = 1; + GDMA.conf0[0].in_rst = 0; + GDMA.conf0[0].out_rst = 1; + GDMA.conf0[0].out_rst = 0; + + /* Start transfer */ + GDMA.out_link[0].start = 1; +} + +/* The initial hash value for SHA512/t is generated according to the + algorithm described in the TRM, chapter SHA-Accelerator +*/ +int esp_sha_512_t_init_hash(uint16_t t) +{ + uint32_t t_string = 0; + uint8_t t0, t1, t2, t_len; + + if (t == 384) { + ESP_LOGE(TAG, "Invalid t for SHA512/t, t = %u,cannot be 384", t); + return -1; + } + + if (t <= 9) { + t_string = (uint32_t)((1 << 23) | ((0x30 + t) << 24)); + t_len = 0x48; + } else if (t <= 99) { + t0 = t % 10; + t1 = (t / 10) % 10; + t_string = (uint32_t)((1 << 15) | ((0x30 + t0) << 16) | + (((0x30 + t1) << 24))); + t_len = 0x50; + } else if (t <= 512) { + t0 = t % 10; + t1 = (t / 10) % 10; + t2 = t / 100; + t_string = (uint32_t)((1 << 7) | ((0x30 + t0) << 8) | + (((0x30 + t1) << 16) + ((0x30 + t2) << 24))); + t_len = 0x58; + } else { + ESP_LOGE(TAG, "Invalid t for SHA512/t, t = %u, must equal or less than 512", t); + return -1; + } + + REG_WRITE(SHA_T_LENGTH_REG, t_len); + REG_WRITE(SHA_T_STRING_REG, t_string); + REG_WRITE(SHA_MODE_REG, SHA2_512T); + REG_WRITE(SHA_START_REG, 1); + + esp_sha_wait_idle(); + + return 0; +} + +/* Performs SHA on multiple blocks at a time */ +static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block) +{ + size_t blk_len = 0; + int ret = 0; + lldesc_t dma_descr_input = {}; + lldesc_t dma_descr_buf = {}; + lldesc_t *dma_descr_head; + + blk_len = block_length(sha_type); + + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_BLOCK_NUM_REG, ((ilen + buf_len) / blk_len)); + + + /* DMA descriptor for Memory to DMA-SHA transfer */ + if (ilen) { + dma_descr_input.length = ilen; + dma_descr_input.size = ilen; + dma_descr_input.owner = 1; + dma_descr_input.eof = 1; + dma_descr_input.buf = (void *)input; + dma_descr_head = &dma_descr_input; + } + /* Check after input to overide head if there is any buf*/ + if (buf_len) { + dma_descr_buf.length = buf_len; + dma_descr_buf.size = buf_len; + dma_descr_buf.owner = 1; + dma_descr_buf.eof = 1; + dma_descr_buf.buf = (void *)buf; + dma_descr_head = &dma_descr_buf; + } + + /* Link DMA lists */ + if (buf_len && ilen) { + dma_descr_buf.eof = 0; + dma_descr_buf.empty = (uint32_t)(&dma_descr_input); + } + + esp_sha_dma_init(dma_descr_head); + + /* Start hashing */ + if (is_first_block) { + REG_WRITE(SHA_DMA_START_REG, 1); + } else { + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); + } + + esp_sha_wait_idle(); + + return ret; +} + diff --git a/components/mbedtls/port/esp_aes_xts.c b/components/mbedtls/port/esp_aes_xts.c index 18d001b806..0c5b64558c 100644 --- a/components/mbedtls/port/esp_aes_xts.c +++ b/components/mbedtls/port/esp_aes_xts.c @@ -40,10 +40,16 @@ #if CONFIG_IDF_TARGET_ESP32 #include "esp32/aes.h" -#elif CONFIG_IDF_TARGET_ESP32S2 +#endif + +#if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/aes.h" #endif +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/aes.h" +#endif + void esp_aes_xts_init( esp_aes_xts_context *ctx ) { esp_aes_init( &ctx->crypt ); diff --git a/components/mbedtls/test/test_aes.c b/components/mbedtls/test/test_aes.c index aaa2f5f5f6..b28366e06c 100644 --- a/components/mbedtls/test/test_aes.c +++ b/components/mbedtls/test/test_aes.c @@ -12,6 +12,284 @@ #include "esp_heap_caps.h" #include "test_utils.h" +static const uint8_t key_256[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, +}; + +static const uint8_t iv[] = { + 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, +}; + +/* Cipher produced via this Python: + from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes + from cryptography.hazmat.backends import default_backend + + def as_c_array(byte_arr): + + hex_str = '' + for idx, byte in enumerate(byte_arr): + hex_str += "0x{:02x}, ".format(byte) + bytes_per_line = 8 + if idx % bytes_per_line == bytes_per_line - 1: + hex_str += '\n' + + return hex_str + + key = bytearray(range(32)) + iv = bytearray(range(16, 0, -1)) + + print("Key: \n{}".format(as_c_array(key))) + print("IV: \n{}".format(as_c_array(iv))) + + # Replace CTR with desired mode + cipher = Cipher(algorithms.AES(key), modes.CTR(iv), backend=default_backend()) + encryptor = cipher.encryptor() + + input_len = 1000 + + plain = b'\x3A'*input_len + print(as_c_array(plain)) + ct = encryptor.update(plain) + encryptor.finalize() + + print("Chipertext: {}".format(as_c_array(ct))) +*/ +TEST_CASE("mbedtls CBC AES-256 test", "[aes]") +{ + const unsigned SZ = 1600; + mbedtls_aes_context ctx; + uint8_t nonce[16]; + + const uint8_t expected_cipher_end[] = { + 0x3e, 0x68, 0x8a, 0x02, 0xe6, 0xf2, 0x6a, 0x9e, + 0x9b, 0xb2, 0xc0, 0xc4, 0x63, 0x63, 0xd9, 0x25, + 0x51, 0xdc, 0xc2, 0x71, 0x96, 0xb3, 0xe5, 0xcd, + 0xbd, 0x0e, 0xf2, 0xef, 0xa9, 0xab, 0xab, 0x2d, + }; + + memcpy(nonce, iv, 16); + + // allocate internal memory + uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + + TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(plaintext); + TEST_ASSERT_NOT_NULL(decryptedtext); + + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, key_256, 256); + + memset(plaintext, 0x3A, SZ); + memset(decryptedtext, 0x0, SZ); + + // Encrypt + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + + // Decrypt + memcpy(nonce, iv, 16); + mbedtls_aes_setkey_dec(&ctx, key_256, 256); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); + + free(plaintext); + free(chipertext); + free(decryptedtext); +} + +TEST_CASE("mbedtls CTR AES-256 test", "[aes]") +{ + const unsigned SZ = 1000; + mbedtls_aes_context ctx; + uint8_t nonce[16]; + uint8_t stream_block[16]; + size_t nc_off = 0; + + const uint8_t expected_cipher_end[] = { + 0xd4, 0xdc, 0x4f, 0x8f, 0xfe, 0x86, 0xee, 0xb5, + 0x14, 0x7f, 0xba, 0x30, 0x25, 0xa6, 0x7f, 0x6c, + 0xb5, 0x73, 0xaf, 0x90, 0xd7, 0xff, 0x36, 0xba, + 0x2b, 0x1d, 0xec, 0xb9, 0x38, 0xfa, 0x0d, 0xeb, + }; + + memcpy(nonce, iv, 16); + + // allocate internal memory + uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + + TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(plaintext); + TEST_ASSERT_NOT_NULL(decryptedtext); + + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, key_256, 256); + + memset(plaintext, 0x3A, SZ); + memset(decryptedtext, 0x0, SZ); + + // Encrypt + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, chipertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + + // Decrypt + nc_off = 0; + memcpy(nonce, iv, 16); + mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, chipertext, decryptedtext); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); + + free(plaintext); + free(chipertext); + free(decryptedtext); +} + +TEST_CASE("mbedtls OFB AES-256 test", "[aes]") +{ + const unsigned SZ = 1000; + mbedtls_aes_context ctx; + uint8_t nonce[16]; + size_t nc_off = 0; + + const uint8_t expected_cipher_end[] = { + 0xca, 0xc3, 0x05, 0x77, 0xae, 0xb9, 0x38, 0xd6, + 0x03, 0x0a, 0xad, 0x90, 0x6e, 0xdd, 0xf3, 0x9a, + 0x41, 0x4d, 0x71, 0x30, 0x04, 0x9f, 0xd3, 0x53, + 0xb7, 0x5e, 0xb4, 0xfd, 0x93, 0xf8, 0x31, 0x6a, + }; + + memcpy(nonce, iv, 16); + + // allocate internal memory + uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + + TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(plaintext); + TEST_ASSERT_NOT_NULL(decryptedtext); + + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, key_256, 256); + + memset(plaintext, 0x3A, SZ); + memset(decryptedtext, 0x0, SZ); + + // Encrypt + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + + // Decrypt + nc_off = 0; + memcpy(nonce, iv, 16); + mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); + + free(plaintext); + free(chipertext); + free(decryptedtext); +} + +TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]") +{ + const unsigned SZ = 1000; + mbedtls_aes_context ctx; + uint8_t nonce[16]; + + const uint8_t expected_cipher_end[] = { + 0x69, 0xdc, 0x1d, 0x8a, 0x0b, 0x9e, 0xbc, 0x84, + 0x29, 0xa2, 0x04, 0xb6, 0x91, 0x6b, 0xb2, 0x83, + 0x13, 0x23, 0x54, 0xcb, 0xf9, 0x6d, 0xcc, 0x53, + 0x04, 0x59, 0xd1, 0xc9, 0xff, 0xab, 0xe2, 0x37, + }; + + memcpy(nonce, iv, 16); + + // allocate internal memory + uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + + TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(plaintext); + TEST_ASSERT_NOT_NULL(decryptedtext); + + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, key_256, 256); + + memset(plaintext, 0x3A, SZ); + memset(decryptedtext, 0x0, SZ); + + // Encrypt + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + + // Decrypt + memcpy(nonce, iv, 16); + mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); + + free(plaintext); + free(chipertext); + free(decryptedtext); +} + +TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]") +{ + const unsigned SZ = 1000; + mbedtls_aes_context ctx; + uint8_t nonce[16]; + size_t nc_off = 0; + + const uint8_t expected_cipher_end[] = { + 0xf3, 0x64, 0x20, 0xa1, 0x70, 0x2a, 0xd9, 0x3f, + 0xb7, 0x48, 0x8c, 0x2c, 0x1f, 0x65, 0x53, 0xc2, + 0xac, 0xfd, 0x82, 0xe5, 0x31, 0x24, 0x1f, 0x30, + 0xaf, 0xcc, 0x8d, 0xb3, 0xf3, 0x63, 0xe1, 0xa0, + }; + + memcpy(nonce, iv, 16); + + // allocate internal memory + uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + + TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(plaintext); + TEST_ASSERT_NOT_NULL(decryptedtext); + + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, key_256, 256); + + memset(plaintext, 0x3A, SZ); + memset(decryptedtext, 0x0, SZ); + + // Encrypt + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, SZ, &nc_off, nonce, plaintext, chipertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + + // Decrypt + nc_off = 0; + memcpy(nonce, iv, 16); + mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, chipertext, decryptedtext); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); + + free(plaintext); + free(chipertext); + free(decryptedtext); +} + TEST_CASE("mbedtls CTR stream test", "[aes]") { const unsigned SZ = 100; @@ -79,11 +357,11 @@ TEST_CASE("mbedtls CTR stream test", "[aes]") memset(decryptedtext, 0x0, SZ); size_t offset = 0; - // Encrypt for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) { // Limit length of last call to avoid exceeding buffer size size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process; + mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce, stream_block, plaintext + idx, chipertext + idx ); } From 9fa06719faa9d9b2d5e1f2bfb3acecb26b8c9437 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 20 Aug 2020 12:22:36 +0800 Subject: [PATCH 10/11] global: enable build uinit test for esp32-s3 --- components/driver/test/adc_dma_test/test_esp32.c | 2 +- components/driver/test/adc_dma_test/test_esp32s2.c | 2 +- components/driver/test/dac_dma_test/test_esp32.c | 2 +- components/driver/test/dac_dma_test/test_esp32s2.c | 2 +- components/driver/test/test_adc2_with_wifi.c | 4 ++++ components/driver/test/test_adc_common.c | 6 +++++- components/driver/test/test_common_spi.c | 6 +++++- components/driver/test/test_dac.c | 3 +++ components/driver/test/test_gpio.c | 4 ++++ components/driver/test/test_i2c.c | 3 +++ components/driver/test/test_i2s.c | 4 ++++ components/driver/test/test_ledc.c | 4 ++++ components/driver/test/test_pcnt.c | 6 +++++- components/driver/test/test_pwm.c | 6 +++++- components/driver/test/test_rmt.c | 4 ++++ components/driver/test/test_rs485.c | 6 +++++- components/driver/test/test_rtcio.c | 6 +++++- components/driver/test/test_sdio.c | 6 +++++- components/driver/test/test_sigmadelta.c | 4 ++++ components/driver/test/test_spi_bus_lock.c | 3 +++ components/driver/test/test_spi_master.c | 3 +++ components/driver/test/test_spi_param.c | 4 ++++ components/driver/test/test_spi_sio.c | 3 +++ components/driver/test/test_spi_slave.c | 4 ++++ components/driver/test/test_spi_slave_hd.c | 5 ++++- components/driver/test/test_timer.c | 4 ++++ components/driver/test/test_uart.c | 4 ++++ components/driver/test/touch_sensor_test/test_esp32.c | 2 +- components/driver/test/touch_sensor_test/test_esp32s2.c | 2 +- components/efuse/test/test_efuse.c | 4 ++++ components/esp_eth/test/test_emac.c | 4 +++- components/newlib/test/test_time.c | 8 +++++++- components/soc/test/test_rtc_clk.c | 2 +- components/ulp/test/CMakeLists.txt | 3 +++ components/wear_levelling/test/test_wl.c | 6 ++++-- docs/en/api-guides/tools/idf-tools-notes.inc | 5 +++++ docs/zh_CN/api-guides/tools/idf-tools-notes.inc | 5 +++++ .../test/test_cxx_exceptions.cpp | 2 +- .../experimental_cpp_component/test/test_i2c.cpp | 3 +-- tools/ci/config/build.yml | 5 +++++ tools/ci/config/target-test.yml | 2 +- tools/ci/python_packages/ttfw_idf/CIScanTests.py | 4 +++- tools/ci/python_packages/ttfw_idf/IDFAssignTest.py | 4 +++- tools/find_build_apps/cmake.py | 2 ++ tools/idf_size.py | 4 ++++ .../components/test_utils/test/ccomp_timer_test_data.c | 4 +++- .../components/test_utils/test/ccomp_timer_test_inst.c | 2 +- tools/unit-test-app/sdkconfig.defaults.esp32s3 | 1 + 48 files changed, 157 insertions(+), 27 deletions(-) create mode 100644 tools/unit-test-app/sdkconfig.defaults.esp32s3 diff --git a/components/driver/test/adc_dma_test/test_esp32.c b/components/driver/test/adc_dma_test/test_esp32.c index 134bbe1785..27bf9183af 100644 --- a/components/driver/test/adc_dma_test/test_esp32.c +++ b/components/driver/test/adc_dma_test/test_esp32.c @@ -29,7 +29,7 @@ #include "test_utils.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2) // This testcase for ESP32 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2, ESP32S3) // This testcase for ESP32 /* * ADC DMA testcase diff --git a/components/driver/test/adc_dma_test/test_esp32s2.c b/components/driver/test/adc_dma_test/test_esp32s2.c index e875c1bfe5..c04b728e6c 100644 --- a/components/driver/test/adc_dma_test/test_esp32s2.c +++ b/components/driver/test/adc_dma_test/test_esp32s2.c @@ -36,7 +36,7 @@ #include "test/test_common_adc.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32, ESP32S3) // This testcase for ESP32S2 #include "soc/system_reg.h" #include "soc/lldesc.h" diff --git a/components/driver/test/dac_dma_test/test_esp32.c b/components/driver/test/dac_dma_test/test_esp32.c index f4fd57af70..7a02da9281 100644 --- a/components/driver/test/dac_dma_test/test_esp32.c +++ b/components/driver/test/dac_dma_test/test_esp32.c @@ -31,7 +31,7 @@ #include "test_dac_audio_file.h" #include "driver/i2s.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2) // This testcase for ESP32 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2, ESP32S3) // This testcase for ESP32 /* * DAC DMA config. diff --git a/components/driver/test/dac_dma_test/test_esp32s2.c b/components/driver/test/dac_dma_test/test_esp32s2.c index 02fcbbcf47..7b84a32fef 100644 --- a/components/driver/test/dac_dma_test/test_esp32s2.c +++ b/components/driver/test/dac_dma_test/test_esp32s2.c @@ -37,7 +37,7 @@ #include "soc/dac_periph.h" #include "test/test_common_adc.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32, ESP32S3) // This testcase for ESP32S2 #include "soc/system_reg.h" #include "esp32s2/rom/lldesc.h" diff --git a/components/driver/test/test_adc2_with_wifi.c b/components/driver/test/test_adc2_with_wifi.c index 080d05eef4..1b709665b2 100644 --- a/components/driver/test/test_adc2_with_wifi.c +++ b/components/driver/test/test_adc2_with_wifi.c @@ -12,6 +12,8 @@ #include "nvs_flash.h" #include "test_utils.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + static const char* TAG = "test_adc2"; #ifdef CONFIG_IDF_TARGET_ESP32 @@ -165,3 +167,5 @@ TEST_CASE("adc2 work with wifi","[adc]") TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); } + +#endif diff --git a/components/driver/test/test_adc_common.c b/components/driver/test/test_adc_common.c index 2b7929f553..c269a466e9 100644 --- a/components/driver/test/test_adc_common.c +++ b/components/driver/test/test_adc_common.c @@ -15,6 +15,8 @@ #include "test_utils.h" #include "soc/adc_periph.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + static const char *TAG = "test_adc"; #ifdef CONFIG_IDF_TARGET_ESP32 @@ -382,4 +384,6 @@ void test_adc_slope_debug(void) vTaskDelay(SCOPE_DEBUG_FREQ_MS / portTICK_RATE_MS); } #endif -} \ No newline at end of file +} + +#endif \ No newline at end of file diff --git a/components/driver/test/test_common_spi.c b/components/driver/test/test_common_spi.c index 59bfc49e3e..07ca8c7584 100644 --- a/components/driver/test/test_common_spi.c +++ b/components/driver/test/test_common_spi.c @@ -3,6 +3,8 @@ #include "esp_log.h" #include "driver/gpio.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + int test_freq_default[]=TEST_FREQ_DEFAULT(); const char MASTER_TAG[] = "test_master"; @@ -204,4 +206,6 @@ void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func); GPIO.func_out_sel_cfg[gpio_num].func_sel=signal_idx; -} \ No newline at end of file +} + +#endif diff --git a/components/driver/test/test_dac.c b/components/driver/test/test_dac.c index e3ab9cf521..755e5490f6 100644 --- a/components/driver/test/test_dac.c +++ b/components/driver/test/test_dac.c @@ -14,6 +14,7 @@ #include "test_utils.h" #include "driver/i2s.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #include "esp_adc_cal.h" static const char *TAG = "test_dac"; @@ -180,3 +181,5 @@ TEST_CASE("esp32s2 adc2-dac with adc2 calibration", "[adc-dac]") subtest_adc_dac(2500, &chars); } #endif + +#endif diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c index e7cc42a67b..b12790c26d 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/test_gpio.c @@ -16,6 +16,8 @@ #include "esp_rom_uart.h" #include "esp_rom_sys.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated. #if CONFIG_IDF_TARGET_ESP32 @@ -770,3 +772,5 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]") gpio_uninstall_isr_service(); TEST_ASSERT((io18_param.isr_cnt == 1) && (io19_param.isr_cnt == 1)); } + +#endif diff --git a/components/driver/test/test_i2c.c b/components/driver/test/test_i2c.c index 6548b30e46..d1dcc1567d 100644 --- a/components/driver/test/test_i2c.c +++ b/components/driver/test/test_i2c.c @@ -19,6 +19,7 @@ #include "driver/periph_ctrl.h" #include "esp_rom_gpio.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #define DATA_LENGTH 512 /*! (b)? (b): (a)) #endif @@ -1164,3 +1166,5 @@ spitest_param_set_t mode_conf[] = { TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") #endif + +#endif diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/test_spi_sio.c index 6a3196a044..9146b417e8 100644 --- a/components/driver/test/test_spi_sio.c +++ b/components/driver/test/test_spi_sio.c @@ -25,6 +25,7 @@ #include "hal/spi_ll.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) /******************************************************************************** * Test SIO @@ -221,3 +222,5 @@ void test_sio_slave(void) TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); #endif + +#endif diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index d1c448b6a9..925b7f0a8e 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -12,6 +12,8 @@ #include "test/test_common_spi.h" #include "esp_rom_gpio.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #ifndef CONFIG_SPIRAM //This test should be removed once the timing test is merged. @@ -142,3 +144,5 @@ TEST_CASE("test slave send unaligned","[spi]") } #endif // !CONFIG_SPIRAM + +#endif \ No newline at end of file diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index 95caf676ae..e978841e4c 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -17,6 +17,7 @@ #include "unity.h" #include "test/test_common_spi.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #define TEST_DMA_MAX_SIZE 14000 #define TEST_BUFFER_SIZE 256 ///< buffer size of each wrdma buffer in fifo mode @@ -573,4 +574,6 @@ TEST_CASE("test spi slave hd continuous mode, master too long", "[spi][spi_slv_h master_free_device_bus(spi); } -#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 \ No newline at end of file +#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 + +#endif diff --git a/components/driver/test/test_timer.c b/components/driver/test/test_timer.c index 1445314d38..9a58eed1dd 100644 --- a/components/driver/test/test_timer.c +++ b/components/driver/test/test_timer.c @@ -9,6 +9,8 @@ #include "soc/rtc.h" #include "esp_rom_sys.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #define TIMER_DIVIDER 16 #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */ #define TIMER_DELTA 0.001 @@ -973,3 +975,5 @@ TEST_CASE_MULTIPLE_STAGES("timer_group software reset test", "[intr_status][intr_status = 0]", timer_group_test_first_stage, timer_group_test_second_stage); + +#endif diff --git a/components/driver/test/test_uart.c b/components/driver/test/test_uart.c index 7f1c285e0b..d86c3cb581 100644 --- a/components/driver/test/test_uart.c +++ b/components/driver/test/test_uart.c @@ -6,6 +6,8 @@ #include "esp_log.h" #include "esp_system.h" // for uint32_t esp_random() +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #define UART_TAG "Uart" #define UART_NUM1 (UART_NUM_1) #define BUF_SIZE (100) @@ -312,3 +314,5 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]") free(rd_data); free(wr_data); } + +#endif diff --git a/components/driver/test/touch_sensor_test/test_esp32.c b/components/driver/test/touch_sensor_test/test_esp32.c index 6ad6902119..c5fa040196 100644 --- a/components/driver/test/touch_sensor_test/test_esp32.c +++ b/components/driver/test/touch_sensor_test/test_esp32.c @@ -34,7 +34,7 @@ #include "soc/rtc_io_struct.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2) // This testcase for ESP32 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2, ESP32S3) // This testcase for ESP32 static const char *TAG = "test_touch"; diff --git a/components/driver/test/touch_sensor_test/test_esp32s2.c b/components/driver/test/touch_sensor_test/test_esp32s2.c index c0ce93209f..0191538fac 100644 --- a/components/driver/test/touch_sensor_test/test_esp32s2.c +++ b/components/driver/test/touch_sensor_test/test_esp32s2.c @@ -38,7 +38,7 @@ #include "driver/rtc_io.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2 +#if !DISABLED_FOR_TARGETS(ESP8266, ESP32, ESP32S3) // This testcase for ESP32S2 static const char *TAG = "test_touch"; diff --git a/components/efuse/test/test_efuse.c b/components/efuse/test/test_efuse.c index 1c06370c6a..f5e02c8a29 100644 --- a/components/efuse/test/test_efuse.c +++ b/components/efuse/test/test_efuse.c @@ -19,6 +19,8 @@ #include "esp_rom_efuse.h" #include "bootloader_common.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + static const char* TAG = "efuse_test"; static void test_read_blob(void) @@ -858,3 +860,5 @@ TEST_CASE("Test chip_revision APIs return the same value", "[efuse]") esp_efuse_utility_update_virt_blocks(); TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision()); } + +#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/esp_eth/test/test_emac.c b/components/esp_eth/test/test_emac.c index d6fd28bfa9..e05fdb771d 100644 --- a/components/esp_eth/test/test_emac.c +++ b/components/esp_eth/test/test_emac.c @@ -35,6 +35,8 @@ static const char *TAG = "esp32_eth_test"; #define ETH_PING_DURATION_MS (5000) #define ETH_PING_END_TIMEOUT_MS (ETH_PING_DURATION_MS * 2) +#define TEST_ICMP_DESTINATION_DOMAIN_NAME "127.0.0.1" + // compute md5 of download file static md5_context_t md5_context; static uint8_t digest[16]; @@ -343,7 +345,7 @@ TEST_CASE("esp32 ethernet icmp test", "[ethernet][test_env=UT_T2_Ethernet]") memset(&hint, 0, sizeof(hint)); memset(&target_addr, 0, sizeof(target_addr)); /* convert URL to IP */ - TEST_ASSERT(getaddrinfo("www.espressif.com", NULL, &hint, &res) == 0); + TEST_ASSERT(getaddrinfo(TEST_ICMP_DESTINATION_DOMAIN_NAME, NULL, &hint, &res) == 0); struct in_addr addr4 = ((struct sockaddr_in *)(res->ai_addr))->sin_addr; inet_addr_to_ip4addr(ip_2_ip4(&target_addr), &addr4); freeaddrinfo(res); diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c index d5aa58c097..995a90c329 100644 --- a/components/newlib/test/test_time.c +++ b/components/newlib/test/test_time.c @@ -9,6 +9,7 @@ #include "freertos/semphr.h" #include "sdkconfig.h" #include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" #include "esp_system.h" #include "test_utils.h" #include "esp_log.h" @@ -17,8 +18,13 @@ #if CONFIG_IDF_TARGET_ESP32 #include "esp32/clk.h" +#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" +#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ #endif #if portNUM_PROCESSORS == 2 @@ -32,7 +38,7 @@ TEST_CASE("Reading RTC registers on APP CPU doesn't affect clock", "[newlib]") for (int i = 0; i < 200000; ++i) { // wait for 20us, reading one of RTC registers uint32_t ccount = xthal_get_ccount(); - while (xthal_get_ccount() - ccount < 20 * CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) { + while (xthal_get_ccount() - ccount < 20 * TARGET_DEFAULT_CPU_FREQ_MHZ) { volatile uint32_t val = REG_READ(RTC_CNTL_STATE0_REG); (void) val; } diff --git a/components/soc/test/test_rtc_clk.c b/components/soc/test/test_rtc_clk.c index 0b45c1a9de..b763d51943 100644 --- a/components/soc/test/test_rtc_clk.c +++ b/components/soc/test/test_rtc_clk.c @@ -17,7 +17,7 @@ extern void rtc_clk_select_rtc_slow_clk(void); -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) #include "esp32/clk.h" diff --git a/components/ulp/test/CMakeLists.txt b/components/ulp/test/CMakeLists.txt index b71796927d..d800757fd2 100644 --- a/components/ulp/test/CMakeLists.txt +++ b/components/ulp/test/CMakeLists.txt @@ -1,3 +1,6 @@ +if(IDF_TARGET STREQUAL "esp32s3") + return() +endif() idf_component_register(SRC_DIRS ${IDF_TARGET} PRIV_INCLUDE_DIRS . PRIV_REQUIRES cmock ulp soc esp_common) diff --git a/components/wear_levelling/test/test_wl.c b/components/wear_levelling/test/test_wl.c index 93a45083d4..19537316a6 100644 --- a/components/wear_levelling/test/test_wl.c +++ b/components/wear_levelling/test/test_wl.c @@ -7,10 +7,12 @@ #include "freertos/portable.h" #include "freertos/task.h" #include "freertos/semphr.h" -#ifdef CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/clk.h" -#elif defined(CONFIG_IDF_TARGET_ESP32S2) +#elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #endif #include "soc/cpu.h" #include "esp_rom_sys.h" diff --git a/docs/en/api-guides/tools/idf-tools-notes.inc b/docs/en/api-guides/tools/idf-tools-notes.inc index 7600e28c09..41ca6e01d4 100644 --- a/docs/en/api-guides/tools/idf-tools-notes.inc +++ b/docs/en/api-guides/tools/idf-tools-notes.inc @@ -10,6 +10,11 @@ .. tool-xtensa-esp32s2-elf-notes +--- + +.. tool-xtensa-esp32s3-elf-notes + + --- .. tool-esp32ulp-elf-notes diff --git a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc index ba5bdc43de..3e22db2113 100644 --- a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc +++ b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc @@ -12,6 +12,11 @@ .. tool-xtensa-esp32s2-elf-notes +--- + +.. tool-xtensa-esp32s3-elf-notes + + --- .. tool-esp32ulp-elf-notes diff --git a/examples/cxx/experimental/experimental_cpp_component/test/test_cxx_exceptions.cpp b/examples/cxx/experimental/experimental_cpp_component/test/test_cxx_exceptions.cpp index e5b55ab857..c4e16cd27e 100644 --- a/examples/cxx/experimental/experimental_cpp_component/test/test_cxx_exceptions.cpp +++ b/examples/cxx/experimental/experimental_cpp_component/test/test_cxx_exceptions.cpp @@ -13,7 +13,7 @@ using namespace idf; #if CONFIG_IDF_TARGET_ESP32 #define LEAKS "300" -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define LEAKS "800" #else #error "unknown target in CXX tests, can't set leaks threshold" diff --git a/examples/cxx/experimental/experimental_cpp_component/test/test_i2c.cpp b/examples/cxx/experimental/experimental_cpp_component/test/test_i2c.cpp index 4ce9f14a2e..fb6218575a 100644 --- a/examples/cxx/experimental/experimental_cpp_component/test/test_i2c.cpp +++ b/examples/cxx/experimental/experimental_cpp_component/test/test_i2c.cpp @@ -20,9 +20,8 @@ #include #include "test_utils.h" // unity_send_signal -#include "i2c_cxx.hpp" - #ifdef __cpp_exceptions +#include "i2c_cxx.hpp" using namespace std; using namespace idf; diff --git a/tools/ci/config/build.yml b/tools/ci/config/build.yml index edf3ca0113..88660e5f0b 100644 --- a/tools/ci/config/build.yml +++ b/tools/ci/config/build.yml @@ -83,6 +83,11 @@ build_esp_idf_tests_cmake_esp32s2: variables: IDF_TARGET: esp32s2 +build_esp_idf_tests_cmake_esp32s3: + extends: .build_esp_idf_tests_cmake + variables: + IDF_TARGET: esp32s3 + .build_examples_template: extends: .build_template artifacts: diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml index 1c9c944696..8737fb0be4 100644 --- a/tools/ci/config/target-test.yml +++ b/tools/ci/config/target-test.yml @@ -432,7 +432,7 @@ UT_001: UT_002: extends: .unit_test_template - parallel: 12 + parallel: 13 tags: - ESP32_IDF - UT_T1_1 diff --git a/tools/ci/python_packages/ttfw_idf/CIScanTests.py b/tools/ci/python_packages/ttfw_idf/CIScanTests.py index 11af6fe864..250841636b 100644 --- a/tools/ci/python_packages/ttfw_idf/CIScanTests.py +++ b/tools/ci/python_packages/ttfw_idf/CIScanTests.py @@ -8,7 +8,7 @@ from collections import defaultdict from find_apps import find_apps from find_build_apps import BUILD_SYSTEMS, BUILD_SYSTEM_CMAKE from ttfw_idf.IDFAssignTest import ExampleAssignTest, TestAppsAssignTest -from idf_py_actions.constants import SUPPORTED_TARGETS +from idf_py_actions.constants import SUPPORTED_TARGETS, PREVIEW_TARGETS TEST_LABELS = { 'example_test': 'BOT_LABEL_EXAMPLE_TEST', @@ -90,6 +90,8 @@ def main(): if e.errno != errno.EEXIST: raise e + SUPPORTED_TARGETS.extend(PREVIEW_TARGETS) + if (not build_standalone_apps) and (not build_test_case_apps): for target in SUPPORTED_TARGETS: output_json([], target, args.build_system, args.output_path) diff --git a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py index 200d3618ad..75c581c1e8 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py +++ b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py @@ -17,7 +17,7 @@ except ImportError: import gitlab_api from tiny_test_fw.Utility import CIAssignTest -from idf_py_actions.constants import SUPPORTED_TARGETS +from idf_py_actions.constants import SUPPORTED_TARGETS, PREVIEW_TARGETS IDF_PATH_FROM_ENV = os.getenv('IDF_PATH') @@ -311,6 +311,8 @@ if __name__ == '__main__': parser.add_argument('--test-case-file-pattern', help='file name pattern used to find Python test case files') args = parser.parse_args() + SUPPORTED_TARGETS.extend(PREVIEW_TARGETS) + test_case_paths = [os.path.join(IDF_PATH_FROM_ENV, path) if not os.path.isabs(path) else path for path in args.test_case_paths] args_list = [test_case_paths, args.config] if args.case_group == 'example_test': diff --git a/tools/find_build_apps/cmake.py b/tools/find_build_apps/cmake.py index 27ed361bb0..5d3b65d67f 100644 --- a/tools/find_build_apps/cmake.py +++ b/tools/find_build_apps/cmake.py @@ -19,6 +19,7 @@ SUPPORTED_TARGETS_REGEX = re.compile(r'Supported [Tt]argets((?:[\s|]+(?:ESP[0-9A FORMAL_TO_USUAL = { 'ESP32': 'esp32', 'ESP32-S2': 'esp32s2', + 'ESP32-S3': 'esp32s3', } @@ -99,6 +100,7 @@ class CMakeBuildSystem(BuildSystem): formal_to_usual = { 'ESP32': 'esp32', 'ESP32-S2': 'esp32s2', + 'ESP32-S3': 'esp32s3', } readme_file_content = BuildSystem._read_readme(app_path) diff --git a/tools/idf_size.py b/tools/idf_size.py index 7bd84bace4..a4fc173a60 100755 --- a/tools/idf_size.py +++ b/tools/idf_size.py @@ -124,6 +124,10 @@ class MemRegions(object): # MemRegDef(0x3FFF8000, 0x4000, MemRegions.DIRAM_ID, 0x40068000), # MemRegDef(0x3FFFC000, 0x4000, MemRegions.DIRAM_ID, 0x4006C000), ]) + elif target == 'esp32s3': + return sorted([ + MemRegDef(0x3FC88000, 0x8000 + 6 * 0x10000, MemRegions.DIRAM_ID, 0x40378000), + ]) else: return None diff --git a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c index e1f620fabc..8009a4606d 100644 --- a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c +++ b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c @@ -14,6 +14,8 @@ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARTGET_ESP32S3 +#include "esp32s3/clk.h" #endif #include "unity.h" @@ -28,7 +30,7 @@ static const char* TAG = "test_ccomp_timer"; #define CACHE_SIZE (1 << 15) // Only test half due to lack of memory #define TEST_SIZE (CACHE_SIZE / 2) -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // Default cache configuration - no override specified on // test_utils config #define CACHE_WAYS 8 diff --git a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c index bd26f057e7..0797730de2 100644 --- a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c +++ b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c @@ -17,7 +17,7 @@ #define CACHE_LINE_SIZE 32 #define CACHE_SIZE (1 << 15) // Only test half due to lack of memory -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // Default cache configuration - no override specified on // test_utils config #define CACHE_WAYS 8 diff --git a/tools/unit-test-app/sdkconfig.defaults.esp32s3 b/tools/unit-test-app/sdkconfig.defaults.esp32s3 new file mode 100644 index 0000000000..117349c012 --- /dev/null +++ b/tools/unit-test-app/sdkconfig.defaults.esp32s3 @@ -0,0 +1 @@ +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240=y From 0bb21281cafb58069ae383a76c3e12df3981f47c Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 7 Sep 2020 14:12:07 +0800 Subject: [PATCH 11/11] esp32s3: select esp32s3 beta version in menuconfig --- Kconfig | 13 +++++++++++++ components/esptool_py/Kconfig.projbuild | 2 +- components/esptool_py/esptool | 2 +- components/esptool_py/project_include.cmake | 9 ++++++++- 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index 02a9380814..0e5d247d7d 100644 --- a/Kconfig +++ b/Kconfig @@ -34,6 +34,19 @@ mainmenu "Espressif IoT Development Framework Configuration" bool default "y" if IDF_TARGET="esp32s3" + choice IDF_TARGET_ESP32S3_BETA_VERSION + prompt "ESP32-S3 beta version" + depends on IDF_TARGET_ESP32S3 + default IDF_TARGET_ESP32S3_BETA_VERSION_2 + help + Currently ESP32-S3 has several beta versions for internal use only. + Select the one that matches your chip model. + + config IDF_TARGET_ESP32S3_BETA_VERSION_2 + bool + prompt "ESP32-S3 beta2" + endchoice + config IDF_FIRMWARE_CHIP_ID hex default 0x0000 if IDF_TARGET_ESP32 diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index 16eca6e003..3069be8a69 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -57,7 +57,7 @@ menu "Serial flasher config" config ESPTOOLPY_WITH_STUB # Only real reason to disable this is when ESP32-S2 Secure Download Mode is set bool - default "y" if !IDF_TARGET_ESP32S3 + default "y" depends on !SECURE_ENABLE_SECURE_ROM_DL_MODE choice ESPTOOLPY_FLASHMODE diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index 09549c0311..0f064e1d6c 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit 09549c03111a2b330371d361d56227a457af66c5 +Subproject commit 0f064e1d6c5640785a602de564b21040dcc32926 diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index c421458474..db56a9cd19 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -4,7 +4,14 @@ idf_build_get_property(target IDF_TARGET) idf_build_get_property(python PYTHON) -set(ESPTOOLPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${target}) +set(chip_model ${target}) +if(target STREQUAL "esp32s3") + if(CONFIG_IDF_TARGET_ESP32S3_BETA_VERSION_2) + set(chip_model "esp32s3beta2") + endif() +endif() + +set(ESPTOOLPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model}) set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") set(ESPEFUSEPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espefuse.py")