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esp32s2: reset systimer clk on startup

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This commit is contained in:
Renz Bagaporo
2021-01-21 16:23:52 +08:00
committed by Marius Vikhammer
parent cebab7fa7f
commit b07276265a
1 changed files with 3 additions and 0 deletions
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3
components/esp_system/port/soc/esp32s2/clk.c
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@@ -35,6 +35,7 @@
#include "driver/periph_ctrl.h" #include "driver/periph_ctrl.h"
#include "bootloader_clock.h" #include "bootloader_clock.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#include "hal/clk_gate_ll.h"
static const char *TAG = "clk"; static const char *TAG = "clk";
@@ -313,6 +314,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M); DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW); DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
periph_ll_reset(PERIPH_SYSTIMER_MODULE);
/* Enable RNG clock. */ /* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE); periph_module_enable(PERIPH_RNG_MODULE);
} }