From b11f28655566cdf09405e18440d47d9f81d43986 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Thu, 22 Feb 2024 15:56:40 +0530 Subject: [PATCH] feat(esp_system/esp32c5): revised cypto clock to be used This commit updated crypto clock to use 160M SPLL clock --- components/esp_system/port/soc/esp32c5/clk.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index fc017b5c02..34f972a637 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -106,6 +106,9 @@ __attribute__((weak)) void esp_clk_init(void) // Re calculate the ccount to make time calculation correct. esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz); + + // Set crypto clock (`clk_sec`) to use 160M SPLL clock + REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2); } static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)