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fix(esp32c5mp): fix public headers

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This commit is contained in:
laokaiyao
2024-03-11 20:45:09 +08:00
parent 71257c6ef4
commit b1a3e92f2a
14 changed files with 91 additions and 61 deletions
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2
components/hal/esp32c5/include/hal/clk_tree_ll.h
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@@ -339,7 +339,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
/* Configure 480M PLL */ /* Configure 480M PLL */
switch (xtal_freq_mhz) { switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M: case SOC_XTAL_FREQ_40M:
default: default:
div_ref = 0; div_ref = 0;
div7_0 = 8; div7_0 = 8;

4
components/hal/esp32c5/include/hal/gdma_ll.h
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@@ -8,6 +8,8 @@
#include <stddef.h> /* Required for NULL constant */ #include <stddef.h> /* Required for NULL constant */
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "soc/soc_caps.h"
#if SOC_GDMA_SUPPORTED // TODO: [ESP32C5] IDF-8710
#include "hal/gdma_types.h" #include "hal/gdma_types.h"
#include "soc/gdma_struct.h" #include "soc/gdma_struct.h"
#include "soc/gdma_reg.h" #include "soc/gdma_reg.h"
@@ -625,3 +627,5 @@ static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel,
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // SOC_GDMA_SUPPORTED

4
components/hal/esp32c5/include/hal/i2c_ll.h
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@@ -9,8 +9,10 @@
#pragma once #pragma once
#include <stdbool.h> #include <stdbool.h>
#include "soc/soc_caps.h"
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/assert.h" #include "hal/assert.h"
#if SOC_I2C_SUPPORTED // TODO: [ESP32C5] IDF-8694
#include "soc/i2c_periph.h" #include "soc/i2c_periph.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "soc/i2c_struct.h" #include "soc/i2c_struct.h"
@@ -1119,3 +1121,5 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // SOC_I2C_SUPPORTED

9
components/hal/esp32c5/include/hal/mmu_ll.h
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@@ -8,11 +8,16 @@
#pragma once #pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/spi_mem_reg.h" #include "soc/spi_mem_reg.h"
#include "soc/ext_mem_defs.h" #include "soc/ext_mem_defs.h"
#include "soc/soc_caps.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/mmu_types.h" #include "hal/mmu_types.h"
#if SOC_EFUSE_SUPPORTED
#include "hal/efuse_ll.h" #include "hal/efuse_ll.h"
#endif
#ifdef __cplusplus #ifdef __cplusplus
@@ -53,10 +58,14 @@ static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_t
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
{ {
// TODO: [ESP32C5] IDF-8658 (inherit from C6) // TODO: [ESP32C5] IDF-8658 (inherit from C6)
#if SOC_EFUSE_SUPPORTED
unsigned cnt = efuse_ll_get_flash_crypt_cnt(); unsigned cnt = efuse_ll_get_flash_crypt_cnt();
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
return (cnt == 1); return (cnt == 1);
#else
return false;
#endif
} }
/** /**

6
components/hal/esp32c5/include/hal/rtc_io_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -16,8 +16,8 @@
#include <stdbool.h> #include <stdbool.h>
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "soc/pcr_struct.h" #include "soc/pcr_struct.h"
#include "soc/lp_io_struct.h" // #include "soc/lp_io_struct.h"
#include "soc/lp_aon_struct.h" // #include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h" #include "soc/pmu_struct.h"
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/assert.h" #include "hal/assert.h"

2
components/hal/include/hal/spi_hal.h
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@@ -29,7 +29,9 @@
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "hal/spi_types.h" #include "hal/spi_types.h"
#include "hal/dma_types.h" #include "hal/dma_types.h"
#if SOC_GDMA_SUPPORTED
#include "soc/gdma_channel.h" #include "soc/gdma_channel.h"
#endif
#if SOC_GPSPI_SUPPORTED #if SOC_GPSPI_SUPPORTED
#include "hal/spi_ll.h" #include "hal/spi_ll.h"
#endif #endif

2
components/hal/include/hal/spi_slave_hd_hal.h
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@@ -46,7 +46,9 @@
#include "esp_types.h" #include "esp_types.h"
#include "esp_err.h" #include "esp_err.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if SOC_GDMA_SUPPORTED
#include "soc/gdma_channel.h" #include "soc/gdma_channel.h"
#endif
#include "hal/spi_types.h" #include "hal/spi_types.h"
#include "hal/dma_types.h" #include "hal/dma_types.h"
#if SOC_GPSPI_SUPPORTED #if SOC_GPSPI_SUPPORTED

6
components/soc/esp32c5/mp/include/soc/aes_struct.h
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@@ -314,10 +314,10 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** continue : WT; bitpos: [0]; default: 0; /** conti : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation. * Set this bit to continue GCM operation.
*/ */
uint32_t continue:1; uint32_t conti:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
@@ -392,7 +392,7 @@ typedef struct {
volatile aes_inc_sel_reg_t inc_sel; volatile aes_inc_sel_reg_t inc_sel;
volatile aes_aad_block_num_reg_t aad_block_num; volatile aes_aad_block_num_reg_t aad_block_num;
volatile aes_remainder_bit_num_reg_t remainder_bit_num; volatile aes_remainder_bit_num_reg_t remainder_bit_num;
volatile aes_continue_reg_t continue; volatile aes_continue_reg_t conti;
volatile aes_int_clear_reg_t int_clear; volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena; volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date; volatile aes_date_reg_t date;

4
components/soc/esp32c5/mp/include/soc/huk_struct.h
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@@ -149,10 +149,10 @@ typedef union {
* Write 1 to continue HUK Generator operation at LOAD/GAIN state. * Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/ */
uint32_t start:1; uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0; /** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state. * Write 1 to start HUK Generator at IDLE state.
*/ */
uint32_t continue:1; uint32_t conti:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
}; };
uint32_t val; uint32_t val;

6
components/soc/esp32c5/mp/include/soc/keymng_struct.h
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@@ -223,10 +223,10 @@ typedef union {
* Write 1 to continue Key Manager operation at LOAD/GAIN state. * Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/ */
uint32_t start:1; uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0; /** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state. * Write 1 to start Key Manager at IDLE state.
*/ */
uint32_t continue:1; uint32_t conti:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
}; };
uint32_t val; uint32_t val;
@@ -338,7 +338,7 @@ typedef struct {
volatile keymng_int_st_reg_t int_st; volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena; volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr; volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static; volatile keymng_static_reg_t static_cfg;
volatile keymng_lock_reg_t lock; volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf; volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start; volatile keymng_start_reg_t start;

98
components/soc/esp32c5/mp/include/soc/sha_struct.h
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@@ -62,10 +62,10 @@ typedef union {
typedef union { typedef union {
struct { struct {
uint32_t reserved_0:1; uint32_t reserved_0:1;
/** continue : RO; bitpos: [31:1]; default: 0; /** conti : RO; bitpos: [31:1]; default: 0;
* Write 1 to continue Typical SHA calculation. * Write 1 to continue Typical SHA calculation.
*/ */
uint32_t continue:31; uint32_t conti:31;
}; };
uint32_t val; uint32_t val;
} sha_continue_reg_t; } sha_continue_reg_t;
@@ -127,113 +127,113 @@ typedef union {
uint32_t val; uint32_t val;
} sha_t_length_reg_t; } sha_t_length_reg_t;
/** Type of 3_mode register /** Type of mode register
* Initial configuration register 0. * Initial configuration register 0.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_mode : R/W; bitpos: [2:0]; default: 0; /** mode : R/W; bitpos: [2:0]; default: 0;
* Sha3 mode * Sha3 mode
*/ */
uint32_t 3_mode:3; uint32_t mode:3;
uint32_t reserved_3:29; uint32_t reserved_3:29;
}; };
uint32_t val; uint32_t val;
} sha_3_mode_reg_t; } sha_3_mode_reg_t;
/** Type of 3_clean_m register /** Type of clean_m register
* Initial configuration register 1. * Initial configuration register 1.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_clean_m : WO; bitpos: [0]; default: 0; /** clean_m : WO; bitpos: [0]; default: 0;
* Clean Message. * Clean Message.
*/ */
uint32_t 3_clean_m:1; uint32_t clean_m:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_clean_m_reg_t; } sha_3_clean_m_reg_t;
/** Type of 3_dma_block_num register /** Type of dma_block_num register
* DMA configuration register 0. * DMA configuration register 0.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_dma_block_num : R/W; bitpos: [5:0]; default: 0; /** dma_block_num : R/W; bitpos: [5:0]; default: 0;
* DMA-SHA3 block number. * DMA-SHA3 block number.
*/ */
uint32_t 3_dma_block_num:6; uint32_t dma_block_num:6;
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} sha_3_dma_block_num_reg_t; } sha_3_dma_block_num_reg_t;
/** Type of 3_start register /** Type of start register
* Typical SHA3 configuration register 0. * Typical SHA3 configuration register 0.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_start : WO; bitpos: [0]; default: 0; /** start : WO; bitpos: [0]; default: 0;
* Start typical sha3. * Start typical sha3.
*/ */
uint32_t 3_start:1; uint32_t start:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_start_reg_t; } sha_3_start_reg_t;
/** Type of 3_continue register /** Type of continue register
* Typical SHA3 configuration register 1. * Typical SHA3 configuration register 1.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_continue : WO; bitpos: [0]; default: 0; /** conti : WO; bitpos: [0]; default: 0;
* Continue typical sha3. * Continue typical sha3.
*/ */
uint32_t 3_continue:1; uint32_t conti:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_continue_reg_t; } sha_3_continue_reg_t;
/** Type of 3_dma_start register /** Type of dma_start register
* DMA configuration register 1. * DMA configuration register 1.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_dma_start : WO; bitpos: [0]; default: 0; /** dma_start : WO; bitpos: [0]; default: 0;
* Start dma-sha3. * Start dma-sha3.
*/ */
uint32_t 3_dma_start:1; uint32_t dma_start:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_dma_start_reg_t; } sha_3_dma_start_reg_t;
/** Type of 3_dma_continue register /** Type of dma_continue register
* DMA configuration register 2. * DMA configuration register 2.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_dma_continue : WO; bitpos: [0]; default: 0; /** dma_continue : WO; bitpos: [0]; default: 0;
* Continue dma-sha3. * Continue dma-sha3.
*/ */
uint32_t 3_dma_continue:1; uint32_t dma_continue:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_dma_continue_reg_t; } sha_3_dma_continue_reg_t;
/** Type of 3_shake_length register /** Type of shake_length register
* DMA configuration register 3. * DMA configuration register 3.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_shake_length : WO; bitpos: [10:0]; default: 50; /** shake_length : WO; bitpos: [10:0]; default: 50;
* SHAKE output hash word length * SHAKE output hash word length
*/ */
uint32_t 3_shake_length:11; uint32_t shake_length:11;
uint32_t reserved_11:21; uint32_t reserved_11:21;
}; };
uint32_t val; uint32_t val;
@@ -307,15 +307,15 @@ typedef union {
/** Group: memory type */ /** Group: memory type */
/** Group: Status Register */ /** Group: Status Register */
/** Type of 3_busy register /** Type of busy register
* Busy register. * Busy register.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_busy_reg : RO; bitpos: [0]; default: 0; /** busy_reg : RO; bitpos: [0]; default: 0;
* Sha3 busy state. 1'b0: idle. 1'b1: busy. * Sha3 busy state. 1'b0: idle. 1'b1: busy.
*/ */
uint32_t 3_busy_reg:1; uint32_t busy_reg:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
@@ -323,29 +323,29 @@ typedef union {
/** Group: Interrupt Register */ /** Group: Interrupt Register */
/** Type of 3_clear_int register /** Type of clear_int register
* Interrupt clear register. * Interrupt clear register.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_clear_int : WO; bitpos: [0]; default: 0; /** clear_int : WO; bitpos: [0]; default: 0;
* Clear sha3 interrupt. * Clear sha3 interrupt.
*/ */
uint32_t 3_clear_int:1; uint32_t clear_int:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} sha_3_clear_int_reg_t; } sha_3_clear_int_reg_t;
/** Type of 3_int_ena register /** Type of int_ena register
* Interrupt enable register. * Interrupt enable register.
*/ */
typedef union { typedef union {
struct { struct {
/** 3_int_ena : R/W; bitpos: [0]; default: 0; /** int_ena : R/W; bitpos: [0]; default: 0;
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
*/ */
uint32_t 3_int_ena:1; uint32_t int_ena:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
@@ -358,7 +358,7 @@ typedef struct {
volatile sha_t_length_reg_t t_length; volatile sha_t_length_reg_t t_length;
volatile sha_dma_block_num_reg_t dma_block_num; volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start; volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue; volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy; volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start; volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue; volatile sha_dma_continue_reg_t dma_continue;
@@ -369,22 +369,22 @@ typedef struct {
volatile uint32_t h[16]; volatile uint32_t h[16];
volatile uint32_t m[16]; volatile uint32_t m[16];
uint32_t reserved_0c0[464]; uint32_t reserved_0c0[464];
volatile sha_3_mode_reg_t 3_mode; volatile sha_3_mode_reg_t mode_3;
volatile sha_3_clean_m_reg_t 3_clean_m; volatile sha_3_clean_m_reg_t clean_m_3;
uint32_t reserved_808; uint32_t reserved_808;
volatile sha_3_dma_block_num_reg_t 3_dma_block_num; volatile sha_3_dma_block_num_reg_t dma_block_num_3;
volatile sha_3_start_reg_t 3_start; volatile sha_3_start_reg_t start_3;
volatile sha_3_continue_reg_t 3_continue; volatile sha_3_continue_reg_t continue_3;
volatile sha_3_busy_reg_t 3_busy; volatile sha_3_busy_reg_t busy_3;
volatile sha_3_dma_start_reg_t 3_dma_start; volatile sha_3_dma_start_reg_t dma_start_3;
volatile sha_3_dma_continue_reg_t 3_dma_continue; volatile sha_3_dma_continue_reg_t dma_continue_3;
volatile sha_3_clear_int_reg_t 3_clear_int; volatile sha_3_clear_int_reg_t clear_int_3;
volatile sha_3_int_ena_reg_t 3_int_ena; volatile sha_3_int_ena_reg_t int_ena_3;
volatile sha_3_shake_length_reg_t 3_shake_length; volatile sha_3_shake_length_reg_t shake_length_3;
uint32_t reserved_830[52]; uint32_t reserved_830[52];
volatile uint32_t 3_m_out[50]; volatile uint32_t m_out_3[50];
uint32_t reserved_9c8[14]; uint32_t reserved_9c8[14];
volatile uint32_t 3_m[50]; volatile uint32_t m_3[50];
} sha_dev_t; } sha_dev_t;
extern sha_dev_t SHA; extern sha_dev_t SHA;

2
components/soc/include/soc/adc_periph.h
View File

@@ -8,7 +8,9 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if SOC_ADC_SUPPORTED
#include "soc/adc_channel.h" #include "soc/adc_channel.h"
#endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

3
components/soc/include/soc/hwcrypto_periph.h
View File

@@ -7,10 +7,13 @@
#pragma once #pragma once
#include "sdkconfig.h" #include "sdkconfig.h"
#include "soc/soc_caps.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
/* included here for ESP-IDF v4.x compatibility */ /* included here for ESP-IDF v4.x compatibility */
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#endif #endif
#if SOC_SHA_SUPPORTED
#include "soc/hwcrypto_reg.h" #include "soc/hwcrypto_reg.h"
#endif

4
components/soc/include/soc/i2c_periph.h
View File

@@ -8,15 +8,18 @@
#include "soc/i2c_reg.h" #include "soc/i2c_reg.h"
#include "soc/i2c_struct.h" #include "soc/i2c_struct.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if SOC_I2C_SUPPORTED // TODO: [ESP32C5] IDF-8694
#include "soc/periph_defs.h" #include "soc/periph_defs.h"
#if SOC_PM_SUPPORT_TOP_PD #if SOC_PM_SUPPORT_TOP_PD
#include "soc/regdma.h" #include "soc/regdma.h"
#endif #endif
#endif // SOC_I2C_SUPPORTED
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if SOC_I2C_SUPPORTED
typedef struct { typedef struct {
const uint8_t sda_out_sig; const uint8_t sda_out_sig;
const uint8_t sda_in_sig; const uint8_t sda_in_sig;
@@ -36,6 +39,7 @@ typedef struct {
extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_I2C_NUM]; extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_I2C_NUM];
#endif #endif
#endif // SOC_I2C_SUPPORTED
#ifdef __cplusplus #ifdef __cplusplus
} }