From b4a9078f9884336b9eb08fb938600c02d5372049 Mon Sep 17 00:00:00 2001 From: Wang Fang Date: Tue, 23 May 2023 11:44:47 +0800 Subject: [PATCH] docs: update the description for check_speed_hz --- components/driver/spi/include/driver/spi_master.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/driver/spi/include/driver/spi_master.h b/components/driver/spi/include/driver/spi_master.h index 5cc1f469c4..f677e2a552 100644 --- a/components/driver/spi/include/driver/spi_master.h +++ b/components/driver/spi/include/driver/spi_master.h @@ -71,7 +71,7 @@ typedef struct { uint16_t duty_cycle_pos; ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128. uint16_t cs_ena_pretrans; ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions. uint8_t cs_ena_posttrans; ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16) - int clock_speed_hz; ///< Clock speed, divisors of the SPI `clock_source`, in Hz + int clock_speed_hz; ///< SPI clock speed in Hz. Derived from `clock_source`. int input_delay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO valid, including the possible clock delay from slave to master. The driver uses this value to give an extra delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing