From b51fc7c390f21f597707c6025b00d1fa743053a6 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 19 Jun 2024 17:20:37 +0800 Subject: [PATCH] ci(parlio_rx): enable target test for h2 and p4 --- .../test_apps/.build-test-rules.yml | 4 ---- .../test_apps/parlio/main/test_parlio_rx.c | 5 +++++ .../test_apps/parlio/pytest_parlio_unity.py | 2 ++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 ++++++++++ components/soc/esp32p4/include/soc/soc_caps.h | 3 +++ examples/peripherals/.build-test-rules.yml | 8 ------- .../logic_analyzer/pytest_logic_analyzer.py | 22 +++++++++++++++++++ .../logic_analyzer/sdkconfig.ci.flash_stream | 1 + 8 files changed, 45 insertions(+), 12 deletions(-) create mode 100644 examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py create mode 100644 examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream diff --git a/components/esp_driver_parlio/test_apps/.build-test-rules.yml b/components/esp_driver_parlio/test_apps/.build-test-rules.yml index c2c576d51f..efce473ee7 100644 --- a/components/esp_driver_parlio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_parlio/test_apps/.build-test-rules.yml @@ -3,9 +3,5 @@ components/esp_driver_parlio/test_apps/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h2", "esp32p4"] - temporary: true - reason: IDF-9806 waiting for the fix of the bit shift issue after reset depends_components: - esp_driver_parlio diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index 60aacfd5b9..cf5f0befcb 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -178,6 +178,8 @@ static void pulse_delimiter_sender_task_i2s(void *args) } } +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-9806 fix the bit shift issue in other target + static void cs_high(spi_transaction_t *trans) { gpio_set_level(TEST_VALID_GPIO, 1); @@ -274,6 +276,7 @@ static void level_delimiter_sender_task_spi(void *args) vTaskDelay(portMAX_DELAY); } } +#endif static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_clk, void (*sender_task_thread)(void *args)) { @@ -339,6 +342,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_ return is_success; } +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-9806 fix the bit shift issue in other target // This test case uses level delimiter TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]") { @@ -358,6 +362,7 @@ TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]") TEST_ESP_OK(parlio_del_rx_delimiter(deli)); TEST_ASSERT(is_success); } +#endif // This test case uses pulse delimiter TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]") diff --git a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py index dbb3f9d4e0..a6a6d8ec4e 100644 --- a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py +++ b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py @@ -5,6 +5,8 @@ from pytest_embedded import Dut @pytest.mark.esp32c6 +@pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize( 'config', diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index b64a04283b..f45af2fc0b 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1095,10 +1095,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH int default 16 +config SOC_PARLIO_TX_CLK_SUPPORT_GATING + bool + default y + +config SOC_PARLIO_RX_CLK_SUPPORT_GATING + bool + default y + config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT bool default y +config SOC_PARLIO_TRANS_BIT_ALIGN + bool + default y + config SOC_PARLIO_TX_SIZE_BY_DMA bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index aaf844bde9..9acb9c4e75 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -417,7 +417,10 @@ #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ +#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */ +#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ +#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ #define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */ /*--------------------------- MPI CAPS ---------------------------------------*/ diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 16a6e4fc82..6949eafd20 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -256,20 +256,12 @@ examples/peripherals/mcpwm/mcpwm_sync: examples/peripherals/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runner depends_components: - esp_driver_parlio examples/peripherals/parlio/parlio_rx: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runner depends_components: - esp_driver_parlio diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py b/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py new file mode 100644 index 0000000000..270d0dc4d4 --- /dev/null +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py @@ -0,0 +1,22 @@ +# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32c6 +@pytest.mark.esp32h2 +@pytest.mark.esp32p4 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'flash_stream', + ], + indirect=True, +) +def test_logic_analyzer_flash_stream(dut: Dut) -> None: + dut.expect(r'flash_fat: Probe data partition base addr: \w+ size: \w+') + dut.expect(r'flash_fat: flash FATFS mounted') + dut.expect(r'esp_probe: Dump data size reached the max dump size') + dut.expect(r'example: Probe finished! [0-9]+ \(\w+\) bytes dumped') diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream b/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream new file mode 100644 index 0000000000..4149416a65 --- /dev/null +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream @@ -0,0 +1 @@ +CONFIG_EXAMPLE_FLASH_STREAM=y