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Merge branch 'bugfix/format_ulp_astyle' into 'master'

Browse Source 
fix(ulp): enable astyle linter and format ULP component

See merge request espressif/esp-idf!28597
This commit is contained in:
Marius Vikhammer
2024-01-26 10:22:18 +08:00
parent b7184ccf73 1bcfde4e7f
commit b5540cfda6
51 changed files with 525 additions and 589 deletions
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2
components/ulp/lp_core/include/lp_core_i2c.h
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@@ -26,7 +26,6 @@ typedef struct {
bool scl_pullup_en; /*!< SCL line enable internal pullup. Can be configured if external pullup is not used. */ bool scl_pullup_en; /*!< SCL line enable internal pullup. Can be configured if external pullup is not used. */
} lp_core_i2c_pin_cfg_t; } lp_core_i2c_pin_cfg_t;
/** /**
* @brief LP Core I2C timing config parameters * @brief LP Core I2C timing config parameters
*/ */
@@ -34,7 +33,6 @@ typedef struct {
uint32_t clk_speed_hz; /*!< LP I2C clock speed for master mode */ uint32_t clk_speed_hz; /*!< LP I2C clock speed for master mode */
} lp_core_i2c_timing_cfg_t; } lp_core_i2c_timing_cfg_t;
/** /**
* @brief LP Core I2C config parameters * @brief LP Core I2C config parameters
*/ */

1
components/ulp/lp_core/include/ulp_lp_core.h
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@@ -15,7 +15,6 @@
extern "C" { extern "C" {
#endif #endif
#define ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup) #define ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup)
#define ULP_LP_CORE_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses #define ULP_LP_CORE_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses
#define ULP_LP_CORE_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt #define ULP_LP_CORE_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt

4
components/ulp/lp_core/lp_core.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -104,7 +104,6 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
return ESP_OK; return ESP_OK;
} }
@@ -129,7 +128,6 @@ esp_err_t ulp_lp_core_load_binary(const uint8_t* program_binary, size_t program_
return ESP_OK; return ESP_OK;
} }
void ulp_lp_core_stop(void) void ulp_lp_core_stop(void)
{ {
/* Disable wake-up source and put lp core to sleep */ /* Disable wake-up source and put lp core to sleep */

2
components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

2
components/ulp/lp_core/lp_core/lp_core_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

12
components/ulp/lp_core/lp_core/lp_core_print.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -178,8 +178,9 @@ static int lp_core_ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap
cp = "<null>"; cp = "<null>";
} }
length = 0; length = 0;
while (cp[length] != '\0') while (cp[length] != '\0') {
length++; length++;
}
break; break;
case 'c': case 'c':
case 'C': case 'C':
@@ -192,13 +193,14 @@ static int lp_core_ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap
case 'B': case 'B':
length = left_prec; length = left_prec;
if (left_prec == 0) { if (left_prec == 0) {
if (islonglong) if (islonglong) {
length = sizeof(long long) * 8; length = sizeof(long long) * 8;
else if (islong) } else if (islong) {
length = sizeof(long) * 8; length = sizeof(long) * 8;
else } else {
length = sizeof(int) * 8; length = sizeof(int) * 8;
} }
}
for (int i = 0; i < length - 1; i++) { for (int i = 0; i < length - 1; i++) {
buf[i] = ((val & ((long long)1 << i)) ? '1' : '.'); buf[i] = ((val & ((long long)1 << i)) ? '1' : '.');
} }

2
components/ulp/lp_core/lp_core/lp_core_startup.c
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@@ -7,10 +7,8 @@
#include "ulp_lp_core_lp_timer_shared.h" #include "ulp_lp_core_lp_timer_shared.h"
#include "ulp_lp_core_memory_shared.h" #include "ulp_lp_core_memory_shared.h"
extern void main(); extern void main();
/* Initialize lp core related system functions before calling user's main*/ /* Initialize lp core related system functions before calling user's main*/
void lp_core_startup() void lp_core_startup()
{ {

4
components/ulp/lp_core/lp_core/lp_core_utils.c
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@@ -1,10 +1,9 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdint.h> #include <stdint.h>
#include "riscv/csr.h" #include "riscv/csr.h"
#include "soc/soc.h" #include "soc/soc.h"
@@ -77,7 +76,6 @@ void ulp_lp_core_wakeup_main_processor(void)
REG_SET_FIELD(PMU_HP_LP_CPU_COMM_REG, PMU_LP_TRIGGER_HP, 1); REG_SET_FIELD(PMU_HP_LP_CPU_COMM_REG, PMU_LP_TRIGGER_HP, 1);
} }
/** /**
* @brief Makes the co-processor busy wait for a certain number of microseconds * @brief Makes the co-processor busy wait for a certain number of microseconds
* *

2
components/ulp/lp_core/lp_core_uart.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

1
components/ulp/lp_core/shared/include/ulp_lp_core_lp_timer_shared.h
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@@ -24,7 +24,6 @@ extern "C" {
*/ */
void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us); void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us);
/** /**
* @brief Disables the lp timer alarm and clears any pending alarm interrupts * @brief Disables the lp timer alarm and clears any pending alarm interrupts
* *

3
components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c
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@@ -26,7 +26,6 @@ static uint64_t lp_timer_hal_get_cycle_count(void)
uint32_t lo = lp_timer_ll_get_counter_value_low(lp_timer_context.dev, 0); uint32_t lo = lp_timer_ll_get_counter_value_low(lp_timer_context.dev, 0);
uint32_t hi = lp_timer_ll_get_counter_value_high(lp_timer_context.dev, 0); uint32_t hi = lp_timer_ll_get_counter_value_high(lp_timer_context.dev, 0);
lp_timer_counter_value_t result = { lp_timer_counter_value_t result = {
.lo = lo, .lo = lo,
.hi = hi .hi = hi
@@ -35,7 +34,6 @@ static uint64_t lp_timer_hal_get_cycle_count(void)
return result.val; return result.val;
} }
void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us) void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us)
{ {
uint64_t cycle_cnt = lp_timer_hal_get_cycle_count(); uint64_t cycle_cnt = lp_timer_hal_get_cycle_count();
@@ -44,7 +42,6 @@ void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us)
lp_timer_hal_set_alarm_target(alarm_target); lp_timer_hal_set_alarm_target(alarm_target);
} }
void ulp_lp_core_lp_timer_disable(void) void ulp_lp_core_lp_timer_disable(void)
{ {
lp_timer_ll_set_target_enable(lp_timer_context.dev, TIMER_ID, false); lp_timer_ll_set_target_enable(lp_timer_context.dev, TIMER_ID, false);

1
components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c
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@@ -9,7 +9,6 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "esp_assert.h" #include "esp_assert.h"
/* The last CONFIG_ULP_SHARED_MEM bytes of the reserved memory are reserved for a shared cfg struct /* The last CONFIG_ULP_SHARED_MEM bytes of the reserved memory are reserved for a shared cfg struct
The main cpu app and the ulp binary can share variables automatically through the linkerscript generated from The main cpu app and the ulp binary can share variables automatically through the linkerscript generated from
esp32ulp_mapgen.py, but this is not available when compiling the ULP library. esp32ulp_mapgen.py, but this is not available when compiling the ULP library.

4
components/ulp/test_apps/lp_core/main/lp_core/test_main.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -10,8 +10,6 @@
#include "test_shared.h" #include "test_shared.h"
#include "ulp_lp_core_utils.h" #include "ulp_lp_core_utils.h"
volatile lp_core_test_commands_t main_cpu_command = LP_CORE_NO_COMMAND; volatile lp_core_test_commands_t main_cpu_command = LP_CORE_NO_COMMAND;
volatile lp_core_test_command_reply_t main_cpu_reply = LP_CORE_COMMAND_INVALID; volatile lp_core_test_command_reply_t main_cpu_reply = LP_CORE_COMMAND_INVALID;
volatile lp_core_test_commands_t command_resp = LP_CORE_NO_COMMAND; volatile lp_core_test_commands_t command_resp = LP_CORE_NO_COMMAND;

1
components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c
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@@ -12,7 +12,6 @@
volatile uint32_t gpio_test_finished; volatile uint32_t gpio_test_finished;
volatile uint32_t gpio_test_succeeded; volatile uint32_t gpio_test_succeeded;
int main(void) int main(void)
{ {
ulp_lp_core_gpio_init(LP_IO_NUM_0); ulp_lp_core_gpio_init(LP_IO_NUM_0);

2
components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

6
components/ulp/test_apps/lp_core/main/test_lp_core.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -137,7 +137,6 @@ static void do_ulp_wakeup_deepsleep(lp_core_test_commands_t ulp_cmd)
UNITY_TEST_FAIL(__LINE__, "Should not get here!"); UNITY_TEST_FAIL(__LINE__, "Should not get here!");
} }
static void check_reset_reason_ulp_wakeup(void) static void check_reset_reason_ulp_wakeup(void)
{ {
TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause()); TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause());
@@ -195,7 +194,6 @@ static void check_reset_reason_and_sleep_duration(void)
TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause()); TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause());
int64_t sleep_duration = (tv_stop.tv_sec - tv_start.tv_sec) * 1000 + (tv_stop.tv_usec - tv_start.tv_usec) / 1000; int64_t sleep_duration = (tv_stop.tv_sec - tv_start.tv_sec) * 1000 + (tv_stop.tv_usec - tv_start.tv_usec) / 1000;
int64_t expected_sleep_duration_ms = ulp_counter_wakeup_limit * LP_TIMER_TEST_SLEEP_DURATION_US / 1000; int64_t expected_sleep_duration_ms = ulp_counter_wakeup_limit * LP_TIMER_TEST_SLEEP_DURATION_US / 1000;
@@ -210,7 +208,6 @@ TEST_CASE_MULTIPLE_STAGES("LP Timer can wakeup lp core periodically during deep
#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) #endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)
TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]") TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
{ {
int64_t start, test_duration; int64_t start, test_duration;
@@ -232,7 +229,6 @@ TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_counter, "LP Core did not wake up the expected number of times"); TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_counter, "LP Core did not wake up the expected number of times");
} }
static bool ulp_is_running(uint32_t *counter_variable) static bool ulp_is_running(uint32_t *counter_variable)
{ {
uint32_t start_cnt = *counter_variable; uint32_t start_cnt = *counter_variable;

6
components/ulp/test_apps/lp_core/main/test_lp_core_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -31,14 +31,12 @@ static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_
} }
#define I2C_SCL_IO 7 /*!<gpio number for i2c clock, for C6 only GPIO7 is valid */ #define I2C_SCL_IO 7 /*!<gpio number for i2c clock, for C6 only GPIO7 is valid */
#define I2C_SDA_IO 6 /*!<gpio number for i2c data, for C6 only GPIO6 is valid */ #define I2C_SDA_IO 6 /*!<gpio number for i2c data, for C6 only GPIO6 is valid */
#define I2C_SLAVE_NUM I2C_NUM_0 /*!<I2C port number for slave dev */ #define I2C_SLAVE_NUM I2C_NUM_0 /*!<I2C port number for slave dev */
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */ #define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */ #define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
static uint8_t expected_master_write_data[DATA_LENGTH]; static uint8_t expected_master_write_data[DATA_LENGTH];
static uint8_t expected_master_read_data[DATA_LENGTH]; static uint8_t expected_master_read_data[DATA_LENGTH];
@@ -97,8 +95,6 @@ static void i2c_master_write_read_test(void)
} }
} }
static i2c_config_t i2c_slave_init(void) static i2c_config_t i2c_slave_init(void)
{ {
i2c_config_t conf_slave = { i2c_config_t conf_slave = {

12
components/ulp/test_apps/ulp_fsm/main/test_ulp.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -34,7 +34,8 @@ extern const uint8_t ulp_test_app_bin_end[] asm("_binary_ulp_test_app_bin_end"
#define HEX_DUMP_DEBUG 0 #define HEX_DUMP_DEBUG 0
static void hexdump(const uint32_t* src, size_t count) { static void hexdump(const uint32_t* src, size_t count)
{
#if HEX_DUMP_DEBUG #if HEX_DUMP_DEBUG
for (size_t i = 0; i < count; ++i) { for (size_t i = 0; i < count; ++i) {
printf("%08x ", *src); printf("%08x ", *src);
@@ -246,7 +247,6 @@ TEST_CASE_MULTIPLE_STAGES("ULP FSM deep-sleep wakeup test", "[deepsleep][reset=D
ulp_fsm_deepsleep_wakeup_test, ulp_fsm_deepsleep_wakeup_test,
check_sleep_reset) check_sleep_reset)
TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]") TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
{ {
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -378,9 +378,6 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
} }
} }
TEST_CASE("ULP FSM timer setting", "[ulp]") TEST_CASE("ULP FSM timer setting", "[ulp]")
{ {
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -418,7 +415,8 @@ TEST_CASE("ULP FSM timer setting", "[ulp]")
100000, // 100 ms 100000, // 100 ms
200000, // 200 ms 200000, // 200 ms
500000, // 500 ms 500000, // 500 ms
1000000 }; // 1 sec 1000000
}; // 1 sec
const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]); const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
for (size_t i = 0; i < tests_count; ++i) { for (size_t i = 0; i < tests_count; ++i) {

4
components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -183,8 +183,6 @@ void ulp_fsm_temp_sens(void)
} }
#endif //#if !DISABLED_FOR_TARGETS(ESP32) #endif //#if !DISABLED_FOR_TARGETS(ESP32)
void ulp_fsm_adc(void) void ulp_fsm_adc(void)
{ {
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");

8
components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -261,8 +261,6 @@ TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]"
TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter)); TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
} }
TEST_CASE("ULP-RISC-V mutex", "[ulp]") TEST_CASE("ULP-RISC-V mutex", "[ulp]")
{ {
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */ /* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
@@ -291,7 +289,6 @@ TEST_CASE("ULP-RISC-V mutex", "[ulp]")
TEST_ASSERT_EQUAL(2 * MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer); TEST_ASSERT_EQUAL(2 * MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer);
} }
static void do_ulp_wakeup_deepsleep(riscv_test_commands_t ulp_cmd, bool rtc_periph_pd) static void do_ulp_wakeup_deepsleep(riscv_test_commands_t ulp_cmd, bool rtc_periph_pd)
{ {
if (!rtc_periph_pd) { if (!rtc_periph_pd) {
@@ -328,7 +325,6 @@ TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep
do_ulp_wakeup_after_long_delay_deepsleep, do_ulp_wakeup_after_long_delay_deepsleep,
check_reset_reason_ulp_wakeup); check_reset_reason_ulp_wakeup);
static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void) static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void)
{ {
do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST, false); do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST, false);
@@ -347,7 +343,6 @@ TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep
do_ulp_wakeup_after_short_delay_deepsleep, do_ulp_wakeup_after_short_delay_deepsleep,
check_reset_reason_ulp_wakeup); check_reset_reason_ulp_wakeup);
static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void) static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void)
{ {
do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST, false); do_ulp_wakeup_deepsleep(RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST, false);
@@ -445,7 +440,6 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core
TEST_CASE("ULP ADC can init-deinit-init", "[ulp]") TEST_CASE("ULP ADC can init-deinit-init", "[ulp]")
{ {
ulp_adc_cfg_t riscv_adc_cfg = { ulp_adc_cfg_t riscv_adc_cfg = {
.adc_n = ADC_UNIT, .adc_n = ADC_UNIT,
.channel = CHANNEL, .channel = CHANNEL,

3
components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,7 +12,6 @@
#include "ulp_riscv_lock_ulp_core.h" #include "ulp_riscv_lock_ulp_core.h"
#include "ulp_test_shared.h" #include "ulp_test_shared.h"
volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND; volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID; volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND; volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND;

2
components/ulp/ulp_common/ulp_common.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

13
components/ulp/ulp_fsm/include/esp32/ulp.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -22,7 +22,6 @@ extern "C" {
* @{ * @{
*/ */
#define R0 0 /*!< general purpose register 0 */ #define R0 0 /*!< general purpose register 0 */
#define R1 1 /*!< general purpose register 1 */ #define R1 1 /*!< general purpose register 1 */
#define R2 2 /*!< general purpose register 2 */ #define R2 2 /*!< general purpose register 2 */
@@ -102,7 +101,6 @@ extern "C" {
#define SUB_OPCODE_MACRO_LABELPC 2 /*!< Label pointer macro */ #define SUB_OPCODE_MACRO_LABELPC 2 /*!< Label pointer macro */
/**@}*/ /**@}*/
/** /**
* @brief Instruction format structure * @brief Instruction format structure
* *
@@ -306,7 +304,8 @@ union ulp_insn {
* @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals.
* @return periph_sel value for the peripheral to which this register belongs. * @return periph_sel value for the peripheral to which this register belongs.
*/ */
static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
{
uint32_t ret = 3; uint32_t ret = 3;
if (reg < DR_REG_RTCCNTL_BASE) { if (reg < DR_REG_RTCCNTL_BASE) {
assert(0 && "invalid register base"); assert(0 && "invalid register base");
@@ -465,7 +464,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.sub_opcode = SUB_OPCODE_ST, \ .sub_opcode = SUB_OPCODE_ST, \
.opcode = OPCODE_ST } } .opcode = OPCODE_ST } }
/** /**
* Load value from RTC memory into reg_dest register. * Load value from RTC memory into reg_dest register.
* *
@@ -480,7 +478,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.unused2 = 0, \ .unused2 = 0, \
.opcode = OPCODE_LD } } .opcode = OPCODE_LD } }
/** /**
* Branch relative if R0 less than immediate value. * Branch relative if R0 less than immediate value.
* *
@@ -596,7 +593,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.sub_opcode = SUB_OPCODE_BX, \ .sub_opcode = SUB_OPCODE_BX, \
.opcode = OPCODE_BRANCH } } .opcode = OPCODE_BRANCH } }
/** /**
* Addition: dest = src1 + src2 * Addition: dest = src1 + src2
*/ */
@@ -669,7 +665,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.sub_opcode = SUB_OPCODE_ALU_REG, \ .sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right: dest = src >> shift * Logical shift right: dest = src >> shift
*/ */
@@ -694,7 +689,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Subtract register and an immediate value: dest = src - imm * Subtract register and an immediate value: dest = src - imm
*/ */
@@ -755,7 +749,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right register value by an immediate: dest = val >> imm * Logical shift right register value by an immediate: dest = val >> imm
*/ */

4
components/ulp/ulp_fsm/include/esp32s2/ulp.h
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@@ -22,7 +22,6 @@ extern "C" {
* @{ * @{
*/ */
#define R0 0 /*!< general purpose register 0 */ #define R0 0 /*!< general purpose register 0 */
#define R1 1 /*!< general purpose register 1 */ #define R1 1 /*!< general purpose register 1 */
#define R2 2 /*!< general purpose register 2 */ #define R2 2 /*!< general purpose register 2 */
@@ -906,7 +905,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_REG, \ .sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right: dest = src >> shift * Logical shift right: dest = src >> shift
*/ */
@@ -933,7 +931,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Subtract register and an immediate value: dest = src - imm * Subtract register and an immediate value: dest = src - imm
*/ */
@@ -999,7 +996,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right register value by an immediate: dest = val >> imm * Logical shift right register value by an immediate: dest = val >> imm
*/ */

4
components/ulp/ulp_fsm/include/esp32s3/ulp.h
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@@ -22,7 +22,6 @@ extern "C" {
* @{ * @{
*/ */
#define R0 0 /*!< general purpose register 0 */ #define R0 0 /*!< general purpose register 0 */
#define R1 1 /*!< general purpose register 1 */ #define R1 1 /*!< general purpose register 1 */
#define R2 2 /*!< general purpose register 2 */ #define R2 2 /*!< general purpose register 2 */
@@ -906,7 +905,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_REG, \ .sub_opcode = SUB_OPCODE_ALU_REG, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right: dest = src >> shift * Logical shift right: dest = src >> shift
*/ */
@@ -933,7 +931,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Subtract register and an immediate value: dest = src - imm * Subtract register and an immediate value: dest = src - imm
*/ */
@@ -999,7 +996,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
.sub_opcode = SUB_OPCODE_ALU_IMM, \ .sub_opcode = SUB_OPCODE_ALU_IMM, \
.opcode = OPCODE_ALU } } .opcode = OPCODE_ALU } }
/** /**
* Logical shift right register value by an immediate: dest = val >> imm * Logical shift right register value by an immediate: dest = val >> imm
*/ */

2
components/ulp/ulp_fsm/ulp.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

3
components/ulp/ulp_fsm/ulp_macro.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -84,7 +84,6 @@ static int reloc_sort_func(const void* p_lhs, const void* p_rhs)
return 0; return 0;
} }
/* Processing branch and label macros involves four steps: /* Processing branch and label macros involves four steps:
* *
* 1. Iterate over program and count all instructions * 1. Iterate over program and count all instructions

2
components/ulp/ulp_riscv/include/ulp_riscv.h
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@@ -112,7 +112,6 @@ esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_si
*/ */
void ulp_riscv_timer_stop(void); void ulp_riscv_timer_stop(void);
/** /**
* @brief Resumes the ULP timer * @brief Resumes the ULP timer
* *
@@ -121,7 +120,6 @@ void ulp_riscv_timer_stop(void);
*/ */
void ulp_riscv_timer_resume(void); void ulp_riscv_timer_resume(void);
/** /**
* @brief Halts the program currently running on the ULP-RISC-V * @brief Halts the program currently running on the ULP-RISC-V
* *

1
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h
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@@ -11,7 +11,6 @@
extern "C" { extern "C" {
#endif #endif
/** /**
* @brief Locks are based on the Peterson's algorithm, https://en.wikipedia.org/wiki/Peterson%27s_algorithm * @brief Locks are based on the Peterson's algorithm, https://en.wikipedia.org/wiki/Peterson%27s_algorithm
* *

3
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_print.h
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@@ -13,7 +13,6 @@ extern "C" {
/* Underlying driver function for printing a char, e.g. over UART */ /* Underlying driver function for printing a char, e.g. over UART */
typedef void (*putc_fn_t)(const void *ctx, const char c); typedef void (*putc_fn_t)(const void *ctx, const char c);
/** /**
* @brief Installs a print driver that will be used for ulp_riscv_print calls * @brief Installs a print driver that will be used for ulp_riscv_print calls
* *
@@ -22,7 +21,6 @@ typedef void (*putc_fn_t)(const void *ctx, const char c);
*/ */
void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx); void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx);
/** /**
* @brief Prints a null-terminated string * @brief Prints a null-terminated string
* *
@@ -30,7 +28,6 @@ void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx);
*/ */
void ulp_riscv_print_str(const char *str); void ulp_riscv_print_str(const char *str);
/** /**
* @brief Prints a hex number. Does not print 0x, only the digits * @brief Prints a hex number. Does not print 0x, only the digits
* *

1
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
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@@ -83,7 +83,6 @@ esp_err_t ulp_riscv_touch_pad_sleep_channel_read_benchmark(touch_pad_t touch_num
*/ */
esp_err_t ulp_riscv_touch_pad_sleep_channel_read_smooth(touch_pad_t touch_num, uint32_t *smooth_data); esp_err_t ulp_riscv_touch_pad_sleep_channel_read_smooth(touch_pad_t touch_num, uint32_t *smooth_data);
/** /**
* @brief Reset benchmark of touch sensor sleep channel. * @brief Reset benchmark of touch sensor sleep channel.
* @note Refer `touch_pad_sleep_channel_reset_benchmark()` for more details * @note Refer `touch_pad_sleep_channel_reset_benchmark()` for more details

1
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_uart_ulp_core.h
View File

@@ -22,7 +22,6 @@ typedef struct {
gpio_num_t tx_pin; // TX pin number gpio_num_t tx_pin; // TX pin number
} ulp_riscv_uart_t; // Context for the driver, initialized by ulp_riscv_uart_init } ulp_riscv_uart_t; // Context for the driver, initialized by ulp_riscv_uart_init
/** /**
* @brief Initialize the bit-banged UART driver * @brief Initialize the bit-banged UART driver
* *

4
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -67,7 +67,6 @@ void __attribute__((__noreturn__)) ulp_riscv_halt(void);
*/ */
void ulp_riscv_timer_stop(void); void ulp_riscv_timer_stop(void);
/** /**
* @brief Resumes the ULP timer * @brief Resumes the ULP timer
* *
@@ -80,7 +79,6 @@ void ulp_riscv_timer_resume(void);
asm volatile("rdcycle %0;" : "=r"(__ccount)); \ asm volatile("rdcycle %0;" : "=r"(__ccount)); \
__ccount; }) __ccount; })
#if CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32S2
/* These are only approximate default numbers, the default frequency /* These are only approximate default numbers, the default frequency
of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting

2
components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

2
components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

5
components/ulp/ulp_riscv/ulp_riscv.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -99,7 +99,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
{ {
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
#if CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32S2
/* Reset COCPU when power on. */ /* Reset COCPU when power on. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
@@ -128,7 +127,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
/* Disable ULP timer */ /* Disable ULP timer */
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
/* wait for at least 1 RTC_SLOW_CLK cycle */ /* wait for at least 1 RTC_SLOW_CLK cycle */
@@ -159,7 +157,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
esp_rom_delay_us(20); esp_rom_delay_us(20);
REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR); REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR);
#endif #endif
return ret; return ret;

2
components/ulp/ulp_riscv/ulp_riscv_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

1
tools/ci/astyle-rules.yml
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@@ -107,7 +107,6 @@ components_not_formatted_temporary:
- "/components/spiffs/" - "/components/spiffs/"
- "/components/tcp_transport/" - "/components/tcp_transport/"
- "/components/touch_element/" - "/components/touch_element/"
- "/components/ulp/"
- "/components/unity/" - "/components/unity/"
- "/components/vfs/" - "/components/vfs/"
- "/components/wear_levelling/" - "/components/wear_levelling/"