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hal/esp32h2: Enable ll layer for flash encryption

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This commit is contained in:
Aditya Patwardhan
2023-02-23 19:40:22 +05:30
parent aaf5d0670e
commit b5b7f32e46
2 changed files with 23 additions and 21 deletions
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4
components/hal/CMakeLists.txt
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@@ -47,8 +47,10 @@ if(NOT BOOTLOADER_BUILD)
list(APPEND srcs list(APPEND srcs
"spi_flash_hal.c" "spi_flash_hal.c"
"spi_flash_hal_iram.c" "spi_flash_hal_iram.c"
"spi_flash_encrypt_hal_iram.c"
) )
if(CONFIG_SOC_FLASH_ENC_SUPPORTED)
list(APPEND srcs "spi_flash_encrypt_hal_iram.c")
endif()
endif() endif()
if(CONFIG_SOC_SYSTIMER_SUPPORTED AND NOT CONFIG_HAL_SYSTIMER_USE_ROM_IMPL) if(CONFIG_SOC_SYSTIMER_SUPPORTED AND NOT CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)

40
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -35,9 +35,9 @@ typedef enum
*/ */
static inline void spi_flash_encrypt_ll_enable(void) static inline void spi_flash_encrypt_ll_enable(void)
{ {
// REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
// HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
// HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
} }
/* /*
@@ -45,8 +45,8 @@ static inline void spi_flash_encrypt_ll_enable(void)
*/ */
static inline void spi_flash_encrypt_ll_disable(void) static inline void spi_flash_encrypt_ll_disable(void)
{ {
// REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
// HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
} }
/** /**
@@ -59,8 +59,8 @@ static inline void spi_flash_encrypt_ll_disable(void)
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{ {
// Our hardware only support flash encryption // Our hardware only support flash encryption
// HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
// REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type); REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
} }
/** /**
@@ -71,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{ {
// Desired block should not be larger than the block size. // Desired block should not be larger than the block size.
// REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5); REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
} }
/** /**
@@ -84,8 +84,8 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
*/ */
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size) static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
{ {
// uint32_t plaintext_offs = (address % 64); uint32_t plaintext_offs = (address % 64);
// memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size); memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
} }
/** /**
@@ -95,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/ */
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{ {
// REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr); REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
} }
/** /**
@@ -103,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/ */
static inline void spi_flash_encrypt_ll_calculate_start(void) static inline void spi_flash_encrypt_ll_calculate_start(void)
{ {
// REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1); REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
} }
/** /**
@@ -111,8 +111,8 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/ */
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{ {
// while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) { while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
// } }
} }
/** /**
@@ -120,9 +120,9 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/ */
static inline void spi_flash_encrypt_ll_done(void) static inline void spi_flash_encrypt_ll_done(void)
{ {
// REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE); REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
// while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) { while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
// } }
} }
/** /**
@@ -130,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/ */
static inline void spi_flash_encrypt_ll_destroy(void) static inline void spi_flash_encrypt_ll_destroy(void)
{ {
// REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY); REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
} }
/** /**
@@ -141,7 +141,7 @@ static inline void spi_flash_encrypt_ll_destroy(void)
*/ */
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{ {
return false;//((address % length) == 0) ? true : false; return ((address % length) == 0) ? true : false;
} }
#ifdef __cplusplus #ifdef __cplusplus