From b947ff99da2734c626b277c419b7d22ec9d202f5 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 8 Aug 2024 14:38:20 +0800 Subject: [PATCH 1/2] feat(sdm): remove sigma delta gpio on c61 --- .../soc/esp32c61/include/soc/clk_tree_defs.h | 16 ---------------- components/soc/esp32c61/include/soc/soc_caps.h | 3 +-- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index ab58324479..3a52fefe79 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -258,22 +258,6 @@ typedef enum { SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ } soc_periph_spi_clk_src_t; -//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of SDM - */ -#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} - -/** - * @brief Sigma Delta Modulator clock source - */ -typedef enum { - SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ - SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ -} soc_periph_sdm_clk_src_t; - //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 8525e5b7cc..d0f8f511a2 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -161,10 +161,9 @@ // ESP32-C61 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 22 -// \#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340 // GPIO peripheral has the ETM extension -// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340 +// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9318 // Target has the full LP IO subsystem // On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. From a1fc225aaa0a3b4f017085c87adab7510c07b592 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 8 Aug 2024 18:29:55 +0800 Subject: [PATCH 2/2] feat(glitch_filter): remove glitch filter on c61 --- components/soc/esp32c61/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32c61/include/soc/soc_caps.h | 1 + 2 files changed, 5 insertions(+) diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index c57abf756f..0284406515 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -227,6 +227,10 @@ config SOC_GPIO_PIN_COUNT int default 22 +config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER + bool + default y + config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index d0f8f511a2..f3bedfa321 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -161,6 +161,7 @@ // ESP32-C61 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 22 +#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 // GPIO peripheral has the ETM extension // \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9318