From ba0a2db0376652aea1a0b746c57797774ea278c1 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 2 Apr 2025 17:26:29 +0800 Subject: [PATCH] refactor(esp32c61): update bus_monitor registers for C61 --- .../esp32c61/register/soc/assist_debug_reg.h | 1150 +++++++---------- .../register/soc/assist_debug_struct.h | 524 +++----- .../esp32c61/register/soc/mem_monitor_reg.h | 203 ++- .../register/soc/mem_monitor_struct.h | 209 ++- 4 files changed, 826 insertions(+), 1260 deletions(-) diff --git a/components/soc/esp32c61/register/soc/assist_debug_reg.h b/components/soc/esp32c61/register/soc/assist_debug_reg.h index 95529bc19c..07efd7fac3 100644 --- a/components/soc/esp32c61/register/soc/assist_debug_reg.h +++ b/components/soc/esp32c61/register/soc/assist_debug_reg.h @@ -1,822 +1,602 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register - * core0 monitor enable configuration register +/** BUS_MONITOR_CORE_0_MONTR_ENA_REG register + * Configures whether to enable HP CPU monitoring */ -#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; - * Configures whether to monitor read operations in region 0 by the Data bus. \\ - * 0: Not monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x0) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Configures whether to monitor read operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; - * Configures whether to monitor write operations in region 0 by the Data bus.\\ - * 0: Not monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Configures whether to monitor write operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; - * Configures whether to monitor read operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Configures whether to monitor read operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; - * Configures whether to monitor write operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Configures whether to monitor write operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; - * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Configures whether to monitor read operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; - * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Configures whether to monitor write operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; - * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Configures whether to monitor read operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; - * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Configures whether to monitor write operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; * Configures whether to monitor SP exceeding the lower bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * region. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; * Configures whether to monitor SP exceeding the upper bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor enable - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enable - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register - * core0 monitor interrupt status register - */ -#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; - * The raw interrupt status of read operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; - * The raw interrupt status of write operations in region 0 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; - * The raw interrupt status of read operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; - * The raw interrupt status of write operations in region 1 by Data bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; - * The raw interrupt status of read operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; - * The raw interrupt status of write operations in region 0 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; - * The raw interrupt status of read operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; - * The raw interrupt status of write operations in region 1 by Peripheral bus. - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; - * The raw interrupt status of SP exceeding the lower bound address of SP monitored * region. + * 0: Not Monitor + * 1: Monitor */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; - * The raw interrupt status of SP exceeding the upper bound address of SP monitored - * region. - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt status - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; - * DBUS busy monitor initerrupt status - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register - * core0 monitor interrupt enable register +/** BUS_MONITOR_CORE_0_INTR_RAW_REG register + * HP CPU monitor raw interrupt status register */ -#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; - * Core0 dram0 area0 read monitor interrupt enable +#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x4) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; - * Core0 dram0 area0 write monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; - * Core0 dram0 area1 read monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; - * Core0 dram0 area1 write monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; - * Core0 PIF area0 read monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; - * Core0 PIF area0 write monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; - * Core0 PIF area1 read monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; - * Core0 PIF area1 write monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; - * Core0 stackpoint underflow monitor interrupt enable +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; - * Core0 stackpoint overflow monitor interrupt enable +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enable - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11 +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S 9 -/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register - * core0 monitor interrupt clear register +/** BUS_MONITOR_CORE_0_INTR_ENA_REG register + * HP CPU monitor interrupt enable register */ -#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Data bus. +#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x8) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Data bus. +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Data bus. +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Data bus. +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP - * monitored region. +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP - * monitored region. +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt clr - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt clr - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register +/** BUS_MONITOR_CORE_0_INTR_CLR_REG register + * HP CPU monitor interrupt clear register + */ +#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0xc) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. + */ +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. + */ +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S) +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S 9 + +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG register * Configures lower boundary address of region 0 monitored on Data bus */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x10) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Data bus region 0. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG register * Configures upper boundary address of region 0 monitored on Data bus */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x14) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Data bus region 0. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG register * Configures lower boundary address of region 1 monitored on Data bus */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x18) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Data bus region 1. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG register * Configures upper boundary address of region 1 monitored on Data bus */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x1c) +/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Data bus region 1. */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG register * Configures lower boundary address of region 0 monitored on Peripheral bus */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x20) +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Peripheral bus region 0. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG register * Configures upper boundary address of region 0 monitored on Peripheral bus */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x24) +/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Peripheral bus region 0. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG register * Configures lower boundary address of region 1 monitored on Peripheral bus */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x28) +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Peripheral bus region 1. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG register * Configures upper boundary address of region 1 monitored on Peripheral bus */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x2c) +/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Peripheral bus region 1. */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S) +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register - * Region monitoring HP CPU PC status register +/** BUS_MONITOR_CORE_0_AREA_PC_REG register + * Represents the PC value when HP CPU region monitor is triggered */ -#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) -/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x30) +/** BUS_MONITOR_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; * Represents the PC value when an interrupt is triggered during region monitoring. */ -#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) -#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 +#define BUS_MONITOR_CORE_0_AREA_PC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PC_M (BUS_MONITOR_CORE_0_AREA_PC_V << BUS_MONITOR_CORE_0_AREA_PC_S) +#define BUS_MONITOR_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_PC_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register - * Region monitoring HP CPU SP status register +/** BUS_MONITOR_CORE_0_AREA_SP_REG register + * Represents the SP value when HP CPU region monitor is triggered */ -#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) -/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0x34) +/** BUS_MONITOR_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; * Represents the SP value when an interrupt is triggered during region monitoring. */ -#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) -#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 +#define BUS_MONITOR_CORE_0_AREA_SP 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_SP_M (BUS_MONITOR_CORE_0_AREA_SP_V << BUS_MONITOR_CORE_0_AREA_SP_S) +#define BUS_MONITOR_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_AREA_SP_S 0 -/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register - * Configures stack monitoring lower boundary address +/** BUS_MONITOR_CORE_0_SP_MIN_REG register + * Configures SP monitoring lower boundary address */ -#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) -/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; - * Configures the lower bound address of SP. +#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x38) +/** BUS_MONITOR_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of SP monitored region. */ -#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) -#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 +#define BUS_MONITOR_CORE_0_SP_MIN 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MIN_M (BUS_MONITOR_CORE_0_SP_MIN_V << BUS_MONITOR_CORE_0_SP_MIN_S) +#define BUS_MONITOR_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MIN_S 0 -/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register - * Configures stack monitoring upper boundary address +/** BUS_MONITOR_CORE_0_SP_MAX_REG register + * Configures SP monitoring upper boundary address */ -#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) -/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the upper bound address of SP. +#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x3c) +/** BUS_MONITOR_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the upper bound address of SP monitored region. */ -#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) -#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 +#define BUS_MONITOR_CORE_0_SP_MAX 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MAX_M (BUS_MONITOR_CORE_0_SP_MAX_V << BUS_MONITOR_CORE_0_SP_MAX_S) +#define BUS_MONITOR_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_MAX_S 0 -/** ASSIST_DEBUG_CORE_0_SP_PC_REG register - * Stack monitoring HP CPU PC status register +/** BUS_MONITOR_CORE_0_SP_PC_REG register + * Represents the PC value when HP CPU SP monitor is triggered */ -#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) -/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * Represents the PC value during stack monitoring. +#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x40) +/** BUS_MONITOR_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value when SP monitoring is triggered. */ -#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) -#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 +#define BUS_MONITOR_CORE_0_SP_PC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_PC_M (BUS_MONITOR_CORE_0_SP_PC_V << BUS_MONITOR_CORE_0_SP_PC_S) +#define BUS_MONITOR_CORE_0_SP_PC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_SP_PC_S 0 -/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register +/** BUS_MONITOR_CORE_0_RCD_EN_REG register * HP CPU PC logging enable register */ -#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) -/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; - * Configures whether to enable PC logging.\\ - * 0: Disable\\ - * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ +#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0x44) +/** BUS_MONITOR_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable PC and SP logging. + * 0: Disable + * 1: BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time, + * BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG starts to record SP in real time */ -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; - * Configures whether to enable HP CPU debugging.\\ - * 0: Disable\\ - * 1: HP CPU outputs PC\\ +#define BUS_MONITOR_CORE_0_RCD_RECORDEN (BIT(0)) +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_M (BUS_MONITOR_CORE_0_RCD_RECORDEN_V << BUS_MONITOR_CORE_0_RCD_RECORDEN_S) +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_V 0x00000001U +#define BUS_MONITOR_CORE_0_RCD_RECORDEN_S 0 +/** BUS_MONITOR_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Configures whether to enable HP CPU debugging. + * 0: Disable + * 1: HP CPU outputs PC */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_M (BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V << BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S 1 -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * PC logging register +/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG register + * HP CPU PC logging register */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0x48) +/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; * Represents the PC value at HP CPU reset. */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_M (BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V << BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S 0 -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * PC logging register +/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG register + * HP CPU SP logging register */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0x4c) +/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; * Represents SP. */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_M (BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V << BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S) +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register0 +/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * PC of the last command before HP CPU enters exception */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_0 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31 - -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_1 - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register2 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register3 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register - * exception monitor status register4 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_0 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register - * exception monitor status register5 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register - * exception monitor status register6 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register - * exception monitor status register7 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_1 - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 - -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register - * cpu status register - */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0x70) +/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; * Represents the PC of the last command before the HP CPU enters exception. */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_M (BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V << BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S) +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S 0 -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register - * cpu status register +/** BUS_MONITOR_CORE_0_DEBUG_MODE_REG register + * HP CPU debug mode status register */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; - * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ - * 1: In debugging mode\\ - * 0: Not in debugging mode\\ +#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0x74) +/** BUS_MONITOR_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * Represents whether RISC-V CPU (HP CPU) is in debugging mode. + * 1: In debugging mode + * 0: Not in debugging mode */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 -/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; - * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ - * 1: Active status\\ - * Other: Inactive status\\ +#define BUS_MONITOR_CORE_0_DEBUG_MODE (BIT(0)) +#define BUS_MONITOR_CORE_0_DEBUG_MODE_M (BUS_MONITOR_CORE_0_DEBUG_MODE_V << BUS_MONITOR_CORE_0_DEBUG_MODE_S) +#define BUS_MONITOR_CORE_0_DEBUG_MODE_V 0x00000001U +#define BUS_MONITOR_CORE_0_DEBUG_MODE_S 0 +/** BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * Represents the status of the RISC-V CPU (HP CPU) debug module. + * 1: Active status + * Other: Inactive status */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_M (BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V << BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S 1 -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register - * exception monitor status register8 +/** BUS_MONITOR_CLOCK_GATE_REG register + * Clock control register */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_0 +#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_MONITOR_BASE + 0x108) +/** BUS_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 +#define BUS_MONITOR_CLK_EN (BIT(0)) +#define BUS_MONITOR_CLK_EN_M (BUS_MONITOR_CLK_EN_V << BUS_MONITOR_CLK_EN_S) +#define BUS_MONITOR_CLK_EN_V 0x00000001U +#define BUS_MONITOR_CLK_EN_S 0 -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register - * exception monitor status register9 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_1 - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 - -/** ASSIST_DEBUG_CLOCK_GATE_REG register - * Register clock control - */ -#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108) -/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to enable the register clock gating. \\ - * 0: Disable\\ - * 1: Enable\\ - */ -#define ASSIST_DEBUG_CLK_EN (BIT(0)) -#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) -#define ASSIST_DEBUG_CLK_EN_V 0x00000001U -#define ASSIST_DEBUG_CLK_EN_S 0 - -/** ASSIST_DEBUG_DATE_REG register +/** BUS_MONITOR_DATE_REG register * Version control register */ -#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) -/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; - * version register +#define BUS_MONITOR_DATE_REG (DR_REG_BUS_MONITOR_BASE + 0x3fc) +/** BUS_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34640176; + * Version control register. */ -#define ASSIST_DEBUG_DATE 0x0FFFFFFFU -#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) -#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU -#define ASSIST_DEBUG_DATE_S 0 +#define BUS_MONITOR_DATE 0x0FFFFFFFU +#define BUS_MONITOR_DATE_M (BUS_MONITOR_DATE_V << BUS_MONITOR_DATE_S) +#define BUS_MONITOR_DATE_V 0x0FFFFFFFU +#define BUS_MONITOR_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32c61/register/soc/assist_debug_struct.h b/components/soc/esp32c61/register/soc/assist_debug_struct.h index ca55d0cb8f..89e028fe20 100644 --- a/components/soc/esp32c61/register/soc/assist_debug_struct.h +++ b/components/soc/esp32c61/register/soc/assist_debug_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,86 +10,78 @@ extern "C" { #endif -/** Group: monitor configuration registers */ +/** Group: Monitor configuration registers */ /** Type of core_0_montr_ena register - * core0 monitor enable configuration register + * Configures whether to enable HP CPU monitoring */ typedef union { struct { /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; - * Configures whether to monitor read operations in region 0 by the Data bus. \\ - * 0: Not monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ uint32_t core_0_area_dram0_0_rd_ena:1; /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; - * Configures whether to monitor write operations in region 0 by the Data bus.\\ - * 0: Not monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 0 by the Data bus. + * 0: Not monitor + * 1: Monitor */ uint32_t core_0_area_dram0_0_wr_ena:1; /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; - * Configures whether to monitor read operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_dram0_1_rd_ena:1; /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; - * Configures whether to monitor write operations in region 1 by the Data bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 1 by the Data bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_dram0_1_wr_ena:1; /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; - * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_0_rd_ena:1; /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; - * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 0 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_0_wr_ena:1; /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; - * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor read operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_1_rd_ena:1; /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; - * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * Configures whether to monitor write operations in region 1 by the Peripheral bus. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_area_pif_1_wr_ena:1; /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; * Configures whether to monitor SP exceeding the lower bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * region. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_sp_spill_min_ena:1; /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; * Configures whether to monitor SP exceeding the upper bound address of SP monitored - * region.\\ - * 0: Not Monitor\\ - * 1: Monitor\\ + * region. + * 0: Not Monitor + * 1: Monitor */ uint32_t core_0_sp_spill_max_ena:1; - /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor enable - */ - uint32_t core_0_iram0_exception_monitor_ena:1; - /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor enable - */ - uint32_t core_0_dram0_exception_monitor_ena:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_montr_ena_reg_t; +} bus_monitor_core_0_montr_ena_reg_t; /** Type of core_0_area_dram0_0_min register * Configures lower boundary address of region 0 monitored on Data bus @@ -102,7 +94,7 @@ typedef union { uint32_t core_0_area_dram0_0_min:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_0_min_reg_t; +} bus_monitor_core_0_area_dram0_0_min_reg_t; /** Type of core_0_area_dram0_0_max register * Configures upper boundary address of region 0 monitored on Data bus @@ -115,7 +107,7 @@ typedef union { uint32_t core_0_area_dram0_0_max:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_0_max_reg_t; +} bus_monitor_core_0_area_dram0_0_max_reg_t; /** Type of core_0_area_dram0_1_min register * Configures lower boundary address of region 1 monitored on Data bus @@ -128,7 +120,7 @@ typedef union { uint32_t core_0_area_dram0_1_min:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_1_min_reg_t; +} bus_monitor_core_0_area_dram0_1_min_reg_t; /** Type of core_0_area_dram0_1_max register * Configures upper boundary address of region 1 monitored on Data bus @@ -141,7 +133,7 @@ typedef union { uint32_t core_0_area_dram0_1_max:32; }; uint32_t val; -} assist_debug_core_0_area_dram0_1_max_reg_t; +} bus_monitor_core_0_area_dram0_1_max_reg_t; /** Type of core_0_area_pif_0_min register * Configures lower boundary address of region 0 monitored on Peripheral bus @@ -154,7 +146,7 @@ typedef union { uint32_t core_0_area_pif_0_min:32; }; uint32_t val; -} assist_debug_core_0_area_pif_0_min_reg_t; +} bus_monitor_core_0_area_pif_0_min_reg_t; /** Type of core_0_area_pif_0_max register * Configures upper boundary address of region 0 monitored on Peripheral bus @@ -167,7 +159,7 @@ typedef union { uint32_t core_0_area_pif_0_max:32; }; uint32_t val; -} assist_debug_core_0_area_pif_0_max_reg_t; +} bus_monitor_core_0_area_pif_0_max_reg_t; /** Type of core_0_area_pif_1_min register * Configures lower boundary address of region 1 monitored on Peripheral bus @@ -180,7 +172,7 @@ typedef union { uint32_t core_0_area_pif_1_min:32; }; uint32_t val; -} assist_debug_core_0_area_pif_1_min_reg_t; +} bus_monitor_core_0_area_pif_1_min_reg_t; /** Type of core_0_area_pif_1_max register * Configures upper boundary address of region 1 monitored on Peripheral bus @@ -193,10 +185,10 @@ typedef union { uint32_t core_0_area_pif_1_max:32; }; uint32_t val; -} assist_debug_core_0_area_pif_1_max_reg_t; +} bus_monitor_core_0_area_pif_1_max_reg_t; /** Type of core_0_area_pc register - * Region monitoring HP CPU PC status register + * Represents the PC value when HP CPU region monitor is triggered */ typedef union { struct { @@ -206,10 +198,10 @@ typedef union { uint32_t core_0_area_pc:32; }; uint32_t val; -} assist_debug_core_0_area_pc_reg_t; +} bus_monitor_core_0_area_pc_reg_t; /** Type of core_0_area_sp register - * Region monitoring HP CPU SP status register + * Represents the SP value when HP CPU region monitor is triggered */ typedef union { struct { @@ -219,255 +211,228 @@ typedef union { uint32_t core_0_area_sp:32; }; uint32_t val; -} assist_debug_core_0_area_sp_reg_t; +} bus_monitor_core_0_area_sp_reg_t; /** Type of core_0_sp_min register - * Configures stack monitoring lower boundary address + * Configures SP monitoring lower boundary address */ typedef union { struct { /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; - * Configures the lower bound address of SP. + * Configures the lower bound address of SP monitored region. */ uint32_t core_0_sp_min:32; }; uint32_t val; -} assist_debug_core_0_sp_min_reg_t; +} bus_monitor_core_0_sp_min_reg_t; /** Type of core_0_sp_max register - * Configures stack monitoring upper boundary address + * Configures SP monitoring upper boundary address */ typedef union { struct { /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the upper bound address of SP. + * Configures the upper bound address of SP monitored region. */ uint32_t core_0_sp_max:32; }; uint32_t val; -} assist_debug_core_0_sp_max_reg_t; +} bus_monitor_core_0_sp_max_reg_t; /** Type of core_0_sp_pc register - * Stack monitoring HP CPU PC status register + * Represents the PC value when HP CPU SP monitor is triggered */ typedef union { struct { /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; - * Represents the PC value during stack monitoring. + * Represents the PC value when SP monitoring is triggered. */ uint32_t core_0_sp_pc:32; }; uint32_t val; -} assist_debug_core_0_sp_pc_reg_t; +} bus_monitor_core_0_sp_pc_reg_t; -/** Group: interrupt configuration register */ +/** Group: Interrupt configuration registers */ /** Type of core_0_intr_raw register - * core0 monitor interrupt status register + * HP CPU monitor raw interrupt status register */ typedef union { struct { /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; - * The raw interrupt status of read operations in region 0 by Data bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. */ uint32_t core_0_area_dram0_0_rd_raw:1; /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; - * The raw interrupt status of write operations in region 0 by Data bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. */ uint32_t core_0_area_dram0_0_wr_raw:1; /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; - * The raw interrupt status of read operations in region 1 by Data bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. */ uint32_t core_0_area_dram0_1_rd_raw:1; /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; - * The raw interrupt status of write operations in region 1 by Data bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. */ uint32_t core_0_area_dram0_1_wr_raw:1; /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; - * The raw interrupt status of read operations in region 0 by Peripheral bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. */ uint32_t core_0_area_pif_0_rd_raw:1; /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; - * The raw interrupt status of write operations in region 0 by Peripheral bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. */ uint32_t core_0_area_pif_0_wr_raw:1; /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; - * The raw interrupt status of read operations in region 1 by Peripheral bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. */ uint32_t core_0_area_pif_1_rd_raw:1; /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; - * The raw interrupt status of write operations in region 1 by Peripheral bus. + * The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. */ uint32_t core_0_area_pif_1_wr_raw:1; /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; - * The raw interrupt status of SP exceeding the lower bound address of SP monitored - * region. + * The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. */ uint32_t core_0_sp_spill_min_raw:1; /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; - * The raw interrupt status of SP exceeding the upper bound address of SP monitored - * region. + * The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. */ uint32_t core_0_sp_spill_max_raw:1; - /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt status - */ - uint32_t core_0_iram0_exception_monitor_raw:1; - /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0; - * DBUS busy monitor initerrupt status - */ - uint32_t core_0_dram0_exception_monitor_raw:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_raw_reg_t; +} bus_monitor_core_0_intr_raw_reg_t; /** Type of core_0_intr_ena register - * core0 monitor interrupt enable register + * HP CPU monitor interrupt enable register */ typedef union { struct { /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0; - * Core0 dram0 area0 read monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. */ uint32_t core_0_area_dram0_0_rd_intr_ena:1; /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0; - * Core0 dram0 area0 write monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. */ uint32_t core_0_area_dram0_0_wr_intr_ena:1; /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0; - * Core0 dram0 area1 read monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. */ uint32_t core_0_area_dram0_1_rd_intr_ena:1; /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0; - * Core0 dram0 area1 write monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. */ uint32_t core_0_area_dram0_1_wr_intr_ena:1; /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0; - * Core0 PIF area0 read monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. */ uint32_t core_0_area_pif_0_rd_intr_ena:1; /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0; - * Core0 PIF area0 write monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. */ uint32_t core_0_area_pif_0_wr_intr_ena:1; /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0; - * Core0 PIF area1 read monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. */ uint32_t core_0_area_pif_1_rd_intr_ena:1; /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0; - * Core0 PIF area1 write monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. */ uint32_t core_0_area_pif_1_wr_intr_ena:1; /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0; - * Core0 stackpoint underflow monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. */ uint32_t core_0_sp_spill_min_intr_ena:1; /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0; - * Core0 stackpoint overflow monitor interrupt enable + * Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. */ uint32_t core_0_sp_spill_max_intr_ena:1; - /** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt enable - */ - uint32_t core_0_iram0_exception_monitor_intr_ena:1; - /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt enable - */ - uint32_t core_0_dram0_exception_monitor_intr_ena:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_ena_reg_t; +} bus_monitor_core_0_intr_ena_reg_t; /** Type of core_0_intr_clr register - * core0 monitor interrupt clear register + * HP CPU monitor interrupt clear register */ typedef union { struct { /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Data bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. */ uint32_t core_0_area_dram0_0_rd_clr:1; /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Data bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. */ uint32_t core_0_area_dram0_0_wr_clr:1; /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Data bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. */ uint32_t core_0_area_dram0_1_rd_clr:1; /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Data bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. */ uint32_t core_0_area_dram0_1_wr_clr:1; /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. */ uint32_t core_0_area_pif_0_rd_clr:1; /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. */ uint32_t core_0_area_pif_0_wr_clr:1; /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. */ uint32_t core_0_area_pif_1_rd_clr:1; /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. + * Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. */ uint32_t core_0_area_pif_1_wr_clr:1; /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP - * monitored region. + * Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. */ uint32_t core_0_sp_spill_min_clr:1; /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; - * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP - * monitored region. + * Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. */ uint32_t core_0_sp_spill_max_clr:1; - /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0; - * IBUS busy monitor interrupt clr - */ - uint32_t core_0_iram0_exception_monitor_clr:1; - /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0; - * DBUS busy monitor interrupt clr - */ - uint32_t core_0_dram0_exception_monitor_clr:1; - uint32_t reserved_12:20; + uint32_t reserved_10:22; }; uint32_t val; -} assist_debug_core_0_intr_clr_reg_t; +} bus_monitor_core_0_intr_clr_reg_t; -/** Group: pc recording configuration register */ +/** Group: PC recording configuration register */ /** Type of core_0_rcd_en register * HP CPU PC logging enable register */ typedef union { struct { /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; - * Configures whether to enable PC logging.\\ - * 0: Disable\\ - * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ + * Configures whether to enable PC and SP logging. + * 0: Disable + * 1: BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time, + * BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG starts to record SP in real time */ uint32_t core_0_rcd_recorden:1; /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; - * Configures whether to enable HP CPU debugging.\\ - * 0: Disable\\ - * 1: HP CPU outputs PC\\ + * Configures whether to enable HP CPU debugging. + * 0: Disable + * 1: HP CPU outputs PC */ uint32_t core_0_rcd_pdebugen:1; uint32_t reserved_2:30; }; uint32_t val; -} assist_debug_core_0_rcd_en_reg_t; +} bus_monitor_core_0_rcd_en_reg_t; -/** Group: pc recording status register */ +/** Group: PC recording status registers */ /** Type of core_0_rcd_pdebugpc register - * PC logging register + * HP CPU PC logging register */ typedef union { struct { @@ -477,10 +442,10 @@ typedef union { uint32_t core_0_rcd_pdebugpc:32; }; uint32_t val; -} assist_debug_core_0_rcd_pdebugpc_reg_t; +} bus_monitor_core_0_rcd_pdebugpc_reg_t; /** Type of core_0_rcd_pdebugsp register - * PC logging register + * HP CPU SP logging register */ typedef union { struct { @@ -490,174 +455,12 @@ typedef union { uint32_t core_0_rcd_pdebugsp:32; }; uint32_t val; -} assist_debug_core_0_rcd_pdebugsp_reg_t; +} bus_monitor_core_0_rcd_pdebugsp_reg_t; -/** Group: exception monitor register */ -/** Type of core_0_iram0_exception_monitor_0 register - * exception monitor status register0 - */ -typedef union { - struct { - /** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_0 - */ - uint32_t core_0_iram0_recording_addr_0:30; - /** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_0 - */ - uint32_t core_0_iram0_recording_wr_0:1; - /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_0 - */ - uint32_t core_0_iram0_recording_loadstore_0:1; - }; - uint32_t val; -} assist_debug_core_0_iram0_exception_monitor_0_reg_t; - -/** Type of core_0_iram0_exception_monitor_1 register - * exception monitor status register1 - */ -typedef union { - struct { - /** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_iram0_recording_addr_1 - */ - uint32_t core_0_iram0_recording_addr_1:30; - /** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0; - * reg_core_0_iram0_recording_wr_1 - */ - uint32_t core_0_iram0_recording_wr_1:1; - /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0; - * reg_core_0_iram0_recording_loadstore_1 - */ - uint32_t core_0_iram0_recording_loadstore_1:1; - }; - uint32_t val; -} assist_debug_core_0_iram0_exception_monitor_1_reg_t; - -/** Type of core_0_dram0_exception_monitor_0 register - * exception monitor status register2 - */ -typedef union { - struct { - /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_0 - */ - uint32_t core_0_dram0_recording_wr_0:1; - /** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_0 - */ - uint32_t core_0_dram0_recording_byteen_0:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_0_reg_t; - -/** Type of core_0_dram0_exception_monitor_1 register - * exception monitor status register3 - */ -typedef union { - struct { - /** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_0 - */ - uint32_t core_0_dram0_recording_addr_0:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_1_reg_t; - -/** Type of core_0_dram0_exception_monitor_2 register - * exception monitor status register4 - */ -typedef union { - struct { - /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_0 - */ - uint32_t core_0_dram0_recording_pc_0:32; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_2_reg_t; - -/** Type of core_0_dram0_exception_monitor_3 register - * exception monitor status register5 - */ -typedef union { - struct { - /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0; - * reg_core_0_dram0_recording_wr_1 - */ - uint32_t core_0_dram0_recording_wr_1:1; - /** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0; - * reg_core_0_dram0_recording_byteen_1 - */ - uint32_t core_0_dram0_recording_byteen_1:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_3_reg_t; - -/** Type of core_0_dram0_exception_monitor_4 register - * exception monitor status register6 - */ -typedef union { - struct { - /** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; - * reg_core_0_dram0_recording_addr_1 - */ - uint32_t core_0_dram0_recording_addr_1:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_4_reg_t; - -/** Type of core_0_dram0_exception_monitor_5 register - * exception monitor status register7 - */ -typedef union { - struct { - /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0; - * reg_core_0_dram0_recording_pc_1 - */ - uint32_t core_0_dram0_recording_pc_1:32; - }; - uint32_t val; -} assist_debug_core_0_dram0_exception_monitor_5_reg_t; - -/** Type of core_x_iram0_dram0_exception_monitor_0 register - * exception monitor status register8 - */ -typedef union { - struct { - /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_0 - */ - uint32_t core_x_iram0_dram0_limit_cycle_0:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t; - -/** Type of core_x_iram0_dram0_exception_monitor_1 register - * exception monitor status register9 - */ -typedef union { - struct { - /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0; - * reg_core_x_iram0_dram0_limit_cycle_1 - */ - uint32_t core_x_iram0_dram0_limit_cycle_1:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t; - - -/** Group: cpu status registers */ +/** Group: CPU status registers */ /** Type of core_0_lastpc_before_exception register - * cpu status register + * PC of the last command before HP CPU enters exception */ typedef union { struct { @@ -667,106 +470,99 @@ typedef union { uint32_t core_0_lastpc_before_exc:32; }; uint32_t val; -} assist_debug_core_0_lastpc_before_exception_reg_t; +} bus_monitor_core_0_lastpc_before_exception_reg_t; /** Type of core_0_debug_mode register - * cpu status register + * HP CPU debug mode status register */ typedef union { struct { /** core_0_debug_mode : RO; bitpos: [0]; default: 0; - * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ - * 1: In debugging mode\\ - * 0: Not in debugging mode\\ + * Represents whether RISC-V CPU (HP CPU) is in debugging mode. + * 1: In debugging mode + * 0: Not in debugging mode */ uint32_t core_0_debug_mode:1; /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; - * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ - * 1: Active status\\ - * Other: Inactive status\\ + * Represents the status of the RISC-V CPU (HP CPU) debug module. + * 1: Active status + * Other: Inactive status */ uint32_t core_0_debug_module_active:1; uint32_t reserved_2:30; }; uint32_t val; -} assist_debug_core_0_debug_mode_reg_t; +} bus_monitor_core_0_debug_mode_reg_t; -/** Group: Configuration Registers */ +/** Group: Clock control register */ /** Type of clock_gate register - * Register clock control + * Clock control register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to enable the register clock gating. \\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} assist_debug_clock_gate_reg_t; +} bus_monitor_clock_gate_reg_t; + +/** Group: Version control register */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 34640176; - * version register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; }; uint32_t val; -} assist_debug_date_reg_t; +} bus_monitor_date_reg_t; typedef struct { - volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena; - volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; - volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; - volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; - volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; - volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; - volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; - volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; - volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; - volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; - volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; - volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; - volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; - volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; - volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; - volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; - volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; - volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; - volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; - volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; - volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0; - volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1; - volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0; - volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1; - volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2; - volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3; - volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4; - volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5; - volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; - volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; - uint32_t reserved_078[34]; - volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; - volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; - volatile assist_debug_clock_gate_reg_t clock_gate; + volatile bus_monitor_core_0_montr_ena_reg_t core_0_montr_ena; + volatile bus_monitor_core_0_intr_raw_reg_t core_0_intr_raw; + volatile bus_monitor_core_0_intr_ena_reg_t core_0_intr_ena; + volatile bus_monitor_core_0_intr_clr_reg_t core_0_intr_clr; + volatile bus_monitor_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile bus_monitor_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile bus_monitor_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile bus_monitor_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile bus_monitor_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile bus_monitor_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile bus_monitor_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile bus_monitor_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile bus_monitor_core_0_area_pc_reg_t core_0_area_pc; + volatile bus_monitor_core_0_area_sp_reg_t core_0_area_sp; + volatile bus_monitor_core_0_sp_min_reg_t core_0_sp_min; + volatile bus_monitor_core_0_sp_max_reg_t core_0_sp_max; + volatile bus_monitor_core_0_sp_pc_reg_t core_0_sp_pc; + volatile bus_monitor_core_0_rcd_en_reg_t core_0_rcd_en; + volatile bus_monitor_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile bus_monitor_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + uint32_t reserved_050[8]; + volatile bus_monitor_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile bus_monitor_core_0_debug_mode_reg_t core_0_debug_mode; + uint32_t reserved_078[36]; + volatile bus_monitor_clock_gate_reg_t clock_gate; uint32_t reserved_10c[188]; - volatile assist_debug_date_reg_t date; -} assist_debug_dev_t; + volatile bus_monitor_date_reg_t date; +} bus_monitor_dev_t; -extern assist_debug_dev_t ASSIST_DEBUG; +extern bus_monitor_dev_t ASSIST_DEBUG; #ifndef __cplusplus -_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/register/soc/mem_monitor_reg.h b/components/soc/esp32c61/register/soc/mem_monitor_reg.h index 71a6e1890a..9486a8f389 100644 --- a/components/soc/esp32c61/register/soc/mem_monitor_reg.h +++ b/components/soc/esp32c61/register/soc/mem_monitor_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,63 +12,55 @@ extern "C" { #endif /** MEM_MONITOR_LOG_SETTING_REG register - * Bus access logging configuration register + * Configures bus access logging */ #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) /** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0; - * Configures monitoring modes.bit[0]: Configures write monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[1]: Configures word monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[2]: Configures halfword monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[3]: Configures byte monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ + * Configures monitoring modes. + * 1: Enable write monitoring + * 2: Enable word monitoring + * 4: Enable halfword monitoring + * 8: Enable byte monitoring + * Other values: Invalid */ #define MEM_MONITOR_LOG_MODE 0x0000000FU #define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) #define MEM_MONITOR_LOG_MODE_V 0x0000000FU #define MEM_MONITOR_LOG_MODE_S 0 /** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1; - * Configures the writing mode for recorded data.1: Loop mode\\ - * 0: Non-loop mode\\ + * Configures the writing mode for recorded data. + * 0: Non-loop mode + * 1: Loop mode */ #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4)) #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4 /** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0; - * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to - * enable HP CPU bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable HP CPU bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ #define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU #define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S) #define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU #define MEM_MONITOR_LOG_CORE_ENA_S 8 /** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0; - * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether - * to enable DMA_0 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_0 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ #define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU #define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S) #define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU #define MEM_MONITOR_LOG_DMA_0_ENA_S 16 /** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0; - * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether - * to enable DMA_1 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_1 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ #define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU #define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S) @@ -76,26 +68,24 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_1_ENA_S 24 /** MEM_MONITOR_LOG_SETTING1_REG register - * Bus access logging configuration register + * Configures bus access logging */ #define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) /** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0; - * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether - * to enable DMA_2 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_2 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ #define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU #define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S) #define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU #define MEM_MONITOR_LOG_DMA_2_ENA_S 0 /** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0; - * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether - * to enable DMA_3 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_3 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ #define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU #define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S) @@ -103,7 +93,7 @@ extern "C" { #define MEM_MONITOR_LOG_DMA_3_ENA_S 8 /** MEM_MONITOR_LOG_CHECK_DATA_REG register - * Configures monitored data in Bus access logging + * Configures data to be monitored for bus access logging */ #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8) /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; @@ -115,27 +105,28 @@ extern "C" { #define MEM_MONITOR_LOG_CHECK_DATA_S 0 /** MEM_MONITOR_LOG_DATA_MASK_REG register - * Configures masked data in Bus access logging + * Configures data mask for bus access logging */ #define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc) /** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; - * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: - * Configures whether to mask the least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ - * 0: Not mask \\ - * 1: Mask\\ + * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask. Multiple bytes + * can be masked at the same time. + * bit[0]: Configures whether to mask the least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[1]: Configures whether to mask the second least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[2]: Configures whether to mask the second most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[3]: Configures whether to mask the most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask */ #define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU #define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) @@ -143,7 +134,7 @@ extern "C" { #define MEM_MONITOR_LOG_DATA_MASK_S 0 /** MEM_MONITOR_LOG_MIN_REG register - * Configures monitored address space in Bus access logging + * Configures the monitored lower address for bus access logging */ #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10) /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; @@ -155,7 +146,7 @@ extern "C" { #define MEM_MONITOR_LOG_MIN_S 0 /** MEM_MONITOR_LOG_MAX_REG register - * Configures monitored address space in Bus access logging + * Configures the monitored upper address for bus access logging */ #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14) /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; @@ -167,25 +158,26 @@ extern "C" { #define MEM_MONITOR_LOG_MAX_S 0 /** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + * Configures whether to update the monitored address space for HP CPU bus access + * logging */ #define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18) /** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the HP CPU bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the HP CPU bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S) #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0 /** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0; - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ - * 0: Not update\\ + * Configures whether to update the monitored address space of all masters as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update */ #define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31)) #define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S) @@ -193,49 +185,49 @@ extern "C" { #define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31 /** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + * Configures whether to update the monitored address space for DMA_0 bus access + * logging */ #define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) /** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_0 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_0 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S) #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0 /** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_1 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_1 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S) #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8 /** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_2 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_2 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S) #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16 /** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_3 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_3 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ #define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU #define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S) @@ -284,9 +276,10 @@ extern "C" { */ #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c) /** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; - * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to - * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ - * 0: Not update (default) \\ + * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to the + * value of MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG. + * 0: Not update + * 1: Update */ #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) @@ -294,21 +287,22 @@ extern "C" { #define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 /** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register - * Logging overflow status register + * Represents logging buffer overflow status register */ #define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30) /** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; - * Represents whether data overflows the storage space.0: Not Overflow\\ - * 1: Overflow\\ + * Represents whether data overflows the storage space. + * 0: Not Overflow + * 1: Overflow */ #define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) #define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) #define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U #define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 /** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; - * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not - * clear\\ - * 1: Clear\\ + * Configures whether to clear theMEM_MONITOR_LOG_MEM_FULL_FLAG flag bit. + * 0: Not clear (default) + * 1: Clear */ #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) @@ -316,12 +310,13 @@ extern "C" { #define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 /** MEM_MONITOR_CLOCK_GATE_REG register - * Register clock control + * Clock gating control register */ #define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34) /** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the register clock gating.0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable */ #define MEM_MONITOR_CLK_EN (BIT(0)) #define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) diff --git a/components/soc/esp32c61/register/soc/mem_monitor_struct.h b/components/soc/esp32c61/register/soc/mem_monitor_struct.h index 5b810b2b67..0c82a04215 100644 --- a/components/soc/esp32c61/register/soc/mem_monitor_struct.h +++ b/components/soc/esp32c61/register/soc/mem_monitor_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,55 +10,47 @@ extern "C" { #endif -/** Group: configuration registers */ +/** Group: Bus logging configuration registers */ /** Type of log_setting register - * Bus access logging configuration register + * Configures bus access logging */ typedef union { struct { /** log_mode : R/W; bitpos: [3:0]; default: 0; - * Configures monitoring modes.bit[0]: Configures write monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[1]: Configures word monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[2]: Configures halfword monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ - * bit[3]: Configures byte monitoring. \\ - * 0: Disable \\ - * 1: Enable\\ + * Configures monitoring modes. + * 1: Enable write monitoring + * 2: Enable word monitoring + * 4: Enable halfword monitoring + * 8: Enable byte monitoring + * Other values: Invalid */ uint32_t log_mode:4; /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1; - * Configures the writing mode for recorded data.1: Loop mode\\ - * 0: Non-loop mode\\ + * Configures the writing mode for recorded data. + * 0: Non-loop mode + * 1: Loop mode */ uint32_t log_mem_loop_enable:1; uint32_t reserved_5:3; /** log_core_ena : R/W; bitpos: [15:8]; default: 0; - * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to - * enable HP CPU bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable HP CPU bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ uint32_t log_core_ena:8; /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0; - * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether - * to enable DMA_0 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_0 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ uint32_t log_dma_0_ena:8; /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0; - * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether - * to enable DMA_1 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_1 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ uint32_t log_dma_1_ena:8; }; @@ -66,24 +58,22 @@ typedef union { } mem_monitor_log_setting_reg_t; /** Type of log_setting1 register - * Bus access logging configuration register + * Configures bus access logging */ typedef union { struct { /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0; - * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether - * to enable DMA_2 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_2 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ uint32_t log_dma_2_ena:8; /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0; - * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether - * to enable DMA_3 bus access logging. \\ - * 0: Disable \\ - * 1: Enable\\ - * Bit[7:1]: Reserved + * Configures whether to enable DMA_3 bus access logging. + * 0: Disable + * 1: Enable + * Other values: Invalid */ uint32_t log_dma_3_ena:8; uint32_t reserved_16:16; @@ -92,7 +82,7 @@ typedef union { } mem_monitor_log_setting1_reg_t; /** Type of log_check_data register - * Configures monitored data in Bus access logging + * Configures data to be monitored for bus access logging */ typedef union { struct { @@ -105,28 +95,29 @@ typedef union { } mem_monitor_log_check_data_reg_t; /** Type of log_data_mask register - * Configures masked data in Bus access logging + * Configures data mask for bus access logging */ typedef union { struct { /** log_data_mask : R/W; bitpos: [3:0]; default: 0; - * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: - * Configures whether to mask the least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ - * 0: Not mask \\ - * 1: Mask\\ + * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask. Multiple bytes + * can be masked at the same time. + * bit[0]: Configures whether to mask the least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[1]: Configures whether to mask the second least significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[2]: Configures whether to mask the second most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask * bit[3]: Configures whether to mask the most significant byte of - * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ - * 0: Not mask \\ - * 1: Mask\\ + * MEM_MONITOR_LOG_CHECK_DATA_REG. + * 0: Not mask + * 1: Mask */ uint32_t log_data_mask:4; uint32_t reserved_4:28; @@ -135,7 +126,7 @@ typedef union { } mem_monitor_log_data_mask_reg_t; /** Type of log_min register - * Configures monitored address space in Bus access logging + * Configures the monitored lower address for bus access logging */ typedef union { struct { @@ -148,7 +139,7 @@ typedef union { } mem_monitor_log_min_reg_t; /** Type of log_max register - * Configures monitored address space in Bus access logging + * Configures the monitored upper address for bus access logging */ typedef union { struct { @@ -161,24 +152,25 @@ typedef union { } mem_monitor_log_max_reg_t; /** Type of log_mon_addr_update_0 register - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + * Configures whether to update the monitored address space for HP CPU bus access + * logging */ typedef union { struct { /** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the HP CPU bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the HP CPU bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ uint32_t log_mon_addr_core_update:8; uint32_t reserved_8:23; /** log_mon_addr_all_update : WT; bitpos: [31]; default: 0; - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ - * 0: Not update\\ + * Configures whether to update the monitored address space of all masters as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update */ uint32_t log_mon_addr_all_update:1; }; @@ -186,41 +178,41 @@ typedef union { } mem_monitor_log_mon_addr_update_0_reg_t; /** Type of log_mon_addr_update_1 register - * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to - * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + * Configures whether to update the monitored address space for DMA_0 bus access + * logging */ typedef union { struct { /** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_0 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_0 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ uint32_t log_mon_addr_dma_0_update:8; /** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_1 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_1 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ uint32_t log_mon_addr_dma_1_update:8; /** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_2 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_2 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ uint32_t log_mon_addr_dma_2_update:8; /** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0; - * Configures the monitored address space of the certain master. Bit[0]: Configures - * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the - * monitored address space of the DMA_3 bus.1: Update\\ - * 0: Not update\\ - * Bit[7:1]: Reserved\\ + * Configures whether to update the monitored address space of the DMA_3 bus as the + * address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. + * 0: Not update + * 1: Update + * Other values: Invalid */ uint32_t log_mon_addr_dma_3_update:8; }; @@ -273,9 +265,10 @@ typedef union { typedef union { struct { /** log_mem_addr_update : WT; bitpos: [0]; default: 0; - * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to - * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ - * 0: Not update (default) \\ + * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to the + * value of MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG. + * 0: Not update + * 1: Update */ uint32_t log_mem_addr_update:1; uint32_t reserved_1:31; @@ -284,19 +277,20 @@ typedef union { } mem_monitor_log_mem_addr_update_reg_t; /** Type of log_mem_full_flag register - * Logging overflow status register + * Represents logging buffer overflow status register */ typedef union { struct { /** log_mem_full_flag : RO; bitpos: [0]; default: 0; - * Represents whether data overflows the storage space.0: Not Overflow\\ - * 1: Overflow\\ + * Represents whether data overflows the storage space. + * 0: Not Overflow + * 1: Overflow */ uint32_t log_mem_full_flag:1; /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; - * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not - * clear\\ - * 1: Clear\\ + * Configures whether to clear theMEM_MONITOR_LOG_MEM_FULL_FLAG flag bit. + * 0: Not clear (default) + * 1: Clear */ uint32_t clr_log_mem_full_flag:1; uint32_t reserved_2:30; @@ -305,15 +299,16 @@ typedef union { } mem_monitor_log_mem_full_flag_reg_t; -/** Group: clk register */ +/** Group: Clock gating control register */ /** Type of clock_gate register - * Register clock control + * Clock gating control register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the register clock gating.0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the register clock gating. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -322,7 +317,7 @@ typedef union { } mem_monitor_clock_gate_reg_t; -/** Group: version register */ +/** Group: Version control register */ /** Type of date register * Version control register */