From ba2af7f611ce5ca86d5012605b363ca987923ba3 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Mon, 1 Jul 2024 14:19:33 +0530 Subject: [PATCH] feat(esp_tee): Support for ESP-TEE - `hal`, `soc` and `freertos` components --- .../FreeRTOS-Kernel-SMP/portable/riscv/port.c | 17 ++++++++++++++-- components/hal/CMakeLists.txt | 3 ++- components/hal/efuse_hal.c | 5 +++++ components/hal/include/hal/efuse_hal.h | 5 +++++ .../soc/esp32c6/include/soc/interrupt_reg.h | 20 +++++++++++++++++++ .../soc/esp32c6/register/soc/reg_base.h | 1 + 6 files changed, 48 insertions(+), 3 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c index 0baffbcd82..d08948517d 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c @@ -127,10 +127,23 @@ void vPortSetStackWatchpoint(void *pxStackStart) UBaseType_t ulPortSetInterruptMask(void) { int ret; - unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); + unsigned old_xstatus; + +#if CONFIG_SECURE_ENABLE_TEE + old_xstatus = RV_CLEAR_CSR(ustatus, USTATUS_UIE); +#else + // For non-secure configuration + old_xstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); +#endif + ret = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG); REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, RVHAL_EXCM_LEVEL); - RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); + +#if CONFIG_SECURE_ENABLE_TEE + RV_SET_CSR(ustatus, old_xstatus & USTATUS_UIE); +#else + RV_SET_CSR(mstatus, old_xstatus & MSTATUS_MIE); +#endif /** * In theory, this function should not return immediately as there is a * delay between the moment we mask the interrupt threshold register and diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 698bd8adff..422a4965b5 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -1,4 +1,5 @@ idf_build_get_property(target IDF_TARGET) +idf_build_get_property(esp_tee_build ESP_TEE_BUILD) set(srcs "hal_utils.c") set(includes "platform_port/include") @@ -44,7 +45,7 @@ if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) endif() endif() -if(NOT BOOTLOADER_BUILD) +if(NOT BOOTLOADER_BUILD AND NOT esp_tee_build) list(APPEND srcs "color_hal.c") if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c index 28cdaed788..43a007aca2 100644 --- a/components/hal/efuse_hal.c +++ b/components/hal/efuse_hal.c @@ -33,6 +33,11 @@ IRAM_ATTR bool efuse_hal_get_disable_wafer_version_major(void) return efuse_ll_get_disable_wafer_version_major(); } +IRAM_ATTR uint32_t efuse_hal_get_chip_ver_pkg(void) +{ + return efuse_ll_get_chip_ver_pkg(); +} + IRAM_ATTR bool efuse_hal_get_disable_blk_version_major(void) { return efuse_ll_get_disable_blk_version_major(); diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h index 73f092ee00..cfed79f591 100644 --- a/components/hal/include/hal/efuse_hal.h +++ b/components/hal/include/hal/efuse_hal.h @@ -69,6 +69,11 @@ uint32_t efuse_hal_get_major_chip_version(void); */ uint32_t efuse_hal_get_minor_chip_version(void); +/** + * @brief Returns the chip package version + */ +uint32_t efuse_hal_get_chip_ver_pkg(void); + #if SOC_EFUSE_ECDSA_KEY /** * @brief Set the efuse block that should be used as ECDSA private key diff --git a/components/soc/esp32c6/include/soc/interrupt_reg.h b/components/soc/esp32c6/include/soc/interrupt_reg.h index 50f8a6e1c6..e111811dbf 100644 --- a/components/soc/esp32c6/include/soc/interrupt_reg.h +++ b/components/soc/esp32c6/include/soc/interrupt_reg.h @@ -10,16 +10,36 @@ #include "soc/plic_reg.h" #include "soc/soc_caps.h" +#ifdef __has_include +# if __has_include("sdkconfig.h") +# include "sdkconfig.h" +# endif +#endif + +#if CONFIG_SECURE_ENABLE_TEE +#define INTERRUPT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_UXINT_THRESH_REG +#else #define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG +#endif /** * ESP32C6 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y) * Keep the following macros for backward compatibility reasons */ +#if CONFIG_SECURE_ENABLE_TEE +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_UXINT_ENABLE_REG +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_UXINT_THRESH_REG +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_UXINT_CLEAR_REG +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_UXINT_TYPE_REG +#define INTC_INT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) +#else #define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG #define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG #define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG #define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG #define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#endif + #define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32c6/register/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h index f2da385dc1..603ccc602e 100644 --- a/components/soc/esp32c6/register/soc/reg_base.h +++ b/components/soc/esp32c6/register/soc/reg_base.h @@ -8,6 +8,7 @@ #define DR_REG_PLIC_UX_BASE 0x20001400 #define DR_REG_CLINT_M_BASE 0x20001800 #define DR_REG_CLINT_U_BASE 0x20001C00 +#define DR_REG_CLINT_U_END 0x20002000 #define DR_REG_UART_BASE 0x60000000 #define DR_REG_UART1_BASE 0x60001000