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i2s: bringup i2s on esp32c6

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This commit is contained in:
laokaiyao
2022-09-15 17:28:32 +08:00
parent 7197e987cb
commit bae4944b90
16 changed files with 1208 additions and 29 deletions
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5
components/driver/deprecated/i2s_legacy.c
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@@ -625,6 +625,7 @@ err:
/*------------------------------------------------------------- /*-------------------------------------------------------------
I2S clock operation I2S clock operation
-------------------------------------------------------------*/ -------------------------------------------------------------*/
// [clk_tree] TODO: replace the following switch table by clk_tree API
static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk) static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
{ {
#if SOC_I2S_SUPPORTS_APLL #if SOC_I2S_SUPPORTS_APLL
@@ -651,12 +652,12 @@ static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint3
/* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */ /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
return real_freq; return real_freq;
} }
return esp_clk_apb_freq() * 2; // [clk_tree] TODO: replace the following switch table by clk_tree API return esp_clk_apb_freq() * 2;
#else #else
if (use_apll) { if (use_apll) {
ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source"); ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source");
} }
return esp_clk_apb_freq() * 2; // [clk_tree] TODO: replace the following switch table by clk_tree API return esp_clk_apb_freq() * 2;
#endif #endif
} }

3
components/driver/i2s/i2s_common.c
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@@ -474,6 +474,7 @@ static uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz)
} }
#endif #endif
// [clk_tree] TODO: replace the following switch table by clk_tree API
uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
{ {
switch (clk_src) switch (clk_src)
@@ -488,7 +489,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
return esp_clk_xtal_freq(); return esp_clk_xtal_freq();
#endif #endif
default: // I2S_CLK_SRC_PLL_160M default: // I2S_CLK_SRC_PLL_160M
return esp_clk_apb_freq() * 2; // [clk_tree] TODO: replace the following switch table by clk_tree API return esp_clk_apb_freq() * 2;
} }
} }

2
components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h
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@@ -44,7 +44,7 @@ extern "C" {
#define SLAVE_WS_IO 15 #define SLAVE_WS_IO 15
#define DATA_IN_IO 19 #define DATA_IN_IO 19
#define DATA_OUT_IO 18 #define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32H2 #elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
#define MASTER_MCK_IO 0 #define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4 #define MASTER_BCK_IO 4
#define MASTER_WS_IO 5 #define MASTER_WS_IO 5

4
components/hal/esp32/include/hal/i2s_ll.h
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@@ -286,7 +286,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */
@@ -362,7 +362,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */

4
components/hal/esp32c3/include/hal/i2s_ll.h
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@@ -224,7 +224,7 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
hw->rx_clkm_conf.rx_clk_sel = 2; hw->rx_clkm_conf.rx_clk_sel = 2;
break; break;
default: default:
hw->rx_clkm_conf.rx_clk_sel = 2; HAL_ASSERT(false && "unsupported clock source");
break; break;
} }
} }
@@ -278,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */

1166
components/hal/esp32c6/include/hal/i2s_ll.h Normal file
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File diff suppressed because it is too large Load Diff

4
components/hal/esp32h2/include/hal/i2s_ll.h
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@@ -225,7 +225,7 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
hw->rx_clkm_conf.rx_clk_sel = 2; hw->rx_clkm_conf.rx_clk_sel = 2;
break; break;
default: default:
hw->rx_clkm_conf.rx_clk_sel = 2; HAL_ASSERT(false && "unsupported clock source");
break; break;
} }
} }
@@ -279,7 +279,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */

4
components/hal/esp32s2/include/hal/i2s_ll.h
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@@ -278,7 +278,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32S2 is shared by both TX and RX channel * @note mclk on ESP32S2 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */
@@ -354,7 +354,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32S2 is shared by both TX and RX channel * @note mclk on ESP32S2 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */

4
components/hal/esp32s3/include/hal/i2s_ll.h
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@@ -225,7 +225,7 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
hw->rx_clkm_conf.rx_clk_sel = 2; hw->rx_clkm_conf.rx_clk_sel = 2;
break; break;
default: default:
hw->rx_clkm_conf.rx_clk_sel = 2; HAL_ASSERT(false && "unsupported clock source");
break; break;
} }
} }
@@ -278,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param sclk system clock
* @param mclk module clock * @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk * @param mclk_div integer part of the division from sclk to mclk
*/ */

1
components/soc/esp32c6/CMakeLists.txt
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@@ -20,7 +20,6 @@ list(REMOVE_ITEM srcs
"adc_periph.c" # TODO: IDF-5310 "adc_periph.c" # TODO: IDF-5310
"dedic_gpio_periph.c" # TODO: IDF-5331 "dedic_gpio_periph.c" # TODO: IDF-5331
"ledc_periph.c" # TODO: IDF-5328 "ledc_periph.c" # TODO: IDF-5328
"i2s_periph.c" # TODO: IDF-5314
"i2c_periph.c" # TODO: IDF-5326 "i2c_periph.c" # TODO: IDF-5326
"temperature_sensor_periph.c" # TODO: IDF-5322 "temperature_sensor_periph.c" # TODO: IDF-5322
) )

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
bool bool
default y default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED config SOC_SYSTIMER_SUPPORTED
bool bool
default y default y

11
components/soc/esp32c6/include/soc/clk_tree_defs.h
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@@ -215,14 +215,23 @@ typedef enum {
/** /**
* @brief Array initializer for all supported clock sources of I2S * @brief Array initializer for all supported clock sources of I2S
*/ */
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M} #if CONFIG_IDF_ENV_FPGA
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
#else
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
#endif
/** /**
* @brief I2S clock source enum * @brief I2S clock source enum
*/ */
typedef enum { typedef enum {
#if CONFIG_IDF_ENV_FPGA
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
#else
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
#endif
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t; } soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

16
components/soc/esp32c6/include/soc/i2s_struct.h
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@@ -255,7 +255,7 @@ typedef union {
*/ */
uint32_t rx_clk_active:1; uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0; /** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. * Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/ */
uint32_t rx_clk_sel:2; uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0; /** mclk_sel : R/W; bitpos: [29]; default: 0;
@@ -448,7 +448,7 @@ typedef union {
uint32_t val; uint32_t val;
} i2s_rx_tdm_ctrl_reg_t; } i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register /** Type of rx_eof_num register
* I2S RX data number control register. * I2S RX data number control register.
*/ */
typedef union { typedef union {
@@ -461,7 +461,7 @@ typedef union {
uint32_t reserved_12:20; uint32_t reserved_12:20;
}; };
uint32_t val; uint32_t val;
} i2s_rxeof_num_reg_t; } i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */ /** Group: TX Control and configuration registers */
@@ -627,7 +627,7 @@ typedef union {
*/ */
uint32_t tx_clk_active:1; uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0; /** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: * Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in. * I2S_MCLK_in.
*/ */
uint32_t tx_clk_sel:2; uint32_t tx_clk_sel:2;
@@ -914,7 +914,7 @@ typedef union {
uint32_t val; uint32_t val;
} i2s_lc_hung_conf_reg_t; } i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register /** Type of conf_single_data register
* I2S signal data register * I2S signal data register
*/ */
typedef union { typedef union {
@@ -925,7 +925,7 @@ typedef union {
uint32_t single_data:32; uint32_t single_data:32;
}; };
uint32_t val; uint32_t val;
} i2s_conf_sigle_data_reg_t; } i2s_conf_single_data_reg_t;
/** Group: TX status registers */ /** Group: TX status registers */
@@ -1005,8 +1005,8 @@ typedef struct i2s_dev_t {
volatile i2s_rx_timing_reg_t rx_timing; volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing; volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf; volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num; volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data; volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state; volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf; volatile i2s_etm_conf_reg_t etm_conf;
uint32_t reserved_074[3]; uint32_t reserved_074[3];

4
components/soc/esp32c6/include/soc/pcr_struct.h
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@@ -607,7 +607,7 @@ typedef union {
*/ */
uint32_t i2s_tx_clkm_div_num:8; uint32_t i2s_tx_clkm_div_num:8;
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: * Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in. * I2S_MCLK_in.
*/ */
uint32_t i2s_tx_clkm_sel:2; uint32_t i2s_tx_clkm_sel:2;
@@ -661,7 +661,7 @@ typedef union {
*/ */
uint32_t i2s_rx_clkm_div_num:8; uint32_t i2s_rx_clkm_div_num:8;
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. * Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/ */
uint32_t i2s_rx_clkm_sel:2; uint32_t i2s_rx_clkm_sel:2;
/** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;

3
components/soc/esp32c6/include/soc/soc_caps.h
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@@ -40,7 +40,7 @@
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-5314 #define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-5320 // #define SOC_RMT_SUPPORTED 1 // TODO: IDF-5320
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-5318 // #define SOC_SDM_SUPPORTED 1 // TODO: IDF-5318
// #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328 // #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328
@@ -181,7 +181,6 @@
#define SOC_I2C_SUPPORT_XTAL (1) #define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1) #define SOC_I2C_SUPPORT_RTC (1)
// TODO: IDF-5314 (Copy from esp32c3, need check)
/*-------------------------- I2S CAPS ----------------------------------------*/ /*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1) #define SOC_I2S_NUM (1)
#define SOC_I2S_HW_VERSION_2 (1) #define SOC_I2S_HW_VERSION_2 (1)

2
examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
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@@ -30,7 +30,7 @@
#define EXAMPLE_SD_SPI_MOSI_IO (17) #define EXAMPLE_SD_SPI_MOSI_IO (17)
#define EXAMPLE_SD_SPI_MISO_IO (16) #define EXAMPLE_SD_SPI_MISO_IO (16)
#define EXAMPLE_SD_SPI_CS_IO (15) #define EXAMPLE_SD_SPI_CS_IO (15)
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
#define EXAMPLE_I2C_NUM (0) #define EXAMPLE_I2C_NUM (0)
#define EXAMPLE_I2C_SDA_IO (3) #define EXAMPLE_I2C_SDA_IO (3)
#define EXAMPLE_I2C_SCL_IO (2) #define EXAMPLE_I2C_SCL_IO (2)