From bc182ef010b09f72b85d428859e1e071eb3bad1b Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Fri, 21 Jul 2023 11:51:38 +0800
Subject: [PATCH] feat(brc_predictor): p4 base support for branch predictor

---
 components/esp_hw_support/include/esp_cpu.h | 12 +++++++++++-
 components/esp_system/port/cpu_start.c      |  9 ++++++++-
 components/riscv/include/riscv/rv_utils.h   | 13 ++++++++++++-
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/components/esp_hw_support/include/esp_cpu.h b/components/esp_hw_support/include/esp_cpu.h
index 1d62ebcad6..2f81e3f293 100644
--- a/components/esp_hw_support/include/esp_cpu.h
+++ b/components/esp_hw_support/include/esp_cpu.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -550,6 +550,16 @@ FORCE_INLINE_ATTR intptr_t esp_cpu_get_call_addr(intptr_t return_address)
  */
 bool esp_cpu_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value);
 
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+/**
+ * @brief Enable branch prediction
+ */
+FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
+{
+    rv_utils_en_branch_predictor();
+}
+#endif  //#if SOC_BRANCH_PREDICTOR_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 5b0503808e..a9579cd88c 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -152,6 +152,10 @@ void startup_resume_other_cores(void)
 
 void IRAM_ATTR call_start_cpu1(void)
 {
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+    esp_cpu_branch_prediction_enable();
+#endif  //#if SOC_BRANCH_PREDICTOR_SUPPORTED
+
     esp_cpu_intr_set_ivt_addr(&_vector_table);
 
     ets_set_appcpu_boot_addr(0);
@@ -317,6 +321,9 @@ void IRAM_ATTR call_start_cpu0(void)
     );
 #endif
 
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+    esp_cpu_branch_prediction_enable();
+#endif
     // Move exception vectors to IRAM
     esp_cpu_intr_set_ivt_addr(&_vector_table);
 
diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h
index 2b0a9a95a1..609c271fc7 100644
--- a/components/riscv/include/riscv/rv_utils.h
+++ b/components/riscv/include/riscv/rv_utils.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -229,6 +229,17 @@ FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_
     return (old_value == compare_value);
 }
 
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
+{
+#define MHCR 0x7c1
+#define MHCR_RS (1<<4)   /* R/W, address return stack set bit */
+#define MHCR_BFE (1<<5)  /* R/W, allow predictive jump set bit */
+#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
+    RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
+}
+#endif
+
 #ifdef __cplusplus
 }
 #endif