From bc74cf808d24f8a6ee5de0461754e9db29670757 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Mon, 12 Feb 2024 13:40:57 +0100 Subject: [PATCH] feat(ulp-riscv): Added Kconfig option to enable ULP RISC-V interrupts This commit adds a Kconfig option, CONFIG_ULP_RISCV_INTERRUPT_ENABLE, to enable interrupts on the ULP RISC-V core on the esp32s2 and esp32s3. --- components/ulp/Kconfig | 7 +++++++ components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h | 5 +++++ .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_interrupt.h | 4 ++++ .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h | 3 +++ components/ulp/ulp_riscv/ulp_core/start.S | 5 ++++- components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c | 3 +++ components/ulp/ulp_riscv/ulp_core/ulp_riscv_interrupt.c | 7 ++++++- components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c | 7 ++++++- components/ulp/ulp_riscv/ulp_core/ulp_riscv_vectors.S | 6 +++++- .../system/ulp/ulp_riscv/interrupts/sdkconfig.defaults | 1 + 10 files changed, 44 insertions(+), 4 deletions(-) diff --git a/components/ulp/Kconfig b/components/ulp/Kconfig index fd144a4087..5b8a7c5ce1 100644 --- a/components/ulp/Kconfig +++ b/components/ulp/Kconfig @@ -43,6 +43,13 @@ menu "Ultra Low Power (ULP) Co-processor" menu "ULP RISC-V Settings" depends on ULP_COPROC_TYPE_RISCV + config ULP_RISCV_INTERRUPT_ENABLE + bool + prompt "Enable ULP RISC-V interrupts" + default "n" + help + Turn on this setting to enabled interrupts on the ULP RISC-V core. + config ULP_RISCV_UART_BAUDRATE int prompt "Baudrate used by the bitbanged ULP RISC-V UART driver" diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h index 7deffbaab7..11e486c2f6 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h @@ -10,6 +10,7 @@ extern "C" { #endif +#include "sdkconfig.h" #include "soc/rtc_io_reg.h" #include "soc/sens_reg.h" #include "ulp_riscv_register_ops.h" @@ -131,6 +132,8 @@ static inline void ulp_riscv_gpio_pulldown_disable(gpio_num_t gpio_num) CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_RDE); } +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE + /** * @brief Set RTC IO interrupt type and handler * @@ -152,6 +155,8 @@ esp_err_t ulp_riscv_gpio_isr_register(gpio_num_t gpio_num, ulp_riscv_gpio_int_ty */ esp_err_t ulp_riscv_gpio_isr_deregister(gpio_num_t gpio_num); +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ + #ifdef __cplusplus } #endif diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_interrupt.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_interrupt.h index 746acf095e..0bdba291d5 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_interrupt.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_interrupt.h @@ -14,6 +14,8 @@ extern "C" { #endif +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE + /* ULP RISC-V Interrupt sources */ typedef enum { ULP_RISCV_SW_INTR_SOURCE = 0, /**< Interrupt triggered by SW */ @@ -62,6 +64,8 @@ esp_err_t ulp_riscv_intr_alloc(ulp_riscv_interrupt_source_t source, intr_handler */ esp_err_t ulp_riscv_intr_free(ulp_riscv_interrupt_source_t source); +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ + #ifdef __cplusplus } #endif diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h index e8a07d3c4d..463da9d37c 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h @@ -111,6 +111,7 @@ void static inline ulp_riscv_delay_cycles(uint32_t cycles) */ void ulp_riscv_gpio_wakeup_clear(void); +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE /** * @brief Enable ULP RISC-V SW Interrupt * @@ -131,6 +132,8 @@ void ulp_riscv_disable_sw_intr(void); */ void ulp_riscv_trigger_sw_intr(void); +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ + #ifdef __cplusplus } #endif diff --git a/components/ulp/ulp_riscv/ulp_core/start.S b/components/ulp/ulp_riscv/ulp_core/start.S index cad6db5f5a..e1f0b123e1 100644 --- a/components/ulp/ulp_riscv/ulp_core/start.S +++ b/components/ulp/ulp_riscv/ulp_core/start.S @@ -1,9 +1,10 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "ulp_riscv_interrupt_ops.h" .section .text @@ -14,8 +15,10 @@ __start: /* setup the stack pointer */ la sp, __stack_top +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE /* Enable interrupts globally */ maskirq_insn(zero, zero) +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ /* Start ULP user code */ call ulp_riscv_rescue_from_monitor diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c index 43d370644a..ae0792c0d5 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c @@ -3,9 +3,11 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "ulp_riscv_gpio.h" #include "include/ulp_riscv_gpio.h" +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE esp_err_t ulp_riscv_gpio_isr_register(gpio_num_t gpio_num, ulp_riscv_gpio_int_type_t intr_type, intr_handler_t handler, void *arg) { if (gpio_num < 0 || gpio_num >= GPIO_NUM_MAX) { @@ -31,3 +33,4 @@ esp_err_t ulp_riscv_gpio_isr_deregister(gpio_num_t gpio_num) { return ulp_riscv_intr_free(ULP_RISCV_RTCIO0_INTR_SOURCE + gpio_num); } +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_interrupt.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_interrupt.c index e236acd989..18b5a418d3 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_interrupt.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_interrupt.c @@ -1,15 +1,18 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include +#include "sdkconfig.h" #include "include/ulp_riscv_interrupt.h" #include "ulp_riscv_register_ops.h" #include "ulp_riscv_interrupt.h" #include "ulp_riscv_gpio.h" #include "soc/sens_reg.h" +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE + #define ULP_RISCV_TIMER_INT (1 << 0U) /* Internal Timer Interrupt */ #define ULP_RISCV_EBREAK_ECALL_ILLEGAL_INSN_INT (1 << 1U) /* EBREAK, ECALL or Illegal instruction */ #define ULP_RISCV_BUS_ERROR_INT (1 << 2U) /* Bus Error (Unaligned Memory Access) */ @@ -130,3 +133,5 @@ void __attribute__((weak)) _ulp_riscv_interrupt_handler(uint32_t q1) /* TODO: RTC I2C interrupt */ } } + +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c index c4b8027fe7..8fce93363a 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c @@ -1,9 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "ulp_riscv_utils.h" #include "ulp_riscv_register_ops.h" #include "soc/soc.h" @@ -48,6 +49,8 @@ void ulp_riscv_gpio_wakeup_clear(void) SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR); } +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE + void ulp_riscv_enable_sw_intr(intr_handler_t handler, void *arg) { /* Enable ULP RISC-V SW interrupt */ @@ -72,3 +75,5 @@ void ulp_riscv_trigger_sw_intr(void) { SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SW_INT_TRIGGER); } + +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_vectors.S b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_vectors.S index b302db429a..855894ce45 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_vectors.S +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_vectors.S @@ -1,9 +1,10 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "ulp_riscv_interrupt_ops.h" #include "riscv/rvruntime-frames.h" .equ SAVE_REGS, 17 @@ -69,6 +70,7 @@ reset_vector: j __start +#if CONFIG_ULP_RISCV_INTERRUPT_ENABLE /* Interrupt handler */ .balign 0x10 irq_vector: @@ -89,3 +91,5 @@ irq_vector: /* Exit interrupt handler by executing the custom retirq instruction which will retore pc and re-enable interrupts */ retirq_insn() + +#endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ diff --git a/examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults b/examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults index e3745e5057..16f5110d63 100644 --- a/examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults +++ b/examples/system/ulp/ulp_riscv/interrupts/sdkconfig.defaults @@ -2,6 +2,7 @@ CONFIG_ULP_COPROC_ENABLED=y CONFIG_ULP_COPROC_TYPE_RISCV=y CONFIG_ULP_COPROC_RESERVE_MEM=4096 +CONFIG_ULP_RISCV_INTERRUPT_ENABLE=y # Set log level to Warning to produce clean output CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y CONFIG_BOOTLOADER_LOG_LEVEL=2