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fix(mspi): Refactor mspi ll/soc for c5 and c61

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This commit is contained in:
C.S.M
2024-07-15 11:39:35 +08:00
parent e5e146365b
commit bc80476411
34 changed files with 13196 additions and 10355 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+26 -74
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@@ -18,19 +18,8 @@
#endif
#include "hal/spi_flash_ll.h"
#include "rom/spi_flash.h"
#if CONFIG_IDF_TARGET_ESP32
# include "soc/spi_struct.h"
# include "soc/spi_reg.h"
/* SPI flash controller */
# define SPIFLASH SPI1
# define SPI0 SPI0
#else
# include "hal/spimem_flash_ll.h"
# include "soc/spi_mem_struct.h"
# include "soc/spi_mem_reg.h"
/* SPI flash controller */
# define SPIFLASH SPIMEM1
# define SPI0 SPIMEM0
#if !CONFIG_IDF_TARGET_ESP32
#include "hal/spimem_flash_ll.h"
#endif
// This dependency will be removed in the future. IDF-5025
@@ -587,61 +576,43 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
{
assert(mosi_len <= 32);
assert(miso_len <= 32);
uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
uint32_t old_user_reg = SPIFLASH.user.val;
uint32_t old_user1_reg = SPIFLASH.user1.val;
uint32_t old_user2_reg = SPIFLASH.user2.val;
// Clear ctrl regs.
SPIFLASH.ctrl.val = 0;
uint32_t old_ctrl_reg = 0;
uint32_t old_user_reg = 0;
uint32_t old_user1_reg = 0;
uint32_t old_user2_reg = 0;
spi_flash_ll_get_common_command_register_info(&SPIMEM_LL_APB, &old_ctrl_reg, &old_user_reg, &old_user1_reg, &old_user2_reg);
SPIMEM_LL_APB.ctrl.val = 0;
#if CONFIG_IDF_TARGET_ESP32
spi_flash_ll_set_wp_level(&SPIFLASH, true);
spi_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
#else
spimem_flash_ll_set_wp_level(&SPIFLASH, true);
spimem_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
#endif
//command phase
SPIFLASH.user.usr_command = 1;
SPIFLASH.user2.usr_command_bitlen = 7;
SPIFLASH.user2.usr_command_value = command;
spi_flash_ll_set_command(&SPIMEM_LL_APB, command, 8);
//addr phase
SPIFLASH.user.usr_addr = addr_len > 0;
SPIFLASH.user1.usr_addr_bitlen = addr_len - 1;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.addr = (addr_len > 0)? (address << (32-addr_len)) : 0;
#else
SPIFLASH.addr = address;
#endif
spi_flash_ll_set_addr_bitlen(&SPIMEM_LL_APB, addr_len);
spi_flash_ll_set_usr_address(&SPIMEM_LL_APB, address, addr_len);
//dummy phase
uint32_t total_dummy = dummy_len;
if (miso_len > 0) {
total_dummy += g_rom_spiflash_dummy_len_plus[1];
}
SPIFLASH.user.usr_dummy = total_dummy > 0;
SPIFLASH.user1.usr_dummy_cyclelen = total_dummy - 1;
spi_flash_ll_set_dummy(&SPIMEM_LL_APB, total_dummy);
//output data
SPIFLASH.user.usr_mosi = mosi_len > 0;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
#else
SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
#endif
SPIFLASH.data_buf[0] = mosi_data;
spi_flash_ll_set_mosi_bitlen(&SPIMEM_LL_APB, mosi_len);
spi_flash_ll_set_buffer_data(&SPIMEM_LL_APB, &mosi_data, mosi_len / 8);
//input data
SPIFLASH.user.usr_miso = miso_len > 0;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
#else
SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
#endif
spi_flash_ll_set_miso_bitlen(&SPIMEM_LL_APB, miso_len);
SPIFLASH.cmd.usr = 1;
while (SPIFLASH.cmd.usr != 0) {
spi_flash_ll_user_start(&SPIMEM_LL_APB, false);
while(!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
}
SPIFLASH.ctrl.val = old_ctrl_reg;
SPIFLASH.user.val = old_user_reg;
SPIFLASH.user1.val = old_user1_reg;
SPIFLASH.user2.val = old_user2_reg;
spi_flash_ll_set_common_command_register_info(&SPIMEM_LL_APB, old_ctrl_reg, old_user_reg, old_user1_reg, old_user2_reg);
uint32_t ret = SPIFLASH.data_buf[0];
uint32_t output_data = 0;
spi_flash_ll_get_buffer_data(&SPIMEM_LL_APB, &output_data, miso_len / 8);
uint32_t ret = output_data;
if (miso_len < 32) {
//set unused bits to 0
ret &= ~(UINT32_MAX << miso_len);
@@ -793,28 +764,9 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
#endif //XMC_SUPPORT
FORCE_INLINE_ATTR void bootloader_mspi_reset(void)
{
#if CONFIG_IDF_TARGET_ESP32
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
SPI1.slave.sync_reset = 1;
SPI0.slave.sync_reset = 1;
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
#else
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
#endif
}
esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
{
bootloader_mspi_reset();
spi_flash_ll_sync_reset();
// Seems that sync_reset cannot make host totally idle.'
// Sending an extra(useless) command to make the host idle in order to send reset command.
bootloader_execute_flash_command(0x05, 0, 0, 0);
@@ -844,7 +796,7 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
{
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPIMEM_LL_CACHE);
#if CONFIG_IDF_TARGET_ESP32
if (spi_ctrl & SPI_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;