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feat(soc): Merge spi2_reg.h and spi3_reg.h

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This commit is contained in:
Armando
2023-06-27 14:19:15 +08:00
parent 989c6f6e46
commit bd9e566d6d
4 changed files with 77 additions and 3524 deletions
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1830
components/soc/esp32p4/include/soc/spi3_reg.h
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1442
components/soc/esp32p4/include/soc/spi3_struct.h
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File diff suppressed because it is too large Load Diff

36
components/soc/esp32p4/include/soc/spi2_reg_s.h → components/soc/esp32p4/include/soc/spi_reg.h
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@@ -18,6 +18,7 @@ extern "C" {
/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
* Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_CONF_BITLEN 0x0003FFFFU
#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
#define SPI_CONF_BITLEN_V 0x0003FFFFU
@@ -84,6 +85,7 @@ extern "C" {
* Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
* state.
*/
//this field is only for GPSPI2
#define SPI_FADDR_OCT (BIT(7))
#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
#define SPI_FADDR_OCT_V 0x00000001U
@@ -108,6 +110,7 @@ extern "C" {
* Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
* state.
*/
//this field is only for GPSPI2
#define SPI_FCMD_OCT (BIT(10))
#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
#define SPI_FCMD_OCT_V 0x00000001U
@@ -132,6 +135,7 @@ extern "C" {
* In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can
* be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_FREAD_OCT (BIT(16))
#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
#define SPI_FREAD_OCT_V 0x00000001U
@@ -253,6 +257,7 @@ extern "C" {
* Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
* Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_OPI_MODE (BIT(4))
#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
#define SPI_OPI_MODE_V 0x00000001U
@@ -317,6 +322,7 @@ extern "C" {
* In the write operations read-data phase apply 8 signals. Can be configured in CONF
* state.
*/
//this field is only for GPSPI2
#define SPI_FWRITE_OCT (BIT(14))
#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
#define SPI_FWRITE_OCT_V 0x00000001U
@@ -326,6 +332,7 @@ extern "C" {
* will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
* not seg-trans mode. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_USR_CONF_NXT (BIT(15))
#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
#define SPI_USR_CONF_NXT_V 0x00000001U
@@ -522,6 +529,7 @@ extern "C" {
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_CS3_DIS (BIT(3))
#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
#define SPI_CS3_DIS_V 0x00000001U
@@ -530,6 +538,7 @@ extern "C" {
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_CS4_DIS (BIT(4))
#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
#define SPI_CS4_DIS_V 0x00000001U
@@ -538,6 +547,7 @@ extern "C" {
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_CS5_DIS (BIT(5))
#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
#define SPI_CS5_DIS_V 0x00000001U
@@ -553,6 +563,7 @@ extern "C" {
* In the master mode the bits are the polarity of spi cs line, the value is
* equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
*/
//This field for GPSPI3 is only 3-bit-width
#define SPI_MASTER_CS_POL 0x0000003FU
#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
#define SPI_MASTER_CS_POL_V 0x0000003FU
@@ -561,6 +572,7 @@ extern "C" {
* 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR
* mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.
*/
//this field is only for GPSPI2
#define SPI_CLK_DATA_DTR_EN (BIT(16))
#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
#define SPI_CLK_DATA_DTR_EN_V 0x00000001U
@@ -570,6 +582,7 @@ extern "C" {
* 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
* Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DATA_DTR_EN (BIT(17))
#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
#define SPI_DATA_DTR_EN_V 0x00000001U
@@ -579,6 +592,7 @@ extern "C" {
* 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_ADDR_DTR_EN (BIT(18))
#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
#define SPI_ADDR_DTR_EN_V 0x00000001U
@@ -588,6 +602,7 @@ extern "C" {
* 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_CMD_DTR_EN (BIT(19))
#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
#define SPI_CMD_DTR_EN_V 0x00000001U
@@ -603,6 +618,7 @@ extern "C" {
/** SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0;
* The default value of spi_dqs. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DQS_IDLE_EDGE (BIT(24))
#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
#define SPI_DQS_IDLE_EDGE_V 0x00000001U
@@ -676,6 +692,7 @@ extern "C" {
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN4_MODE 0x00000003U
#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
#define SPI_DIN4_MODE_V 0x00000003U
@@ -685,6 +702,7 @@ extern "C" {
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN5_MODE 0x00000003U
#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
#define SPI_DIN5_MODE_V 0x00000003U
@@ -694,6 +712,7 @@ extern "C" {
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN6_MODE 0x00000003U
#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
#define SPI_DIN6_MODE_V 0x00000003U
@@ -703,6 +722,7 @@ extern "C" {
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN7_MODE 0x00000003U
#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
#define SPI_DIN7_MODE_V 0x00000003U
@@ -756,6 +776,7 @@ extern "C" {
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN4_NUM 0x00000003U
#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
#define SPI_DIN4_NUM_V 0x00000003U
@@ -764,6 +785,7 @@ extern "C" {
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN5_NUM 0x00000003U
#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
#define SPI_DIN5_NUM_V 0x00000003U
@@ -772,6 +794,7 @@ extern "C" {
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN6_NUM 0x00000003U
#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
#define SPI_DIN6_NUM_V 0x00000003U
@@ -780,6 +803,7 @@ extern "C" {
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DIN7_NUM 0x00000003U
#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
#define SPI_DIN7_NUM_V 0x00000003U
@@ -830,6 +854,7 @@ extern "C" {
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DOUT4_MODE (BIT(4))
#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
#define SPI_DOUT4_MODE_V 0x00000001U
@@ -839,6 +864,7 @@ extern "C" {
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DOUT5_MODE (BIT(5))
#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
#define SPI_DOUT5_MODE_V 0x00000001U
@@ -848,6 +874,7 @@ extern "C" {
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DOUT6_MODE (BIT(6))
#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
#define SPI_DOUT6_MODE_V 0x00000001U
@@ -857,6 +884,7 @@ extern "C" {
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_DOUT7_MODE (BIT(7))
#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
#define SPI_DOUT7_MODE_V 0x00000001U
@@ -866,6 +894,7 @@ extern "C" {
* delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
//this field is only for GPSPI2
#define SPI_D_DQS_MODE (BIT(8))
#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
#define SPI_D_DQS_MODE_V 0x00000001U
@@ -1068,6 +1097,7 @@ extern "C" {
/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
* The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
//this field is only for GPSPI2
#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U
@@ -1220,6 +1250,7 @@ extern "C" {
/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
* The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
//this field is only for GPSPI2
#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U
@@ -1389,6 +1420,7 @@ extern "C" {
* The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
* is error in the DMA seg-conf-trans. 0: others.
*/
//this field is only for GPSPI2
#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U
@@ -1546,6 +1578,7 @@ extern "C" {
/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
* The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
//this field is only for GPSPI2
#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U
@@ -1698,6 +1731,7 @@ extern "C" {
/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
* The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
//this field is only for GPSPI2
#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U
@@ -2009,6 +2043,7 @@ extern "C" {
/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
* The magic value of BM table in master DMA seg-trans.
*/
//this field is only for GPSPI2
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU
#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU
@@ -2032,6 +2067,7 @@ extern "C" {
* 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
* will start. 0: This is not seg-trans mode.
*/
//this field is only for GPSPI2
#define SPI_USR_CONF (BIT(28))
#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S)
#define SPI_USR_CONF_V 0x00000001U

293
components/soc/esp32p4/include/soc/spi2_s_struct.h → components/soc/esp32p4/include/soc/spi_struct.h
View File

@@ -19,7 +19,7 @@ typedef union {
/** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
* Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
*/
uint32_t conf_bitlen:18;
uint32_t conf_bitlen:18; //this field is only for GPSPI2
uint32_t reserved_18:5;
/** update : WT; bitpos: [23]; default: 0;
* Set this bit to synchronize SPI registers from APB clock domain into SPI module
@@ -70,7 +70,7 @@ typedef union {
* Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
* Can be configured in CONF state.
*/
uint32_t opi_mode:1;
uint32_t opi_mode:1; //this field is only for GPSPI2
/** tsck_i_edge : R/W; bitpos: [5]; default: 0;
* In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
* spi_ck_i. 1:tsck = !spi_ck_i.
@@ -111,13 +111,13 @@ typedef union {
* In the write operations read-data phase apply 8 signals. Can be configured in CONF
* state.
*/
uint32_t fwrite_oct:1;
uint32_t fwrite_oct:1; //this field is only for GPSPI2
/** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
* 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
* will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
* not seg-trans mode. Can be configured in CONF state.
*/
uint32_t usr_conf_nxt:1;
uint32_t usr_conf_nxt:1; //this field is only for GPSPI2
uint32_t reserved_16:1;
/** sio : R/W; bitpos: [17]; default: 0;
* Set the bit to enable 3-line half duplex communication mosi and miso signals share
@@ -255,7 +255,7 @@ typedef union {
* Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
* state.
*/
uint32_t faddr_oct:1;
uint32_t faddr_oct:1; //this field is only for GPSPI2
/** fcmd_dual : R/W; bitpos: [8]; default: 0;
* Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
* state.
@@ -270,7 +270,7 @@ typedef union {
* Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
* state.
*/
uint32_t fcmd_oct:1;
uint32_t fcmd_oct:1; //this field is only for GPSPI2
uint32_t reserved_11:3;
/** fread_dual : R/W; bitpos: [14]; default: 0;
* In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
@@ -286,7 +286,7 @@ typedef union {
* In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can
* be configured in CONF state.
*/
uint32_t fread_oct:1;
uint32_t fread_oct:1; //this field is only for GPSPI2
uint32_t reserved_17:1;
/** q_pol : R/W; bitpos: [18]; default: 1;
* The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
@@ -365,17 +365,17 @@ typedef union {
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
uint32_t cs3_dis:1;
uint32_t cs3_dis:1; //this field is only for GPSPI2
/** cs4_dis : R/W; bitpos: [4]; default: 1;
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
uint32_t cs4_dis:1;
uint32_t cs4_dis:1; //this field is only for GPSPI2
/** cs5_dis : R/W; bitpos: [5]; default: 1;
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
*/
uint32_t cs5_dis:1;
uint32_t cs5_dis:1; //this field is only for GPSPI2
/** ck_dis : R/W; bitpos: [6]; default: 0;
* 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
*/
@@ -384,31 +384,31 @@ typedef union {
* In the master mode the bits are the polarity of spi cs line, the value is
* equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
*/
uint32_t master_cs_pol:6;
uint32_t master_cs_pol:6; //This field for GPSPI3 is only 3-bit-width
uint32_t reserved_13:3;
/** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
* 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR
* mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.
*/
uint32_t clk_data_dtr_en:1;
uint32_t clk_data_dtr_en:1; //this field is only for GPSPI2
/** data_dtr_en : R/W; bitpos: [17]; default: 0;
* 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
* 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
* Can be configured in CONF state.
*/
uint32_t data_dtr_en:1;
uint32_t data_dtr_en:1; //this field is only for GPSPI2
/** addr_dtr_en : R/W; bitpos: [18]; default: 0;
* 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
* 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
* configured in CONF state.
*/
uint32_t addr_dtr_en:1;
uint32_t addr_dtr_en:1; //this field is only for GPSPI2
/** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
* 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
* 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
* configured in CONF state.
*/
uint32_t cmd_dtr_en:1;
uint32_t cmd_dtr_en:1; //this field is only for GPSPI2
uint32_t reserved_20:3;
/** slave_cs_pol : R/W; bitpos: [23]; default: 0;
* spi slave input cs polarity select. 1: inv 0: not change. Can be configured in
@@ -418,7 +418,7 @@ typedef union {
/** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
* The default value of spi_dqs. Can be configured in CONF state.
*/
uint32_t dqs_idle_edge:1;
uint32_t dqs_idle_edge:1; //this field is only for GPSPI2
uint32_t reserved_25:4;
/** ck_idle_edge : R/W; bitpos: [29]; default: 0;
* 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be
@@ -554,7 +554,7 @@ typedef union {
/** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
* The magic value of BM table in master DMA seg-trans.
*/
uint32_t dma_seg_magic_value:4;
uint32_t dma_seg_magic_value:4; //this field is only for GPSPI2
/** slave_mode : R/W; bitpos: [26]; default: 0;
* Set SPI work mode. 1: slave mode 0: master mode.
*/
@@ -568,7 +568,7 @@ typedef union {
* 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
* will start. 0: This is not seg-trans mode.
*/
uint32_t usr_conf:1;
uint32_t usr_conf:1; //this field is only for GPSPI2
/** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
* In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
* starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
@@ -696,25 +696,25 @@ typedef union {
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
uint32_t din4_mode:2;
uint32_t din4_mode:2; //this field is only for GPSPI2
/** din5_mode : R/W; bitpos: [11:10]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: input without delayed,
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
uint32_t din5_mode:2;
uint32_t din5_mode:2; //this field is only for GPSPI2
/** din6_mode : R/W; bitpos: [13:12]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: input without delayed,
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
uint32_t din6_mode:2;
uint32_t din6_mode:2; //this field is only for GPSPI2
/** din7_mode : R/W; bitpos: [15:14]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: input without delayed,
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
* with the spi_clk. Can be configured in CONF state.
*/
uint32_t din7_mode:2;
uint32_t din7_mode:2; //this field is only for GPSPI2
/** timing_hclk_active : R/W; bitpos: [16]; default: 0;
* 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF
* state.
@@ -754,22 +754,22 @@ typedef union {
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
uint32_t din4_num:2;
uint32_t din4_num:2; //this field is only for GPSPI2
/** din5_num : R/W; bitpos: [11:10]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
uint32_t din5_num:2;
uint32_t din5_num:2; //this field is only for GPSPI2
/** din6_num : R/W; bitpos: [13:12]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
uint32_t din6_num:2;
uint32_t din6_num:2; //this field is only for GPSPI2
/** din7_num : R/W; bitpos: [15:14]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
*/
uint32_t din7_num:2;
uint32_t din7_num:2; //this field is only for GPSPI2
uint32_t reserved_16:16;
};
uint32_t val;
@@ -809,31 +809,31 @@ typedef union {
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
uint32_t dout4_mode:1;
uint32_t dout4_mode:1; //this field is only for GPSPI2
/** dout5_mode : R/W; bitpos: [5]; default: 0;
* The output signal $n is delayed by the SPI module clock, 0: output without delayed,
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
uint32_t dout5_mode:1;
uint32_t dout5_mode:1; //this field is only for GPSPI2
/** dout6_mode : R/W; bitpos: [6]; default: 0;
* The output signal $n is delayed by the SPI module clock, 0: output without delayed,
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
uint32_t dout6_mode:1;
uint32_t dout6_mode:1; //this field is only for GPSPI2
/** dout7_mode : R/W; bitpos: [7]; default: 0;
* The output signal $n is delayed by the SPI module clock, 0: output without delayed,
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
uint32_t dout7_mode:1;
uint32_t dout7_mode:1; //this field is only for GPSPI2
/** d_dqs_mode : R/W; bitpos: [8]; default: 0;
* The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
* delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
* configured in CONF state.
*/
uint32_t d_dqs_mode:1;
uint32_t d_dqs_mode:1; //this field is only for GPSPI2
uint32_t reserved_9:23;
};
uint32_t val;
@@ -905,7 +905,7 @@ typedef union {
/** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
* The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_ena:1;
uint32_t seg_magic_err_int_ena:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
* The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
@@ -999,7 +999,7 @@ typedef union {
/** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
* The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_clr:1;
uint32_t seg_magic_err_int_clr:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
* The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
@@ -1110,7 +1110,7 @@ typedef union {
* The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
* is error in the DMA seg-conf-trans. 0: others.
*/
uint32_t seg_magic_err_int_raw:1;
uint32_t seg_magic_err_int_raw:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
* The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
* of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
@@ -1209,7 +1209,7 @@ typedef union {
/** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
* The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_st:1;
uint32_t seg_magic_err_int_st:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
* The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
@@ -1303,7 +1303,7 @@ typedef union {
/** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
* The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_set:1;
uint32_t seg_magic_err_int_set:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
* The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
@@ -1334,214 +1334,18 @@ typedef union {
} spi_dma_int_set_reg_t;
/** Group: CPU-controlled data buffer */
/** Type of w0 register
* SPI CPU-controlled buffer0
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf0:32;
};
uint32_t val;
} spi_w0_reg_t;
/** Type of w1 register
* SPI CPU-controlled buffer1
*/
typedef union {
struct {
/** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf1:32;
};
uint32_t val;
} spi_w1_reg_t;
/** Type of w2 register
* SPI CPU-controlled buffer2
*/
typedef union {
struct {
/** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf2:32;
};
uint32_t val;
} spi_w2_reg_t;
/** Type of w3 register
* SPI CPU-controlled buffer3
*/
typedef union {
struct {
/** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf3:32;
};
uint32_t val;
} spi_w3_reg_t;
/** Type of w4 register
* SPI CPU-controlled buffer4
*/
typedef union {
struct {
/** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf4:32;
};
uint32_t val;
} spi_w4_reg_t;
/** Type of w5 register
* SPI CPU-controlled buffer5
*/
typedef union {
struct {
/** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf5:32;
};
uint32_t val;
} spi_w5_reg_t;
/** Type of w6 register
* SPI CPU-controlled buffer6
*/
typedef union {
struct {
/** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf6:32;
};
uint32_t val;
} spi_w6_reg_t;
/** Type of w7 register
* SPI CPU-controlled buffer7
*/
typedef union {
struct {
/** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf7:32;
};
uint32_t val;
} spi_w7_reg_t;
/** Type of w8 register
* SPI CPU-controlled buffer8
*/
typedef union {
struct {
/** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf8:32;
};
uint32_t val;
} spi_w8_reg_t;
/** Type of w9 register
* SPI CPU-controlled buffer9
*/
typedef union {
struct {
/** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf9:32;
};
uint32_t val;
} spi_w9_reg_t;
/** Type of w10 register
* SPI CPU-controlled buffer10
*/
typedef union {
struct {
/** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf10:32;
};
uint32_t val;
} spi_w10_reg_t;
/** Type of w11 register
* SPI CPU-controlled buffer11
*/
typedef union {
struct {
/** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf11:32;
};
uint32_t val;
} spi_w11_reg_t;
/** Type of w12 register
* SPI CPU-controlled buffer12
*/
typedef union {
struct {
/** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf12:32;
};
uint32_t val;
} spi_w12_reg_t;
/** Type of w13 register
* SPI CPU-controlled buffer13
*/
typedef union {
struct {
/** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf13:32;
};
uint32_t val;
} spi_w13_reg_t;
/** Type of w14 register
* SPI CPU-controlled buffer14
*/
typedef union {
struct {
/** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf14:32;
};
uint32_t val;
} spi_w14_reg_t;
/** Type of w15 register
* SPI CPU-controlled buffer15
/** Type of wn register
* SPI CPU-controlled buffer
*/
typedef union {
struct {
/** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf15:32;
uint32_t buf:32;
};
uint32_t val;
} spi_w15_reg_t;
} spi_wn_reg_t;
/** Group: Version register */
@@ -1580,22 +1384,7 @@ typedef struct {
volatile spi_dma_int_st_reg_t dma_int_st;
volatile spi_dma_int_set_reg_t dma_int_set;
uint32_t reserved_048[20];
volatile spi_w0_reg_t w0;
volatile spi_w1_reg_t w1;
volatile spi_w2_reg_t w2;
volatile spi_w3_reg_t w3;
volatile spi_w4_reg_t w4;
volatile spi_w5_reg_t w5;
volatile spi_w6_reg_t w6;
volatile spi_w7_reg_t w7;
volatile spi_w8_reg_t w8;
volatile spi_w9_reg_t w9;
volatile spi_w10_reg_t w10;
volatile spi_w11_reg_t w11;
volatile spi_w12_reg_t w12;
volatile spi_w13_reg_t w13;
volatile spi_w14_reg_t w14;
volatile spi_w15_reg_t w15;
volatile spi_wn_reg_t data_buf[16];
uint32_t reserved_0d8[2];
volatile spi_slave_reg_t slave;
volatile spi_slave1_reg_t slave1;