diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 85e4aa8027..ffa52379d7 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -47,12 +47,7 @@ void bootloader_console_init(void)
 {
     const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
 
-#if !ESP_ROM_SUPPORT_MULTIPLE_UART
-    /* esp_rom_install_channel_put is not available unless multiple UARTs are supported */
     esp_rom_install_uart_printf();
-#else
-    esp_rom_install_channel_putc(1, esp_rom_uart_putc);
-#endif
 
     // Wait for UART FIFO to be empty.
     esp_rom_uart_tx_wait_idle(0);
@@ -61,10 +56,10 @@ void bootloader_console_init(void)
     // Some constants to make the following code less upper-case
     const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
     const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
+
     // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
-#if ESP_ROM_SUPPORT_MULTIPLE_UART
     esp_rom_uart_set_as_console(uart_num);
-#endif
+
     // If console is attached to UART1 or if non-default pins are used,
     // need to reconfigure pins using GPIO matrix
     if (uart_num != 0 ||
diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in
index 4707ff484e..ed129cb84e 100644
--- a/components/esp_rom/esp32/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32/Kconfig.soc_caps.in
@@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE
     bool
     default y
 
-config ESP_ROM_SUPPORT_MULTIPLE_UART
-    bool
-    default y
-
 config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
     bool
     default y
diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h
index 1d19be8571..959075b29c 100644
--- a/components/esp_rom/esp32/esp_rom_caps.h
+++ b/components/esp_rom/esp32/esp_rom_caps.h
@@ -9,5 +9,4 @@
 #define ESP_ROM_HAS_CRC_LE              (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_HAS_CRC_BE              (1) // ROM CRC library supports Big Endian
 #define ESP_ROM_HAS_JPEG_DECODE         (1) // ROM has JPEG decode library
-#define ESP_ROM_SUPPORT_MULTIPLE_UART   (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
index 565d2a6a40..3e7c7ab600 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
@@ -28,6 +28,7 @@ PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
 PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
 PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
 PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
 PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret );
diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
index 7945722adc..437ebe7daf 100644
--- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
+++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
@@ -30,6 +30,7 @@ PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
 PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
 PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
 PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
 
diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
index 7945722adc..437ebe7daf 100644
--- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
+++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
@@ -30,6 +30,7 @@ PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
 PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
 PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
 PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
 
diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in
index 2b753e7e0d..870795370c 100644
--- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in
@@ -7,10 +7,6 @@ config ESP_ROM_HAS_CRC_LE
     bool
     default y
 
-config ESP_ROM_SUPPORT_MULTIPLE_UART
-    bool
-    default y
-
 config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
     bool
     default y
diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h
index 1078ff8997..1032eef93a 100644
--- a/components/esp_rom/esp32s2/esp_rom_caps.h
+++ b/components/esp_rom/esp32s2/esp_rom_caps.h
@@ -7,5 +7,4 @@
 #pragma once
 
 #define ESP_ROM_HAS_CRC_LE            (1) // ROM CRC library supports Little Endian
-#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in
index 9788a68b77..1d474656fc 100644
--- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in
@@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE
     bool
     default y
 
-config ESP_ROM_SUPPORT_MULTIPLE_UART
-    bool
-    default y
-
 config ESP_ROM_UART_CLK_IS_XTAL
     bool
     default y
@@ -46,3 +42,7 @@ config ESP_ROM_HAS_HAL_WDT
 config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
     bool
     default y
+
+config ESP_ROM_HAS_ETS_PRINTF_BUG
+    bool
+    default y
diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h
index a5362a68e4..566f38b0b5 100644
--- a/components/esp_rom/esp32s3/esp_rom_caps.h
+++ b/components/esp_rom/esp32s3/esp_rom_caps.h
@@ -9,7 +9,6 @@
 #define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
 #define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-#define ESP_ROM_SUPPORT_MULTIPLE_UART       (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
@@ -17,3 +16,4 @@
 #define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
 #define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
+#define ESP_ROM_HAS_ETS_PRINTF_BUG          (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
diff --git a/components/esp_rom/patches/esp_rom_uart.c b/components/esp_rom/patches/esp_rom_uart.c
index 7f71a542e2..470b6f5205 100644
--- a/components/esp_rom/patches/esp_rom_uart.c
+++ b/components/esp_rom/patches/esp_rom_uart.c
@@ -9,6 +9,7 @@
 #include "esp_attr.h"
 #include "sdkconfig.h"
 #include "hal/uart_ll.h"
+#include "hal/efuse_hal.h"
 
 #if CONFIG_IDF_TARGET_ESP32
 /**
@@ -24,3 +25,25 @@ IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_h
 {
     uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz);
 }
+
+#if CONFIG_IDF_TARGET_ESP32C3
+/**
+ * The ESP32-C3 ROM has released two versions, one is the ECO3 version,
+ * and the other is the version before ECO3 (include ECO0 ECO1 ECO2).
+ * These two versions of the ROM code do not list uart_tx_switch wrap
+ * function in the ROM interface, so here use the uart_tx_switch direct
+ * address instead.
+ */
+IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no)
+{
+    typedef void (*rom_func_t)(uint8_t);
+    rom_func_t uart_tx_switch = NULL;
+
+    if (efuse_hal_chip_revision() < 3) {
+        uart_tx_switch = (rom_func_t)0x4004b8ca;
+    } else {
+        uart_tx_switch = (rom_func_t)0x4004c166;
+    }
+    uart_tx_switch(uart_no);
+}
+#endif