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fix(adc): fix adc do not enable/disable regi2c registers

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This commit is contained in:
gaoxu
2025-04-25 14:39:01 +08:00
parent d6fb99b5ad
commit bf335a38f7
38 changed files with 215 additions and 366 deletions
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3
components/bootloader_support/src/bootloader_random_esp32c5.c
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@@ -18,8 +18,7 @@ void bootloader_random_enable(void)
adc_ll_digi_controller_clk_div(0, 0, 0); adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_reset(false); regi2c_ctrl_ll_i2c_sar_periph_enable();
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime // enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE(); ANALOG_CLOCK_ENABLE();

3
components/bootloader_support/src/bootloader_random_esp32c6.c
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@@ -18,8 +18,7 @@ void bootloader_random_enable(void)
adc_ll_digi_controller_clk_div(0, 0, 0); adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_reset(false); regi2c_ctrl_ll_i2c_sar_periph_enable();
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime // enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE(); ANALOG_CLOCK_ENABLE();

3
components/bootloader_support/src/bootloader_random_esp32c61.c
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@@ -18,8 +18,7 @@ void bootloader_random_enable(void)
adc_ll_digi_controller_clk_div(0, 0, 0); adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_reset(false); regi2c_ctrl_ll_i2c_sar_periph_enable();
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime // enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE(); ANALOG_CLOCK_ENABLE();

2
components/bootloader_support/src/bootloader_random_esp32h2.c
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@@ -18,7 +18,7 @@ void bootloader_random_enable(void)
adc_ll_digi_controller_clk_div(0, 0, 0); adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_i2c_periph_enable(); regi2c_ctrl_ll_i2c_sar_periph_enable();
// enable analog i2c master clock for RNG runtime // enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE(); ANALOG_CLOCK_ENABLE();

17
components/driver/deprecated/adc_legacy.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -459,10 +459,6 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
adc_lock_release(ADC_UNIT_2); adc_lock_release(ADC_UNIT_2);
#endif #endif
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_UNIT_2);
#endif
return ESP_OK; return ESP_OK;
} }
@@ -539,11 +535,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
bitwidth = ADC_BITWIDTH_12; bitwidth = ADC_BITWIDTH_12;
#endif #endif
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_2, channel);
adc_set_hw_calibration_code(ADC_UNIT_2, atten);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
/** For ESP32S2 and S3, the right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/ /** For ESP32S2 and S3, the right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/
if (adc_lock_try_acquire(ADC_UNIT_2) != ESP_OK) { if (adc_lock_try_acquire(ADC_UNIT_2) != ESP_OK) {
@@ -553,6 +544,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif #endif
sar_periph_ctrl_adc_oneshot_power_acquire(); //in critical section with whole rtc module sar_periph_ctrl_adc_oneshot_power_acquire(); //in critical section with whole rtc module
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_UNIT_2);
adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_2, channel);
adc_set_hw_calibration_code(ADC_UNIT_2, atten);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
//avoid collision with other tasks //avoid collision with other tasks
adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here. adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
SARADC2_ENTER(); SARADC2_ENTER();

8
components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
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@@ -139,23 +139,23 @@ TEST_CASE("Legacy ADC oneshot high/low test", "[legacy_adc_oneshot]")
test_adc_set_io_level(ADC_UNIT_1, (adc1_channel_t)ADC1_TEST_CHAN0, 0); test_adc_set_io_level(ADC_UNIT_1, (adc1_channel_t)ADC1_TEST_CHAN0, 0);
adc_raw = adc1_get_raw(ADC1_TEST_CHAN0); adc_raw = adc1_get_raw(ADC1_TEST_CHAN0);
ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_1, ADC1_TEST_CHAN0, adc_raw); ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_1 + 1, ADC1_TEST_CHAN0, adc_raw);
TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw); TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw);
test_adc_set_io_level(ADC_UNIT_1, (adc1_channel_t)ADC1_TEST_CHAN0, 1); test_adc_set_io_level(ADC_UNIT_1, (adc1_channel_t)ADC1_TEST_CHAN0, 1);
adc_raw = adc1_get_raw(ADC1_TEST_CHAN0); adc_raw = adc1_get_raw(ADC1_TEST_CHAN0);
ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_1, ADC1_TEST_CHAN0, adc_raw); ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_1 + 1, ADC1_TEST_CHAN0, adc_raw);
TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw); TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw);
#if ADC_TEST_ADC2 #if ADC_TEST_ADC2
test_adc_set_io_level(ADC_UNIT_2, (adc2_channel_t)ADC2_TEST_CHAN0, 0); test_adc_set_io_level(ADC_UNIT_2, (adc2_channel_t)ADC2_TEST_CHAN0, 0);
TEST_ESP_OK(adc2_get_raw(ADC2_TEST_CHAN0, ADC_WIDTH_BIT_DEFAULT, &adc_raw)); TEST_ESP_OK(adc2_get_raw(ADC2_TEST_CHAN0, ADC_WIDTH_BIT_DEFAULT, &adc_raw));
ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_2, ADC2_TEST_CHAN0, adc_raw); ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_2 + 1, ADC2_TEST_CHAN0, adc_raw);
TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw); TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, adc_raw);
test_adc_set_io_level(ADC_UNIT_2, (adc2_channel_t)ADC2_TEST_CHAN0, 1); test_adc_set_io_level(ADC_UNIT_2, (adc2_channel_t)ADC2_TEST_CHAN0, 1);
TEST_ESP_OK(adc2_get_raw(ADC2_TEST_CHAN0, ADC_WIDTH_BIT_DEFAULT, &adc_raw)); TEST_ESP_OK(adc2_get_raw(ADC2_TEST_CHAN0, ADC_WIDTH_BIT_DEFAULT, &adc_raw));
ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_2, ADC2_TEST_CHAN0, adc_raw); ESP_LOGI(TAG, "ADC%d Channel %d raw: %d", ADC_UNIT_2 + 1, ADC2_TEST_CHAN0, adc_raw);
TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw); TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, adc_raw);
#endif #endif
} }

8
components/esp_adc/adc_continuous.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -258,10 +258,6 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already"); ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
ANALOG_CLOCK_ENABLE(); ANALOG_CLOCK_ENABLE();
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_UNIT_1);
adc_hal_calibration_init(ADC_UNIT_2);
#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
//reset ADC digital part to reset ADC sampling EOF counter //reset ADC digital part to reset ADC sampling EOF counter
ADC_BUS_CLK_ATOMIC() { ADC_BUS_CLK_ATOMIC() {
@@ -284,9 +280,11 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
if (handle->use_adc1) { if (handle->use_adc1) {
adc_hal_calibration_init(ADC_UNIT_1);
adc_set_hw_calibration_code(ADC_UNIT_1, handle->adc1_atten); adc_set_hw_calibration_code(ADC_UNIT_1, handle->adc1_atten);
} }
if (handle->use_adc2) { if (handle->use_adc2) {
adc_hal_calibration_init(ADC_UNIT_2);
adc_set_hw_calibration_code(ADC_UNIT_2, handle->adc2_atten); adc_set_hw_calibration_code(ADC_UNIT_2, handle->adc2_atten);
} }
#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED

19
components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -19,6 +19,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
@@ -83,13 +84,14 @@ void sar_periph_ctrl_pwdet_power_release(void)
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* ADC Power * ADC Power
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
static int s_saradc_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_adc_power_acquire(void) static void s_sar_adc_power_acquire(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt++; regi2c_saradc_enable();
if (s_saradc_power_on_cnt == 1) { s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) {
adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON); adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -98,14 +100,15 @@ static void s_sar_adc_power_acquire(void)
static void s_sar_adc_power_release(void) static void s_sar_adc_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt--; s_sar_power_on_cnt--;
if (s_saradc_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_saradc_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM); adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM);
} }
regi2c_saradc_disable();
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }

19
components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -19,6 +19,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
@@ -83,13 +84,14 @@ void sar_periph_ctrl_pwdet_power_release(void)
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* ADC Power * ADC Power
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
static int s_saradc_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_adc_power_acquire(void) static void s_sar_adc_power_acquire(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt++; regi2c_saradc_enable();
if (s_saradc_power_on_cnt == 1) { s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) {
adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON); adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -98,14 +100,15 @@ static void s_sar_adc_power_acquire(void)
static void s_sar_adc_power_release(void) static void s_sar_adc_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt--; s_sar_power_on_cnt--;
if (s_saradc_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_saradc_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM); adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM);
} }
regi2c_saradc_disable();
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }

4
components/esp_hw_support/port/esp32c5/pmu_init.c
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@@ -208,10 +208,6 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void) void pmu_init(void)
{ {
/* Peripheral reg i2c power up */
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
pmu_hp_system_init_default(PMU_instance()); pmu_hp_system_init_default(PMU_instance());
pmu_lp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance());

21
components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -18,6 +18,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
@@ -48,17 +49,18 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_pwdet_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
regi2c_saradc_enable();
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++; s_sar_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -67,15 +69,16 @@ static void s_sar_power_acquire(void)
static void s_sar_power_release(void) static void s_sar_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--; s_sar_power_on_cnt--;
if (s_pwdet_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_pwdet_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_disable();
modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
} }

4
components/esp_hw_support/port/esp32c6/pmu_init.c
View File

@@ -209,10 +209,6 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void) void pmu_init(void)
{ {
/* Peripheral reg i2c power up */
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);

21
components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -18,6 +18,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
@@ -49,17 +50,18 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_pwdet_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
regi2c_saradc_enable();
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++; s_sar_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -68,15 +70,16 @@ static void s_sar_power_acquire(void)
static void s_sar_power_release(void) static void s_sar_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--; s_sar_power_on_cnt--;
if (s_pwdet_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_pwdet_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_disable();
modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
} }

4
components/esp_hw_support/port/esp32c61/pmu_init.c
View File

@@ -209,10 +209,6 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void) void pmu_init(void)
{ {
/* Peripheral reg i2c power up */
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
pmu_hp_system_init_default(PMU_instance()); pmu_hp_system_init_default(PMU_instance());
pmu_lp_system_init_default(PMU_instance()); pmu_lp_system_init_default(PMU_instance());

21
components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -18,6 +18,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
@@ -48,17 +49,18 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_pwdet_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
regi2c_saradc_enable();
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++; s_sar_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -67,15 +69,16 @@ static void s_sar_power_acquire(void)
static void s_sar_power_release(void) static void s_sar_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--; s_sar_power_on_cnt--;
if (s_pwdet_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_pwdet_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_disable();
modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
} }

21
components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -17,6 +17,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
@@ -48,17 +49,18 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_pwdet_power_on_cnt; static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
regi2c_saradc_enable();
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++; s_sar_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -67,15 +69,16 @@ static void s_sar_power_acquire(void)
static void s_sar_power_release(void) static void s_sar_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--; s_sar_power_on_cnt--;
if (s_pwdet_power_on_cnt < 0) { if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock); portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort(); abort();
} else if (s_pwdet_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_disable();
modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
} }

7
components/esp_hw_support/port/esp32p4/sar_periph_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -18,6 +18,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
@@ -48,7 +49,7 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_sar_power_on_cnt; static int s_sar_power_on_cnt;
@@ -56,6 +57,7 @@ static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_enable();
s_sar_power_on_cnt++; s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
@@ -74,6 +76,7 @@ static void s_sar_power_release(void)
} else if (s_sar_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
} }
regi2c_saradc_disable();
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }

49
components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -19,6 +19,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
@@ -52,34 +53,48 @@ void sar_periph_ctrl_power_disable(void)
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* PWDET Power * PWDET Power
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
static int s_pwdet_power_on_cnt; static int s_sar_power_on_cnt;
void sar_periph_ctrl_pwdet_power_acquire(void) void s_sar_power_acquire(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++; s_sar_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
regi2c_saradc_enable();
} }
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }
void s_sar_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_sar_power_on_cnt--;
/* Sanity check */
if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort();
} else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
regi2c_saradc_disable();
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_pwdet_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_pwdet_power_release(void) void sar_periph_ctrl_pwdet_power_release(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); s_sar_power_release();
s_pwdet_power_on_cnt--;
/* Sanity check */
if (s_pwdet_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
abort();
} else if (s_pwdet_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* ADC Power * ADC Power
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/

7
components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -19,6 +19,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "hal/sar_ctrl_ll.h" #include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
@@ -51,7 +52,7 @@ void sar_periph_ctrl_power_disable(void)
/** /**
* This gets incremented when s_sar_power_acquire() is called, * This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called. * and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero. * PWDET and REG_I2C are powered down when the value reaches zero.
* Should be modified within critical section. * Should be modified within critical section.
*/ */
static int s_sar_power_on_cnt; static int s_sar_power_on_cnt;
@@ -59,6 +60,7 @@ static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void) static void s_sar_power_acquire(void)
{ {
portENTER_CRITICAL_SAFE(&rtc_spinlock); portENTER_CRITICAL_SAFE(&rtc_spinlock);
regi2c_saradc_enable();
s_sar_power_on_cnt++; s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) { if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON); sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
@@ -77,6 +79,7 @@ static void s_sar_power_release(void)
} else if (s_sar_power_on_cnt == 0) { } else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
} }
regi2c_saradc_disable();
portEXIT_CRITICAL_SAFE(&rtc_spinlock); portEXIT_CRITICAL_SAFE(&rtc_spinlock);
} }

4
components/esp_hw_support/regi2c_ctrl.c
View File

@@ -100,7 +100,7 @@ void regi2c_saradc_enable(void)
regi2c_enter_critical(); regi2c_enter_critical();
s_i2c_saradc_enable_cnt++; s_i2c_saradc_enable_cnt++;
if (s_i2c_saradc_enable_cnt == 1) { if (s_i2c_saradc_enable_cnt == 1) {
regi2c_ctrl_ll_i2c_saradc_enable(); regi2c_ctrl_ll_i2c_sar_periph_enable();
} }
regi2c_exit_critical(); regi2c_exit_critical();
} }
@@ -113,7 +113,7 @@ void regi2c_saradc_disable(void)
regi2c_exit_critical(); regi2c_exit_critical();
ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled"); ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled");
} else if (s_i2c_saradc_enable_cnt == 0) { } else if (s_i2c_saradc_enable_cnt == 0) {
regi2c_ctrl_ll_i2c_saradc_disable(); regi2c_ctrl_ll_i2c_sar_periph_disable();
} }
regi2c_exit_critical(); regi2c_exit_critical();

11
components/hal/adc_hal_common.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -91,16 +91,9 @@ void adc_hal_calibration_init(adc_unit_t adc_n)
adc_ll_calibration_init(adc_n); adc_ll_calibration_init(adc_n);
} }
static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {
[0 ... (SOC_ADC_PERIPH_NUM - 1)] = -1,
};
void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param) void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
if (param != s_previous_init_code[adc_n]) { adc_ll_set_calibration_param(adc_n, param);
adc_ll_set_calibration_param(adc_n, param);
s_previous_init_code[adc_n] = param;
}
} }
#if SOC_ADC_SELF_HW_CALI_SUPPORTED #if SOC_ADC_SELF_HW_CALI_SUPPORTED

8
components/hal/esp32/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -39,9 +39,9 @@ static inline void regi2c_ctrl_ll_i2c_apll_enable(void)
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
// Not used on ESP32, but leave a blank function here. // Not used on ESP32, but leave a blank function here.
// I2C_SARADC is only used for enabling some analog features. However, // I2C_SARADC is only used for enabling some analog features. However,
@@ -52,7 +52,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
// Not used on ESP32, but leave a blank function here. // Not used on ESP32, but leave a blank function here.
// I2C_SARADC is only used for enabling some analog features. However, // I2C_SARADC is only used for enabling some analog features. However,

8
components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -60,9 +60,9 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
@@ -71,7 +71,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);

8
components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -40,9 +40,9 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
@@ -51,7 +51,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);

44
components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
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@@ -97,52 +97,26 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
// TODO: IDF-8727 //Enter regi2c reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
//Enable REGI2C for SAR_ADC and TSENS
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
//Release regi2c reset mode, enter work mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{
// TODO: IDF-8727
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
} }
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

47
components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
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@@ -95,55 +95,26 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); //Enter regi2c reset mode
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
//Enable REGI2C for SAR_ADC and TSENS
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
//Release regi2c reset mode, enter work mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
} }
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

45
components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
View File

@@ -97,53 +97,26 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
// TODO: IDF-9322 //Enter regi2c reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
//Enable REGI2C for SAR_ADC and TSENS
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
//Release regi2c reset mode, enter work mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{
// TODO: IDF-9322
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
} }
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

26
components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
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@@ -96,35 +96,17 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PU);
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
{
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{ {
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
} }
/** /**
* @brief Disable regi2c controlled periph registers * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_periph_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
} }

15
components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -11,6 +11,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/regi2c_defs.h" #include "soc/regi2c_defs.h"
#include "soc/i2c_ana_mst_reg.h" #include "soc/i2c_ana_mst_reg.h"
#include "soc/pmu_reg.h"
//TODO: [ESP32H21] IDF-11550, inherit from h2 //TODO: [ESP32H21] IDF-11550, inherit from h2
@@ -79,21 +80,19 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PD); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PU);
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
} }
#ifdef __cplusplus #ifdef __cplusplus

14
components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h
View File

@@ -46,21 +46,21 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); // TODO: [ESP32H4] IDF-12368 IDF-12370
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); abort();
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); // TODO: [ESP32H4] IDF-12368 IDF-12370
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); abort();
} }
#ifdef __cplusplus #ifdef __cplusplus

20
components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,6 +13,7 @@
#include "soc/hp_sys_clkrst_reg.h" #include "soc/hp_sys_clkrst_reg.h"
#include "soc/lpperi_struct.h" #include "soc/lpperi_struct.h"
#include "soc/i2c_ana_mst_struct.h" #include "soc/i2c_ana_mst_struct.h"
#include "soc/pmu_reg.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -110,21 +111,24 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_mpll_calibratio
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); //Enter regi2c reset mode
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
//Enable REGI2C for SAR_ADC and TSENS
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
//Release regi2c reset mode, enter work mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} }
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
} }
#ifdef __cplusplus #ifdef __cplusplus

8
components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -39,9 +39,9 @@ static inline void regi2c_ctrl_ll_i2c_apll_enable(void)
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
@@ -50,7 +50,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); CLEAR_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
} }

8
components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -32,9 +32,9 @@ static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
} }
/** /**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
@@ -43,7 +43,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
/** /**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/ */
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{ {
CLEAR_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); CLEAR_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
} }

14
components/soc/esp32c6/include/soc/regi2c_defs.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,15 +13,3 @@
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x600AF81C
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_CONFIG2_REG 0x600AF820
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)

14
components/soc/esp32h2/include/soc/regi2c_defs.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -14,18 +14,6 @@
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24))
// I2C_MST_ANA_CONF1_REG
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
// I2C_MST_ANA_CONF2_REG
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/** /**
* Restore regi2c analog calibration related configuration registers. * Restore regi2c analog calibration related configuration registers.
* This is a workaround for calibration error when waking up from light sleep * This is a workaround for calibration error when waking up from light sleep

21
components/soc/esp32h21/include/soc/regi2c_defs.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,22 +13,3 @@
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24))
// I2C_MST_ANA_CONF1_REG
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
// I2C_MST_ANA_CONF2_REG
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround for calibration error when waking up from light sleep
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

12
components/soc/esp32h4/include/soc/regi2c_defs.h
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@@ -13,15 +13,3 @@
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x600AF81C
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_CONFIG2_REG 0x600AF820
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)

13
components/soc/esp32p4/include/soc/regi2c_defs.h
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@@ -1,19 +1,8 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#pragma once #pragma once
#include "esp_bit_defs.h" #include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x5012401C
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_CONFIG2_REG 0x50124020
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)