From 28f19cf0e6354ab33ca1d37e85e29aa7f0253cd5 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sat, 26 Aug 2023 22:08:23 +0800 Subject: [PATCH 1/3] fix(ram_app): Fixed issue ram_app can't use the SPI Flash 1st bootloader won't help to initialize the MSPI & cache properly as it usually do when loading from flash. And the ram app doesn't have valid headers. Since there is no enough space in 2nd bootloader, we replace the `bootloader_init_spi_flash` in the ram_app (!pure_ram_app), with an customized alternative of it for the ram_app. This alternative helps to initialize the MSPI & cache properly, without the help of 1st bootloader or image headers. --- .../include/bootloader_flash_config.h | 5 ++ .../esp_private/bootloader_flash_internal.h | 9 ++ .../src/bootloader_flash_config_esp32.c | 88 ++++++++++++++++++- .../src/bootloader_flash_config_esp32c2.c | 68 +++++++++++++- .../src/bootloader_flash_config_esp32c3.c | 70 ++++++++++++++- .../src/bootloader_flash_config_esp32c6.c | 66 ++++++++++++++ .../src/bootloader_flash_config_esp32h2.c | 67 ++++++++++++++ .../src/bootloader_flash_config_esp32p4.c | 65 ++++++++++++++ .../src/bootloader_flash_config_esp32s2.c | 70 ++++++++++++++- .../src/bootloader_flash_config_esp32s3.c | 79 ++++++++++++++++- .../bootloader_support/src/bootloader_init.c | 2 + .../src/esp32/bootloader_esp32.c | 8 +- .../src/esp32c2/bootloader_esp32c2.c | 6 +- .../src/esp32c3/bootloader_esp32c3.c | 6 +- .../src/esp32c6/bootloader_esp32c6.c | 6 +- .../src/esp32h2/bootloader_esp32h2.c | 6 +- .../src/esp32p4/bootloader_esp32p4.c | 6 +- .../src/esp32s2/bootloader_esp32s2.c | 6 +- .../src/esp32s3/bootloader_esp32s3.c | 6 +- components/esp_system/port/cpu_start.c | 30 +++---- 20 files changed, 615 insertions(+), 54 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h b/components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h index 6fbb6d4fc8..2709a3da30 100644 --- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h +++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h @@ -58,6 +58,7 @@ void bootloader_flash_clock_config(const esp_image_header_t* pfhdr); */ void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr); +#ifdef CONFIG_IDF_TARGET_ESP32 /** * @brief Configure SPI flash read dummy based on different mode and frequency. * @@ -66,6 +67,10 @@ void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr); * @return None */ void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr); +#else +// The meaning has changed on this chip. Deprecated, Call `bootloader_configure_spi_pins()` and `bootloader_flash_set_dummy_out()` directly. +void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr) __attribute__((deprecated)); +#endif #ifdef CONFIG_IDF_TARGET_ESP32 /** diff --git a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h index 4bff3f9dea..92c9d3988d 100644 --- a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h +++ b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h @@ -18,6 +18,15 @@ extern "C" { */ esp_err_t bootloader_init_spi_flash(void); +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +/** + * @brief Config all flash related stuff according to the header. The consistency of all flash configs is ensured. + * + * @return None + */ +void bootloader_flash_hardware_init(void); +#endif + #ifdef __cplusplus } #endif diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index 99f6421c85..140969b692 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,7 @@ #include "soc/gpio_periph.h" #include "soc/efuse_reg.h" #include "soc/spi_reg.h" +#include "soc/dport_reg.h" #include "soc/soc_caps.h" #include "soc/soc_pins.h" #include "soc/chip_revision.h" @@ -354,6 +355,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); } + static void IRAM_ATTR bootloader_init_flash_configure(void) { bootloader_flash_gpio_config(&bootloader_image_hdr); @@ -384,3 +386,87 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); + + // reset MMU + /* completely reset MMU in case serial bootloader was running */ + Cache_Read_Disable(0); +#if !CONFIG_FREERTOS_UNICORE + Cache_Read_Disable(1); +#endif + Cache_Flush(0); +#if !CONFIG_FREERTOS_UNICORE + Cache_Flush(1); +#endif + mmu_init(0); +#if !CONFIG_FREERTOS_UNICORE + /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are + necessary to work around a hardware bug. */ + DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); + mmu_init(1); + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); +#endif + + /* normal ROM boot exits with DROM0 cache unmasked, + but serial bootloader exits with it masked. */ + DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); +#if !CONFIG_FREERTOS_UNICORE + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); +#endif + + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_gpio_config(&hdr); + bootloader_flash_dummy_config(&hdr); + bootloader_flash_cs_timing_config(); + + /* Remaining parts in bootloader_init_spi_flash */ + bootloader_flash_unlock(); + update_flash_config(&hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index 85f7c16654..626b9bc1f8 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -71,6 +71,7 @@ void IRAM_ATTR bootloader_flash_set_dummy_out(void) REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); } +//deprecated void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) { bootloader_configure_spi_pins(1); @@ -220,7 +221,8 @@ static void bootloader_print_mmu_page_size(void) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); bootloader_flash_cs_timing_config(); } @@ -248,3 +250,67 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(0, false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_set_dummy_out(); + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + bootloader_print_mmu_page_size(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index fb1f2329d1..f5a3d13076 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -75,6 +75,7 @@ void IRAM_ATTR bootloader_flash_set_dummy_out(void) REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); } +//deprecated void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) { bootloader_configure_spi_pins(1); @@ -222,7 +223,8 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); bootloader_flash_cs_timing_config(); } @@ -256,3 +258,69 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_set_dummy_out(); + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 6a1e62459c..2d000ab1f5 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -219,3 +219,69 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(0, false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + // TODO: set proper dummy output + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index b4b1bb94c3..951f053502 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -221,3 +221,70 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(0, false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_clock_init(); + // TODO: set proper dummy output + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index 14887abe94..9f5eccc159 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -207,3 +207,68 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(0, false); + + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c index a1855bb4c4..33cbb44c0c 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c @@ -81,6 +81,7 @@ void IRAM_ATTR bootloader_flash_set_dummy_out(void) REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); } +//deprecated void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr) { bootloader_configure_spi_pins(1); @@ -247,7 +248,8 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); bootloader_flash_cs_timing_config(); } @@ -274,3 +276,69 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); + + // init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked. + REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_set_dummy_out(); + bootloader_flash_cs_timing_config(); + + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c index 7ab25e7fc8..730b6a1e51 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c @@ -87,6 +87,7 @@ void IRAM_ATTR bootloader_flash_set_dummy_out(void) REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); } +//deprecated void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) { bootloader_configure_spi_pins(1); @@ -254,7 +255,8 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); bootloader_flash_cs_timing_config(); } @@ -297,3 +299,78 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_wp(); return ESP_OK; } + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_set_dummy_out(); + bootloader_flash_cs_timing_config(); + +#if CONFIG_BOOTLOADER_FLASH_DC_AWARE + // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. + bootloader_spi_flash_reset(); +#endif + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH || CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH + bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode()); +#endif + + cache_hal_disable(CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); + +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index 1dd9b3958d..a68e57543b 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -23,7 +23,9 @@ static const char *TAG = "boot"; +#if !CONFIG_APP_BUILD_TYPE_RAM esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr; +#endif void bootloader_clear_bss_section(void) { diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index ddea3ee159..fd6441023b 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -39,7 +39,7 @@ static const char *TAG = "boot.esp32"; -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM static void bootloader_reset_mmu(void) { /* completely reset MMU in case serial bootloader was running */ @@ -208,7 +208,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM // reset MMU bootloader_reset_mmu(); // update flash ID @@ -218,7 +218,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -227,12 +226,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // #if !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // #if !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c index a19fa85443..3d9e1af1f4 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c +++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c @@ -120,14 +120,13 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //init mmu mmu_hal_init(); // update flash ID bootloader_flash_update_id(); -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -136,12 +135,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 0160b921f1..199ff65624 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -159,7 +159,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //init mmu @@ -171,7 +171,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -180,12 +179,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif //#if !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif //#if !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index 76fd0b90b3..d269657992 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -143,7 +143,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //init mmu @@ -155,7 +155,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -164,12 +163,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index e5b23acfe3..5cf7869c17 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -132,7 +132,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //init mmu @@ -144,7 +144,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -153,12 +152,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index 085ab34559..aa515759ec 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -136,7 +136,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //reset mmu @@ -148,7 +148,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -157,12 +156,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index cf2a27fe65..4624e29f27 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -139,7 +139,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM // init cache hal cache_hal_init(); //init mmu @@ -153,7 +153,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -162,12 +161,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index 06b4825a3a..368aa648b4 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -178,7 +178,7 @@ esp_err_t bootloader_init(void) /* print 2nd bootloader banner */ bootloader_print_banner(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_RAM //init cache hal cache_hal_init(); //init mmu @@ -190,7 +190,6 @@ esp_err_t bootloader_init(void) ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } -#if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; @@ -199,12 +198,11 @@ esp_err_t bootloader_init(void) if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } -#endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } -#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#endif // !CONFIG_APP_BUILD_TYPE_RAM // check whether a WDT reset happend bootloader_check_wdt_reset(); diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 53d9f3e67f..99d6e8b42d 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -101,6 +101,7 @@ #if CONFIG_APP_BUILD_TYPE_RAM #include "esp_rom_spiflash.h" #include "bootloader_init.h" +#include "esp_private/bootloader_flash_internal.h" #endif // CONFIG_APP_BUILD_TYPE_RAM //This dependency will be removed in the future @@ -429,14 +430,10 @@ void IRAM_ATTR call_start_cpu0(void) // When the APP is loaded into ram for execution, some hardware initialization behaviors // in the bootloader are still necessary #if CONFIG_APP_BUILD_TYPE_RAM -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP -#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE - esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); -#else - esp_rom_spiflash_attach(0, false); -#endif -#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP bootloader_init(); +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + bootloader_flash_hardware_init(); +#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #endif //#if CONFIG_APP_BUILD_TYPE_RAM #ifndef CONFIG_BOOTLOADER_WDT_ENABLE @@ -722,22 +719,19 @@ void IRAM_ATTR call_start_cpu0(void) } #endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + // External devices (including SPI0/1, cache) should be initialized + +#if !CONFIG_APP_BUILD_TYPE_RAM + // Normal startup flow. We arrive here with the help of 1st, 2nd bootloader. There are valid headers (app/bootloader) + // Read the application binary image header. This will also decrypt the header if the image is encrypted. __attribute__((unused)) esp_image_header_t fhdr = {0}; -#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO; - fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2; - fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB; - bootloader_flash_unlock(); -#else // This assumes that DROM is the first segment in the application binary, i.e. that we can read // the binary header through cache by accessing SOC_DROM_LOW address. hal_memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr)); -#endif // CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if CONFIG_IDF_TARGET_ESP32 #if !CONFIG_SPIRAM_BOOT_INIT // If psram is uninitialized, we need to improve some flash configuration. @@ -756,6 +750,10 @@ void IRAM_ATTR call_start_cpu0(void) } bootloader_flash_update_size(app_flash_size); #endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE +#else + // CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + bootloader_flash_unlock(); +#endif #endif //!CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE From cc2867468622ed7b45dd454b605b0211b39e7fcf Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sun, 27 Aug 2023 01:12:21 +0800 Subject: [PATCH 2/3] refactor(bootloader_flash): make cache enable more obvious --- .../src/bootloader_flash_config_esp32.c | 13 ++++++++++--- .../src/bootloader_flash_config_esp32c2.c | 10 ++++++---- .../src/bootloader_flash_config_esp32c3.c | 10 ++++++---- .../src/bootloader_flash_config_esp32c6.c | 10 ++++++---- .../src/bootloader_flash_config_esp32h2.c | 10 ++++++---- .../src/bootloader_flash_config_esp32p4.c | 10 ++++++---- .../src/bootloader_flash_config_esp32s2.c | 10 ++++++---- .../src/bootloader_flash_config_esp32s3.c | 10 ++++++---- 8 files changed, 52 insertions(+), 31 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index 140969b692..3c23ec5abc 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -270,13 +270,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - Cache_Read_Disable(0); // Set flash chip size esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode // TODO: set frequency - Cache_Flush(0); - Cache_Read_Enable(0); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -381,7 +378,12 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + Cache_Read_Disable(0); update_flash_config(&bootloader_image_hdr); + Cache_Flush(0); + Cache_Read_Enable(0); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -465,7 +467,12 @@ void bootloader_flash_hardware_init(void) /* Remaining parts in bootloader_init_spi_flash */ bootloader_flash_unlock(); + + Cache_Read_Disable(0); update_flash_config(&hdr); + Cache_Flush(0); + Cache_Read_Enable(0); + //ensure the flash is write-protected bootloader_enable_wp(); } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index 626b9bc1f8..cf5a56809f 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -128,10 +128,8 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -245,7 +243,11 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_print_mmu_page_size(); print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -306,9 +308,9 @@ void bootloader_flash_hardware_init(void) bootloader_print_mmu_page_size(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index f5a3d13076..7b0eecefc4 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -139,10 +139,8 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -253,7 +251,11 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -316,9 +318,9 @@ void bootloader_flash_hardware_init(void) bootloader_spi_flash_resume(); bootloader_flash_unlock(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 2d000ab1f5..2e9ed60a12 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -103,10 +103,8 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -214,7 +212,11 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -277,9 +279,9 @@ void bootloader_flash_hardware_init(void) bootloader_spi_flash_resume(); bootloader_flash_unlock(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index 951f053502..e9888da6f9 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -110,10 +110,8 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -216,7 +214,11 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -280,9 +282,9 @@ void bootloader_flash_hardware_init(void) bootloader_spi_flash_resume(); bootloader_flash_unlock(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index 9f5eccc159..89894d5edd 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -97,10 +97,8 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -202,7 +200,11 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -264,9 +266,9 @@ void bootloader_flash_hardware_init(void) bootloader_spi_flash_resume(); bootloader_flash_unlock(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c index 33cbb44c0c..40587e4960 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c @@ -153,12 +153,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) default: size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode // TODO: set frequency - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -271,7 +269,11 @@ esp_err_t bootloader_init_spi_flash(void) #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -334,9 +336,9 @@ void bootloader_flash_hardware_init(void) bootloader_flash_unlock(); - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c index 730b6a1e51..c02aad5bbf 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c @@ -160,12 +160,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) size = 2; } - cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); // Set flash chip size esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode // TODO: set frequency - cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } static void print_flash_info(const esp_image_header_t *bootloader_hdr) @@ -294,7 +292,11 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode()); #endif print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + //ensure the flash is write-protected bootloader_enable_wp(); return ESP_OK; @@ -365,9 +367,9 @@ void bootloader_flash_hardware_init(void) bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode()); #endif - cache_hal_disable(CACHE_TYPE_ALL); + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); update_flash_config(&hdr); - cache_hal_enable(CACHE_TYPE_ALL); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); //ensure the flash is write-protected bootloader_enable_wp(); From 24ef7f6034bbcc0d27625c3931433f528b218b48 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Fri, 7 Jul 2023 01:48:54 +0800 Subject: [PATCH 3/3] ci(ram_load_app): enable target tests for all targets --- tools/test_apps/.build-test-rules.yml | 6 ------ tools/test_apps/system/ram_loadable_app/README.md | 4 ++-- .../ram_loadable_app/pytest_ram_loadable_app.py | 13 ++----------- .../ram_loadable_app/sdkconfig.defaults.esp32 | 6 ------ 4 files changed, 4 insertions(+), 25 deletions(-) delete mode 100644 tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32 diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index 5cf3291d28..faef23a9e2 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -173,12 +173,6 @@ tools/test_apps/system/panic: temporary: true reason: target(s) not supported yet # TODO: IDF-7511 -tools/test_apps/system/ram_loadable_app: - disable: - - if: IDF_TARGET == "esp32h2" - temporary: true - reason: lack of runners - tools/test_apps/system/startup: disable: - if: CONFIG_NAME == "main_task_cpu1" and IDF_TARGET not in ["esp32", "esp32s3"] diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index f535057154..0283938f98 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # RAM loadable app Example diff --git a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py index 71953f16f2..22b6011a38 100644 --- a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py +++ b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py @@ -5,12 +5,7 @@ import pytest from pytest_embedded_idf.dut import IdfDut -@pytest.mark.esp32 -@pytest.mark.esp32c2 -@pytest.mark.esp32c3 -@pytest.mark.esp32c6 -@pytest.mark.esp32s2 -@pytest.mark.esp32s3 +@pytest.mark.supported_targets @pytest.mark.generic @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,) def test_pure_ram_loadable_app(dut: IdfDut) -> None: @@ -18,11 +13,7 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None: dut.expect('Time since boot: 3 seconds...', timeout=10) -@pytest.mark.esp32c2 -@pytest.mark.esp32c3 -@pytest.mark.esp32c6 -@pytest.mark.esp32s2 -@pytest.mark.esp32s3 +@pytest.mark.supported_targets @pytest.mark.generic @pytest.mark.parametrize('config', ['defaults',], indirect=True,) def test_ram_loadable_app(dut: IdfDut) -> None: diff --git a/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32 b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32 deleted file mode 100644 index d2816a3ebd..0000000000 --- a/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32 +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_APP_BUILD_TYPE_RAM=y - -# Reset is meaningless to ram_app -CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT=y - -CONFIG_APP_BUILD_TYPE_PURE_RAM_APP=y