diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 62f22784c3..8ee4c3acdf 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -44,12 +44,7 @@ void bootloader_console_init(void)
 {
     const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
 
-#if !ESP_ROM_SUPPORT_MULTIPLE_UART
-    /* esp_rom_install_channel_put is not available unless multiple UARTs are supported */
     esp_rom_install_uart_printf();
-#else
-    esp_rom_install_channel_putc(1, esp_rom_uart_putc);
-#endif
 
     // Wait for UART FIFO to be empty.
     esp_rom_uart_tx_wait_idle(0);
@@ -58,10 +53,10 @@ void bootloader_console_init(void)
     // Some constants to make the following code less upper-case
     const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
     const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
+
     // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
-#if ESP_ROM_SUPPORT_MULTIPLE_UART
     esp_rom_uart_set_as_console(uart_num);
-#endif
+
     // If console is attached to UART1 or if non-default pins are used,
     // need to reconfigure pins using GPIO matrix
     if (uart_num != 0 ||
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index ccb2469800..19388d9f0f 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -19,7 +19,7 @@ else()
                         "patches/esp_rom_uart.c"
                         "patches/esp_rom_tjpgd.c"
                         "patches/esp_rom_efuse.c")
-    list(APPEND private_required_comp soc hal)
+    list(APPEND private_required_comp soc hal efuse)
 endif()
 
 if(CONFIG_IDF_TARGET_ARCH_XTENSA)
diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h
index 1d19be8571..959075b29c 100644
--- a/components/esp_rom/esp32/esp_rom_caps.h
+++ b/components/esp_rom/esp32/esp_rom_caps.h
@@ -9,5 +9,4 @@
 #define ESP_ROM_HAS_CRC_LE              (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_HAS_CRC_BE              (1) // ROM CRC library supports Big Endian
 #define ESP_ROM_HAS_JPEG_DECODE         (1) // ROM has JPEG decode library
-#define ESP_ROM_SUPPORT_MULTIPLE_UART   (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h
index 977d73fc90..034a5c19d9 100644
--- a/components/esp_rom/esp32c3/esp_rom_caps.h
+++ b/components/esp_rom/esp32c3/esp_rom_caps.h
@@ -22,3 +22,4 @@
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
+#define ESP_ROM_HAS_ETS_PRINTF_BUG          (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h
index 7a210f1a53..5d1c583d35 100644
--- a/components/esp_rom/esp32h2/esp_rom_caps.h
+++ b/components/esp_rom/esp32h2/esp_rom_caps.h
@@ -21,3 +21,4 @@
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
+#define ESP_ROM_HAS_ETS_PRINTF_BUG          (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h
index 1078ff8997..1032eef93a 100644
--- a/components/esp_rom/esp32s2/esp_rom_caps.h
+++ b/components/esp_rom/esp32s2/esp_rom_caps.h
@@ -7,5 +7,4 @@
 #pragma once
 
 #define ESP_ROM_HAS_CRC_LE            (1) // ROM CRC library supports Little Endian
-#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h
index 65847c4064..2b2c337079 100644
--- a/components/esp_rom/esp32s3/esp_rom_caps.h
+++ b/components/esp_rom/esp32s3/esp_rom_caps.h
@@ -17,9 +17,9 @@
 #define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
 #define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-#define ESP_ROM_SUPPORT_MULTIPLE_UART       (1) // ROM has multiple UARTs available for logging
 #define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
+#define ESP_ROM_HAS_ETS_PRINTF_BUG          (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c
index 4b87d2d081..30b5d8c34a 100644
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@@ -16,7 +16,7 @@
 #include <stdbool.h>
 #include "esp_attr.h"
 
-#include "sdkconfig.h"
+#include "esp_rom_caps.h"
 
 IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
 {
@@ -34,14 +34,16 @@ IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
     }
 }
 
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#if ESP_ROM_HAS_ETS_PRINTF_BUG
 IRAM_ATTR void esp_rom_install_uart_printf(void)
 {
     extern void ets_install_uart_printf(void);
     extern bool g_uart_print;
+    extern bool g_usb_print;
     // If ROM log is disabled permanently via eFuse or temporarily via RTC storage register,
     // this ROM symbol will be set to false, and cause ``esp_rom_printf`` can't work on esp-idf side.
     g_uart_print = true;
+    g_usb_print = true;
     ets_install_uart_printf();
 }
 #endif
diff --git a/components/esp_rom/patches/esp_rom_uart.c b/components/esp_rom/patches/esp_rom_uart.c
index 78fa08ec1a..f7567b1abe 100644
--- a/components/esp_rom/patches/esp_rom_uart.c
+++ b/components/esp_rom/patches/esp_rom_uart.c
@@ -15,6 +15,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include "esp_attr.h"
+#include "esp_efuse.h"
 #include "sdkconfig.h"
 #include "hal/uart_ll.h"
 
@@ -33,3 +34,25 @@ IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_h
     (void)clock_hz;
     uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate);
 }
+
+#if CONFIG_IDF_TARGET_ESP32C3
+/**
+ * The ESP32-C3 ROM has released two versions, one is the ECO3 version,
+ * and the other is the version before ECO3 (include ECO0 ECO1 ECO2).
+ * These two versions of the ROM code do not list uart_tx_switch wrap
+ * function in the ROM interface, so here use the uart_tx_switch direct
+ * address instead.
+ */
+IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no)
+{
+    typedef void (*rom_func_t)(uint8_t);
+    rom_func_t uart_tx_switch = NULL;
+
+    if (esp_efuse_get_chip_ver() < 3) {
+        uart_tx_switch = (rom_func_t)0x4004b8ca;
+    } else {
+        uart_tx_switch = (rom_func_t)0x4004c166;
+    }
+    uart_tx_switch(uart_no);
+}
+#endif