forked from espressif/esp-idf
fix(esp32c5): fixed the lack of crosscore ll on c5
This commit is contained in:
@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -145,6 +145,12 @@ extern "C" {
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#define PMU_SLEEP_PD_RC32K BIT(13)
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#define PMU_SLEEP_PD_RC32K BIT(13)
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#define PMU_SLEEP_PD_LP_PERIPH BIT(14)
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#define PMU_SLEEP_PD_LP_PERIPH BIT(14)
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/**
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* This macro only used for detecting whether the enums are declared
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* So that to avoid use the enum when PMU is not supported
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*/
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#define ESP_PMU_ENUMS_DECLARED
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typedef struct {
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typedef struct {
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pmu_hal_context_t *hal;
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pmu_hal_context_t *hal;
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void *mc;
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void *mc;
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@@ -6,6 +6,12 @@ set(srcs "rtc_clk_init.c"
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"chip_info.c"
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"chip_info.c"
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)
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)
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# TODO: [ESP32C5] IDF-8667
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if(IDF_TARGET STREQUAL "esp32c5")
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list(REMOVE_ITEM srcs "pmu_init.c"
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"pmu_param.c")
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endif()
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if(NOT BOOTLOADER_BUILD)
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if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "sar_periph_ctrl.c"
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list(APPEND srcs "sar_periph_ctrl.c"
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"esp_crypto_lock.c")
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"esp_crypto_lock.c")
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@@ -10,10 +10,8 @@
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#include <stdlib.h>
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#include <stdlib.h>
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#include <esp_types.h>
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#include <esp_types.h>
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#include "soc/soc_caps.h"
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#include "soc/soc_caps.h"
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#if SOC_PMU_SUPPORTED
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#include "soc/pmu_struct.h"
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#include "soc/pmu_struct.h"
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#include "hal/pmu_hal.h"
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#include "hal/pmu_hal.h"
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#endif
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// TODO: [ESP32C5] IDF-8643
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// TODO: [ESP32C5] IDF-8643
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@@ -25,8 +23,6 @@ extern "C" {
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#define HP_CALI_DBIAS 25
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#define HP_CALI_DBIAS 25
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#define LP_CALI_DBIAS 26
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#define LP_CALI_DBIAS 26
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#if SOC_PMU_SUPPORTED
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// FOR XTAL FORCE PU IN SLEEP
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// FOR XTAL FORCE PU IN SLEEP
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#define PMU_PD_CUR_SLEEP_ON 0
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#define PMU_PD_CUR_SLEEP_ON 0
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#define PMU_BIASSLP_SLEEP_ON 0
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#define PMU_BIASSLP_SLEEP_ON 0
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@@ -474,8 +470,6 @@ typedef struct pmu_sleep_machine_constant {
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} \
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} \
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}
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}
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#endif // SOC_PMU_SUPPORTED
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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@@ -23,7 +23,6 @@
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#include "hal/clk_tree_ll.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#include "soc/pmu_reg.h"
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#include "pmu_param.h"
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#include "pmu_param.h"
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static const char *TAG = "rtc_clk_init";
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static const char *TAG = "rtc_clk_init";
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@@ -42,6 +41,10 @@ static const char *TAG = "rtc_clk_init";
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*/
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*/
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static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
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static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
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{
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{
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// If PMU has not supported yet, the enum has not declared, use macro instead
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#ifndef ESP_PMU_ENUMS_DECLARED
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#define PMU_HP_ICG_MODEM_CODE_ACTIVE 2
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#endif
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/* Configure modem ICG code in PMU_ACTIVE state */
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/* Configure modem ICG code in PMU_ACTIVE state */
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pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
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pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
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@@ -53,6 +56,9 @@ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
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/* Software trigger force update modem ICG code and ICG switch */
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/* Software trigger force update modem ICG code and ICG switch */
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pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
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pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
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pmu_ll_imm_update_dig_icg_switch(&PMU, true);
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pmu_ll_imm_update_dig_icg_switch(&PMU, true);
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#ifndef ESP_PMU_ENUMS_DECLARED
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#undef PMU_HP_ICG_MODEM_CODE_ACTIVE
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#endif
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}
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}
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@@ -57,8 +57,8 @@ void esp_cache_err_int_init(void)
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* Set the type and priority to cache error interrupts. */
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/* Set the type and priority to cache error interrupts. */
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esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
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esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
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esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* On the hardware side, start by clearing all the bits reponsible for cache access error */
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/* On the hardware side, start by clearing all the bits reponsible for cache access error */
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52
components/hal/esp32c5/include/hal/crosscore_int_ll.h
Normal file
52
components/hal/esp32c5/include/hal/crosscore_int_ll.h
Normal file
@@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/intpri_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -31,10 +31,6 @@ config SOC_FLASH_ENC_SUPPORTED
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bool
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bool
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default y
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default y
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config SOC_PMU_SUPPORTED
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bool
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default y
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config SOC_SPI_FLASH_SUPPORTED
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config SOC_SPI_FLASH_SUPPORTED
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bool
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bool
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default y
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default y
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@@ -56,7 +56,7 @@
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// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
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// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
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// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
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// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
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// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
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// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
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#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
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// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
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// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
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// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
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// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
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// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
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// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
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// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
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