fix(esp32c5): fixed the lack of crosscore ll on c5

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -145,6 +145,12 @@ extern "C" {
 #define PMU_SLEEP_PD_RC32K          BIT(13)
 #define PMU_SLEEP_PD_LP_PERIPH      BIT(14)
 
+/**
+ * This macro only used for detecting whether the enums are declared
+ * So that to avoid use the enum when PMU is not supported
+ */
+#define ESP_PMU_ENUMS_DECLARED
+
 typedef struct {
     pmu_hal_context_t *hal;
     void *mc;

components/esp_hw_support/port/esp32c5/CMakeLists.txt

@@ -6,6 +6,12 @@ set(srcs "rtc_clk_init.c"
          "chip_info.c"
          )
 
+# TODO: [ESP32C5] IDF-8667
+if(IDF_TARGET STREQUAL "esp32c5")
+    list(REMOVE_ITEM srcs "pmu_init.c"
+                          "pmu_param.c")
+endif()
+
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "sar_periph_ctrl.c"
                      "esp_crypto_lock.c")

components/esp_hw_support/port/esp32c5/private_include/pmu_param.h

@@ -10,10 +10,8 @@
 #include <stdlib.h>
 #include <esp_types.h>
 #include "soc/soc_caps.h"
-#if SOC_PMU_SUPPORTED
 #include "soc/pmu_struct.h"
 #include "hal/pmu_hal.h"
-#endif
 
 // TODO: [ESP32C5] IDF-8643
 
@@ -25,8 +23,6 @@ extern "C" {
 #define HP_CALI_DBIAS   25
 #define LP_CALI_DBIAS   26
 
-#if SOC_PMU_SUPPORTED
-
 // FOR  XTAL FORCE PU IN SLEEP
 #define PMU_PD_CUR_SLEEP_ON    0
 #define PMU_BIASSLP_SLEEP_ON   0
@@ -474,8 +470,6 @@ typedef struct pmu_sleep_machine_constant {
     }                                           \
 }
 
-#endif  // SOC_PMU_SUPPORTED
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32c5/rtc_clk_init.c

@@ -23,7 +23,6 @@
 #include "hal/clk_tree_ll.h"
 #include "hal/modem_syscon_ll.h"
 #include "hal/modem_lpcon_ll.h"
-#include "soc/pmu_reg.h"
 #include "pmu_param.h"
 
 static const char *TAG = "rtc_clk_init";
@@ -42,6 +41,10 @@ static const char *TAG = "rtc_clk_init";
  */
 static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
 {
+// If PMU has not supported yet, the enum has not declared, use macro instead
+#ifndef ESP_PMU_ENUMS_DECLARED
+#define PMU_HP_ICG_MODEM_CODE_ACTIVE 2
+#endif
     /* Configure modem ICG code in PMU_ACTIVE state */
     pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
 
@@ -53,6 +56,9 @@ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
     /* Software trigger force update modem ICG code and ICG switch */
     pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
     pmu_ll_imm_update_dig_icg_switch(&PMU, true);
+#ifndef ESP_PMU_ENUMS_DECLARED
+#undef PMU_HP_ICG_MODEM_CODE_ACTIVE
+#endif
 }
 
 

components/esp_system/port/soc/esp32c5/cache_err_int.c

@@ -57,8 +57,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/hal/esp32c5/include/hal/crosscore_int_ll.h

@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp_attr.h"
+#include "soc/intpri_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Clear the crosscore interrupt that just occurred on the current core
+ */
+FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
+{
+    WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
+}
+
+
+/**
+ * @brief Trigger a crosscore interrupt on the given core
+ *
+ * @param core_id Core to trigger an interrupt on. Ignored on single core targets.
+ */
+FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
+{
+    WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
+}
+
+
+/**
+ * @brief Get the state of the crosscore interrupt register for the given core
+ *
+ * @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
+ *
+ * @return Non zero value if a software interrupt is pending on the given core,
+ *         0 if no software interrupt is pending.
+ */
+FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
+{
+    return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -31,10 +31,6 @@ config SOC_FLASH_ENC_SUPPORTED
     bool
     default y
 
-config SOC_PMU_SUPPORTED
-    bool
-    default y
-
 config SOC_SPI_FLASH_SUPPORTED
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -56,7 +56,7 @@
 // #define SOC_SECURE_BOOT_SUPPORTED       1  // TODO: [ESP32C5] IDF-8623
 // #define SOC_BOD_SUPPORTED               1  // TODO: [ESP32C5] IDF-8647
 // #define SOC_APM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8614
-#define SOC_PMU_SUPPORTED               1     // TODO: [ESP32C5] IDF-8667
+// #define SOC_PMU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8667
 // #define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638, IDF-8640
 // #define SOC_LP_TIMER_SUPPORTED          1  // TODO: [ESP32C5] IDF-8636
 // #define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638, IDF-8640