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apm: updated APM HAL/LL APIs.

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This commit is contained in:
Sachin Billore
2023-09-28 16:31:06 +05:30
parent c28bb81b28
commit c106f5caf6
8 changed files with 704 additions and 240 deletions
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15
components/bootloader_support/src/bootloader_mem.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,15 +12,14 @@
#include "bootloader_mem.h" #include "bootloader_mem.h"
#include "esp_cpu.h" #include "esp_cpu.h"
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 #if SOC_APM_SUPPORTED
#include "soc/hp_apm_reg.h" #include "hal/apm_hal.h"
#include "soc/lp_apm_reg.h"
#include "soc/lp_apm0_reg.h"
#endif #endif
void bootloader_init_mem(void) void bootloader_init_mem(void)
{ {
#if SOC_APM_SUPPORTED
#if !defined(BOOTLOADER_BUILD) && defined(SOC_APM_SUPPORTED)
/* By default, these access path filters are enable and allow the /* By default, these access path filters are enable and allow the
* access to masters only if they are in TEE mode. Since all masters * access to masters only if they are in TEE mode. Since all masters
* except HP CPU boots in REE mode, default setting of these filters * except HP CPU boots in REE mode, default setting of these filters
@@ -28,9 +27,7 @@ void bootloader_init_mem(void)
* So, at boot disabling these filters. They will enable as per the * So, at boot disabling these filters. They will enable as per the
* use case by TEE initialization code. * use case by TEE initialization code.
*/ */
REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); apm_hal_apm_ctrl_filter_enable_all(false);
REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
#endif #endif
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE

107
components/hal/apm_hal.c
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@@ -7,10 +7,11 @@
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/apm_hal.h" #include "hal/apm_hal.h"
#include "hal/apm_ll.h" #include "hal/apm_ll.h"
#include "hal/log.h"
void apm_tee_hal_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode) void apm_tee_hal_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode)
{ {
apm_tee_ll_set_master_secure_mode(master_id, sec_mode); apm_tee_ll_set_master_secure_mode(apm_ctrl, master_id, sec_mode);
} }
void apm_tee_hal_clk_gating_enable(bool enable) void apm_tee_hal_clk_gating_enable(bool enable)
@@ -18,63 +19,113 @@ void apm_tee_hal_clk_gating_enable(bool enable)
apm_tee_ll_clk_gating_enable(enable); apm_tee_ll_clk_gating_enable(enable);
} }
void apm_hp_hal_region_filter_enable(uint32_t regn_num, bool enable) void apm_hal_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, uint32_t regn_num, bool enable)
{ {
apm_hp_ll_region_filter_enable(regn_num, enable); apm_ll_apm_ctrl_region_filter_enable(apm_ctrl, regn_num, enable);
} }
void apm_hp_hal_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) void apm_hal_apm_ctrl_filter_enable(apm_ctrl_path_t *apm_path, bool enable)
{ {
apm_hp_ll_m_filter_enable(hp_m_path, enable); apm_ll_apm_ctrl_filter_enable(apm_path->apm_ctrl, apm_path->apm_m_path, enable);
} }
void apm_hp_hal_region_config(const apm_hp_hal_region_config_data_t *pms_data) void apm_hal_apm_ctrl_filter_enable_all(bool enable)
{ {
HAL_ASSERT((!pms_data) || (pms_data->regn_num > APM_LL_HP_MAX_REGION_NUM)); apm_ctrl_path_t apm_path;
apm_hp_ll_set_region_start_address(pms_data->regn_num, pms_data->regn_start_addr); for (int i = 0; i < HP_APM_MAX_ACCESS_PATH; i++) {
apm_hp_ll_set_region_end_address(pms_data->regn_num, pms_data->regn_end_addr); apm_path.apm_ctrl = HP_APM_CTRL;
apm_hp_ll_sec_mode_region_attr_config(pms_data->regn_num, pms_data->sec_mode, pms_data->regn_pms); apm_path.apm_m_path = i;
apm_hal_apm_ctrl_filter_enable(&apm_path, enable);
}
for (int i = 0; i < LP_APM_MAX_ACCESS_PATH; i++) {
apm_path.apm_ctrl = LP_APM_CTRL;
apm_path.apm_m_path = i;
apm_hal_apm_ctrl_filter_enable(&apm_path, enable);
}
#if CONFIG_IDF_TARGET_ESP32C6
for (int i = 0; i < LP_APM0_MAX_ACCESS_PATH; i++) {
apm_path.apm_ctrl = LP_APM0_CTRL;
apm_path.apm_m_path = i;
apm_hal_apm_ctrl_filter_enable(&apm_path, enable);
}
#endif
} }
uint8_t apm_hp_hal_m_exception_status(apm_ll_hp_access_path_t hp_m_path) void apm_hal_apm_ctrl_region_config(const apm_ctrl_region_config_data_t *pms_data)
{ {
return apm_hp_ll_m_exception_status(hp_m_path); HAL_ASSERT(pms_data);
apm_ll_apm_ctrl_set_region_start_address(pms_data->apm_ctrl, pms_data->regn_num, pms_data->regn_start_addr);
apm_ll_apm_ctrl_set_region_end_address(pms_data->apm_ctrl, pms_data->regn_num, pms_data->regn_end_addr);
apm_ll_apm_ctrl_sec_mode_region_attr_config(pms_data->apm_ctrl, pms_data->regn_num, pms_data->sec_mode, pms_data->regn_pms);
} }
void apm_hp_hal_m_exception_clear(apm_ll_hp_access_path_t hp_m_path) uint8_t apm_hal_apm_ctrl_exception_status(apm_ctrl_path_t *apm_path)
{ {
apm_hp_ll_m_exception_clear(hp_m_path); return apm_ll_apm_ctrl_exception_status(apm_path->apm_ctrl, apm_path->apm_m_path);
} }
void apm_hp_hal_get_m_exception_info(apm_hp_m_exception_info_t *excp_info) void apm_hal_apm_ctrl_exception_clear(apm_ctrl_path_t *apm_path)
{ {
apm_hp_ll_get_m_exception_info(excp_info); apm_ll_apm_ctrl_exception_clear(apm_path->apm_ctrl, apm_path->apm_m_path);
} }
void apm_hp_hal_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) void apm_hal_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
{ {
apm_hp_ll_m_interrupt_enable(hp_m_path, enable); apm_ll_apm_ctrl_get_exception_info(excp_info);
} }
void apm_hp_hal_clk_gating_enable(bool enable) void apm_hal_apm_ctrl_interrupt_enable(apm_ctrl_path_t *apm_path, bool enable)
{ {
apm_hp_ll_clk_gating_enable(enable); apm_ll_apm_ctrl_interrupt_enable(apm_path->apm_ctrl, apm_path->apm_m_path, enable);
} }
/* TBD: IDF-6759 */ void apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
void apm_hp_hal_master_sec_mode_config(apm_hp_secure_mode_config_t *sec_mode_data)
{ {
apm_ll_apm_ctrl_clk_gating_enable(apm_ctrl, enable);
}
void apm_hal_apm_ctrl_master_sec_mode_config(apm_ctrl_secure_mode_config_t *sec_mode_data)
{
apm_ctrl_path_t apm_path;
/* Configure given secure mode for all specified Masters. */
for (int i = 0; i < APM_LL_MASTER_MAX; i++) { for (int i = 0; i < APM_LL_MASTER_MAX; i++) {
if (sec_mode_data->master_ids & (1 << i)) { if (sec_mode_data->master_ids & (1 << i)) {
apm_tee_hal_set_master_secure_mode(i, sec_mode_data->sec_mode); apm_tee_hal_set_master_secure_mode(sec_mode_data->apm_ctrl, i, sec_mode_data->sec_mode);
} }
} }
sec_mode_data->pms_data->sec_mode = sec_mode_data->sec_mode;
apm_hp_hal_region_config(sec_mode_data->pms_data); /* Configure the given APM Ctrl for all Masters for the:
* - Secure mode,
* - Regions range,
* - access permissions and
* - region filter
*/
for (int i = 0; i < sec_mode_data->regn_count; i++) {
sec_mode_data->pms_data[i].sec_mode = sec_mode_data->sec_mode;
sec_mode_data->pms_data[i].apm_ctrl = sec_mode_data->apm_ctrl;
apm_hal_apm_ctrl_region_config(&sec_mode_data->pms_data[i]);
apm_hal_apm_ctrl_region_filter_enable(sec_mode_data->pms_data[i].apm_ctrl, i,
sec_mode_data->pms_data[i].filter_enable);
}
/* Configure APM Ctrl access path(M[0:n]) */
for (int i = 0; i < sec_mode_data->apm_m_cnt; i++) {
apm_path.apm_ctrl = sec_mode_data->apm_ctrl;
apm_path.apm_m_path = i;
apm_hal_apm_ctrl_filter_enable(&apm_path, 1);
}
} }
void apm_hp_hal_reset_event_enable(bool enable) void apm_hal_apm_ctrl_reset_event_enable(bool enable)
{ {
apm_hp_ll_reset_event_enable(enable); apm_ll_apm_ctrl_reset_event_enable(enable);
}
esp_err_t apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path)
{
return apm_ll_apm_ctrl_get_int_src_num(apm_path->apm_ctrl, apm_path->apm_m_path);
} }

357
components/hal/esp32c6/include/hal/apm_ll.h
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@@ -7,30 +7,130 @@
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "esp_err.h"
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "soc/tee_reg.h" #include "soc/tee_reg.h"
#include "soc/lp_tee_reg.h"
#include "soc/lp_apm0_reg.h"
#include "soc/hp_apm_reg.h" #include "soc/hp_apm_reg.h"
#include "soc/hp_apm_struct.h" #include "soc/lp_apm_reg.h"
#include "soc/interrupts.h"
#include "hal/assert.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) #define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU
#define APM_LL_REGION_ADDR_START_REG(regn_num) (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_ID_S 18
#define APM_LL_REGION_ADDR_END_REG(regn_num) (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU
#define APM_LL_REGION_ADDR_ATTR_REG(regn_num) (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U
#define APM_LL_TEE_EXCP_STATUS_REG(sec_mode) (HP_APM_M0_STATUS_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_MODE_S 16
#define APM_LL_TEE_EXCP_CLR_REG(sec_mode) (HP_APM_M0_STATUS_CLR_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U
#define APM_LL_TEE_EXCP_INFO0_REG(sec_mode) (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU
#define APM_LL_CTRL_EXCEPTION_REGION_S 0
#define APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) #define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU
#define APM_LL_HP_SEC_MODE_REGION_ATTR_V 0x00000003U
#define APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_HP_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
#define APM_LL_HP_MAX_REGION_NUM 15 #define APM_LL_HP_MAX_REGION_NUM 15
#define APM_LL_LP_MAX_REGION_NUM 3
#define APM_LL_MASTER_MAX 32 #define APM_LL_MASTER_MAX 32
#define LP_APM0_MAX_ACCESS_PATH 0x1
#define HP_APM_MAX_ACCESS_PATH 0x4
#define LP_APM_MAX_ACCESS_PATH 0x2
#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION_FILTER_EN_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION_FILTER_EN_REG) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : 0)); \
})
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : 0)); \
})
#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : 0)); \
})
#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : 0)); \
})
#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0)); \
})
#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0))
#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : 0)); \
})
#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : 0)); \
})
#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0)); \
})
#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : 0)); \
})
#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U
#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_INT_EN_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_INT_EN_REG) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) : 0)); \
})
#define APM_CTRL_CLK_EN (BIT(0))
#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_CLOCK_GATE_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_CLOCK_GATE_REG) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : 0)); \
})
#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \
({\
(LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_FUNC_CTRL_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_FUNC_CTRL_REG) : \
((LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : 0)); \
})
/** /**
* @brief APM Master ID * @brief APM Master ID
*/ */
@@ -52,46 +152,70 @@ typedef enum {
APM_LL_MASTER_GDMA_PARLIO = 25, APM_LL_MASTER_GDMA_PARLIO = 25,
} apm_ll_master_id_t; } apm_ll_master_id_t;
/**
* @brief APM Controller
*/
typedef enum {
LP_APM0_CTRL = 0,
HP_APM_CTRL = 1,
LP_APM_CTRL = 2,
} apm_ll_apm_ctrl_t;
/** /**
* @brief APM Secure Mode * @brief APM Secure Mode
*/ */
typedef enum { typedef enum {
APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */
APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */
APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */
APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */
} apm_ll_secure_mode_t; } apm_ll_secure_mode_t;
/** /**
* @brief APM HP access path * @brief APM Ctrl access path
*/ */
typedef enum { typedef enum {
APM_LL_HP_ACCESS_PATH_M0 = 0x0, APM_CTRL_ACCESS_PATH_M0 = 0x0,
APM_LL_HP_ACCESS_PATH_M1 = 0x1, APM_CTRL_ACCESS_PATH_M1 = 0x1,
APM_LL_HP_ACCESS_PATH_M2 = 0x2, APM_CTRL_ACCESS_PATH_M2 = 0x2,
APM_LL_HP_ACCESS_PATH_M3 = 0x3, APM_CTRL_ACCESS_PATH_M3 = 0x3,
} apm_ll_hp_access_path_t; } apm_ll_ctrl_access_path_t;
/**
* @brief APM Ctrl path.
*/
typedef struct {
apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */
apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */
} apm_ctrl_path_t;
/** /**
* @brief APM exception information * @brief APM exception information
*/ */
typedef struct { typedef struct {
uint8_t excp_id; apm_ctrl_path_t apm_path;
apm_ll_secure_mode_t sec_mode;
uint8_t excp_regn; uint8_t excp_regn;
uint8_t excp_mode; uint8_t excp_mode;
uint8_t excp_id;
uint8_t excp_type;
uint32_t excp_addr; uint32_t excp_addr;
} apm_hp_m_exception_info_t; } apm_ctrl_exception_info_t;
/** /**
* @brief Set secure mode * @brief Set secure mode
* *
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param master_id APM master ID * @param master_id APM master ID
* @param mode Secure mode * @param sec_mode Secure mode
*/ */
static inline void apm_tee_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode) static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
apm_ll_secure_mode_t sec_mode)
{ {
if (apm_ctrl == HP_APM_CTRL) {
REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
} else if ((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) {
REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, sec_mode);
}
} }
/** /**
@@ -109,133 +233,192 @@ static inline void apm_tee_ll_clk_gating_enable(bool enable)
} }
/** /**
* @brief enable/disable HP Region access permission filter * @brief enable/disable APM Ctrl Region access permission filter
* *
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param regn_num Memory Region number * @param regn_num Memory Region number
* @param enable Flag for Region access filter enable/disable * @param enable Flag for Region access filter enable/disable
*/ */
static inline void apm_hp_ll_region_filter_enable(uint32_t regn_num, bool enable) static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
} else { } else {
REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
} }
} }
/** /**
* @brief enable/disable HP access path(M[0:3]) * @brief enable/disable APM Ctrl access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param enable Flag for HP M path filter enable/disable * @param apm_m_path APM Ctrl access path
* @param enable Flag for LP APM0 M path filter enable/disable
*/ */
static inline void apm_hp_ll_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path, bool enable)
{ {
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
} else { } else {
REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
} }
} }
/** /**
* @brief HP Region start address configuration * @brief APM Ctrl Region start address configuration
* *
* @param regn_num HP Region number to be configured * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param regn_num Region number to be configured
* @param addr Region start address * @param addr Region start address
*/ */
static inline void apm_hp_ll_set_region_start_address(uint32_t regn_num, uint32_t addr) static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, uint32_t addr)
{ {
REG_WRITE(APM_LL_REGION_ADDR_START_REG(regn_num), addr); HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr);
} }
/** /**
* @brief HP Region end address configuration * @brief APM Ctrl Region end address configuration
* *
* @param regn_num HP Region number to be configured * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param regn_num Region number to be configured
* @param addr Region end address * @param addr Region end address
*/ */
static inline void apm_hp_ll_set_region_end_address(uint32_t regn_num, uint32_t addr) static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, uint32_t addr)
{ {
REG_WRITE(APM_LL_REGION_ADDR_END_REG(regn_num), addr); HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr);
} }
/** /**
* @brief HP Region pms attributes configuration * @brief HP Region pms attributes configuration
* *
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param regn_num Region number to be configured * @param regn_num Region number to be configured
* @param sec_mode Secure mode of the Master * @param sec_mode Secure mode of the Master
* @param regn_pms XWR permissions for the given secure mode and Region number * @param regn_pms XWR permissions for the given secure mode and Region number
*/ */
static inline void apm_hp_ll_sec_mode_region_attr_config(uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
{ {
HAL_ASSERT((((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
uint32_t val = 0; uint32_t val = 0;
val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(regn_num)); val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num));
val &= ~APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode); val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode);
val |= APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(regn_num), val); REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val);
} }
/** /**
* @brief Get HP access path(M[0:3]) exception status * @brief Get APM Ctrl access path(M[0:n]) exception status
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param apm_m_path APM Ctrl access path
*/ */
static inline uint8_t apm_hp_ll_m_exception_status(apm_ll_hp_access_path_t hp_m_path) static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path)
{ {
return REG_READ(APM_LL_TEE_EXCP_STATUS_REG(hp_m_path)); HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path));
} }
/** /**
* @brief Clear HP access path(M[0:3]) exception * @brief Clear APM Ctrl access path(M[0:n]) exception
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param amp_m_path APM Ctrl access path
*/ */
static inline void apm_hp_ll_m_exception_clear(apm_ll_hp_access_path_t hp_m_path) static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path)
{ {
REG_SET_BIT(APM_LL_TEE_EXCP_CLR_REG(hp_m_path), HP_APM_M0_REGION_STATUS_CLR); HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path),
APM_CTRL_M_REGION_STATUS_CLR);
} }
/** /**
* @brief Get HP access path(M[0:3]) exception information * @brief Get APM Ctrl access path(M[0:n]) exception information
* *
* @param excp_info Exception related information like addr, * @param excp_info Exception related information like addr,
* region, sec_mode and master id * region, apm_ctrl, apm_m_path, sec_mode and master id
*/ */
static inline void apm_hp_ll_get_m_exception_info(apm_hp_m_exception_info_t *excp_info) static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
{ {
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_ID); HAL_ASSERT(((excp_info->apm_path.apm_ctrl == LP_APM0_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_MODE); ((excp_info->apm_path.apm_ctrl == HP_APM_CTRL) && (excp_info->apm_path.apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_REGION); ((excp_info->apm_path.apm_ctrl == LP_APM_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM_MAX_ACCESS_PATH))
excp_info->excp_addr = REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG); );
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_ID);
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_MODE);
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_REGION);
excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path);
excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path));
} }
/** /**
* @brief Interrupt enable for access path(M[0:3]) * @brief Interrupt enable for APM Ctrl at access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param apm_m_path APM Ctrl access patch(M[0:n])
* @param enable Flag for access path interrupt enable/disable * @param enable Flag for access path interrupt enable/disable
*/ */
static inline void apm_hp_ll_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path, bool enable)
{ {
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
} else { } else {
REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
} }
} }
/** /**
* @brief HP clock auto gating enable * @brief APM Ctrl clock auto gating enable
* *
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param enable Flag for HP clock auto gating enable/disable * @param enable Flag for HP clock auto gating enable/disable
*/ */
static inline void apm_hp_ll_clk_gating_enable(bool enable) static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
} else { } else {
REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
} }
} }
@@ -249,7 +432,7 @@ static inline void apm_hp_ll_clk_gating_enable(bool enable)
* *
* @param enable Flag for event bypass enable/disable * @param enable Flag for event bypass enable/disable
*/ */
static inline void apm_hp_ll_reset_event_enable(bool enable) static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
@@ -257,6 +440,32 @@ static inline void apm_hp_ll_reset_event_enable(bool enable)
REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
} }
} }
/**
* @brief Return APM Ctrl interrupt source number.
*
* @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM)
* @param apm_m_path APM Ctrl access patch(M[0:n])
*/
static inline esp_err_t apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path)
{
HAL_ASSERT(((apm_ctrl == LP_APM0_CTRL) && (apm_m_path < LP_APM0_MAX_ACCESS_PATH)) ||
((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
switch (apm_ctrl) {
case LP_APM0_CTRL :
return (ETS_LP_APM0_INTR_SOURCE);
case HP_APM_CTRL :
return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path);
case LP_APM_CTRL :
return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path);
}
return -1;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

331
components/hal/esp32h2/include/hal/apm_ll.h
View File

@@ -7,30 +7,116 @@
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "esp_err.h"
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "soc/tee_reg.h" #include "soc/tee_reg.h"
#include "soc/lp_apm0_reg.h"
#include "soc/hp_apm_reg.h" #include "soc/hp_apm_reg.h"
#include "soc/hp_apm_struct.h" #include "soc/lp_apm_reg.h"
#include "soc/interrupts.h"
#include "hal/assert.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) #define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU
#define APM_LL_REGION_ADDR_START_REG(regn_num) (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_ID_S 18
#define APM_LL_REGION_ADDR_END_REG(regn_num) (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU
#define APM_LL_REGION_ADDR_ATTR_REG(regn_num) (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) #define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U
#define APM_LL_TEE_EXCP_STATUS_REG(sec_mode) (HP_APM_M0_STATUS_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_MODE_S 16
#define APM_LL_TEE_EXCP_CLR_REG(sec_mode) (HP_APM_M0_STATUS_CLR_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U
#define APM_LL_TEE_EXCP_INFO0_REG(sec_mode) (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (sec_mode)) #define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU
#define APM_LL_CTRL_EXCEPTION_REGION_S 0
#define APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) #define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU
#define APM_LL_HP_SEC_MODE_REGION_ATTR_V 0x00000003U
#define APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_HP_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
#define APM_LL_HP_MAX_REGION_NUM 15 #define APM_LL_HP_MAX_REGION_NUM 15
#define APM_LL_LP_MAX_REGION_NUM 3
#define APM_LL_MASTER_MAX 32 #define APM_LL_MASTER_MAX 32
#define HP_APM_MAX_ACCESS_PATH 0x4
#define LP_APM_MAX_ACCESS_PATH 0x1
#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION_FILTER_EN_REG) : 0); \
})
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : 0); \
})
#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : 0); \
})
#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : 0); \
})
#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0); \
})
#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0))
#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : 0); \
})
#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : 0); \
})
#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : 0); \
})
#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : 0); \
})
#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U
#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_INT_EN_REG) : 0); \
})
#define APM_CTRL_CLK_EN (BIT(0))
#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_CLOCK_GATE_REG) : 0); \
})
#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \
({\
(LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : \
((HP_APM_CTRL == apm_ctrl) ? (HP_APM_FUNC_CTRL_REG) : 0); \
})
/** /**
* @brief APM Master ID * @brief APM Master ID
*/ */
@@ -52,46 +138,67 @@ typedef enum {
APM_LL_MASTER_GDMA_PARLIO = 25, APM_LL_MASTER_GDMA_PARLIO = 25,
} apm_ll_master_id_t; } apm_ll_master_id_t;
/**
* @brief APM Controller
*/
typedef enum {
LP_APM_CTRL = 0,
HP_APM_CTRL = 1,
} apm_ll_apm_ctrl_t;
/** /**
* @brief APM Secure Mode * @brief APM Secure Mode
*/ */
typedef enum { typedef enum {
APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */
APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */
APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */
APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */ APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */
} apm_ll_secure_mode_t; } apm_ll_secure_mode_t;
/** /**
* @brief APM HP access path * @brief APM Ctrl access path
*/ */
typedef enum { typedef enum {
APM_LL_HP_ACCESS_PATH_M0 = 0x0, APM_CTRL_ACCESS_PATH_M0 = 0x0,
APM_LL_HP_ACCESS_PATH_M1 = 0x1, APM_CTRL_ACCESS_PATH_M1 = 0x1,
APM_LL_HP_ACCESS_PATH_M2 = 0x2, APM_CTRL_ACCESS_PATH_M2 = 0x2,
APM_LL_HP_ACCESS_PATH_M3 = 0x3, APM_CTRL_ACCESS_PATH_M3 = 0x3,
} apm_ll_hp_access_path_t; } apm_ll_ctrl_access_path_t;
/**
* @brief APM Ctrl path.
*/
typedef struct {
apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM/HP APM. */
apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */
} apm_ctrl_path_t;
/** /**
* @brief APM exception information * @brief APM exception information
*/ */
typedef struct { typedef struct {
uint8_t excp_id; apm_ctrl_path_t apm_path;
apm_ll_secure_mode_t sec_mode;
uint8_t excp_regn; uint8_t excp_regn;
uint8_t excp_mode; uint8_t excp_mode;
uint8_t excp_id;
uint8_t excp_type;
uint32_t excp_addr; uint32_t excp_addr;
} apm_hp_m_exception_info_t; } apm_ctrl_exception_info_t;
/** /**
* @brief Set secure mode * @brief Set secure mode
* *
* @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param master_id APM master ID * @param master_id APM master ID
* @param mode Secure mode * @param sec_mode Secure mode
*/ */
static inline void apm_tee_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode) static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
apm_ll_secure_mode_t sec_mode)
{ {
if (apm_ctrl == HP_APM_CTRL) {
REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
}
} }
/** /**
@@ -109,133 +216,187 @@ static inline void apm_tee_ll_clk_gating_enable(bool enable)
} }
/** /**
* @brief enable/disable HP Region access permission filter * @brief enable/disable APM Ctrl Region access permission filter
* *
* @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param regn_num Memory Region number * @param regn_num Memory Region number
* @param enable Flag for Region access filter enable/disable * @param enable Flag for Region access filter enable/disable
*/ */
static inline void apm_hp_ll_region_filter_enable(uint32_t regn_num, bool enable) static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
} else { } else {
REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
} }
} }
/** /**
* @brief enable/disable HP access path(M[0:3]) * @brief enable/disable APM Ctrl access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param enable Flag for HP M path filter enable/disable * @param apm_m_path APM Ctrl access path
* @param enable Flag for APM Ctrl M path filter enable/disable
*/ */
static inline void apm_hp_ll_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path, bool enable)
{ {
HAL_ASSERT(((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
} else { } else {
REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
} }
} }
/** /**
* @brief HP Region start address configuration * @brief APM Ctrl Region start address configuration
* *
* @param regn_num HP Region number to be configured * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param regn_num Region number to be configured
* @param addr Region start address * @param addr Region start address
*/ */
static inline void apm_hp_ll_set_region_start_address(uint32_t regn_num, uint32_t addr) static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, uint32_t addr)
{ {
REG_WRITE(APM_LL_REGION_ADDR_START_REG(regn_num), addr); HAL_ASSERT(((apm_ctrl == LP_APM_CTRL) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr);
} }
/** /**
* @brief HP Region end address configuration * @brief APM Ctrl Region end address configuration
* *
* @param regn_num HP Region number to be configured * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param regn_num Region number to be configured
* @param addr Region end address * @param addr Region end address
*/ */
static inline void apm_hp_ll_set_region_end_address(uint32_t regn_num, uint32_t addr) static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, uint32_t addr)
{ {
REG_WRITE(APM_LL_REGION_ADDR_END_REG(regn_num), addr); HAL_ASSERT(((apm_ctrl == LP_APM_CTRL) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr);
} }
/** /**
* @brief HP Region pms attributes configuration * @brief HP Region pms attributes configuration
* *
* @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param regn_num Region number to be configured * @param regn_num Region number to be configured
* @param sec_mode Secure mode of the Master * @param sec_mode Secure mode of the Master
* @param regn_pms XWR permissions for the given secure mode and Region number * @param regn_pms XWR permissions for the given secure mode and Region number
*/ */
static inline void apm_hp_ll_sec_mode_region_attr_config(uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl,
uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
{ {
HAL_ASSERT(((apm_ctrl == LP_APM_CTRL) && (regn_num <= APM_LL_LP_MAX_REGION_NUM)) ||
((apm_ctrl == HP_APM_CTRL) && (regn_num <= APM_LL_HP_MAX_REGION_NUM))
);
uint32_t val = 0; uint32_t val = 0;
val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(regn_num)); val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num));
val &= ~APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode); val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode);
val |= APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(regn_num), val); REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val);
} }
/** /**
* @brief Get HP access path(M[0:3]) exception status * @brief Get APM Ctrl access path(M[0:n]) exception status
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param apm_m_path APM Ctrl access path
*/ */
static inline uint8_t apm_hp_ll_m_exception_status(apm_ll_hp_access_path_t hp_m_path) static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path)
{ {
return REG_READ(APM_LL_TEE_EXCP_STATUS_REG(hp_m_path)); HAL_ASSERT(((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path));
} }
/** /**
* @brief Clear HP access path(M[0:3]) exception * @brief Clear APM Ctrl access path(M[0:n]) exception
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param amp_m_path APM Ctrl access path
*/ */
static inline void apm_hp_ll_m_exception_clear(apm_ll_hp_access_path_t hp_m_path) static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path)
{ {
REG_SET_BIT(APM_LL_TEE_EXCP_CLR_REG(hp_m_path), HP_APM_M0_REGION_STATUS_CLR); HAL_ASSERT(((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path),
APM_CTRL_M_REGION_STATUS_CLR);
} }
/** /**
* @brief Get HP access path(M[0:3]) exception information * @brief Get APM Ctrl access path(M[0:n]) exception information
* *
* @param excp_info Exception related information like addr, * @param excp_info Exception related information like addr,
* region, sec_mode and master id * region, apm_ctrl, apm_m_path, sec_mode and master id
*/ */
static inline void apm_hp_ll_get_m_exception_info(apm_hp_m_exception_info_t *excp_info) static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
{ {
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_ID); HAL_ASSERT(((excp_info->apm_path.apm_ctrl == HP_APM_CTRL) && (excp_info->apm_path.apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_MODE); ((excp_info->apm_path.apm_ctrl == LP_APM_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM_MAX_ACCESS_PATH))
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_REGION); );
excp_info->excp_addr = REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG);
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_ID);
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_MODE);
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
APM_LL_CTRL_EXCEPTION_REGION);
excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path);
excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path));
} }
/** /**
* @brief Interrupt enable for access path(M[0:3]) * @brief Interrupt enable for APM Ctrl at access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param apm_m_path APM Ctrl access patch(M[0:n])
* @param enable Flag for access path interrupt enable/disable * @param enable Flag for access path interrupt enable/disable
*/ */
static inline void apm_hp_ll_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable) static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl,
apm_ll_ctrl_access_path_t apm_m_path, bool enable)
{ {
HAL_ASSERT(((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
} else { } else {
REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
} }
} }
/** /**
* @brief HP clock auto gating enable * @brief APM Ctrl clock auto gating enable
* *
* @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param enable Flag for HP clock auto gating enable/disable * @param enable Flag for HP clock auto gating enable/disable
*/ */
static inline void apm_hp_ll_clk_gating_enable(bool enable) static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
} else { } else {
REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
} }
} }
@@ -249,7 +410,7 @@ static inline void apm_hp_ll_clk_gating_enable(bool enable)
* *
* @param enable Flag for event bypass enable/disable * @param enable Flag for event bypass enable/disable
*/ */
static inline void apm_hp_ll_reset_event_enable(bool enable) static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable)
{ {
if (enable) { if (enable) {
REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
@@ -258,6 +419,28 @@ static inline void apm_hp_ll_reset_event_enable(bool enable)
} }
} }
/**
* @brief Return APM Ctrl interrupt source number.
*
* @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
* @param apm_m_path APM Ctrl access patch(M[0:n])
*/
static inline esp_err_t apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path)
{
HAL_ASSERT(((apm_ctrl == HP_APM_CTRL) && (apm_m_path < HP_APM_MAX_ACCESS_PATH)) ||
((apm_ctrl == LP_APM_CTRL) && (apm_m_path < LP_APM_MAX_ACCESS_PATH))
);
switch (apm_ctrl) {
case HP_APM_CTRL :
return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path);
case LP_APM_CTRL :
return (ETS_LP_APM_M0_INTR_SOURCE);
}
return -1;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

90
components/hal/include/hal/apm_hal.h
View File

@@ -9,6 +9,7 @@
extern "C" { extern "C" {
#endif #endif
#include "esp_err.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if SOC_APM_SUPPORTED #if SOC_APM_SUPPORTED
#include "hal/apm_ll.h" #include "hal/apm_ll.h"
@@ -17,29 +18,36 @@ extern "C" {
* @brief Region configuration data. * @brief Region configuration data.
*/ */
typedef struct { typedef struct {
apm_ll_secure_mode_t sec_mode; uint32_t regn_num; /* Address Region number cover by this configuration data. */
uint32_t regn_num; uint32_t regn_start_addr; /* Address Region start address. */
uint32_t regn_start_addr; uint32_t regn_end_addr; /* Address Region end address. */
uint32_t regn_end_addr; uint32_t regn_pms; /* Access Permission for Master in different secure mode. */
uint32_t regn_pms; bool filter_enable; /* Address Region Filter enable/disable. */
} apm_hp_hal_region_config_data_t; apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */
apm_ll_secure_mode_t sec_mode; /* Master secure mode: TEE/REE[0-2].*/
} apm_ctrl_region_config_data_t;
/** /**
* @brief Secure mode(TEE/REE[0:2] configuration data. * @brief Secure mode(TEE/REE[0:2] configuration data.
*/ */
typedef struct { typedef struct {
apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */
apm_ll_secure_mode_t sec_mode; /* Secure mode to be configured TEE/REE[0:2]. */ apm_ll_secure_mode_t sec_mode; /* Secure mode to be configured TEE/REE[0:2]. */
uint8_t apm_m_cnt; /* Access path M count. */
uint32_t regn_count; /* Access Ctrl region count. */
uint32_t master_ids; /* Bit mask for masters to be part of this secure mode. */ uint32_t master_ids; /* Bit mask for masters to be part of this secure mode. */
apm_hp_hal_region_config_data_t *pms_data; /* Region configuration data. */ apm_ctrl_region_config_data_t *pms_data; /* Region configuration data. */
} apm_hp_secure_mode_config_t; } apm_ctrl_secure_mode_config_t;
/** /**
* @brief Set secure mode * @brief Set secure mode
* *
* @param apm_ctrl APM Ctrl to be configured
* @param master_id APM master ID * @param master_id APM master ID
* @param sec_mode Secure mode * @param sec_mode Secure mode
*/ */
void apm_tee_hal_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode); void apm_tee_hal_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
apm_ll_secure_mode_t sec_mode);
/** /**
* @brief TEE controller clock auto gating enable * @brief TEE controller clock auto gating enable
@@ -49,64 +57,73 @@ void apm_tee_hal_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_sec
void apm_tee_hal_clk_gating_enable(bool enable); void apm_tee_hal_clk_gating_enable(bool enable);
/** /**
* @brief enable/disable HP Region access permission filter * @brief enable/disable APM Ctrl Region access permission filter
* *
* @param apm_ctrl APM Ctrl to be configured
* @param regn_num Memory Region number * @param regn_num Memory Region number
* @param enable Flag for Region access filter enable/disable * @param enable Flag for Region access filter enable/disable
*/ */
void apm_hp_hal_region_filter_enable(uint32_t regn_num, bool enable); void apm_hal_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, uint32_t regn_num, bool enable);
/** /**
* @brief enable/disable HP access path(M[0:3]) * @brief enable/disable APM Ctrl access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_path APM controller and access path to be configured
* @param enable Flag for HP M path filter enable/disable * @param enable Flag for M path filter enable/disable
*/ */
void apm_hp_hal_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable); void apm_hal_apm_ctrl_filter_enable(apm_ctrl_path_t *apm_path, bool enable);
/**
* @brief enable/disable all available APM Ctrl access path(M[0:n])
*
* @param enable Flag for M path filter enable/disable
*/
void apm_hal_apm_ctrl_filter_enable_all(bool enable);
/** /**
* @brief Region configuration * @brief Region configuration
* *
* @param pms_data Region configuration data * @param pms_data Region configuration data
*/ */
void apm_hp_hal_region_config(const apm_hp_hal_region_config_data_t *pms_data); void apm_hal_apm_ctrl_region_config(const apm_ctrl_region_config_data_t *pms_data);
/** /**
* @brief Get HP access path(M[0:3]) exception status * @brief Get APM Ctrl access path(M[0:n]) exception status
* *
* @param hp_m_path HP access path * @param apm_path APM controller and access path to be configured
*/ */
uint8_t apm_hp_hal_m_exception_status(apm_ll_hp_access_path_t hp_m_path); uint8_t apm_hal_apm_ctrl_exception_status(apm_ctrl_path_t *apm_path);
/** /**
* @brief Clear HP access path(M[0:3]) exception * @brief Clear APM Ctrl access path(M[0:n]) exception
* *
* @param hp_m_path HP access path * @param apm_path APM controller and access path to be configured
*/ */
void apm_hp_hal_m_exception_clear(apm_ll_hp_access_path_t hp_m_path); void apm_hal_apm_ctrl_exception_clear(apm_ctrl_path_t *apm_path);
/** /**
* @brief Get HP access path(M[0:3]) exception information * @brief Get APM Ctrl access path exception information
* *
* @param excp_info Exception related information like addr, * @param excp_info Exception related information like addr,
* region, sec_mode and master id * region, amp_ctrl, apm_m_path, sec_mode and master id
*/ */
void apm_hp_hal_get_m_exception_info(apm_hp_m_exception_info_t *excp_info); void apm_hal_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info);
/** /**
* @brief Interrupt enable for access path(M[0:3]) * @brief APM Ctrl interrupt enable for access path(M[0:n])
* *
* @param hp_m_path HP access path * @param apm_path APM controller and access path to be configured
* @param enable Flag for access path interrupt enable/disable * @param enable Flag for access path interrupt enable/disable
*/ */
void apm_hp_hal_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable); void apm_hal_apm_ctrl_interrupt_enable(apm_ctrl_path_t *apm_path, bool enable);
/** /**
* @brief HP clock auto gating enable * @brief APM Ctrl clock auto gating enable
* *
* @apm_ctrl APM Ctrl
* @param enable Flag for HP clock auto gating enable/disable * @param enable Flag for HP clock auto gating enable/disable
*/ */
void apm_hp_hal_clk_gating_enable(bool enable); void apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable);
/** /**
* @brief TEE/REE execution environment configuration. * @brief TEE/REE execution environment configuration.
@@ -116,8 +133,10 @@ void apm_hp_hal_clk_gating_enable(bool enable);
* It includes, allocation of all bus masters, memory ranges and other * It includes, allocation of all bus masters, memory ranges and other
* peripherals to the given secure mode. * peripherals to the given secure mode.
* All this information should be passed by the TEE mode initialization code. * All this information should be passed by the TEE mode initialization code.
*
* @sec_mode_data APM Ctl configuration data.
*/ */
void apm_hp_hal_master_sec_mode_config(apm_hp_secure_mode_config_t *sec_mode_data); void apm_hal_apm_ctrl_master_sec_mode_config(apm_ctrl_secure_mode_config_t *sec_mode_data);
/** /**
* @brief APM/TEE/HP System Reg reset event bypass enable * @brief APM/TEE/HP System Reg reset event bypass enable
@@ -129,7 +148,14 @@ void apm_hp_hal_master_sec_mode_config(apm_hp_secure_mode_config_t *sec_mode_dat
* *
* @param enable Flag for event bypass enable/disable * @param enable Flag for event bypass enable/disable
*/ */
void apm_hp_hal_reset_event_enable(bool enable); void apm_hal_apm_ctrl_reset_event_enable(bool enable);
/**
* @brief Returns APM Ctrl access path interrupt source number.
*
* @param apm_path APM controller and access path to be configured
*/
esp_err_t apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path);
#endif #endif

10
components/soc/esp32c6/include/soc/lp_tee_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -55,10 +55,10 @@ extern "C" {
/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688; /** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688;
* reg_tee_date * reg_tee_date
*/ */
#define LP_TEE_DATE_REG 0x0FFFFFFFU #define LP_TEE_DATE 0x0FFFFFFFU
#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) #define LP_TEE_DATE_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
#define LP_TEE_DATE_REG_V 0x0FFFFFFFU #define LP_TEE_DATE_V 0x0FFFFFFFU
#define LP_TEE_DATE_REG_S 0 #define LP_TEE_DATE_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }

1
components/soc/esp32c6/include/soc/tee_reg.h
View File

@@ -5,7 +5,6 @@
*/ */
#pragma once #pragma once
#include <stdint.h>
#include "soc/soc.h" #include "soc/soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

1
components/soc/esp32h2/include/soc/tee_reg.h
View File

@@ -5,7 +5,6 @@
*/ */
#pragma once #pragma once
#include <stdint.h>
#include "soc/soc.h" #include "soc/soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {