diff --git a/components/bt/hli_vectors.S b/components/bt/hli_vectors.S
index 7d612c7250..8bdd9dc817 100644
--- a/components/bt/hli_vectors.S
+++ b/components/bt/hli_vectors.S
@@ -39,6 +39,30 @@ _l4_save_ctx:
     .type       xt_highint4,@function
     .align      4
 xt_highint4:
+
+#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    /*
+    Here, Timer2 is used to count a little time.
+    The subsequent dram0 write operation is blocked due to live lock, which will
+    cause timer2 to timeout and trigger a l5 interrupt.
+    */
+    rsr.ccount  a0
+    addmi   a0, a0, (240*50)
+    wsr     a0, CCOMPARE2
+
+    /* Enable Timer 2 interrupt */
+    rsr     a0, INTENABLE
+    extui   a0, a0, 16, 1
+    bnez    a0, 1f
+    rsr     a0, INTENABLE
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    wsr     a0, INTENABLE
+1:
+#endif
+
     movi    a0, _l4_save_ctx
     /* save 4 lower registers */
     s32i    a1, a0, 4
@@ -64,6 +88,13 @@ xt_highint4:
     rsr     a2, EPC1
     s32i    a2, a0, 24
 
+#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    rsr     a0, INTENABLE
+    movi    a2, ~(1<<16)
+    and     a0, a2, a0
+    wsr     a0, INTENABLE
+#endif
+
     /* disable exception mode, window overflow */
     movi    a0, PS_INTLEVEL(5) | PS_EXCM  /*TOCHECK*/
     wsr     a0, PS
diff --git a/components/esp32/dport_panic_highint_hdl.S b/components/esp32/dport_panic_highint_hdl.S
index b599c36136..1ba128f602 100644
--- a/components/esp32/dport_panic_highint_hdl.S
+++ b/components/esp32/dport_panic_highint_hdl.S
@@ -71,6 +71,11 @@ xt_highint5:
 #endif // CONFIG_FREERTOS_UNICORE
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    /* Timer 2 interrupt */
+    rsr     a0, INTERRUPT
+    extui   a0, a0, 16, 1
+    bnez    a0, .handle_multicore_debug_int
+
     /* See if we're here for the tg1 watchdog interrupt */
     rsr     a0, INTERRUPT
     extui   a0, a0, ETS_T1_WDT_INUM, 1
@@ -166,6 +171,47 @@ xt_highint5:
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
 
+#define APB_ITCTRL              (0x3f00)
+#define APB_DCRSET              (0x200c)
+
+#define ERI_ADDR(APB)           (0x100000 + (APB))
+
+    .align      4
+.handle_multicore_debug_int:
+
+    wsr     a2, depc                        /* temp storage */
+
+    /* Enable Integration Mode */
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    rer     a0, a2
+    addi    a0, a0, 1
+    wer     a0, a2
+
+    /* Enable and emit BreakOut signal */
+    movi    a2, ERI_ADDR(APB_DCRSET)
+    rer     a0, a2
+    movi    a2, 0x1020000
+    or      a0, a2, a0
+    movi    a2, ERI_ADDR(APB_DCRSET)
+    wer     a0, a2
+
+    .rept   4
+    nop
+    .endr
+
+    /* Disable Normally Mode */
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    rer     a0, a2
+    movi    a2, ~0x1
+    and     a0, a2, a0
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    wer     a0, a2
+
+    rsr     a2, depc
+
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
 /*
 --------------------------------------------------------------------------------
   Macro intr_matrix_map - Attach an CPU interrupt to a hardware source.
diff --git a/components/esp32/int_wdt.c b/components/esp32/int_wdt.c
index 0af4c1b476..a7fe77efa3 100644
--- a/components/esp32/int_wdt.c
+++ b/components/esp32/int_wdt.c
@@ -104,6 +104,35 @@ void esp_int_wdt_init() {
     TIMERG1.wdt_wprotect=0;
     TIMERG1.int_clr_timers.wdt=1;
     timer_group_intr_enable(TIMER_GROUP_1, TIMG_WDT_INT_ENA_M);
+
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+
+#define APB_DCRSET      (0x200c)
+#define APB_ITCTRL      (0x3f00)
+
+#define ERI_ADDR(APB)   (0x100000 + (APB))
+
+#define _SYM2STR(x)     # x
+#define SYM2STR(x)      _SYM2STR(x)
+    uint32_t eriadrs, scratch = 0, immediate = 0;
+    if (xPortGetCoreID() == PRO_CPU_NUM) {
+        __asm__ __volatile__ (
+                /* Enable Xtensa Debug Module Integration Mode */
+                "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"
+                "rer    %[REG], %[ERI]\n"
+                "movi   %[IMM], 1\n"
+                "or     %[REG], %[IMM], %[REG]\n"
+                "wer    %[REG], %[ERI]\n"
+                /* Enable Xtensa Debug Module BreakIn signal */
+                "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_DCRSET)) "\n"
+                "rer    %[REG], %[ERI]\n"
+                "movi   %[IMM], 0x10000\n"
+                "or     %[REG], %[IMM], %[REG]\n"
+                "wer    %[REG], %[ERI]\n"
+                : [ERI] "=r" (eriadrs), [REG] "+r" (scratch), [IMM] "+r" (immediate)
+            );
+    }
+#endif
 }
 
 void esp_int_wdt_cpu_init()
diff --git a/components/freertos/xtensa_vector_defaults.S b/components/freertos/xtensa_vector_defaults.S
index 592dc323bd..6170c0f240 100644
--- a/components/freertos/xtensa_vector_defaults.S
+++ b/components/freertos/xtensa_vector_defaults.S
@@ -32,7 +32,17 @@ The default behaviour is to just exit the interrupt or call the panic handler on
     .align      4
 
 _xt_debugexception:
-    movi    a0,PANIC_RSN_DEBUGEXCEPTION
+
+#define XT_DEBUGCAUSE_DI        (5)
+
+    getcoreid   a0
+    beqz    a0, 1f
+
+    rsr     a0, DEBUGCAUSE
+    extui   a0, a0, XT_DEBUGCAUSE_DI, 1
+    bnez    a0, _xt_debug_di_exc
+
+1:  movi    a0,PANIC_RSN_DEBUGEXCEPTION
     wsr     a0,EXCCAUSE
     /* _xt_panic assumes a level 1 exception. As we're
        crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
@@ -44,6 +54,19 @@ _xt_debugexception:
     call0   _xt_panic                       /* does not return */
     rfi     XCHAL_DEBUGLEVEL
 
+    .align  4
+_xt_debug_di_exc:
+
+    movi    a0, 1234
+1:  addi    a0, a0, -1
+    .rept   4
+    nop
+    .endr
+    bnez    a0, 1b
+
+    rsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL
+    rfi     XCHAL_DEBUGLEVEL
+
 #endif /* Debug exception */