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change(esp_hw_support): fix wifi mac rx buffer link exception caused by pll clock

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This commit is contained in:
Li Shuai
2024-12-26 12:05:49 +08:00
committed by BOT
parent 761833493a
commit c74a5e3e8e
3 changed files with 32 additions and 8 deletions
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6
components/esp_hw_support/sleep_modes.c
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@ -676,6 +676,9 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s
} }
#endif #endif
#if CONFIG_MAC_BB_PD #if CONFIG_MAC_BB_PD
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(false);
# endif
mac_bb_power_down_cb_execute(); mac_bb_power_down_cb_execute();
#endif #endif
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
@ -742,6 +745,9 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
#endif #endif
#if CONFIG_MAC_BB_PD #if CONFIG_MAC_BB_PD
mac_bb_power_up_cb_execute(); mac_bb_power_up_cb_execute();
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(true);
# endif
#endif #endif
#if REGI2C_ANA_CALI_PD_WORKAROUND #if REGI2C_ANA_CALI_PD_WORKAROUND
regi2c_analog_cali_reg_write(); regi2c_analog_cali_reg_write();

15
components/esp_system/port/soc/esp32c5/clk.c
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@ -23,6 +23,7 @@
#include "esp_cpu.h" #include "esp_cpu.h"
#include "hal/efuse_hal.h" #include "hal/efuse_hal.h"
#include "hal/wdt_hal.h" #include "hal/wdt_hal.h"
#include "hal/clk_tree_ll.h"
#if SOC_MODEM_CLOCK_SUPPORTED #if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_lpcon_ll.h" #include "hal/modem_lpcon_ll.h"
#endif #endif
@ -218,14 +219,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif #endif
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix * the issue where the modem module fails to transmit and receive packets
* the issue where the modem module fails to transmit and receive packets * due to the loss of the modem root clock caused by automatic clock gating
* due to the loss of the modem root clock caused by automatic clock gating * during soc root clock source switching. For detailed information, refer
* during soc root clock source switching. For detailed information, refer * to IDF-11064. */
* to IDF-11064. */ clk_ll_soc_root_clk_auto_gating_bypass(true);
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: [ESP32C5] IDF-8844 #if 0 // TODO: [ESP32C5] IDF-8844

19
components/hal/esp32c5/include/hal/clk_tree_ll.h
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@ -9,16 +9,19 @@
#include <stdint.h> #include <stdint.h>
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/clk_tree_defs.h" #include "soc/clk_tree_defs.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h" #include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h" #include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h" #include "soc/pmu_reg.h"
#include "soc/pmu_struct.h" #include "soc/pmu_struct.h"
#include "soc/chip_revision.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32c5/rom/rtc.h" #include "esp32c5/rom/rtc.h"
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -420,6 +423,22 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1; return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
} }
/**
* @brief Enable or disable the soc root clock auto gating logic
*
* @param ena true to enable, false to disable
*/
static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gating_bypass(bool ena)
{
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (ena) {
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
} else {
REG_SET_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *