forked from espressif/esp-idf
efuse_hal: Fix error bits for BLOCK0
eFuse BLOCK0 has only one error reg.
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@@ -66,11 +66,7 @@ void efuse_hal_rs_calculate(const void *data, void *rs_values)
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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{
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{
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if (block == 0) {
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if (block == 0) {
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for (unsigned i = 0; i < 5; i++) {
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return REG_READ(EFUSE_RD_REPEAT_ERR_REG) != 0;
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if (REG_READ(EFUSE_RD_REPEAT_ERR_REG + i * 4)) {
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return true;
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}
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}
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} else if (block <= 3) {
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} else if (block <= 3) {
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// EFUSE_RD_RS_ERR_REG: (hi) ----, ----, ----, ----, ----, BLOCK3, BLOCK2, BLOCK1 (low)
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// EFUSE_RD_RS_ERR_REG: (hi) ----, ----, ----, ----, ----, BLOCK3, BLOCK2, BLOCK1 (low)
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uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR_REG);
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uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR_REG);
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