From 1392cce5e15cdfc5446529fb77a8107de31d4214 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:12:10 +0800 Subject: [PATCH 1/4] bootloader: removed unavailable rtc features --- .../bootloader_support/src/esp32/bootloader_soc.c | 12 ++---------- .../bootloader_support/src/esp32s2/bootloader_soc.c | 12 ++---------- 2 files changed, 4 insertions(+), 20 deletions(-) diff --git a/components/bootloader_support/src/esp32/bootloader_soc.c b/components/bootloader_support/src/esp32/bootloader_soc.c index 242a575508..31525ef277 100644 --- a/components/bootloader_support/src/esp32/bootloader_soc.c +++ b/components/bootloader_support/src/esp32/bootloader_soc.c @@ -3,18 +3,10 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #include -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - (void)enable; -} - -void bootloader_ana_bod_reset_config(bool enable) -{ - (void)enable; -} - +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; diff --git a/components/bootloader_support/src/esp32s2/bootloader_soc.c b/components/bootloader_support/src/esp32s2/bootloader_soc.c index 242a575508..31525ef277 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s2/bootloader_soc.c @@ -3,18 +3,10 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #include -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - (void)enable; -} - -void bootloader_ana_bod_reset_config(bool enable) -{ - (void)enable; -} - +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; From d43934f32de712c32aa8ed97c201b0fe6e1a8fc1 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:13:18 +0800 Subject: [PATCH 2/4] bootloader: fixed super watchdog not enabled issue on C3, S3, H4 --- .../bootloader_support/src/esp32c3/bootloader_esp32c3.c | 6 +++--- components/bootloader_support/src/esp32c3/bootloader_soc.c | 6 +++--- .../bootloader_support/src/esp32s3/bootloader_esp32s3.c | 2 +- components/bootloader_support/src/esp32s3/bootloader_soc.c | 6 +++--- components/soc/esp32c3/include/soc/rtc_cntl_reg.h | 2 +- components/soc/esp32s3/include/soc/rtc_cntl_reg.h | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index c67c9aefe3..cd4488fd61 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -269,20 +269,20 @@ static inline void bootloader_ana_reset_config(void) switch (efuse_hal_chip_revision()) { case 0: case 1: - //Enable WDT reset. Disable BOR and GLITCH reset + //Enable WDT reset. Disable BOD and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(false); bootloader_ana_clock_glitch_reset_config(false); break; case 2: - //Enable WDT and BOR reset. Disable GLITCH reset + //Enable WDT and BOD reset. Disable GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(false); break; case 3: default: - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32c3/bootloader_soc.c b/components/bootloader_support/src/esp32c3/bootloader_soc.c index 7104528a58..f808b72fd5 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index 7e2005391a..aebb1fbf2d 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -314,7 +314,7 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_ana_reset_config(void) { - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32s3/bootloader_soc.c b/components/bootloader_support/src/esp32s3/bootloader_soc.c index 7104528a58..f808b72fd5 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index ac7d7b03b4..55c8cc2cb5 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -2353,7 +2353,7 @@ extern "C" { #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index f7eca5aa48..c66e06b38a 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3571,7 +3571,7 @@ ork.*/ #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) From 6ce4fd9eab78e7971b402ef89d745e8539afa730 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:15:05 +0800 Subject: [PATCH 3/4] bootloader: cleanup ana reset config code --- .../src/esp32c3/bootloader_esp32c3.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index cd4488fd61..7e77f5e9b1 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -261,29 +261,29 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + /* - For origin chip & ECO1: only support swt reset; - For ECO2: fix brownout reset bug, support swt & brownout reset; - For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. + For origin chip & ECO1: brownout & clock glitch reset not available + For ECO2: fix brownout reset bug + For ECO3: fix clock glitch reset bug */ switch (efuse_hal_chip_revision()) { case 0: case 1: - //Enable WDT reset. Disable BOD and GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Disable BOD and GLITCH reset bootloader_ana_bod_reset_config(false); bootloader_ana_clock_glitch_reset_config(false); break; case 2: - //Enable WDT and BOD reset. Disable GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset. Disable GLITCH reset bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(false); break; case 3: default: - //Enable WDT, BOD, and GLITCH reset - bootloader_ana_super_wdt_reset_config(true); + //Enable BOD, and GLITCH reset bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); break; From 8227ca97bd4b27d2aabcd93971590713a36effd5 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Wed, 8 Mar 2023 14:12:34 +0800 Subject: [PATCH 4/4] bootloader: enable super WDT and BOD reset on C2 --- .../src/esp32c2/bootloader_esp32c2.c | 10 +++++++++ .../src/esp32c2/bootloader_soc.c | 21 ++++++++++++++++--- .../soc/esp32c2/include/soc/rtc_cntl_reg.h | 4 ++++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c index 0b6b67f781..8908c515c1 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c +++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c @@ -34,6 +34,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "bootloader_soc.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" @@ -240,10 +241,19 @@ static void bootloader_super_wdt_auto_feed(void) REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); } +static inline void bootloader_ana_reset_config(void) +{ + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset + bootloader_ana_bod_reset_config(true); +} + esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; + bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); // protect memory region bootloader_init_mem(); diff --git a/components/bootloader_support/src/esp32c2/bootloader_soc.c b/components/bootloader_support/src/esp32c2/bootloader_soc.c index 2b20b0415a..2233be7529 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c2/bootloader_soc.c @@ -3,19 +3,34 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #include +#include "soc/rtc_cntl_reg.h" void bootloader_ana_super_wdt_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); + + if (enable) { + REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } } void bootloader_ana_bod_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); + + if (enable) { + REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } else { + REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); + } } +//Not supported but common bootloader calls the function. Do nothing void bootloader_ana_clock_glitch_reset_config(bool enable) { - (void)enable; // ESP32-C2 has none of these features. + (void)enable; } diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h index 2ae5143b01..e70fb47603 100644 --- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h @@ -1678,6 +1678,10 @@ RO CPU.*/ #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOD_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0xFC) /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : ;bitpos:[31] ;default: 1'b0 ; */ /*description: Need add desc.*/