From c82ea4311e24b8e2628a3a3008f8b88596202ead Mon Sep 17 00:00:00 2001 From: wanlei Date: Wed, 20 Dec 2023 16:14:34 +0800 Subject: [PATCH] refactor(spi_slave_hd): replace part of dma_ll in hd hal layer --- .../include/esp_private/spi_common_internal.h | 9 + .../include/esp_private/spi_dma.h | 16 +- components/esp_driver_spi/linker.lf | 3 + .../esp_driver_spi/src/gpspi/spi_common.c | 12 - components/esp_driver_spi/src/gpspi/spi_dma.c | 24 +- .../esp_driver_spi/src/gpspi/spi_slave_hd.c | 183 ++++++++++---- components/hal/esp32s2/include/hal/spi_ll.h | 2 +- components/hal/include/hal/spi_slave_hd_hal.h | 37 +-- components/hal/spi_slave_hd_hal.c | 226 ++---------------- 9 files changed, 235 insertions(+), 277 deletions(-) diff --git a/components/esp_driver_spi/include/esp_private/spi_common_internal.h b/components/esp_driver_spi/include/esp_private/spi_common_internal.h index e98eb40b76..b07bfce3f9 100644 --- a/components/esp_driver_spi/include/esp_private/spi_common_internal.h +++ b/components/esp_driver_spi/include/esp_private/spi_common_internal.h @@ -34,6 +34,15 @@ typedef dma_descriptor_align8_t spi_dma_desc_t; typedef dma_descriptor_align4_t spi_dma_desc_t; #endif +#if SOC_NON_CACHEABLE_OFFSET +#include "hal/cache_ll.h" +#define ADDR_DMA_2_CPU(addr) ((typeof(addr))CACHE_LL_L2MEM_NON_CACHE_ADDR(addr)) +#define ADDR_CPU_2_DMA(addr) ((typeof(addr))CACHE_LL_L2MEM_CACHE_ADDR(addr)) +#else +#define ADDR_DMA_2_CPU(addr) (addr) +#define ADDR_CPU_2_DMA(addr) (addr) +#endif + /// Attributes of an SPI bus typedef struct { spi_bus_config_t bus_cfg; ///< Config used to initialize the bus diff --git a/components/esp_driver_spi/include/esp_private/spi_dma.h b/components/esp_driver_spi/include/esp_private/spi_dma.h index 39ff2c3c8f..32c4c9e94b 100644 --- a/components/esp_driver_spi/include/esp_private/spi_dma.h +++ b/components/esp_driver_spi/include/esp_private/spi_dma.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,6 +36,13 @@ typedef struct { */ void spi_dma_enable_burst(spi_dma_chan_handle_t chan_handle, bool data_burst, bool desc_burst); +/** + * Re-trigger a HW pre-load to pick up appended linked descriptor + * + * @param chan_handle Context of the spi_dma channel. + */ +void spi_dma_append(spi_dma_chan_handle_t chan_handle); + /** * Reset dma channel for spi_dma * @@ -51,6 +58,13 @@ void spi_dma_reset(spi_dma_chan_handle_t chan_handle); */ void spi_dma_start(spi_dma_chan_handle_t chan_handle, void *addr); +/** + * Get EOF descriptor for a dma channel + * + * @param chan_handle Context of the spi_dma channel. + */ +uint32_t spi_dma_get_eof_desc(spi_dma_chan_handle_t chan_handle); + #endif //!SOC_GDMA_SUPPORTED #ifdef __cplusplus diff --git a/components/esp_driver_spi/linker.lf b/components/esp_driver_spi/linker.lf index f3c420c122..450934d495 100644 --- a/components/esp_driver_spi/linker.lf +++ b/components/esp_driver_spi/linker.lf @@ -5,3 +5,6 @@ entries: if SOC_GDMA_SUPPORTED != y && (SPI_MASTER_ISR_IN_IRAM = y || SPI_SLAVE_ISR_IN_IRAM = y): spi_dma: spi_dma_reset (noflash) spi_dma: spi_dma_start (noflash) + + if SOC_SPI_SUPPORT_SLAVE_HD_VER2 = y: + spi_dma: spi_dma_get_eof_desc (noflash) diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index 5c059e6f70..5d29aaf510 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -14,7 +14,6 @@ #include "esp_rom_gpio.h" #include "esp_heap_caps.h" #include "soc/spi_periph.h" -#include "soc/ext_mem_defs.h" #include "driver/spi_master.h" #include "driver/gpio.h" #include "esp_private/gpio.h" @@ -27,9 +26,6 @@ #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" #endif -#if SOC_GDMA_SUPPORTED -#include "esp_private/gdma.h" -#endif static const char *SPI_TAG = "spi"; @@ -307,14 +303,6 @@ esp_err_t spicommon_dma_desc_alloc(spi_dma_ctx_t *dma_ctx, int cfg_max_sz, int * return ESP_OK; } -#if SOC_NON_CACHEABLE_OFFSET -#define ADDR_DMA_2_CPU(addr) ((typeof(addr))((uint32_t)(addr) + SOC_NON_CACHEABLE_OFFSET)) -#define ADDR_CPU_2_DMA(addr) ((typeof(addr))((uint32_t)(addr) - SOC_NON_CACHEABLE_OFFSET)) -#else -#define ADDR_DMA_2_CPU(addr) (addr) -#define ADDR_CPU_2_DMA(addr) (addr) -#endif - void IRAM_ATTR spicommon_dma_desc_setup_link(spi_dma_desc_t *dmadesc, const void *data, int len, bool is_rx) { dmadesc = ADDR_DMA_2_CPU(dmadesc); diff --git a/components/esp_driver_spi/src/gpspi/spi_dma.c b/components/esp_driver_spi/src/gpspi/spi_dma.c index 4d258602e6..1e746831d9 100644 --- a/components/esp_driver_spi/src/gpspi/spi_dma.c +++ b/components/esp_driver_spi/src/gpspi/spi_dma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,8 +21,30 @@ void spi_dma_enable_burst(spi_dma_chan_handle_t chan_handle, bool data_burst, bo } } +#if SOC_SPI_SUPPORT_SLAVE_HD_VER2 +void spi_dma_append(spi_dma_chan_handle_t chan_handle) +{ + spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); + + if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { + spi_dma_ll_tx_restart(spi_dma, chan_handle.chan_id); + } else { + spi_dma_ll_rx_restart(spi_dma, chan_handle.chan_id); + } +} + /************************************* IRAM CONTEXT **************************************/ +uint32_t spi_dma_get_eof_desc(spi_dma_chan_handle_t chan_handle) +{ + spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); + + return (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) ? + spi_dma_ll_get_out_eof_desc_addr(spi_dma, chan_handle.chan_id) : + spi_dma_ll_get_in_suc_eof_desc_addr(spi_dma, chan_handle.chan_id); +} +#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 + void spi_dma_reset(spi_dma_chan_handle_t chan_handle) { spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); diff --git a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c index 22a53255cf..66029d5d35 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -65,11 +65,18 @@ static spi_slave_hd_slot_t *spihost[SOC_SPI_PERIPH_NUM]; static const char TAG[] = "slave_hd"; #if SOC_GDMA_SUPPORTED -static bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); +// for which dma is provided by gdma driver +#define spi_dma_reset gdma_reset +#define spi_dma_start(chan, addr) gdma_start(chan, (intptr_t)(addr)) +#define spi_dma_append gdma_append + +static bool s_spi_slave_hd_append_gdma_isr(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); +#else +// by spi_dma, mainly esp32s2 +static void s_spi_slave_hd_append_legacy_isr(void *arg); #endif // SOC_GDMA_SUPPORTED -static void spi_slave_hd_intr_append(void *arg); -static void spi_slave_hd_intr_segment(void *arg); +static void s_spi_slave_hd_segment_isr(void *arg); esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, const spi_slave_hd_slot_config_t *config) { @@ -102,6 +109,16 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b if (ret != ESP_OK) { goto cleanup; } +#if SOC_GDMA_SUPPORTED + gdma_strategy_config_t dma_strategy = { + .auto_update_desc = true, + .eof_till_data_popped = true, + }; + gdma_apply_strategy(host->dma_ctx->tx_dma_chan, &dma_strategy); +#else + spi_dma_ll_enable_out_auto_wrback(SPI_LL_GET_HW(host->dma_ctx->tx_dma_chan.host_id), host->dma_ctx->tx_dma_chan.chan_id, 1); + spi_dma_ll_set_out_eof_generation(SPI_LL_GET_HW(host->dma_ctx->tx_dma_chan.host_id), host->dma_ctx->tx_dma_chan.chan_id, 1); +#endif ret = spicommon_dma_desc_alloc(host->dma_ctx, bus_config->max_transfer_sz, &host->max_transfer_sz); if (ret != ESP_OK) { goto cleanup; @@ -141,8 +158,6 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b spi_slave_hd_hal_config_t hal_config = { .host_id = host_id, - .dma_in = SPI_LL_GET_HW(host_id), - .dma_out = SPI_LL_GET_HW(host_id), .dma_enabled = host->dma_enabled, .append_mode = append_mode, .mode = config->mode, @@ -150,15 +165,6 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b .rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST), }; -#if SOC_GDMA_SUPPORTED - //temporary used for gdma_ll alias in hal layer - gdma_get_channel_id(host->dma_ctx->tx_dma_chan, (int *)&hal_config.tx_dma_chan); - gdma_get_channel_id(host->dma_ctx->rx_dma_chan, (int *)&hal_config.rx_dma_chan); -#else - hal_config.tx_dma_chan = host->dma_ctx->tx_dma_chan.chan_id; - hal_config.rx_dma_chan = host->dma_ctx->rx_dma_chan.chan_id; -#endif - //Init the hal according to the hal_config set above spi_slave_hd_hal_init(&host->hal, &hal_config); @@ -192,34 +198,28 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b //Alloc intr if (!host->append_mode) { - //Seg mode - ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_segment, + ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, s_spi_slave_hd_segment_isr, (void *)host, &host->intr); if (ret != ESP_OK) { goto cleanup; } - ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_segment, + ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, s_spi_slave_hd_segment_isr, (void *)host, &host->intr_dma); if (ret != ESP_OK) { goto cleanup; } } else { //Append mode - //On ESP32S2, `cmd7` and `cmd8` interrupts registered as spi rx & tx interrupt are from SPI DMA interrupt source. - //although the `cmd7` and `cmd8` interrupt on spi are registered independently here - ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_append, - (void *)host, &host->intr); - if (ret != ESP_OK) { - goto cleanup; - } #if SOC_GDMA_SUPPORTED - // config gmda and ISR callback for gdma supported chip - gdma_tx_event_callbacks_t tx_cbs = { - .on_trans_eof = spi_gdma_tx_channel_callback + // config gmda event callback for gdma supported chip + gdma_rx_event_callbacks_t txrx_cbs = { + .on_recv_eof = s_spi_slave_hd_append_gdma_isr, }; - gdma_register_tx_event_callbacks(host->dma_ctx->tx_dma_chan, &tx_cbs, host); + gdma_register_tx_event_callbacks(host->dma_ctx->tx_dma_chan, (gdma_tx_event_callbacks_t *)&txrx_cbs, host); + gdma_register_rx_event_callbacks(host->dma_ctx->rx_dma_chan, &txrx_cbs, host); #else - ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_append, + //On ESP32S2, `cmd7` and `cmd8` are designed as all `spi_dma` events, so use `dma_src` only + ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, s_spi_slave_hd_append_legacy_isr, (void *)host, &host->intr_dma); if (ret != ESP_OK) { goto cleanup; @@ -321,8 +321,7 @@ static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t } return cb_awoken; } - -static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg) +static IRAM_ATTR void s_spi_slave_hd_segment_isr(void *arg) { spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg; spi_slave_hd_callback_config_t *callback = &host->callback; @@ -396,7 +395,10 @@ static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg) if (!host->tx_curr_trans.trans) { ret = xQueueReceiveFromISR(host->tx_trans_queue, &host->tx_curr_trans, &awoken); if (ret == pdTRUE) { - spi_slave_hd_hal_txdma(hal, host->tx_curr_trans.aligned_buffer, host->tx_curr_trans.trans->len); + spicommon_dma_desc_setup_link(hal->dmadesc_tx->desc, host->tx_curr_trans.aligned_buffer, host->tx_curr_trans.trans->len, false); + spi_dma_reset(host->dma_ctx->tx_dma_chan); + spi_slave_hd_hal_txdma(hal); + spi_dma_start(host->dma_ctx->tx_dma_chan, host->dma_ctx->dmadesc_tx); tx_sent = true; if (callback->cb_send_dma_ready) { spi_slave_hd_event_t ev = { @@ -412,7 +414,10 @@ static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg) if (!host->rx_curr_trans.trans) { ret = xQueueReceiveFromISR(host->rx_trans_queue, &host->rx_curr_trans, &awoken); if (ret == pdTRUE) { - spi_slave_hd_hal_rxdma(hal, host->rx_curr_trans.aligned_buffer, host->rx_curr_trans.trans->len); + spicommon_dma_desc_setup_link(hal->dmadesc_rx->desc, host->rx_curr_trans.aligned_buffer, host->rx_curr_trans.trans->len, true); + spi_dma_reset(host->dma_ctx->rx_dma_chan); + spi_slave_hd_hal_rxdma(hal); + spi_dma_start(host->dma_ctx->rx_dma_chan, host->dma_ctx->dmadesc_rx); rx_sent = true; if (callback->cb_recv_dma_ready) { spi_slave_hd_event_t ev = { @@ -528,31 +533,35 @@ static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg) } #if SOC_GDMA_SUPPORTED -// 'spi_gdma_tx_channel_callback' used as spi tx interrupt of append mode on gdma supported target -static IRAM_ATTR bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static IRAM_ATTR bool s_spi_slave_hd_append_gdma_isr(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { assert(event_data); - spi_slave_hd_append_tx_isr(user_data); + spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)user_data; + + host->hal.current_eof_addr = event_data->tx_eof_desc_addr; + if (host->dma_ctx->tx_dma_chan == dma_chan) { + spi_slave_hd_append_tx_isr(user_data); + } else { + spi_slave_hd_append_rx_isr(user_data); + } return true; } -#endif // SOC_GDMA_SUPPORTED -// SPI slave hd append isr entrance -static IRAM_ATTR void spi_slave_hd_intr_append(void *arg) +#else +static IRAM_ATTR void s_spi_slave_hd_append_legacy_isr(void *arg) { spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg; spi_slave_hd_hal_context_t *hal = &host->hal; bool rx_done = false; bool tx_done = false; - // Append Mode portENTER_CRITICAL_ISR(&host->int_spinlock); if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_RECV)) { + hal->current_eof_addr = spi_dma_get_eof_desc(host->dma_ctx->rx_dma_chan); rx_done = true; } if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_SEND)) { - // NOTE: on gdma supported chips, this flag should NOT checked out, handle entrance is only `spi_gdma_tx_channel_callback`, - // otherwise, here should be target limited. + hal->current_eof_addr = spi_dma_get_eof_desc(host->dma_ctx->tx_dma_chan); tx_done = true; } portEXIT_CRITICAL_ISR(&host->int_spinlock); @@ -564,6 +573,7 @@ static IRAM_ATTR void spi_slave_hd_intr_append(void *arg) spi_slave_hd_append_tx_isr(arg); } } +#endif // SOC_GDMA_SUPPORTED static void s_spi_slave_hd_destroy_priv_trans(spi_host_device_t host, spi_slave_hd_trans_priv_t *priv_trans, spi_slave_chan_t chan) { @@ -626,6 +636,88 @@ static esp_err_t get_ret_queue_result(spi_host_device_t host_id, spi_slave_chan_ return ESP_OK; } +esp_err_t s_spi_slave_hd_append_txdma(spi_slave_hd_slot_t *host, uint8_t *data, size_t len, void *arg) +{ + spi_slave_hd_hal_context_t *hal = &host->hal; + + //Check if there are enough available DMA descriptors for software to use + int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC; + int not_recycled_desc_num = hal->tx_used_desc_cnt - hal->tx_recycled_desc_cnt; + int available_desc_num = hal->dma_desc_num - not_recycled_desc_num; + if (num_required > available_desc_num) { + return ESP_ERR_INVALID_STATE; + } + + spicommon_dma_desc_setup_link(hal->tx_cur_desc->desc, data, len, false); + hal->tx_cur_desc->arg = arg; + + if (!hal->tx_dma_started) { + hal->tx_dma_started = true; + //start a link + hal->tx_dma_tail = hal->tx_cur_desc; + spi_dma_reset(host->dma_ctx->tx_dma_chan); + spi_slave_hd_hal_hw_prepare_tx(hal); + spi_dma_start(host->dma_ctx->tx_dma_chan, hal->tx_cur_desc->desc); + } else { + //there is already a consecutive link + ADDR_DMA_2_CPU(hal->tx_dma_tail->desc)->next = hal->tx_cur_desc->desc; + hal->tx_dma_tail = hal->tx_cur_desc; + spi_dma_append(host->dma_ctx->tx_dma_chan); + } + + //Move the current descriptor pointer according to the number of the linked descriptors + for (int i = 0; i < num_required; i++) { + hal->tx_used_desc_cnt++; + hal->tx_cur_desc++; + if (hal->tx_cur_desc == hal->dmadesc_tx + hal->dma_desc_num) { + hal->tx_cur_desc = hal->dmadesc_tx; + } + } + + return ESP_OK; +} + +esp_err_t s_spi_slave_hd_append_rxdma(spi_slave_hd_slot_t *host, uint8_t *data, size_t len, void *arg) +{ + spi_slave_hd_hal_context_t *hal = &host->hal; + + //Check if there are enough available dma descriptors for software to use + int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC; + int not_recycled_desc_num = hal->rx_used_desc_cnt - hal->rx_recycled_desc_cnt; + int available_desc_num = hal->dma_desc_num - not_recycled_desc_num; + if (num_required > available_desc_num) { + return ESP_ERR_INVALID_STATE; + } + + spicommon_dma_desc_setup_link(hal->rx_cur_desc->desc, data, len, false); + hal->rx_cur_desc->arg = arg; + + if (!hal->rx_dma_started) { + hal->rx_dma_started = true; + //start a link + hal->rx_dma_tail = hal->rx_cur_desc; + spi_dma_reset(host->dma_ctx->rx_dma_chan); + spi_slave_hd_hal_hw_prepare_rx(hal); + spi_dma_start(host->dma_ctx->rx_dma_chan, hal->rx_cur_desc->desc); + } else { + //there is already a consecutive link + ADDR_DMA_2_CPU(hal->rx_dma_tail->desc)->next = hal->rx_cur_desc->desc; + hal->rx_dma_tail = hal->rx_cur_desc; + spi_dma_append(host->dma_ctx->rx_dma_chan); + } + + //Move the current descriptor pointer according to the number of the linked descriptors + for (int i = 0; i < num_required; i++) { + hal->rx_used_desc_cnt++; + hal->rx_cur_desc++; + if (hal->rx_cur_desc == hal->dmadesc_rx + hal->dma_desc_num) { + hal->rx_cur_desc = hal->dmadesc_rx; + } + } + + return ESP_OK; +} + //---------------------------------------------------------Segment Mode Transaction APIs-----------------------------------------------------------// esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t *trans, TickType_t timeout) { @@ -682,7 +774,6 @@ esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t { esp_err_t err; spi_slave_hd_slot_t *host = spihost[host_id]; - spi_slave_hd_hal_context_t *hal = &host->hal; SPIHD_CHECK(trans->len <= SPI_MAX_DMA_LEN, "Currently we only support transaction with data length within 4092 bytes", ESP_ERR_INVALID_ARG); SPIHD_CHECK(host->append_mode == 1, "This API should be used for SPI Slave HD Append Mode", ESP_ERR_INVALID_STATE); @@ -698,13 +789,13 @@ esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t if (ret == pdFALSE) { return ESP_ERR_TIMEOUT; } - err = spi_slave_hd_hal_txdma_append(hal, hd_priv_trans.aligned_buffer, trans->len, trans); + err = s_spi_slave_hd_append_txdma(host, hd_priv_trans.aligned_buffer, trans->len, trans); } else { BaseType_t ret = xSemaphoreTake(host->rx_cnting_sem, timeout); if (ret == pdFALSE) { return ESP_ERR_TIMEOUT; } - err = spi_slave_hd_hal_rxdma_append(hal, hd_priv_trans.aligned_buffer, trans->len, trans); + err = s_spi_slave_hd_append_rxdma(host, hd_priv_trans.aligned_buffer, trans->len, trans); } if (err != ESP_OK) { ESP_LOGE(TAG, "Wait until the DMA finishes its transaction"); diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index ce29ccc1ef..67adaefd0b 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -1079,10 +1079,10 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.wr_buf_done, slv_wrbuf_dlen.wr_buf_done=0) \ item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.rd_dma_done, slv_rd_byte.rd_dma_done=0) \ item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.wr_dma_done, slave1.wr_dma_done=0) \ + item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \ item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof, dma_int_raw.in_suc_eof, dma_int_clr.in_suc_eof=1) \ item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \ item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \ - item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \ item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \ item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \ item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ diff --git a/components/hal/include/hal/spi_slave_hd_hal.h b/components/hal/include/hal/spi_slave_hd_hal.h index bf522ac18b..25e40d7b6f 100644 --- a/components/hal/include/hal/spi_slave_hd_hal.h +++ b/components/hal/include/hal/spi_slave_hd_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -84,11 +84,7 @@ typedef struct { /// Configuration of the HAL typedef struct { uint32_t host_id; ///< Host ID of the spi peripheral - spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address - spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address bool dma_enabled; ///< DMA enabled or not - uint32_t tx_dma_chan; ///< TX DMA channel used. - uint32_t rx_dma_chan; ///< RX DMA channel used. bool append_mode; ///< True for DMA append mode, false for segment mode uint32_t spics_io_num; ///< CS GPIO pin for this device uint8_t mode; ///< SPI mode (0-3) @@ -110,13 +106,10 @@ typedef struct { /* address of the hardware */ spi_dev_t *dev; ///< Beginning address of the peripheral registers. - spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. bool dma_enabled; ///< DMA enabled or not - uint32_t tx_dma_chan; ///< TX DMA channel used. - uint32_t rx_dma_chan; ///< RX DMA channel used. bool append_mode; ///< True for DMA append mode, false for segment mode uint32_t dma_desc_num; ///< Number of the available DMA descriptors. Calculated from ``bus_max_transfer_size``. + uint32_t current_eof_addr; spi_slave_hd_hal_desc_append_t *tx_cur_desc; ///< Current TX DMA descriptor that could be linked (set up). spi_slave_hd_hal_desc_append_t *tx_dma_head; ///< Head of the linked TX DMA descriptors which are not used by hardware spi_slave_hd_hal_desc_append_t *tx_dma_tail; ///< Tail of the linked TX DMA descriptors which are not used by hardware @@ -165,7 +158,7 @@ bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_eve bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); /** - * @brief Enable to invole the ISR of corresponding event. + * @brief Enable to involve the ISR of corresponding event. * * @note The function, compared with :cpp:func:`spi_slave_hd_hal_enable_event_intr`, contains a * workaround to force trigger the interrupt, even if the interrupt source cannot be initialized @@ -194,7 +187,7 @@ void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_eve * @param[out] out_buf Buffer to receive the data * @param len Maximul length to receive */ -void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len); +void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal); /** * @brief Get the length of total received data @@ -204,6 +197,13 @@ void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, s */ int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal); +/** + * @brief Prepare hardware for a new dma rx trans + * + * @param hal Context of the HAL layer + */ +void spi_slave_hd_hal_hw_prepare_rx(spi_slave_hd_hal_context_t *hal); + //////////////////////////////////////////////////////////////////////////////// // TX DMA //////////////////////////////////////////////////////////////////////////////// @@ -214,7 +214,14 @@ int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal); * @param data Buffer of data to send * @param len Size of the buffer, also the maximum length to send */ -void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len); +void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal); + +/** + * @brief Prepare hardware for a new dma tx trans + * + * @param hal Context of the HAL layer + */ +void spi_slave_hd_hal_hw_prepare_tx(spi_slave_hd_hal_context_t *hal); //////////////////////////////////////////////////////////////////////////////// // Shared buffer @@ -223,7 +230,7 @@ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size * @brief Read from the shared register buffer * * @param hal Context of the HAL layer - * @param addr Address of the shared regsiter to read + * @param addr Address of the shared register to read * @param out_data Buffer to store the read data * @param len Length to read from the shared buffer */ @@ -294,7 +301,7 @@ bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, voi * @param hal Context of the HAL layer * @param data Buffer of the transaction data * @param len Length of the data - * @param arg Pointer used by the caller to indicate the tranaction. Will be returned by ``spi_slave_hd_hal_get_tx_finished_trans`` when transaction is finished + * @param arg Pointer used by the caller to indicate the transaction. Will be returned by ``spi_slave_hd_hal_get_tx_finished_trans`` when transaction is finished * @return * - ESP_OK: on success * - ESP_ERR_INVALID_STATE: Function called in invalid state. @@ -307,7 +314,7 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t * @param hal Context of the HAL layer * @param data Buffer of the transaction data * @param len Length of the data - * @param arg Pointer used by the caller to indicate the tranaction. Will be returned by ``spi_slave_hd_hal_get_rx_finished_trans`` when transaction is finished + * @param arg Pointer used by the caller to indicate the transaction. Will be returned by ``spi_slave_hd_hal_get_rx_finished_trans`` when transaction is finished * @return * - ESP_OK: on success * - ESP_ERR_INVALID_STATE: Function called in invalid state. diff --git a/components/hal/spi_slave_hd_hal.c b/components/hal/spi_slave_hd_hal.c index a62a517269..5839bd3b5a 100644 --- a/components/hal/spi_slave_hd_hal.c +++ b/components/hal/spi_slave_hd_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,79 +14,21 @@ #include "soc/spi_periph.h" #include "soc/lldesc.h" #include "soc/soc_caps.h" -#include "soc/ext_mem_defs.h" #include "hal/spi_slave_hd_hal.h" #include "hal/assert.h" -//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros. -#if SOC_GDMA_SUPPORTED -#if (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AHB) && (SOC_AHB_GDMA_VERSION == 1) -#include "soc/gdma_struct.h" -#include "hal/gdma_ll.h" -#define spi_dma_ll_tx_restart(dev, chan) gdma_ll_tx_restart(&GDMA, chan) -#define spi_dma_ll_rx_restart(dev, chan) gdma_ll_rx_restart(&GDMA, chan) -#define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan) -#define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan) -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable) -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable) -#define spi_dma_ll_get_out_eof_desc_addr(dev, chan) gdma_ll_tx_get_eof_desc_addr(&GDMA, chan) -#define spi_dma_ll_get_in_suc_eof_desc_addr(dev, chan) gdma_ll_rx_get_success_eof_desc_addr(&GDMA, chan) -#define spi_dma_ll_rx_start(dev, chan, addr) do {\ - gdma_ll_rx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ - gdma_ll_rx_start(&GDMA, chan);\ - } while (0) -#define spi_dma_ll_tx_start(dev, chan, addr) do {\ - gdma_ll_tx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ - gdma_ll_tx_start(&GDMA, chan);\ - } while (0) - -#elif (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) -#include "hal/axi_dma_ll.h" -#define spi_dma_ll_tx_restart(dev, chan) axi_dma_ll_tx_restart(&AXI_DMA, chan) -#define spi_dma_ll_rx_restart(dev, chan) axi_dma_ll_rx_restart(&AXI_DMA, chan) -#define spi_dma_ll_rx_reset(dev, chan) axi_dma_ll_rx_reset_channel(&AXI_DMA, chan) -#define spi_dma_ll_tx_reset(dev, chan) axi_dma_ll_tx_reset_channel(&AXI_DMA, chan) -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) axi_dma_ll_tx_enable_auto_write_back(&AXI_DMA, chan, enable) -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) axi_dma_ll_tx_set_eof_mode(&AXI_DMA, chan, enable) -#define spi_dma_ll_get_out_eof_desc_addr(dev, chan) axi_dma_ll_tx_get_eof_desc_addr(&AXI_DMA, chan) -#define spi_dma_ll_get_in_suc_eof_desc_addr(dev, chan) axi_dma_ll_rx_get_success_eof_desc_addr(&AXI_DMA, chan) -#define spi_dma_ll_rx_start(dev, chan, addr) do {\ - axi_dma_ll_rx_set_desc_addr(&AXI_DMA, chan, (uint32_t)addr);\ - axi_dma_ll_rx_start(&AXI_DMA, chan);\ - } while (0) -#define spi_dma_ll_tx_start(dev, chan, addr) do {\ - axi_dma_ll_tx_set_desc_addr(&AXI_DMA, chan, (uint32_t)addr);\ - axi_dma_ll_tx_start(&AXI_DMA, chan);\ - } while (0) -#endif -#endif //SOC_GDMA_SUPPORTED - -static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal) -{ - spi_dma_ll_enable_out_auto_wrback(hal->dma_out, hal->tx_dma_chan, 1); - spi_dma_ll_set_out_eof_generation(hal->dma_out, hal->tx_dma_chan, 1); -} void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config) { spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id); hal->dev = hw; - hal->dma_in = hal_config->dma_in; - hal->dma_out = hal_config->dma_out; hal->dma_enabled = hal_config->dma_enabled; - hal->tx_dma_chan = hal_config->tx_dma_chan; - hal->rx_dma_chan = hal_config->rx_dma_chan; hal->append_mode = hal_config->append_mode; hal->tx_cur_desc = hal->dmadesc_tx; hal->rx_cur_desc = hal->dmadesc_rx; hal->tx_dma_head = hal->dmadesc_tx + hal->dma_desc_num -1; hal->rx_dma_head = hal->dmadesc_rx + hal->dma_desc_num -1; - //Configure slave - if (hal_config->dma_enabled) { - s_spi_slave_hd_hal_dma_init_config(hal); - } - spi_ll_slave_hd_init(hw); spi_ll_set_addr_bitlen(hw, hal_config->address_bits); spi_ll_set_command_bitlen(hw, hal_config->command_bits); @@ -115,11 +57,8 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE); } } else { -#if SOC_GDMA_SUPPORTED - spi_ll_enable_intr(hw, SPI_LL_INTR_CMD7); -#else - spi_ll_clear_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7); - spi_ll_enable_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7); +#if !SOC_GDMA_SUPPORTED + spi_ll_enable_intr(hw, SPI_LL_INTR_CMD7 | SPI_LL_INTR_CMD8); #endif //SOC_GDMA_SUPPORTED } @@ -132,42 +71,14 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h } #if SOC_NON_CACHEABLE_OFFSET -#define ADDR_DMA_2_CPU(addr) ((typeof(addr))((uint32_t)(addr) + 0x40000000)) -#define ADDR_CPU_2_DMA(addr) ((typeof(addr))((uint32_t)(addr) - 0x40000000)) +#include "hal/cache_ll.h" +#define ADDR_DMA_2_CPU(addr) ((typeof(addr))CACHE_LL_L2MEM_NON_CACHE_ADDR(addr)) +#define ADDR_CPU_2_DMA(addr) ((typeof(addr))CACHE_LL_L2MEM_CACHE_ADDR(addr)) #else #define ADDR_DMA_2_CPU(addr) (addr) #define ADDR_CPU_2_DMA(addr) (addr) #endif -static void s_spi_hal_dma_desc_setup_link(spi_dma_desc_t *dmadesc, const void *data, int len, bool is_rx) -{ - dmadesc = ADDR_DMA_2_CPU(dmadesc); - int n = 0; - while (len) { - int dmachunklen = len; - if (dmachunklen > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) { - dmachunklen = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; - } - if (is_rx) { - //Receive needs DMA length rounded to next 32-bit boundary - dmadesc[n].dw0.size = (dmachunklen + 3) & (~3); - dmadesc[n].dw0.length = (dmachunklen + 3) & (~3); - } else { - dmadesc[n].dw0.size = dmachunklen; - dmadesc[n].dw0.length = dmachunklen; - } - dmadesc[n].buffer = (uint8_t *)data; - dmadesc[n].dw0.suc_eof = 0; - dmadesc[n].dw0.owner = 1; - dmadesc[n].next = ADDR_CPU_2_DMA(&dmadesc[n + 1]); - len -= dmachunklen; - data += dmachunklen; - n++; - } - dmadesc[n - 1].dw0.suc_eof = 1; //Mark last DMA desc as end of stream. - dmadesc[n - 1].next = NULL; -} - static int s_desc_get_received_len_addr(spi_dma_desc_t* head, spi_dma_desc_t** out_next, void **out_buff_head) { spi_dma_desc_t* desc_cpu = ADDR_DMA_2_CPU(head); @@ -188,41 +99,38 @@ static int s_desc_get_received_len_addr(spi_dma_desc_t* head, spi_dma_desc_t** o return len; } -void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len) +void spi_slave_hd_hal_hw_prepare_rx(spi_slave_hd_hal_context_t *hal) { - s_spi_hal_dma_desc_setup_link(hal->dmadesc_rx->desc, out_buf, len, true); - spi_ll_dma_rx_fifo_reset(hal->dev); - spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); - spi_ll_slave_reset(hal->dev); spi_ll_infifo_full_clr(hal->dev); - spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7); - spi_ll_dma_rx_enable(hal->dev, 1); - spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, (lldesc_t *)hal->dmadesc_rx->desc); } -void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len) +void spi_slave_hd_hal_hw_prepare_tx(spi_slave_hd_hal_context_t *hal) { - s_spi_hal_dma_desc_setup_link(hal->dmadesc_tx->desc, data, len, false); - spi_ll_dma_tx_fifo_reset(hal->dev); - spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); - spi_ll_slave_reset(hal->dev); spi_ll_outfifo_empty_clr(hal->dev); - spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8); - spi_ll_dma_tx_enable(hal->dev, 1); - spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, (lldesc_t *)hal->dmadesc_tx->desc); +} + +void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal) +{ + spi_ll_slave_reset(hal->dev); + spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7); + spi_slave_hd_hal_hw_prepare_rx(hal); +} + +void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal) +{ + spi_ll_slave_reset(hal->dev); + spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8); + spi_slave_hd_hal_hw_prepare_tx(hal); } static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev) { spi_ll_intr_t intr = 0; -#if CONFIG_IDF_TARGET_ESP32S2 - if ((ev & SPI_EV_SEND) && hal->append_mode) intr |= SPI_LL_INTR_OUT_EOF; -#endif - if ((ev & SPI_EV_SEND) && !hal->append_mode) intr |= SPI_LL_INTR_CMD8; + if (ev & SPI_EV_SEND) intr |= SPI_LL_INTR_CMD8; if (ev & SPI_EV_RECV) intr |= SPI_LL_INTR_CMD7; if (ev & SPI_EV_BUF_TX) intr |= SPI_LL_INTR_RDBUF; if (ev & SPI_EV_BUF_RX) intr |= SPI_LL_INTR_WRBUF; @@ -315,8 +223,7 @@ int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal) bool spi_slave_hd_hal_get_tx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, void **real_buff_addr) { - uint32_t desc_now = spi_dma_ll_get_out_eof_desc_addr(hal->dma_out, hal->tx_dma_chan); - if ((uint32_t)hal->tx_dma_head->desc == desc_now) { + if ((uint32_t)hal->tx_dma_head->desc == hal->current_eof_addr) { return false; } @@ -333,8 +240,7 @@ bool spi_slave_hd_hal_get_tx_finished_trans(spi_slave_hd_hal_context_t *hal, voi bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, void **real_buff_addr, size_t *out_len) { - uint32_t desc_now = spi_dma_ll_get_in_suc_eof_desc_addr(hal->dma_in, hal->rx_dma_chan); - if ((uint32_t)hal->rx_dma_head->desc == desc_now) { + if ((uint32_t)hal->rx_dma_head->desc == hal->current_eof_addr) { return false; } @@ -348,85 +254,3 @@ bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, voi hal->rx_recycled_desc_cnt++; return true; } - -esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg) -{ - //Check if there are enough available DMA descriptors for software to use - int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC; - int not_recycled_desc_num = hal->tx_used_desc_cnt - hal->tx_recycled_desc_cnt; - int available_desc_num = hal->dma_desc_num - not_recycled_desc_num; - if (num_required > available_desc_num) { - return ESP_ERR_INVALID_STATE; - } - - s_spi_hal_dma_desc_setup_link(hal->tx_cur_desc->desc, data, len, false); - hal->tx_cur_desc->arg = arg; - - if (!hal->tx_dma_started) { - hal->tx_dma_started = true; - //start a link - hal->tx_dma_tail = hal->tx_cur_desc; - spi_ll_dma_tx_fifo_reset(hal->dma_out); - spi_ll_outfifo_empty_clr(hal->dev); - spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); - spi_ll_dma_tx_enable(hal->dev, 1); - spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, (lldesc_t *)hal->tx_cur_desc->desc); - } else { - //there is already a consecutive link - ADDR_DMA_2_CPU(hal->tx_dma_tail->desc)->next = hal->tx_cur_desc->desc; - hal->tx_dma_tail = hal->tx_cur_desc; - spi_dma_ll_tx_restart(hal->dma_out, hal->tx_dma_chan); - } - - //Move the current descriptor pointer according to the number of the linked descriptors - for (int i = 0; i < num_required; i++) { - hal->tx_used_desc_cnt++; - hal->tx_cur_desc++; - if (hal->tx_cur_desc == hal->dmadesc_tx + hal->dma_desc_num) { - hal->tx_cur_desc = hal->dmadesc_tx; - } - } - - return ESP_OK; -} - -esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg) -{ - //Check if there are enough available dma descriptors for software to use - int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC; - int not_recycled_desc_num = hal->rx_used_desc_cnt - hal->rx_recycled_desc_cnt; - int available_desc_num = hal->dma_desc_num - not_recycled_desc_num; - if (num_required > available_desc_num) { - return ESP_ERR_INVALID_STATE; - } - - s_spi_hal_dma_desc_setup_link(hal->rx_cur_desc->desc, data, len, false); - hal->rx_cur_desc->arg = arg; - - if (!hal->rx_dma_started) { - hal->rx_dma_started = true; - //start a link - hal->rx_dma_tail = hal->rx_cur_desc; - spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); - spi_ll_dma_rx_fifo_reset(hal->dma_in); - spi_ll_infifo_full_clr(hal->dev); - spi_ll_dma_rx_enable(hal->dev, 1); - spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, (lldesc_t *)hal->rx_cur_desc->desc); - } else { - //there is already a consecutive link - ADDR_DMA_2_CPU(hal->rx_dma_tail->desc)->next = hal->rx_cur_desc->desc; - hal->rx_dma_tail = hal->rx_cur_desc; - spi_dma_ll_rx_restart(hal->dma_in, hal->rx_dma_chan); - } - - //Move the current descriptor pointer according to the number of the linked descriptors - for (int i = 0; i < num_required; i++) { - hal->rx_used_desc_cnt++; - hal->rx_cur_desc++; - if (hal->rx_cur_desc == hal->dmadesc_rx + hal->dma_desc_num) { - hal->rx_cur_desc = hal->dmadesc_rx; - } - } - - return ESP_OK; -}