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dedic_gpio: support on esp32s3

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This commit is contained in:
morris
2021-06-30 11:23:02 +08:00
parent 9df57b3ae6
commit c8c3015018
6 changed files with 32 additions and 25 deletions
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2
components/driver/dedic_gpio.c
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@@ -64,7 +64,7 @@ struct dedic_gpio_bundle_t {
uint32_t out_offset; // offset in the bank (seen from output channel) uint32_t out_offset; // offset in the bank (seen from output channel)
uint32_t in_offset; // offset in the bank (seen from input channel) uint32_t in_offset; // offset in the bank (seen from input channel)
size_t nr_gpio; // number of GPIOs in the gpio_array size_t nr_gpio; // number of GPIOs in the gpio_array
int gpio_array[0]; // array of GPIO numbers (configured by user) int gpio_array[]; // array of GPIO numbers (configured by user)
}; };
static esp_err_t dedic_gpio_build_platform(uint32_t core_id) static esp_err_t dedic_gpio_build_platform(uint32_t core_id)

8
components/driver/include/driver/dedic_gpio.h
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@@ -30,10 +30,10 @@ typedef struct {
const int *gpio_array; /*!< Array of GPIO numbers, gpio_array[0] ~ gpio_array[size-1] <=> low_dedic_channel_num ~ high_dedic_channel_num */ const int *gpio_array; /*!< Array of GPIO numbers, gpio_array[0] ~ gpio_array[size-1] <=> low_dedic_channel_num ~ high_dedic_channel_num */
size_t array_size; /*!< Number of GPIOs in gpio_array */ size_t array_size; /*!< Number of GPIOs in gpio_array */
struct { struct {
int in_en: 1; /*!< Enable input */ unsigned int in_en: 1; /*!< Enable input */
int in_invert: 1; /*!< Invert input signal */ unsigned int in_invert: 1; /*!< Invert input signal */
int out_en: 1; /*!< Enable output */ unsigned int out_en: 1; /*!< Enable output */
int out_invert: 1; /*!< Invert output signal */ unsigned int out_invert: 1; /*!< Invert output signal */
} flags; /*!< Flags to control specific behaviour of GPIO bundle */ } flags; /*!< Flags to control specific behaviour of GPIO bundle */
} dedic_gpio_bundle_config_t; } dedic_gpio_bundle_config_t;

4
components/driver/test/test_dedicated_gpio.c
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@@ -58,8 +58,6 @@ TEST_CASE("Dedicated GPIO bundle install/uninstall", "[dedic_gpio]")
#define TEST_GPIO_GROUP_SIZE (4) #define TEST_GPIO_GROUP_SIZE (4)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
// TODO ESP32-S3 IDF-3387
typedef struct { typedef struct {
SemaphoreHandle_t sem; SemaphoreHandle_t sem;
const int gpios[TEST_GPIO_GROUP_SIZE]; const int gpios[TEST_GPIO_GROUP_SIZE];
@@ -161,8 +159,6 @@ TEST_CASE("Dedicated GPIO run on multiple CPU core", "[dedic_gpio]")
vSemaphoreDelete(sem); vSemaphoreDelete(sem);
} }
#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
IRAM_ATTR static void test_dedic_gpio_isr_callback(void *args) IRAM_ATTR static void test_dedic_gpio_isr_callback(void *args)
{ {
SemaphoreHandle_t sem = (SemaphoreHandle_t)args; SemaphoreHandle_t sem = (SemaphoreHandle_t)args;

7
components/hal/esp32s3/include/hal/cpu_ll.h
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@@ -203,12 +203,7 @@ static inline void cpu_ll_write_dedic_gpio_all(uint32_t value)
static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value) static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value)
{ {
// ToDo: check if ESP32-S3 supports mask write instruction asm volatile("ee.wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):);
uint32_t orig = 0;
asm volatile("rur.gpio_out %0" : "=r"(orig) : :);
orig &= ~mask;
orig |= value & mask;
asm volatile("wur.gpio_out %0"::"r"(orig):);
} }
#ifdef __cplusplus #ifdef __cplusplus

32
components/soc/esp32s3/dedic_gpio_periph.c
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@@ -25,26 +25,42 @@ const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
[1] = PRO_ALONEGPIO_IN1_IDX, [1] = PRO_ALONEGPIO_IN1_IDX,
[2] = PRO_ALONEGPIO_IN2_IDX, [2] = PRO_ALONEGPIO_IN2_IDX,
[3] = PRO_ALONEGPIO_IN3_IDX, [3] = PRO_ALONEGPIO_IN3_IDX,
[4] = PRO_ALONEGPIO_IN4_IDX,
[5] = PRO_ALONEGPIO_IN5_IDX,
[6] = PRO_ALONEGPIO_IN6_IDX,
[7] = PRO_ALONEGPIO_IN7_IDX,
}, },
.out_sig_per_channel = { .out_sig_per_channel = {
[0] = PRO_ALONEGPIO_OUT0_IDX, [0] = PRO_ALONEGPIO_OUT0_IDX,
[1] = PRO_ALONEGPIO_OUT1_IDX, [1] = PRO_ALONEGPIO_OUT1_IDX,
[2] = PRO_ALONEGPIO_OUT2_IDX, [2] = PRO_ALONEGPIO_OUT2_IDX,
[3] = PRO_ALONEGPIO_OUT3_IDX, [3] = PRO_ALONEGPIO_OUT3_IDX,
[4] = PRO_ALONEGPIO_OUT4_IDX,
[5] = PRO_ALONEGPIO_OUT5_IDX,
[6] = PRO_ALONEGPIO_OUT6_IDX,
[7] = PRO_ALONEGPIO_OUT7_IDX,
} }
}, },
[1] = { [1] = {
.in_sig_per_channel = { .in_sig_per_channel = {
[0] = PRO_ALONEGPIO_IN4_IDX, [0] = CORE1_GPIO_IN0_IDX,
[1] = PRO_ALONEGPIO_IN5_IDX, [1] = CORE1_GPIO_IN1_IDX,
[2] = PRO_ALONEGPIO_IN6_IDX, [2] = CORE1_GPIO_IN2_IDX,
[3] = PRO_ALONEGPIO_IN7_IDX, [3] = CORE1_GPIO_IN3_IDX,
[4] = CORE1_GPIO_IN4_IDX,
[5] = CORE1_GPIO_IN5_IDX,
[6] = CORE1_GPIO_IN6_IDX,
[7] = CORE1_GPIO_IN7_IDX,
}, },
.out_sig_per_channel = { .out_sig_per_channel = {
[0] = PRO_ALONEGPIO_OUT4_IDX, [0] = CORE1_GPIO_OUT0_IDX,
[1] = PRO_ALONEGPIO_OUT5_IDX, [1] = CORE1_GPIO_OUT1_IDX,
[2] = PRO_ALONEGPIO_OUT6_IDX, [2] = CORE1_GPIO_OUT2_IDX,
[3] = PRO_ALONEGPIO_OUT7_IDX, [3] = CORE1_GPIO_OUT3_IDX,
[4] = CORE1_GPIO_OUT4_IDX,
[5] = CORE1_GPIO_OUT5_IDX,
[6] = CORE1_GPIO_OUT6_IDX,
[7] = CORE1_GPIO_OUT7_IDX,
} }
}, },
}, },

4
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -44,8 +44,8 @@
#include "gpio_caps.h" #include "gpio_caps.h"
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (4) /*!< 4 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (4) /*!< 4 inward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
/*-------------------------- I2C CAPS ----------------------------------------*/ /*-------------------------- I2C CAPS ----------------------------------------*/
#include "i2c_caps.h" #include "i2c_caps.h"