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feat(psram): support 16Mbit PSRAM for esp32

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chenjianqiang
2020-07-03 22:13:00 +08:00
parent 6a253e8809
commit c945cb59d8
2 changed files with 8 additions and 2 deletions
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4
components/esp32/Kconfig
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@ -72,6 +72,9 @@ menu "ESP32-specific"
config SPIRAM_TYPE_AUTO config SPIRAM_TYPE_AUTO
bool "Auto-detect" bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32 config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32 or IS25WP032" bool "ESP-PSRAM32 or IS25WP032"
@ -83,6 +86,7 @@ menu "ESP32-specific"
config SPIRAM_SIZE config SPIRAM_SIZE
int int
default -1 if SPIRAM_TYPE_AUTO default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32 default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0 default 0

6
components/esp32/spiram.c
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@ -114,12 +114,14 @@ bool esp_spiram_test(void)
void IRAM_ATTR esp_spiram_init_cache(void) void IRAM_ATTR esp_spiram_init_cache(void)
{ {
int size = esp_spiram_get_size();
if (size > 4 * 1024 * 1024) size = 4 * 1024 * 1024; // we can map at most 4MByte
//Enable external RAM in MMU //Enable external RAM in MMU
cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 ); cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, (size / 1024 / 32));
//Flush and enable icache for APP CPU //Flush and enable icache for APP CPU
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1); DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 ); cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, (size / 1024 / 32));
#endif #endif
} }