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Merge branch 'fix/memory-layout-c6' into 'master'

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soc: Fix memory layout for esp32c6

Closes IDF-5627

See merge request espressif/esp-idf!21894
This commit is contained in:
Mahavir Jain
2023-01-08 21:51:21 +08:00
parent 23fd449450 b8a4988451
commit c948a70895
3 changed files with 6 additions and 6 deletions
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4
components/heap/port/esp32c6/memory_layout.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -69,7 +69,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
const soc_memory_region_t soc_memory_regions[] = { const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory { 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory { 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level2, can be used as trace memory { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level2, can be used as trace memory
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area) { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP

4
components/soc/esp32c6/include/soc/soc.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -26,7 +26,7 @@
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 #define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
#define REG_TWAI_BASE(i) (DR_REG_TWAI_BASE + (i) * 0x2000) // TWAI0 and TWAI1 #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
//Registers Operation {{ //Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_UNCACHED_ADDR(addr) (addr)

4
tools/idf_size_yaml/esp32c6_data_info.yaml
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@@ -8,10 +8,10 @@ DRAM:
secondary_address: 0x40800000 secondary_address: 0x40800000
CACHE_I: CACHE_I:
primary_address: 0x42000000 primary_address: 0x42000000
length: 0x800000 length: 0x1000000
CACHE_D: CACHE_D:
primary_address: 0x42000000 primary_address: 0x42000000
length: 0x800000 length: 0x1000000
RTC_SLOW_D: # TODO: IDF-5667 Better to rename to LP_RAM RTC_SLOW_D: # TODO: IDF-5667 Better to rename to LP_RAM
primary_address: 0x50000000 primary_address: 0x50000000
length: 0x4000 length: 0x4000