Merge branch 'feature/enable_hal_util_host_test' into 'master'

feat(hal): enable hal host test

Closes IDF-8275

See merge request espressif/esp-idf!26384

components/efuse/test_apps/README.md

@@ -1,3 +1,3 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 

components/esp_rom/linux/esp_rom_sys.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +16,8 @@ static void call_linux_putc(char c);
 
 static void (*s_esp_rom_putc)(char c) = call_linux_putc;
 
-static void call_linux_putc(char c) {
+static void call_linux_putc(char c)
+{
     putc(c, stdout);
 }
 
@@ -52,7 +53,7 @@ static int _cvt(unsigned long long val, char *buf, long radix, const char *digit
 static int esp_rom_vprintf(void (*putc)(char c), const char *fmt, va_list ap)
 {
 #ifdef BINARY_SUPPORT
-    char buf[sizeof(long long)*8];
+    char buf[sizeof(long long) * 8];
     int i;
 #else
     char buf[32];
@@ -118,7 +119,7 @@ static int esp_rom_vprintf(void (*putc)(char c), const char *fmt, va_list ap)
                     val = va_arg(ap, long long);
                 } else if (islong) {
                     val = (long long)va_arg(ap, long);
-                } else{
+                } else {
                     val = (long long)va_arg(ap, int);
                 }
                 if ((c == 'd') || (c == 'D')) {
@@ -129,7 +130,7 @@ static int esp_rom_vprintf(void (*putc)(char c), const char *fmt, va_list ap)
                 } else {
                     if (islong) {
                         val &= (((long long)1) << (sizeof(long) * 8)) - 1;
-                    } else{
+                    } else {
                         val &= (((long long)1) << (sizeof(int) * 8)) - 1;
                     }
                 }
@@ -143,7 +144,7 @@ static int esp_rom_vprintf(void (*putc)(char c), const char *fmt, va_list ap)
                 (*putc)('0');
                 (*putc)('x');
                 zero_fill = true;
-                left_prec = sizeof(unsigned long)*2;
+                left_prec = sizeof(unsigned long) * 2;
             case 'd':
             case 'D':
             case 'u':
@@ -286,3 +287,11 @@ soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no)
 {
     return RESET_REASON_CHIP_POWER_ON;
 }
+
+void __assert_func(const char *file, int line, const char *func, const char *failedexpr)
+{
+    esp_rom_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
+                   failedexpr, file, line,
+                   func ? ", function: " : "", func ? func : "");
+    while (1) {}
+}

components/hal/.build-test-rules.yml

@@ -1,7 +1,3 @@
 components/hal/test_apps/hal_utils:
   enable:
     - if: IDF_TARGET == "linux"
-  disable:
-    - if: IDF_TARGET == "linux"
-      temporary: true
-      reason: env not ready

components/hal/CMakeLists.txt

@@ -1,52 +1,51 @@
-
 idf_build_get_property(target IDF_TARGET)
 
-# On Linux, there is currently no HAL, hence this simple component registration
+set(srcs "hal_utils.c")
-if(${target} STREQUAL "linux")
+set(includes "platform_port/include")
-    idf_component_register()
+
-    return()
+# target specific include must be added before the generic one
+# becuase of the "include_next" directive used by the efuse_hal.h
+if(NOT ${target} STREQUAL "linux")
+    list(APPEND includes "${target}/include")
+endif()
+list(APPEND includes "include")
+
+if(CONFIG_SOC_MPU_SUPPORTED)
+    list(APPEND srcs "mpu_hal.c")
 endif()
 
-set(srcs "mpu_hal.c"
+if(CONFIG_SOC_EFUSE_SUPPORTED)
-         "efuse_hal.c"
+    list(APPEND srcs "efuse_hal.c" "${target}/efuse_hal.c")
-         "hal_utils.c"
-         "${target}/efuse_hal.c")
-
-
-set(includes "${target}/include" "include" "platform_port/include")
-
-if(NOT CONFIG_HAL_WDT_USE_ROM_IMPL)
-    list(APPEND srcs "wdt_hal_iram.c")
-endif()
-
-if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
-    list(APPEND srcs "mmu_hal.c")
-
-    # We wrap Cache ROM APIs as Cache HAL APIs for: 1. internal ram ; 2. unified APIs
-    # ESP32 cache structure / ROM APIs are different and we have a patch `cache_hal_esp32.c` for it.
-    if(${target} STREQUAL "esp32")
-        list(APPEND srcs "esp32/cache_hal_esp32.c")
-    else()
-        list(APPEND srcs "cache_hal.c")
-    endif()
 endif()
 
 if(CONFIG_SOC_LP_TIMER_SUPPORTED)
     list(APPEND srcs "lp_timer_hal.c")
 endif()
 
+if(CONFIG_SOC_WDT_SUPPORTED AND NOT CONFIG_HAL_WDT_USE_ROM_IMPL)
+    list(APPEND srcs "wdt_hal_iram.c")
+endif()
+
+if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
+    if(CONFIG_SOC_MMU_PERIPH_NUM)
+        list(APPEND srcs "mmu_hal.c")
+    endif()
+
+    # We wrap Cache ROM APIs as Cache HAL APIs for: 1. internal ram ; 2. unified APIs
+    # ESP32 cache structure / ROM APIs are different and we have a patch `cache_hal_esp32.c` for it.
+    if(${target} STREQUAL "esp32")
+        list(APPEND srcs "esp32/cache_hal_esp32.c")
+    elseif(NOT ${target} STREQUAL "linux")
+        list(APPEND srcs "cache_hal.c")
+    endif()
+endif()
+
 if(NOT BOOTLOADER_BUILD)
-    list(APPEND srcs
-        "rtc_io_hal.c"
-        "gpio_hal.c"
-        "uart_hal.c"
-        "uart_hal_iram.c")
 
     if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
-        list(APPEND srcs
+        if(CONFIG_SOC_SPI_FLASH_SUPPORTED)
-            "spi_flash_hal.c"
+            list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c")
-            "spi_flash_hal_iram.c"
+        endif()
-        )
         if(CONFIG_SOC_FLASH_ENC_SUPPORTED)
             list(APPEND srcs "spi_flash_encrypt_hal_iram.c")
         endif()
@@ -60,6 +59,18 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "systimer_hal.c")
     endif()
 
+    if(CONFIG_SOC_UART_SUPPORTED)
+        list(APPEND srcs "uart_hal.c" "uart_hal_iram.c")
+    endif()
+
+    if(CONFIG_SOC_GPIO_PORT)
+        list(APPEND srcs "gpio_hal.c")
+    endif()
+
+    if(CONFIG_SOC_RTCIO_PIN_COUNT)
+        list(APPEND srcs "rtc_io_hal.c")
+    endif()
+
     if(CONFIG_SOC_GPTIMER_SUPPORTED)
         list(APPEND srcs "timer_hal.c")
     endif()

components/hal/test_apps/hal_utils/pytest_hal_utils.py

@@ -8,4 +8,6 @@ from pytest_embedded import Dut
 @pytest.mark.linux
 @pytest.mark.host_test
 def test_hal_utils(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
+    dut.expect_exact('Press ENTER to see the list of tests.')
+    dut.write('*')
+    dut.expect_unity_test_output()

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -155,6 +155,18 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_MPU_SUPPORTED
+    bool
+    default y
+
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
     int
     default 5

components/soc/esp32/include/soc/soc_caps.h

@@ -98,6 +98,9 @@
 #define SOC_BOD_SUPPORTED           1
 #define SOC_ULP_FSM_SUPPORTED       1
 #define SOC_CLK_TREE_SUPPORTED      1
+#define SOC_MPU_SUPPORTED           1
+#define SOC_WDT_SUPPORTED           1
+#define SOC_SPI_FLASH_SUPPORTED     1
 
 #if SOC_CAPS_ECO_VER < 200
 #define SOC_DPORT_WORKAROUND                   1

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -103,6 +103,14 @@ config SOC_ASSIST_DEBUG_SUPPORTED
     bool
     default y
 
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_26M
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -50,6 +50,8 @@
 #define SOC_BOD_SUPPORTED               1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED            1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_26M            1

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -155,6 +155,14 @@ config SOC_ASSIST_DEBUG_SUPPORTED
     bool
     default y
 
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -66,6 +66,8 @@
 #define SOC_BOD_SUPPORTED               1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -215,6 +215,14 @@ config SOC_ASSIST_DEBUG_SUPPORTED
     bool
     default y
 
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -78,6 +78,8 @@
 #define SOC_ULP_LP_UART_SUPPORTED       1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -199,6 +199,14 @@ config SOC_ASSIST_DEBUG_SUPPORTED
     bool
     default y
 
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_32M
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -75,6 +75,8 @@
 #define SOC_PAU_SUPPORTED               1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_32M            1

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -55,6 +55,10 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
     bool
     default y
 
+config SOC_EFUSE_SUPPORTED
+    bool
+    default y
+
 config SOC_RTC_FAST_MEM_SUPPORTED
     bool
     default y
@@ -127,6 +131,14 @@ config SOC_PSRAM_DMA_CAPABLE
     bool
     default y
 
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -45,7 +45,7 @@
 #define SOC_SUPPORTS_SECURE_DL_MODE     1
 // #define SOC_RISCV_COPROC_SUPPORTED      1
 #define SOC_EFUSE_KEY_PURPOSE_FIELD     1
-// #define SOC_EFUSE_SUPPORTED             1  //TODO: IDF-7512
+#define SOC_EFUSE_SUPPORTED             1
 #define SOC_RTC_FAST_MEM_SUPPORTED      1
 #define SOC_RTC_MEM_SUPPORTED           1
 #define SOC_RMT_SUPPORTED               1
@@ -81,6 +81,8 @@
 // #define SOC_SDMMC_HOST_SUPPORTED        1  //TODO: IDF-6502
 // #define SOC_CLK_TREE_SUPPORTED          1  //TODO: IDF-7526
 // #define SOC_ASSIST_DEBUG_SUPPORTED      1  //TODO: IDF-7565
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -179,6 +179,18 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_MPU_SUPPORTED
+    bool
+    default y
+
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -83,6 +83,9 @@
 #define SOC_TOUCH_SENSOR_SUPPORTED      1
 #define SOC_BOD_SUPPORTED               1
 #define SOC_CLK_TREE_SUPPORTED          1
+#define SOC_MPU_SUPPORTED               1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -219,6 +219,18 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_MPU_SUPPORTED
+    bool
+    default y
+
+config SOC_WDT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -74,6 +74,9 @@
 #define SOC_TOUCH_SENSOR_SUPPORTED      1
 #define SOC_BOD_SUPPORTED               1
 #define SOC_CLK_TREE_SUPPORTED          1
+#define SOC_MPU_SUPPORTED               1
+#define SOC_WDT_SUPPORTED               1
+#define SOC_SPI_FLASH_SUPPORTED         1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

tools/mocks/soc/include/soc/clk_tree_defs.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of SPI clock source.
+ */
+typedef int soc_periph_spi_clk_src_t;
+
+#ifdef __cplusplus
+}
+#endif

tools/mocks/soc/include/soc/gpio_num.h

@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief GPIO number
+ */
+typedef int gpio_num_t;
+
+#ifdef __cplusplus
+}
+#endif