diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml
index 8d4f8c4a09..9790c1495f 100644
--- a/examples/system/.build-test-rules.yml
+++ b/examples/system/.build-test-rules.yml
@@ -82,17 +82,13 @@ examples/system/himem:
 
 examples/system/ipc/ipc_isr/riscv:
   enable:
-    - if: IDF_TARGET_ARCH_RISCV == 1 and ESP_IPC_ISR_ENABLE == 1
+    - if: IDF_TARGET in ["esp32p4"]
       temporary: true
       reason: The test is intended only for multi-core chips
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: lack of runners
 
 examples/system/ipc/ipc_isr/xtensa:
   enable:
-    - if: IDF_TARGET_ARCH_XTENSA == 1 and ESP_IPC_ISR_ENABLE == 1
+    - if: IDF_TARGET in ["esp32", "esp32s3"]
       temporary: true
       reason: The test is intended only for multi-core chips
 
diff --git a/examples/system/ipc/ipc_isr/riscv/README.md b/examples/system/ipc/ipc_isr/riscv/README.md
index df83241e9c..56db61b3c6 100644
--- a/examples/system/ipc/ipc_isr/riscv/README.md
+++ b/examples/system/ipc/ipc_isr/riscv/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32P4 |
-| ----------------- | ------- |
+| Supported Targets | ESP32-P4 |
+| ----------------- | -------- |
 
 # IPC ISR Example
 
diff --git a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
index e0e831ce26..63e87e4307 100644
--- a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
+++ b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
@@ -7,6 +7,7 @@ from pytest_embedded import Dut
 
 @pytest.mark.esp32p4
 @pytest.mark.generic
+@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='lack of runner')
 def test_ipc_isr(dut: Dut) -> None:
     dut.expect_exact('example: Start')
     dut.expect_exact('example: MSTATUS = 0x3880')