From cd9d8bf2e94e552b356a12ec32bc29bb29efa164 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Mon, 5 Aug 2024 15:06:51 +0800 Subject: [PATCH] feat(uart): support uart on ESP32C61 --- .../test_apps/.build-test-rules.yml | 6 -- .../esp_driver_uart/test_apps/rs485/README.md | 4 +- .../esp_driver_uart/test_apps/uart/README.md | 4 +- components/hal/esp32c61/include/hal/uart_ll.h | 75 ++++++++++++------- .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 - .../soc/esp32c61/include/soc/soc_caps.h | 5 +- .../soc/esp32c61/include/soc/uart_channel.h | 12 +-- .../soc/esp32c61/include/soc/uart_pins.h | 18 ++--- .../soc/esp32c61/include/soc/uart_struct.h | 5 +- components/soc/esp32c61/uart_periph.c | 30 ++++---- docs/docs_not_updated/esp32c61.txt | 1 - 11 files changed, 83 insertions(+), 81 deletions(-) diff --git a/components/esp_driver_uart/test_apps/.build-test-rules.yml b/components/esp_driver_uart/test_apps/.build-test-rules.yml index c6916dd7d1..403036b446 100644 --- a/components/esp_driver_uart/test_apps/.build-test-rules.yml +++ b/components/esp_driver_uart/test_apps/.build-test-rules.yml @@ -3,9 +3,6 @@ components/esp_driver_uart/test_apps/rs485: disable: - if: SOC_UART_SUPPORTED != 1 - - if: IDF_TARGET in ["esp32c61"] - temporary: true - reason: IDF-9320 uart driver disable_test: - if: IDF_TARGET != "esp32" temporary: true @@ -17,9 +14,6 @@ components/esp_driver_uart/test_apps/rs485: components/esp_driver_uart/test_apps/uart: disable: - if: SOC_UART_SUPPORTED != 1 - - if: IDF_TARGET in ["esp32c61"] - temporary: true - reason: IDF-9320 uart driver disable_test: - if: IDF_TARGET == "esp32p4" temporary: true diff --git a/components/esp_driver_uart/test_apps/rs485/README.md b/components/esp_driver_uart/test_apps/rs485/README.md index 3a502b1f86..7b96141437 100644 --- a/components/esp_driver_uart/test_apps/rs485/README.md +++ b/components/esp_driver_uart/test_apps/rs485/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_uart/test_apps/uart/README.md b/components/esp_driver_uart/test_apps/uart/README.md index 3a502b1f86..7b96141437 100644 --- a/components/esp_driver_uart/test_apps/uart/README.md +++ b/components/esp_driver_uart/test_apps/uart/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h index fb2dc72b85..c12c9ecc75 100644 --- a/components/hal/esp32c61/include/hal/uart_ll.h +++ b/components/hal/esp32c61/include/hal/uart_ll.h @@ -19,8 +19,7 @@ #include "soc/pcr_struct.h" #include "soc/pcr_reg.h" #include "esp_attr.h" - -// TODO: [ESP32C61] IDF-9320, inherit from c6 +#include "hal/assert.h" #ifdef __cplusplus extern "C" { @@ -29,7 +28,7 @@ extern "C" { // The default fifo depth #define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) // Get UART hardware instance with giving uart num -#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1)) +#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&UART2))) #define UART_LL_MIN_WAKEUP_THRESH (2) #define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask @@ -40,24 +39,30 @@ extern "C" { #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ if ((hw) == &UART0) { \ HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ - } else { \ + } else if ((hw) == &UART1) { \ HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \ + } else { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart2_##reg_suffix, uart2_##field_suffix, (val)) \ } #define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ - (((hw) == &UART0) ? \ - HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ - HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix)) + (((hw) == &UART0) ? HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ + ((hw) == &UART1) ? HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix) : \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart2_##reg_suffix, uart2_##field_suffix)) #define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ if ((hw) == &UART0) { \ PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \ - } else { \ + } else if ((hw) == &UART1) { \ PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \ + } else { \ + PCR.uart2_##reg_suffix.uart2_##field_suffix = (val); \ } #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ - (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix) + (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : \ + ((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \ + PCR.uart2_##reg_suffix.uart2_##field_suffix) // Define UART interrupts typedef enum { @@ -92,14 +97,18 @@ typedef enum { */ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) { - uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : - (uart_num == 1) ? PCR_UART1_CONF_REG : 0); - uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : - (uart_num == 1) ? PCR_UART1_RST_EN : 0); - uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : - (uart_num == 1) ? PCR_UART1_CLK_EN : 0); - return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && - REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; + switch (uart_num) { + case 0: + return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en; + case 1: // UART_1 + return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en; + case 2: // UART_2 + return PCR.uart2_conf.uart2_clk_en && !PCR.uart2_conf.uart2_rst_en; + default: + HAL_ASSERT(false); + return false; + } + } /** @@ -116,6 +125,9 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) case 1: PCR.uart1_conf.uart1_clk_en = enable; break; + case 2: + PCR.uart2_conf.uart2_clk_en = enable; + break; default: abort(); break; @@ -137,6 +149,10 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) PCR.uart1_conf.uart1_rst_en = 1; PCR.uart1_conf.uart1_rst_en = 0; break; + case 2: + PCR.uart2_conf.uart2_rst_en = 1; + PCR.uart2_conf.uart2_rst_en = 0; + break; default: abort(); break; @@ -191,20 +207,22 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) { + uint32_t sel_value = 0; switch (source_clk) { - case UART_SCLK_PLL_F80M: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1); + case UART_SCLK_XTAL: + sel_value = 0; break; case UART_SCLK_RTC: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2); + sel_value = 1; break; - case UART_SCLK_XTAL: - UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3); + case UART_SCLK_PLL_F80M: + sel_value = 2; break; default: // Invalid UART clock source abort(); } + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); } /** @@ -219,14 +237,14 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source { switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { default: - case 1: - *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; + case 0: + *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; break; - case 2: + case 1: *source_clk = (soc_module_clk_t)UART_SCLK_RTC; break; - case 3: - *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + case 2: + *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; break; } } @@ -270,7 +288,8 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr { typeof(hw->clkdiv_sync) div_reg; div_reg.val = hw->clkdiv_sync.val; - return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1)); + int sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; + return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div); } /** diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 5f96bc2684..a0de48ba4a 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -495,10 +495,6 @@ config SOC_UART_FIFO_LEN int default 128 -config SOC_LP_UART_FIFO_LEN - int - default 16 - config SOC_UART_BITRATE_MAX int default 5000000 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 69b3dfe8a4..d706b2225b 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -19,7 +19,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 // \#define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321 -#define SOC_UART_SUPPORTED 1 //TODO: [ESP32C61] IDF-9320 +#define SOC_UART_SUPPORTED 1 // \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 // \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 #define SOC_GPTIMER_SUPPORTED 1 @@ -70,7 +70,6 @@ // \#define SOC_SDIO_SLAVE_SUPPORTED 0 // \#define SOC_PAU_SUPPORTED 0 // \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337 -// \#define SOC_ULP_LP_UART_SUPPORTED 0 //TODO: [ESP32C61] IDF-9329, IDF-9341 // \#define SOC_PM_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ @@ -422,9 +421,7 @@ // ESP32-C61 has 3 UARTs (3 HP UART) #define SOC_UART_NUM (3) #define SOC_UART_HP_NUM (3) -// \#define SOC_UART_LP_NUM (1U) //TODO: IDF-9341 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ diff --git a/components/soc/esp32c61/include/soc/uart_channel.h b/components/soc/esp32c61/include/soc/uart_channel.h index f62dddf99b..5e9439060e 100644 --- a/components/soc/esp32c61/include/soc/uart_channel.h +++ b/components/soc/esp32c61/include/soc/uart_channel.h @@ -9,10 +9,10 @@ #pragma once //UART channels -#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16 -#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17 +#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 11 +#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 10 -#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL -#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL +#define UART_TXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL +#define UART_RXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL diff --git a/components/soc/esp32c61/include/soc/uart_pins.h b/components/soc/esp32c61/include/soc/uart_pins.h index 0d1cbd792e..2b37ba3520 100644 --- a/components/soc/esp32c61/include/soc/uart_pins.h +++ b/components/soc/esp32c61/include/soc/uart_pins.h @@ -22,10 +22,10 @@ #define U1RTS_GPIO_NUM (-1) #define U1CTS_GPIO_NUM (-1) -#define LP_U0RXD_GPIO_NUM 4 -#define LP_U0TXD_GPIO_NUM 5 -#define LP_U0RTS_GPIO_NUM 2 -#define LP_U0CTS_GPIO_NUM 3 +#define U2RXD_GPIO_NUM (-1) +#define U2TXD_GPIO_NUM (-1) +#define U2RTS_GPIO_NUM (-1) +#define U2CTS_GPIO_NUM (-1) /* The following defines are necessary for reconfiguring the UART * to use IOMUX, at runtime. */ @@ -39,8 +39,8 @@ #define U1RXD_MUX_FUNC (-1) #define U1RTS_MUX_FUNC (-1) #define U1CTS_MUX_FUNC (-1) - -#define LP_U0TXD_MUX_FUNC (1) -#define LP_U0RXD_MUX_FUNC (1) -#define LP_U0RTS_MUX_FUNC (1) -#define LP_U0CTS_MUX_FUNC (1) +/* Same goes for UART2 */ +#define U2TXD_MUX_FUNC (-1) +#define U2RXD_MUX_FUNC (-1) +#define U2RTS_MUX_FUNC (-1) +#define U2CTS_MUX_FUNC (-1) diff --git a/components/soc/esp32c61/include/soc/uart_struct.h b/components/soc/esp32c61/include/soc/uart_struct.h index 870b65310c..0dfffb1a28 100644 --- a/components/soc/esp32c61/include/soc/uart_struct.h +++ b/components/soc/esp32c61/include/soc/uart_struct.h @@ -16,12 +16,11 @@ extern "C" { */ typedef union { struct { - /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0; * Represents the data UART $n read from FIFO.\\ * Measurement unit: byte. */ - uint32_t rxfifo_rd_byte:8; - uint32_t reserved_8:24; + uint32_t rxfifo_rd_byte:32; }; uint32_t val; } uart_fifo_reg_t; diff --git a/components/soc/esp32c61/uart_periph.c b/components/soc/esp32c61/uart_periph.c index 5e3c90c8cc..4f18940705 100644 --- a/components/soc/esp32c61/uart_periph.c +++ b/components/soc/esp32c61/uart_periph.c @@ -75,38 +75,36 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { }, .irq = ETS_UART1_INTR_SOURCE, }, -#if 0 //TODO: [ESP32C61] IDF-9329, IDF-9341 - { // LP UART0 + { // HP UART2 .pins = { [SOC_UART_TX_PIN_IDX] = { - .default_gpio = LP_U0TXD_GPIO_NUM, - .iomux_func = LP_U0TXD_MUX_FUNC, + .default_gpio = U2TXD_GPIO_NUM, + .iomux_func = U2TXD_MUX_FUNC, .input = 0, - .signal = UINT8_MAX, // Signal not available in signal map + .signal = U2TXD_OUT_IDX, }, [SOC_UART_RX_PIN_IDX] = { - .default_gpio = LP_U0RXD_GPIO_NUM, - .iomux_func = LP_U0RXD_MUX_FUNC, + .default_gpio = U2RXD_GPIO_NUM, + .iomux_func = U2RXD_MUX_FUNC, .input = 1, - .signal = UINT8_MAX, // Signal not available in signal map + .signal = U2RXD_IN_IDX, }, [SOC_UART_RTS_PIN_IDX] = { - .default_gpio = LP_U0RTS_GPIO_NUM, - .iomux_func = LP_U0RTS_MUX_FUNC, + .default_gpio = U2RTS_GPIO_NUM, + .iomux_func = U2RTS_MUX_FUNC, .input = 0, - .signal = UINT8_MAX, // Signal not available in signal map + .signal = U2RTS_OUT_IDX, }, [SOC_UART_CTS_PIN_IDX] = { - .default_gpio = LP_U0CTS_GPIO_NUM, - .iomux_func = LP_U0CTS_MUX_FUNC, + .default_gpio = U2CTS_GPIO_NUM, + .iomux_func = U2CTS_MUX_FUNC, .input = 1, - .signal = UINT8_MAX, // Signal not available in signal map + .signal = U2CTS_IN_IDX, }, }, - .irq = ETS_LP_UART_INTR_SOURCE, + .irq = ETS_UART2_INTR_SOURCE, }, -#endif }; diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index 5a8b63cbde..c5242b3946 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -124,7 +124,6 @@ api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/spi_master.rst api-reference/peripherals/index.rst api-reference/peripherals/sdmmc_host.rst -api-reference/peripherals/uart.rst api-reference/peripherals/ecdsa.rst api-reference/peripherals/ldo_regulator.rst api-reference/peripherals/jpeg.rst