Merge branch 'fix/i2s_enable_test_p4_c5_multi' into 'master'

test(driver_i2s): p4 and c5 enable multi dut test

Closes IDF-10321

See merge request espressif/esp-idf!33860

components/esp_driver_i2s/test_apps/.build-test-rules.yml

@@ -11,10 +11,6 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev:
   disable:
     - if: SOC_I2S_SUPPORTED != 1
     - if: SOC_I2S_HW_VERSION_2 != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32p4", "esp32c5"]  # TODO: [ESP32C5] IDF- 10321
-      temporary: true
-      reason: lack of runners
   depends_components:
     - esp_driver_i2s
 

components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -161,6 +161,9 @@ static void test_i2s_tdm_slave(uint32_t sample_rate, i2s_data_bit_width_t bit_wi
     if (sample_rate >= 96000) {
         i2s_tdm_config.clk_cfg.bclk_div = 12;
     }
+#if SOC_I2S_SUPPORTS_APLL
+    i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
+#endif
     TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config));
     TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config));
 
@@ -254,6 +257,8 @@ static void test_i2s_tdm_slave_48k_16bits_8slots(void)
 TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_16bits_8slots", "[I2S_TDM]",
                            test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots);
 
+// The max clock source APLL on P4 is 125M which can't satisfy the following config in slave mode
+#if !CONFIG_IDF_TARGET_ESP32P4
 static void test_i2s_tdm_master_96k_16bits_4slots(void)
 {
     test_i2s_tdm_master(96000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3);
@@ -266,6 +271,7 @@ static void test_i2s_tdm_slave_96k_16bits_4slots(void)
 
 TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_96k_16bits_4slots", "[I2S_TDM]",
                            test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots);
+#endif  // !CONFIG_IDF_TARGET_ESP32P4
 #endif  // !CONFIG_IDF_TARGET_ESP32H2
 
 static void test_i2s_external_clk_src(bool is_master, bool is_external)

components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py

@@ -5,9 +5,10 @@ import pytest
 
 @pytest.mark.esp32s3
 @pytest.mark.esp32c3
-# @pytest.mark.esp32c5  # TODO: [ESP32C5] IDF- 10321
+@pytest.mark.esp32c5
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
+@pytest.mark.esp32p4
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [
     2,

components/esp_driver_i2s/test_apps/test_inc/test_i2s.h

@@ -22,23 +22,7 @@ extern "C" {
 #define SLAVE_WS_IO 22
 #define DATA_IN_IO 19
 #define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
-#define MASTER_MCK_IO 0
-#define MASTER_BCK_IO 4
-#define MASTER_WS_IO 5
-#define SLAVE_BCK_IO 14
-#define SLAVE_WS_IO 15
-#define DATA_IN_IO 19
-#define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32C3
-#define MASTER_MCK_IO 0
-#define MASTER_BCK_IO 4
-#define MASTER_WS_IO 5
-#define SLAVE_BCK_IO 14
-#define SLAVE_WS_IO 15
-#define DATA_IN_IO 19
-#define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32S3
 #define MASTER_MCK_IO 0
 #define MASTER_BCK_IO 4
 #define MASTER_WS_IO 5
@@ -50,8 +34,8 @@ extern "C" {
 #define MASTER_MCK_IO 51
 #define MASTER_BCK_IO 45
 #define MASTER_WS_IO 46
-#define SLAVE_BCK_IO 22
+#define SLAVE_BCK_IO 49
-#define SLAVE_WS_IO 23
+#define SLAVE_WS_IO 50
 #define DATA_IN_IO 47
 #define DATA_OUT_IO 48
 #elif CONFIG_IDF_TARGET_ESP32C5