Merge branch 'feature/gptimer_support_p4' into 'master'

Feature/gptimer support p4

Closes IDF-6515

See merge request espressif/esp-idf!24746

components/esp_system/fpga_overrides.c

@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "sdkconfig.h"
 #include "soc/soc.h"
+#include "esp_private/periph_ctrl.h"
 #ifndef CONFIG_IDF_TARGET_ESP32
 #include "soc/system_reg.h"
 #endif // not CONFIG_IDF_TARGET_ESP32
@@ -76,7 +77,14 @@ void esp_clk_init(void)
 
 void esp_perip_clk_init(void)
 {
-
+    /* Enable TimerGroup 0 clock to ensure its reference counter will never
+     * be decremented to 0 during normal operation and preventing it from
+     * being disabled.
+     * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
+     * registers (Flashboot protection included) will be reenabled, and some
+     * seconds later, will trigger an unintended reset.
+     */
+    periph_module_enable(PERIPH_TIMG0_MODULE);
 }
 
 /**

components/hal/esp32p4/include/hal/timer_ll.h

@@ -0,0 +1,324 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "hal/timer_types.h"
+#include "soc/timer_group_struct.h"
+#include "soc/soc_etm_source.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get timer group register base address with giving group number
+#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
+
+/**
+ * @brief Set clock source for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param clk_src Clock source
+ */
+static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
+{
+    uint8_t clk_id = 0;
+    switch (clk_src) {
+    case GPTIMER_CLK_SRC_XTAL:
+        clk_id = 0;
+        break;
+    case GPTIMER_CLK_SRC_PLL_F80M:
+        clk_id = 2;
+        break;
+    case GPTIMER_CLK_SRC_RC_FAST:
+        clk_id = 1;
+        break;
+    default:
+        HAL_ASSERT(false);
+        break;
+    }
+    if (hw == &TIMERG0) {
+        if (timer_num == 0) {
+            HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_t0_src_sel = clk_id;
+        } else {
+            HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_t1_src_sel = clk_id;
+        }
+    } else {
+        if (timer_num == 0) {
+            HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t0_src_sel = clk_id;
+        } else {
+            HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t1_src_sel = clk_id;
+        }
+    }
+}
+
+/**
+ * @brief Enable Timer Group (GPTimer) module clock
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer index in the group
+ * @param en true to enable, false to disable
+ */
+static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    if (hw == &TIMERG0) {
+        if (timer_num == 0) {
+            HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_t0_clk_en = en;
+        } else {
+            HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_t1_clk_en = en;
+        }
+    } else {
+        if (timer_num == 0) {
+            HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t0_clk_en = en;
+        } else {
+            HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t1_clk_en = en;
+        }
+    }
+}
+
+/**
+ * @brief Enable alarm event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable alarm
+ *           False: disable alarm
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_alarm_en = en;
+}
+
+/**
+ * @brief Set clock prescale for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param divider Prescale value (0 and 1 are not valid)
+ */
+static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
+{
+    HAL_ASSERT(divider >= 2 && divider <= 65536);
+    if (divider >= 65536) {
+        divider = 0;
+    }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
+    hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
+}
+
+/**
+ * @brief Enable auto-reload mode
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable auto reload mode
+ *           False: disable auto reload mode
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_autoreload = en;
+}
+
+/**
+ * @brief Set count direction
+ *
+ * @param hw Timer peripheral register base address
+ * @param timer_num Timer number in the group
+ * @param direction Count direction
+ */
+static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
+{
+    hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
+}
+
+/**
+ * @brief Enable timer, start couting
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable the counter
+ *           False: disable the counter
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_en = en;
+}
+
+/**
+ * @brief Trigger software capture event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+__attribute__((always_inline))
+static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].update.tx_update = 1;
+    // Timer register is in a different clock domain from Timer hardware logic
+    // We need to wait for the update to take effect before fetching the count value
+    while (hw->hw_timer[timer_num].update.tx_update) {
+    }
+}
+
+/**
+ * @brief Get counter value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ *
+ * @return counter value
+ */
+__attribute__((always_inline))
+static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
+}
+
+/**
+ * @brief Set alarm value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param alarm_value When counter reaches alarm value, alarm event will be triggered
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
+{
+    hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
+    hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
+}
+
+/**
+ * @brief Set reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param reload_val Reload counter value
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
+{
+    hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
+    hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
+}
+
+/**
+ * @brief Get reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @return reload count value
+ */
+__attribute__((always_inline))
+static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
+}
+
+/**
+ * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+__attribute__((always_inline))
+static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].load.tx_load = 1;
+}
+
+/**
+ * @brief Enable ETM module
+ *
+ * @param hw Timer Group register base address
+ * @param en True: enable ETM module, False: disable ETM module
+ */
+static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en)
+{
+    hw->regclk.etm_en = en;
+}
+
+/**
+ * @brief Enable timer interrupt by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Mask of interrupt events
+ * @param en True: enable interrupt
+ *           False: disable interrupt
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
+{
+    if (en) {
+        hw->int_ena_timers.val |= mask;
+    } else {
+        hw->int_ena_timers.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Get interrupt status
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status
+ */
+__attribute__((always_inline))
+static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
+{
+    return hw->int_st_timers.val & 0x03;
+}
+
+/**
+ * @brief Clear interrupt status by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Interrupt events mask
+ */
+__attribute__((always_inline))
+static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
+{
+    hw->int_clr_timers.val = mask;
+}
+
+/**
+ * @brief Enable the register clock forever
+ *
+ * @param hw Timer Group register base address
+ * @param en True: Enable the register clock forever
+ *           False: Register clock is enabled only when register operation happens
+ */
+static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
+{
+    hw->regclk.clk_en = en;
+}
+
+/**
+ * @brief Get interrupt status register address
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status register address
+ */
+static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
+{
+    return &hw->int_st_timers;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -19,6 +19,10 @@ config SOC_AXI_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_SUPPORTS_SECURE_DL_MODE
     bool
     default y
@@ -745,7 +749,7 @@ config SOC_TIMER_GROUPS
 
 config SOC_TIMER_GROUP_TIMERS_PER_GROUP
     int
-    default 1
+    default 2
 
 config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
     int
@@ -761,11 +765,7 @@ config SOC_TIMER_GROUP_SUPPORT_RC_FAST
 
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
-    default 2
+    default 4
-
-config SOC_TIMER_SUPPORT_ETM
-    bool
-    default n
 
 config SOC_TWAI_CONTROLLER_NUM
     int
@@ -937,7 +937,7 @@ config SOC_PM_PAU_LINK_NUM
 
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
-    default y
+    default n
 
 config SOC_MODEM_CLOCK_IS_INDEPENDENT
     bool

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -5,6 +5,8 @@
  */
 #pragma once
 
+#include "soc/soc_caps.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -162,16 +164,55 @@ typedef enum {
 
 //////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ *
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#if SOC_CLK_TREE_SUPPORTED
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+#else
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
+#endif
 
+/**
+ * @brief Type of GPTimer clock source
+ */
+typedef enum {
+    GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
+    GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+#if SOC_CLK_TREE_SUPPORTED
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
+#else
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default choice */
+#endif // SOC_CLK_TREE_SUPPORTED
+} soc_periph_gptimer_clk_src_t;
+
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
+typedef enum {
+    TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,     /*!< Timer group clock source is PLL_F80M */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
+#if SOC_CLK_TREE_SUPPORTED
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,      /*!< Timer group clock source default choice is PLL_F80M */
+#else
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL,          /*!< Timer group clock source default choice is XTAL */
+#endif // SOC_CLK_TREE_SUPPORTED
+} soc_periph_tg_clk_src_legacy_t;
 
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
 
-
-
 //////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
 
-
-
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
 
 //TODO: IDF-6511
@@ -187,16 +228,10 @@ typedef enum {
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
 
-
-
 ///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
 
-
-
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
 
-
-
 /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
 
 //TODO: IDF-7502
@@ -217,16 +252,12 @@ typedef enum {
 
 //////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
 
-
 //////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
 
-
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
-
 //////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
 
-
 //////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
 
 //TODO: IDF-6516
@@ -247,10 +278,8 @@ typedef enum {
 
 //////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
 
-
 //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
 
-
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32p4/include/soc/interrupts.h

@@ -61,12 +61,12 @@ typedef enum {
     ETS_RMT_INTR_SOURCE,
     ETS_I2C0_INTR_SOURCE,
     ETS_I2C1_INTR_SOURCE,
+    ETS_TG0_T0_INTR_SOURCE,
+    ETS_TG0_T1_INTR_SOURCE,
     ETS_TG0_WDT_LEVEL_INTR_SOURCE,
+    ETS_TG1_T0_INTR_SOURCE,
+    ETS_TG1_T1_INTR_SOURCE,
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,
-    ETS_TG0_WDT_INTR_SOURCE,
-    ETS_TIMERGROUP1_T0_INTR_SOURCE,
-    ETS_TIMERGROUP1_T1_INTR_SOURCE,
-    ETS_TIMERGROUP1_WDT_INTR_SOURCE,
     ETS_LEDC_INTR_SOURCE,
     ETS_SYSTIMER_TARGET0_INTR_SOURCE,
     ETS_SYSTIMER_TARGET1_INTR_SOURCE,

components/soc/esp32p4/include/soc/soc_caps.h

@@ -32,7 +32,7 @@
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_AHB_GDMA_SUPPORTED          1
 #define SOC_AXI_GDMA_SUPPORTED          1
-// #define SOC_GPTIMER_SUPPORTED           1  //TODO: IDF-6515
+#define SOC_GPTIMER_SUPPORTED           1
 // #define SOC_PCNT_SUPPORTED              1  //TODO: IDF-7475
 // #define SOC_MCPWM_SUPPORTED             1  //TODO: IDF-7493
 // #define SOC_TWAI_SUPPORTED              1  //TODO: IDF-7470
@@ -389,13 +389,12 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
 
 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
+#define SOC_TIMER_GROUPS                  2
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  2
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_XTAL      1
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
+#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   1
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS      4
-#define SOC_TIMER_SUPPORT_ETM             (0)
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 #define SOC_TWAI_CONTROLLER_NUM         2
@@ -470,7 +469,7 @@
 #define SOC_PM_PAU_LINK_NUM             (4)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
-#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
+#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (0)
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */

components/soc/esp32p4/include/soc/timer_group_struct.h

@@ -161,7 +161,6 @@ typedef union {
     uint32_t val;
 } timg_txload_reg_t;
 
-
 /** Group: WDT Control and configuration registers */
 /** Type of wdtconfig0 register
  *  Watchdog timer configuration register
@@ -318,7 +317,6 @@ typedef union {
     uint32_t val;
 } timg_wdtwprotect_reg_t;
 
-
 /** Group: RTC CALI Control and configuration registers */
 /** Type of rtccalicfg register
  *  RTC calibration configure register
@@ -392,7 +390,6 @@ typedef union {
     uint32_t val;
 } timg_rtccalicfg2_reg_t;
 
-
 /** Group: Interrupt registers */
 /** Type of int_ena_timers register
  *  Interrupt enable bits
@@ -482,7 +479,6 @@ typedef union {
     uint32_t val;
 } timg_int_clr_timers_reg_t;
 
-
 /** Group: Version register */
 /** Type of ntimers_date register
  *  Timer version control register
@@ -498,7 +494,6 @@ typedef union {
     uint32_t val;
 } timg_ntimers_date_reg_t;
 
-
 /** Group: Clock configuration registers */
 /** Type of regclk register
  *  Timer group clock gate register
@@ -520,28 +515,20 @@ typedef union {
     uint32_t val;
 } timg_regclk_reg_t;
 
-
 typedef struct {
-    volatile timg_txconfig_reg_t t0config;
+    volatile timg_txconfig_reg_t config;
-    volatile timg_txlo_reg_t t0lo;
+    volatile timg_txlo_reg_t lo;
-    volatile timg_txhi_reg_t t0hi;
+    volatile timg_txhi_reg_t hi;
-    volatile timg_txupdate_reg_t t0update;
+    volatile timg_txupdate_reg_t update;
-    volatile timg_txalarmlo_reg_t t0alarmlo;
+    volatile timg_txalarmlo_reg_t alarmlo;
-    volatile timg_txalarmhi_reg_t t0alarmhi;
+    volatile timg_txalarmhi_reg_t alarmhi;
-    volatile timg_txloadlo_reg_t t0loadlo;
+    volatile timg_txloadlo_reg_t loadlo;
-    volatile timg_txloadhi_reg_t t0loadhi;
+    volatile timg_txloadhi_reg_t loadhi;
-    volatile timg_txload_reg_t t0load;
+    volatile timg_txload_reg_t load;
+} timg_hwtimer_reg_t;
 
-
+typedef struct timg_dev_t {
-    volatile timg_txconfig_reg_t t1config;
+    volatile timg_hwtimer_reg_t hw_timer[2];
-    volatile timg_txlo_reg_t t1lo;
-    volatile timg_txhi_reg_t t1hi;
-    volatile timg_txupdate_reg_t t1update;
-    volatile timg_txalarmlo_reg_t t1alarmlo;
-    volatile timg_txalarmhi_reg_t t1alarmhi;
-    volatile timg_txloadlo_reg_t t1loadlo;
-    volatile timg_txloadhi_reg_t t1loadhi;
-    volatile timg_txload_reg_t t1load;
     volatile timg_wdtconfig0_reg_t wdtconfig0;
     volatile timg_wdtconfig1_reg_t wdtconfig1;
     volatile timg_wdtconfig2_reg_t wdtconfig2;

components/soc/esp32p4/timer_periph.c

@@ -7,5 +7,20 @@
 #include "soc/timer_periph.h"
 
 const timer_group_signal_conn_t timer_group_periph_signals = {
-
+    .groups = {
+        [0] = {
+            .module = PERIPH_TIMG0_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG0_T0_INTR_SOURCE,
+                [1] = ETS_TG0_T1_INTR_SOURCE,
+            }
+        },
+        [1] = {
+            .module = PERIPH_TIMG1_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG1_T0_INTR_SOURCE,
+                [1] = ETS_TG1_T1_INTR_SOURCE,
+            }
+        }
+    }
 };