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Merge branch 'feature/esp32h21_i2c_support' into 'master'

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Feature/esp32h21 i2c support

Closes IDF-11578 and IDF-11580

See merge request espressif/esp-idf!37227
This commit is contained in:
Gao Xu
2025-03-17 15:06:13 +08:00
parent 18f514a4c0 28c531b45b
commit d21adf2535
29 changed files with 1430 additions and 324 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/driver/test_apps/legacy_i2c_driver/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

4
components/esp_driver_i2c/test_apps/i2c_test_apps/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

4
components/esp_lcd/test_apps/i2c_lcd/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
This test app is used to test LCDs with I2C interface.

4
components/esp_lcd/test_apps/i2c_lcd_legacy/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
This test app is used to test LCDs with I2C interface.

4
components/hal/esp32/include/hal/i2c_ll.h
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@ -486,7 +486,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
*length = (hw->status_reg.tx_fifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt);
}
/**
@ -978,7 +978,7 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

2
components/hal/esp32c2/include/hal/i2c_ll.h
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@ -523,7 +523,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**

2
components/hal/esp32c3/include/hal/i2c_ll.h
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@ -1142,7 +1142,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

4
components/hal/esp32c5/include/hal/i2c_ll.h
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@ -561,7 +561,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1181,7 +1181,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

4
components/hal/esp32c6/include/hal/i2c_ll.h
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@ -565,7 +565,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1183,7 +1183,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

4
components/hal/esp32c61/include/hal/i2c_ll.h
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@ -555,7 +555,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1107,7 +1107,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

4
components/hal/esp32h2/include/hal/i2c_ll.h
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@ -551,7 +551,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1090,7 +1090,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

12
components/hal/esp32h21/include/hal/clk_tree_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -276,6 +276,16 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v
return LP_CLKRST.clk_to_hp.clkrst_icg_hp_osc32k;
}
/**
* @brief Get XTAL_CLK frequency
*
* @return Main XTAL clock frequency, in MHz.
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void)
{
return PCR.sysclk_conf.clk_xtal_freq;
}
/**
* @brief Get PLL_CLK frequency
*

1201
components/hal/esp32h21/include/hal/i2c_ll.h Normal file
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File diff suppressed because it is too large Load Diff

4
components/hal/esp32p4/include/hal/i2c_ll.h
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@ -580,7 +580,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1214,7 +1214,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

2
components/hal/esp32s2/include/hal/i2c_ll.h
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@ -531,7 +531,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
*length = (hw->status_reg.tx_fifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt);
}
/**

4
components/hal/esp32s3/include/hal/i2c_ll.h
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@ -612,7 +612,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
__attribute__((always_inline))
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
{
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
*length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
}
/**
@ -1146,7 +1146,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
}
/**
* @brief
* @brief Enable I2C slave TX interrupt
*
* @param hw Beginning address of the peripheral registers
*

4
components/hal/test_apps/hal_i2c/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
# HAL I2C test

10
components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -132,7 +132,13 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
I2C_CLOCK_SRC_ATOMIC() {
i2c_ll_set_source_clk(dev, SOC_MOD_CLK_XTAL);
}
i2c_ll_master_cal_bus_clk(clk_hal_xtal_get_freq_mhz() * MHZ, freq, &clk_cal);
uint32_t xtal_freq = 0;
#if SOC_CLK_TREE_SUPPORTED
xtal_freq = clk_hal_xtal_get_freq_mhz();
#else
xtal_freq = clk_ll_xtal_get_freq_mhz();
#endif
i2c_ll_master_cal_bus_clk(xtal_freq * MHZ, freq, &clk_cal);
i2c_ll_master_set_bus_timing(dev, &clk_cal);
i2c_ll_update(dev);

28
components/soc/esp32h21/i2c_periph.c Normal file
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@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};

60
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
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@ -35,6 +35,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@ -339,6 +343,62 @@ config SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO
bool
default y
config SOC_I2C_NUM
int
default 2
config SOC_HP_I2C_NUM
int
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6

16
components/soc/esp32h21/include/soc/clk_tree_defs.h
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@ -216,6 +216,22 @@ typedef enum {
#endif
} soc_periph_uart_clk_src_legacy_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**

30
components/soc/esp32h21/include/soc/soc_caps.h
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@ -40,7 +40,7 @@
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573
// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11583, IDF-11584, IDF-11587
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568
// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11578, IDF-11580
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598
// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660
#define SOC_MPI_SUPPORTED 1
@ -245,23 +245,23 @@
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-H21 has 2 I2C
// #define SOC_I2C_NUM (2U)
// #define SOC_HP_I2C_NUM (2U)
#define SOC_I2C_NUM (2U)
#define SOC_HP_I2C_NUM (2U)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// #define SOC_I2C_SUPPORT_HW_FSM_RST (1)
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/

215
components/soc/esp32h21/register/soc/i2c_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -909,195 +909,36 @@ typedef union {
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
/** Type of comd register
* I2C command register n
*/
typedef union {
struct {
/** command0 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 0. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Configures command 0. It consists of three parts:
* op_code is the command,
* 0: RSTART,
* 1: WRITE,
* 2: READ,
* 3: STOP,
* 4: END.
*
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
* structure for more information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* When command 0 is done in I2C Master mode, this bit changes to high
* level.
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 1. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* When command 1 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 2. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* When command 2 is done in I2C Master mode, this bit changes to high
* Level.
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 3. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* When command 3 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 4. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* When command 4 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 5. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* When command 5 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 6. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* When command 6 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 7. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* When command 7 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@ -1165,14 +1006,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
volatile i2c_clk_conf_reg_t clk_conf;
volatile i2c_comd0_reg_t comd0;
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@ -1180,16 +1014,15 @@ typedef struct {
uint32_t reserved_088[28];
volatile i2c_date_reg_t date;
uint32_t reserved_0fc;
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
uint32_t reserved_104[31];
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
volatile uint32_t txfifo_mem[32];
volatile uint32_t rxfifo_mem[32];
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
#endif
#ifdef __cplusplus

109
components/soc/esp32h21/register/soc/pcr_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -201,111 +201,59 @@ typedef union {
uint32_t val;
} pcr_mspi_clk_conf_reg_t;
/** Type of i2c0_conf register
/** Type of i2c_conf register
* I2C configuration register
*/
typedef union {
struct {
/** i2c0_clk_en : R/W; bitpos: [0]; default: 1;
/** i2c_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable i2c apb clock
*/
uint32_t i2c0_clk_en:1;
/** i2c0_rst_en : R/W; bitpos: [1]; default: 0;
uint32_t i2c_clk_en:1;
/** i2c_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2c module
*/
uint32_t i2c0_rst_en:1;
/** i2c0_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset i2c0 module
uint32_t i2c_rst_en:1;
/** i2c_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset i2c module
*/
uint32_t i2c0_ready:1;
uint32_t i2c_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_i2c0_conf_reg_t;
} pcr_i2c_conf_reg_t;
/** Type of i2c0_sclk_conf register
/** Type of i2c_sclk_conf register
* I2C_SCLK configuration register
*/
typedef union {
struct {
/** i2c0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
/** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c0_sclk_div_a:6;
/** i2c0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
uint32_t i2c_sclk_div_a:6;
/** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c0_sclk_div_b:6;
/** i2c0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
uint32_t i2c_sclk_div_b:6;
/** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
* The integral part of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c0_sclk_div_num:8;
/** i2c0_sclk_sel : R/W; bitpos: [20]; default: 0;
uint32_t i2c_sclk_div_num:8;
/** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
* set this field to select clock-source. 0(default): XTAL, 1: FOSC.
*/
uint32_t i2c0_sclk_sel:1;
uint32_t i2c_sclk_sel:1;
uint32_t reserved_21:1;
/** i2c0_sclk_en : R/W; bitpos: [22]; default: 1;
/** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
* Set 1 to enable i2c function clock
*/
uint32_t i2c0_sclk_en:1;
uint32_t i2c_sclk_en:1;
uint32_t reserved_23:9;
};
uint32_t val;
} pcr_i2c0_sclk_conf_reg_t;
} pcr_i2c_sclk_conf_reg_t;
/** Type of i2c1_conf register
* I2C configuration register
*/
typedef union {
struct {
/** i2c1_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable i2c apb clock
*/
uint32_t i2c1_clk_en:1;
/** i2c1_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2c module
*/
uint32_t i2c1_rst_en:1;
/** i2c1_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset i2c1 module
*/
uint32_t i2c1_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_i2c1_conf_reg_t;
/** Type of i2c1_sclk_conf register
* I2C_SCLK configuration register
*/
typedef union {
struct {
/** i2c1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c1_sclk_div_a:6;
/** i2c1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c1_sclk_div_b:6;
/** i2c1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
* The integral part of the frequency divider factor of the i2c function clock.
*/
uint32_t i2c1_sclk_div_num:8;
/** i2c1_sclk_sel : R/W; bitpos: [20]; default: 0;
* set this field to select clock-source. 0(default): XTAL, 1: FOSC.
*/
uint32_t i2c1_sclk_sel:1;
uint32_t reserved_21:1;
/** i2c1_sclk_en : R/W; bitpos: [22]; default: 1;
* Set 1 to enable i2c function clock
*/
uint32_t i2c1_sclk_en:1;
uint32_t reserved_23:9;
};
uint32_t val;
} pcr_i2c1_sclk_conf_reg_t;
/** Type of uhci_conf register
* UHCI configuration register
@ -1882,6 +1830,14 @@ typedef struct {
volatile pcr_timergroup_wdt_clk_conf_reg_t timergroup_wdt_clk_conf;
} pcr_timergroup_reg_t;
/**
* @brief The struct of I2C configuration registers
*/
typedef struct {
pcr_i2c_conf_reg_t i2c_conf;
pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
} pcr_i2c_reg_t;
typedef struct {
volatile pcr_uart0_conf_reg_t uart0_conf;
volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
@ -1891,10 +1847,7 @@ typedef struct {
volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
volatile pcr_mspi_conf_reg_t mspi_conf;
volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
volatile pcr_i2c0_conf_reg_t i2c0_conf;
volatile pcr_i2c0_sclk_conf_reg_t i2c0_sclk_conf;
volatile pcr_i2c1_conf_reg_t i2c1_conf;
volatile pcr_i2c1_sclk_conf_reg_t i2c1_sclk_conf;
volatile pcr_i2c_reg_t i2c[2];
volatile pcr_uhci_conf_reg_t uhci_conf;
volatile pcr_rmt_conf_reg_t rmt_conf;
volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;

1
docs/docs_not_updated/esp32h21.txt
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@ -176,7 +176,6 @@ api-reference/peripherals/sdio_slave.rst
api-reference/peripherals/bitscrambler.rst
api-reference/peripherals/temp_sensor.rst
api-reference/peripherals/usb_device.rst
api-reference/peripherals/i2c.rst
api-reference/peripherals/jpeg.rst
api-reference/peripherals/mcpwm.rst
api-reference/peripherals/usb_host.rst

4
examples/peripherals/i2c/i2c_basic/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
# Basic I2C Master Example

4
examples/peripherals/i2c/i2c_eeprom/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
# I2C EEPROM example

4
examples/peripherals/i2c/i2c_tools/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
# I2C Tools Example

4
examples/peripherals/lcd/i2c_oled/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
# I2C OLED example